Isolation transformer with integrated shielding topology for reduced emi

Abstract

A packaged electronic device (100) includes first conductive leads (124-131) and second conductive leads (132-139) at least partially exposed to an exterior of a package structure (120), and a multi-level laminate structure (112) in the package structure (120). The multi-level laminate structure (112) includes first patterned conductive features (111) having a plurality of turns in a first level to form a first winding coupled in a first circuit (161) to at least one of the first conductive leads (124-131), second patterned conductive features (109) having a plurality of turns in a different level to form a second winding coupled in a second circuit (162) isolated from the first circuit (161) to at least one of the second conductive leads (132-139), and a conductive shield trace (111S) having a plurality of turns in a second level spaced apart from and between the first patterned conductive features (111) and the second patterned conductive features (109), the conductive shield trace (111S) coupled in the first circuit (161).

Description

Background Technology

[0001] Integrated isolated power supplies are packaged electronic devices with a semiconductor die and an integrated transformer, providing electrical connections to externally accessible leads (e.g., pins or pads) for soldering to a printed circuit board (PCB). Isolated DC-DC converters can be built using integrated high-voltage isolation transformers, where the transformer coils can be fabricated in a laminated structure for integration into the packaged electronics. Many DC-DC converters have design specifications for electromagnetic interference (EMI), such as CISPR32 and CISPR25, which require that the rated RMS AC or DC supply voltage not exceed 600V for multimedia equipment (MME) EMI radiation requirements set by the Comité International Spécial des Perturbations Radioélectriques (CISPR). Switching of primary-side and / or secondary-side transistors in a DC-DC converter can lead to conducted and / or emitted EMI; for example, the transformer in an isolated DC-DC converter can become a path for electromagnetic energy due to its inter-winding capacitance. EMI can be controlled using ferrite beads, additional capacitors, or other external (e.g., board-level) assemblies, but this increases circuit area, weight, and cost. Furthermore, each design has different specifications in terms of electric field, efficiency, and electromagnetic interference (EMI) performance. Other EMI control methods include spread spectrum modulation (SSM) for controlling the switching of DC-to-DC converters, but this requires additional die space and typically only provides incremental EMI improvement. Summary of the Invention

[0002] According to one aspect, a packaged electronic device includes conductive leads at least partially exposed to the outside of a package structure, second conductive leads at least partially exposed to the outside of the package structure, and a multi-level laminated structure in the package structure. The multi-level laminated structure includes first and second patterned conductive features and conductive shielding traces. The first patterned conductive features have multiple turns in a first level of the multi-level laminated structure to form a first winding coupled to at least one of the first conductive leads in a first circuit. The second patterned conductive features have multiple turns in different levels to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit. The conductive shielding trace has multiple turns in a second level spaced apart from and located between the first and second patterned conductive features. The conductive shielding trace is coupled in the first circuit.

[0003] In one example, the multi-layered structure includes a second conductive shielding trace having multiple turns in another layer between the first and second patterned conductive features. The second conductive shielding trace is coupled in a second circuit and is spaced apart from the first conductive shielding trace. In one example, the first conductive shielding trace is coupled to a ground reference node of the first circuit, and the second conductive shielding trace is coupled to a second ground reference node of the second circuit. In some embodiments, one or more shielding elements may be located peripherally relative to the patterned conductive features. In one example, the first conductive shielding trace includes turns laterally spaced outward from the outermost lateral extent of the first patterned conductive feature in the first layer, and the second conductive shielding trace includes turns laterally spaced from the outermost turns of the second patterned conductive features in a different layer. In some embodiments, one or more shielding elements may be interleaved with the patterned conductive features. In one example, the first conductive shielding trace interleaved with the turns of the first patterned conductive feature in the first layer, and the second conductive shielding trace interleaved with the turns of the second patterned conductive features in a different layer.

[0004] According to another aspect, a multi-level laminated structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding, a second patterned conductive feature having multiple turns in different levels to form a second winding, and a conductive shielding trace having multiple turns in a second level spaced apart from and located between the first and second patterned conductive features. In one example, the multi-level laminated structure further includes a second conductive shielding trace having multiple turns in another level between the first and second patterned conductive features. In one example, the first conductive shielding trace includes turns laterally spaced outward from the outermost lateral extent of the first patterned conductive feature in the first level, and the second conductive shielding trace includes turns laterally spaced apart from the outermost turns of the second patterned conductive feature in different levels. In one example, the first conductive shielding trace intersects with the turns of the first patterned conductive feature in the first level, and the second conductive shielding trace intersects with the turns of the second patterned conductive feature in different levels.

[0005] According to another aspect, a method includes attaching a magnetic assembly having a multi-level laminated structure to a support structure, attaching a first semiconductor die to a first die attachment pad, attaching a second semiconductor die to a second die attachment pad, and performing an electrical connection process and a molding process. The electrical connection process couples the first semiconductor die, a first winding of the multi-level laminated structure, a first conductive shielding trace of the multi-level laminated structure, and at least one first conductive lead from a set of first conductive leads in a first circuit. Furthermore, the electrical connection process couples the second semiconductor die, a second winding of the multi-level laminated structure, a second conductive shielding trace of the multi-level laminated structure, and at least one second conductive lead from a set of second conductive leads in a second circuit isolated from the first circuit. The molding process encapsulates portions of the magnetic assembly, die attachment pads, semiconductor die, and the first and second conductive leads within a package structure. In one example, the electrical connection process couples the first conductive shielding trace to a ground reference node of the first circuit and the second conductive shielding trace to a second ground reference node of the second circuit. Attached Figure Description

[0006] Figure 1 It is a bottom view of a packaged electronic device including a magnetic assembly with conductive shielding traces.

[0007] Figure 2 It is along Figure 1 The partial cross-sectional end view of the packaged electronic device is taken from line 2-2 in the figure.

[0008] Figure 3 It is along Figure 1 The partial cross-sectional end view of the packaged electronic device is taken from line 3-3 in the figure.

[0009] Figure 4 It is along Figure 1 The partial cross-sectional end view of the packaged electronic device is taken from line 4-4 in the figure.

[0010] Figure 5 yes Figures 1-4 A top view of a packaged electronic device.

[0011] Figure 6 yes Figures 1-5 Bottom perspective view of the packaged electronic device.

[0012] Figure 7 This is a flowchart of a method for manufacturing packaged electronic devices.

[0013] Figures 8-13 It is based on Figure 7 Manufactured using the method Figures 1-6 A partial cross-sectional end view of a packaged electronic device.

[0014] Figure 14It has first and second windings and first and second conductive shielding traces. Figures 1-6 A bottom view of the multi-layered laminated structure of packaged electronic devices.

[0015] Figure 15 It has Figure 14 The multi-layered laminated structure and upper and lower magnetic cores Figures 1-6 A bottom view of the magnetic assembly of a packaged electronic device.

[0016] Figure 16 It is along Figure 15 A partial cross-sectional end view of an embodiment of the magnetic assembly, taken from line 16-16.

[0017] Figure 17 It is along Figure 15 A partial cross-sectional end view of another embodiment of the magnetic assembly, taken from line 16-16.

[0018] Figure 18 It is along Figure 15 A partial cross-sectional end view of the third embodiment of the magnetic assembly, taken from line 16-16.

[0019] Figure 19 It is along Figure 15 A partial cross-sectional end view of the fourth embodiment of the magnetic assembly, taken from line 16-16.

[0020] Figure 20 It is along Figure 15 A partial cross-sectional end view of the fifth embodiment of the magnetic assembly, taken from line 16-16.

[0021] Figure 21 It is along Figure 15 A partial cross-sectional end view of the sixth embodiment of the magnetic assembly, taken from line 16-16.

[0022] Figure 22 It is along Figure 15 A partial cross-sectional end view of the seventh embodiment of the magnetic assembly, taken from line 16-16.

[0023] Figure 23 It is a first conductive shielded trace having a first ground reference node coupled to the first circuit. Figures 1-6 A schematic diagram of an embodiment of a packaged electronic device.

[0024] Figure 24 It is a second conductive shielded trace having a second ground reference node coupled to the second circuit. Figures 1-6 A schematic diagram of another embodiment of the packaged electronic device.

[0025] Figure 25These are first and second conductive shielded traces having corresponding first and second ground reference nodes coupled to the first and second circuits. Figures 1-6 A schematic diagram of another embodiment of the packaged electronic device. Detailed Implementation

[0026] In the accompanying drawings, the same reference numerals always refer to the same elements, and various features are not necessarily drawn to scale. In the following discussion and claims, the terms “comprising,” “including,” “having,” “possessing,” “with,” or variations thereof are intended to be included in a manner similar to the term “comprising,” and therefore should be interpreted as “including, but not limited to….” Furthermore, the terms “coupled” or “coupled” are intended to include indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled with a second device, the connection may be via a direct electrical connection or via an indirect electrical connection via one or more intermediate devices and connectors.

[0027] First refer to Figures 1-6 The described examples provide packaged electronics with integrated magnets, such as DC-to-DC converters with integrated isolation transformers, which have one or more conductive shielding traces to mitigate or control EMI radiation. The EMI solutions of the examples shown outperform SSMs in reducing EMI and offer advantages in circuit area, weight, and cost compared to using additional board-level assemblies such as ferrite beads and / or additional capacitors. Using transformers with integrated shielding technology allows end users to reduce EMI without the added cost of discrete ferrite beads and without the need for EMI reduction expertise to design systems using packaged electronics. An asymmetrical voltage across the isolation barrier impedance of a DC-to-DC converter can radiate through two isolated ground planes, which act as dipole antennas and radiate noise. Figures 1-6 An example packaged electronic device 100 is shown with a laminated magnetic assembly having conductive shielding traces between windings (such as primary and secondary transformer windings) in different voltage domains.

[0028] Conductive shielding trace solutions can be used in products with symmetrical or asymmetrical magnetic assemblies and offer scalable solutions to accommodate designs with different electric field, efficiency, and / or EMI performance specifications. Conductive shielding trace solutions can be used in conjunction with magnetic assemblies that are mounted together with semiconductor dies. Figures 1-6 The shared die attachment pads, or magnetic assemblies shown, can be individually supported on conductive support structures spaced apart from the integrated semiconductor die and associated conductive die attachment pads. Conductive shielding traces can be disposed in one or more layers or levels of a multi-layered laminate structure. Figure 1A bottom view of example device 100 is shown, and Figures 2-4 Show along Figure 1 Partial section views and front views of the corresponding lines 2-2, 3-3 and 4-4 in the diagram. Figure 5 A top view of the packaged electronic device 100 is shown, and Figure 6 A bottom perspective view of the packaged electronic device 100 is shown.

[0029] Example electronic device 100 has a small outline integrated circuit (SOIC) package type with gull wing leads on opposite sides. Other packaged electronic devices may be provided in different embodiments, including conductive features that can be soldered to another structure or structures for electrical interconnection, such as so-called leadless package types (e.g., flat leadless packages, such as quad flat leadless packages (QFN), dual flat leadless packages (DFN), miniature leadframes (MLF)) and small outline leadless (SON) types with planar conductive leads (such as peripheral pads providing electrical connections to a printed circuit board (PCB) on the bottom and / or sides of the package). In other examples, device 100 includes ball grid array (BGA) packages or pad grid array (LGA) types, such as molded array process ball grid array (MAPBGA) or overmolded BGA (e.g., plastic BGA or PBGA).

[0030] also, Figures 1-6 Example device 100 provides electrical interconnects for first and second circuits, some or all of which are implemented using bonding wires. In other embodiments, different types of interconnects may be used, including substrate-based interconnects (BGA, LGA, etc.), wherein the substrate includes electrical interconnects and signal routing structures (e.g., copper or aluminum traces on one or more layers or levels) used alone or in combination with bonding wire electrical connections. Figure 1 As shown, example device 100 includes conductive features (e.g., conductive die attachment pads or supports) for mounting and supporting first and second semiconductor dies and laminated magnetic assemblies. The die attachment pads and device leads can include any suitable conductive structure, such as copper, aluminum, etc.

[0031] Figure 1 Example device 100 includes a first semiconductor die 102 attached to a first conductive die attachment pad 104 of a leadframe assembly. Device 100 also includes a second semiconductor die 106 attached to a second conductive die attachment pad 108. Electronic device 100 includes a first circuit (e.g., 161, ) associated with a first voltage domain (e.g., a high-voltage primary circuit of an integrated power device). Figure 1(Currently labeled "Circuit 1"). Device 100 also includes a second circuit (e.g., 162, labeled "Circuit 2") associated with a second voltage domain (e.g., isolated lower voltage secondary circuit). In this example, the second circuit 162 includes a secondary winding formed by a second patterned conductive feature 109 (also referred to as a second winding) of the magnetic assembly 110. The laminated magnetic assembly 110 includes a first patterned conductive feature 111 (also referred to as a first winding) in a multi-level laminated structure 112. In the illustrated example, the multi-level laminated structure 112 includes a plurality of conductive features forming the primary and secondary windings of a transformer. The first patterned conductive feature 111 is in the first level (e.g., below). Figures 16-18 The multi-level laminate 112 includes a second patterned conductive feature 109 having multiple turns in different levels to form a second winding (e.g., a transformer secondary winding). The multi-level laminate 112 also includes a conductive guard trace 113 spaced apart from the first patterned conductive feature 111 and located between the outermost turn of the first conductive feature 111 and one side of the device 100 associated with the second voltage domain. This helps maintain the high electric field associated with the voltage difference between the first (e.g., primary) winding and the second (e.g., secondary) circuit leads inside the laminate 112. In other embodiments, the guard trace 113 may be omitted.

[0032] The example multi-level laminated structure 112 includes a first conductive shielding trace 111S, which has multiple turns in a second level between a first patterned conductive feature 111 and a second patterned conductive feature 109. The conductive shielding trace 111S is coupled in a first circuit 161. Figures 1-6 The example multi-level laminated structure 112 further includes a second conductive shielding trace 109S, which has multiple turns in another layer between the first patterned conductive feature 111 and the second patterned conductive feature 109. Figures 1-6 In one example, the second conductive shielding trace 109S is coupled to the conductive protection trace 113 in the second circuit 162. In another example, the second conductive shielding trace 109S is omitted.

[0033] The magnetic assembly 110 also includes one or more magnetic core structures to facilitate the integration of patterned conductive features 111 to form a magnetic circuit. Examples illustrated include those shown in... Figure 1 , Figure 2 , Figure 5 and Figure 6A first (lower or bottom) magnetic core structure 114 is visible. The first magnetic core structure 114 is attached to a first side of the laminate structure 112. The electronic device 100 includes electrical connections, such as bonding wires 115, 116, 117, 118, and 119 forming electrical interconnects between certain components and leads. The packaged electronic device 100 also includes a package structure 120 that encapsulates conductive die attachment pads 104 and 108, semiconductor dies 102 and 106, magnetic assembly 110, and all or part of the conductive leads of the device 100. In one example, the package structure 120 is or includes a molding material, such as plastic. In another example, the package structure 120 is or includes a ceramic material.

[0034] Magnetic assembly 110 also includes a second (upper or top) magnetic core structure 121 (in Figure 1 , Figure 2 , Figure 5 and Figure 6 (See image). A first magnetic core structure 114 is attached to a first side of the laminated structure 112, while a second magnetic core structure 121 is attached to a second side of the laminated structure 112. In one example, the first magnetic core structure 114 has the same dimensions as the second magnetic core structure 121. In another example, the first magnetic core structure 114 is larger than the second magnetic core structure 121. In yet another example, the first magnetic core structure 114 is smaller than the second magnetic core structure 121. In one example, one or both of the magnetic core structures 114 and 121 are prefabricated magnetic cores attached using epoxy resin paste. In another example, one or both of the magnetic core structures 114 and 121 are manufactured using a thick layer of magnetic paste. The laminated magnetic assembly 110 is attached to a support structure 122 integral with the second conductive die attachment pad 108. In another embodiment, the magnetic assembly 110 is mounted to a support structure (not shown) that is separate from and spaced apart from the first die attachment pad 104 and the second die attachment pad 108.

[0035] The first set of electrical connections includes a first set of bonding wires 115 and 116, which couple at least one of a set of first conductive leads 124-131 from a first conductive shielding trace 111S (if included), a first semiconductor die 102, a first patterned conductive feature 111, and a first conductive lead from a first (e.g., high-voltage primary) circuit 161 of the device 100. Figure 1As best illustrated, the first conductive die attachment pad 104 is directly coupled to a single first lead 125. In other examples, the first die attachment pad 104 is directly coupled to multiple conductive first leads. In example device 100, the die attachment pad 104 and the lead 125 are a single continuous metal structure, such as copper or aluminum. A first bonding wire 115 couples a conductive feature (e.g., a bonding pad) of the first semiconductor die 102 to a first lead 126, and a bonding wire 116 couples additional bonding pads of the first semiconductor die 102 to a first end and a second end of a first patterned conductive feature 111, and also couples a ground reference node of the first semiconductor die 102 to a first conductive shield trace 111S.

[0036] In this example, the second set of electrical connections includes a second set of bonding wires 117, 118, and 119, which couple at least one of a set of second conductive leads from a second conductive shielding trace 109S (if included), a second semiconductor die 106, a second patterned conductive feature 109, a conductive protection trace 113 (if included), and a second conductive lead 132-139 from a second circuit 162 (e.g., a lower voltage secondary circuit) isolated from the first circuit 161. A second conductive die attachment pad 108 is directly coupled to a single lead 138, and a connected support structure 122 is directly connected to the single lead 132. In other examples, the second die attachment pad 108 and / or the support structure 122 are directly coupled to multiple conductive leads. In example device 100, the second die attachment pad 108, the support structure 122, and the leads 132 and 138 are a single continuous metal structure, such as copper or aluminum. Bonding wire 117 couples the bonding pads of the second semiconductor die 106 to the second lead 137. Bonding wire 118 couples the additional bonding pads of the second semiconductor die 106 to the first and second ends of the second patterned conductive feature. Furthermore, bonding wire 119 couples the second semiconductor die 106 to the second conductive shielding trace 109S and the conductive protection trace 113.

[0037] like Figures 2-4 and Figure 6 As best shown, package structure 120 encapsulates die attachment pads 104 and 108 and associated support structure 122. Furthermore, package structure 120 encapsulates the internal portions of conductive leads 124-139. In one example, conductive leads 124-139 are so-called gull-wing leads, which are as follows... Figures 2-4 and Figure 6 The diagram shows leads extending downwards and outwards from package structure 120. Different types and shapes of conductive leads (e.g., J-leads) are used in other examples. Figures 2-4 Show along Figure 1 and Figure 5The corresponding cross-sectional views of the packaged electronic device 100, taken by lines 2-2, 3-3, and 4-4 in the figure. (See also...) Figures 2-4 As best shown, the example package structure 120 includes a top side 211 and an opposite bottom side 212.

[0038] The multi-layer laminated structure 112 has a first side 141 facing the first conductive leads 124-131 and a second side 142 facing the second conductive leads 132-139. In this orientation, the conductive protective trace 113 is spaced apart from and located between the first winding formed by the first patterned conductive feature 111 and the second conductive leads 132-139. The package structure 120 has a first direction (e.g., Figures 1-6 The first side 151 and the second side 152 of the package structure 120 are spaced apart from each other in the X direction. First conductive leads 124-131 are positioned along the first side 151 of the package structure 120 and extend outwards, while second conductive leads 132-139 are positioned along the second side 152 of the package structure 120 and extend outwards. A conductive protective trace 113 is spaced apart from and located between the first patterned conductive feature 111 and the second side 152 of the package structure 120. Figure 1 and Figure 6 As shown, the conductive protection trace 113 is along a second direction perpendicular to the direction shown (e.g., Figures 1-6 The first patterned conductive feature 111 has a length of 143 in the Y direction, and the outermost coil of the first patterned conductive feature 111 has a shorter length of 144 in the second direction.

[0039] During operation of the electronic device 100, the voltage of the first patterned conductive feature 111 can be significantly higher than the voltage of the second conductive leads 132-139 along the second side 152 of the package structure 120. The internal portions of the second conductive leads 132-139 are encapsulated by a molding compound or ceramic material of the package structure 120, which has a lower dielectric constant than the laminates or levels of the multilevel laminate structure 112. Furthermore, the external portions of the second conductive leads 132-139 are exposed to ambient air, which has a lower dielectric constant than both the package structure 120 and the multilevel laminate structure 112. The relatively long length and positioning of the conductive protection trace 113 within the multilevel laminate structure 112 help maintain a high electric field in the high-dielectric material of the multilevel laminate structure 112, mitigating or preventing arcing during production testing and normal operation of the packaged electronic device 100.

[0040] Figure 7 Showing the use of manufacturing such as Figures 1-6 The method 700 for packaging electronic devices 100, and Figures 8-13An example packaged electronic device 100 manufactured according to method 700 is shown. Method 700 includes manufacturing a laminated magnetic assembly with conductive shielding traces at 701. In some embodiments, the magnetic assembly is assembled separately and provided as input to method 700. In the illustrated example, the manufacturing of the magnetic assembly at 701 includes attaching a bottom magnetic core (e.g., a sheet) to the back side of a multi-stage laminated structure at 702. Figure 8 An example is shown in which an attachment process 800 is performed to attach a first (lower or bottom) magnetic core structure 114 to the bottom side of an example multi-stage laminate structure 112.

[0041] The multilevel laminate 112 can be any suitable multilayer laminate having patterned conductive features 109 and 111 (such as transformer windings) and conductive protective traces 113. The patterned conductive features 109, 111, and 113 can be produced by any suitable process, such as screen printing conductive material onto the laminate layers. The multilevel laminate 112 may include one or more bonding steps to bond the laminate layers or sheets to each other to form the multilevel laminate 112. In one example, the laminate layers each comprise a bismaleimide triazine (BT) laminate, and one, some, or all of the layers include patterned conductive features (e.g., copper or other conductive materials), such as traces forming windings or winding turns. In some examples, the multi-level laminate structure 112 is constructed layer by layer, for example, starting from a central or intermediate dielectric layer (e.g., a core dielectric layer), and each layer adds any patterned copper conductive features and conductive vias to interconnect the conductive features of different levels, thereby forming the multi-level laminate structure 112. For high-voltage isolation, each level of the multi-level laminate structure 112 is or includes a high-voltage BT laminate material that provides high voltage breakdown strength and can be pre-impregnated with a resin (such as epoxy resin). The individual BT laminate layers can be assembled using any suitable adhesive with any desired curing method (such as curing by a combination of heat and pressure).

[0042] In one example, the core structure 114 is a magnetic sheet structure, but this is not necessary in all possible implementations. The attachment process 800 may include depositing epoxy resin or other adhesives onto the bottom surface of the multi-layer laminate structure 112 and / or the surface of the core structure 114. In one example, the adhesive is printed magnetic ink epoxy resin, but in other examples, non-magnetic adhesives may be used. The attachment process 800 also includes contacting the core structure 114 with the bottom side of the multi-layer laminate structure 112 and / or with the epoxy resin formed thereon. In one example, the attachment process 800 also includes any necessary curing steps (e.g., heat, light, ultraviolet (UV) light, etc.).

[0043] Method 700 continues at 704 by attaching a top magnetic core (e.g., a sheet) to the front side of the laminated structure. Figure 9 An example is shown in which a second attachment process 900 is performed to attach a second (upper or top) magnetic core structure 121 to a second side of the laminate structure 112. Attachment process 900 may be the same as or similar to the first attachment process 800 used to attach a first magnetic core structure 114 to the laminate structure 112. The respective upper magnetic core structures 121 and lower magnetic core structures 114 are attached to the multi-stage laminate structure 112 using epoxy resin or other suitable attachment structures and / or techniques to form a magnetically coupled transformer device. In other examples, one of the upper magnetic core structure 121 or the lower magnetic core structure 114 may be omitted, and the remaining magnetic core structure provides magnetic coupling for the transformer of device 100.

[0044] Method 700 further includes separating (e.g., singulating) the magnetic assembly at 706. In one example, the magnetic assembly process is used to simultaneously manufacture multiple laminated magnetic assemblies, such as using a single large multi-level laminated structure 112, and attaching one or more magnetic core structures 114, 121 to their opposite sides. Figure 10 An example is shown where such a large laminated structure 112 is diced or cut to separate or isolate the individual laminated magnetic assemblies 110 from the initial monolithic structure. Figure 10 In the example, a segmentation process 1000 is performed, which, for example, uses a saw, etching, laser cutting, etc., to segment or separate multiple laminated magnetic assemblies 110 from the initial monolithic structure.

[0045] At 708, the magnetic assembly 110 is attached to the support structure 122. In one embodiment, the attachment at 708 includes attaching the magnetic assembly 110 to the support structure 122, wherein a first side 141 of the multi-stage laminate 112 faces the first conductive leads 124-131, and a second side 142 of the multi-stage laminate 112 faces the second conductive leads 132-139. In this example, the attachment at 708 also includes oriented the magnetic assembly 110 such that a conductive guard trace 113 (if included) is spaced apart from and located between the first winding 111 and the second conductive leads 132-139 of the multi-stage laminate 112.

[0046] In one example, a lead frame structure is provided, which includes conductive leads (e.g., the one above). Figures 1-6 124-139) and conductive die attachment pads 104 and 108. In one embodiment, the lead frame structure is provided on an adhesive tape or other adhesive carrier, wherein the various component structures are assembled in a predetermined relative arrangement to facilitate subsequent assembly steps in method 700. Figure 11An example is shown in which an attachment process 1100 is performed to attach the multi-level laminated structure 112 of the magnetic assembly 110 to a corresponding surface of the support structure 122. Any suitable attachment process 1100 can be used, such as applying an adhesive, bonding the assemblies, and any necessary curing. In another example, the conductive features of the multi-level laminated structure 112 can be soldered to the support structure 122 at 708.

[0047] Process 700 in Figure 7 Continue at 710 and 712, for example, by using adhesive or solder to attach the semiconductor die to the corresponding die attachment pad. Figure 12 An example is shown in which a die attachment process 1200 is performed to attach a first semiconductor die 102 to a first die attachment pad 104 (e.g., where the die attachment pad 104 is a continuous conductive structure including lead 125). At 712, process 1200 also attaches a second semiconductor die 106 to a corresponding second die attachment pad 108 (e.g., also including a continuous conductive structure including lead 138).

[0048] Method 700 also includes electrical connection processing (e.g., wire bonding) at 714. Figure 13 An example is shown in which a wire bonding process 1300 is performed, which forms a connection between one or more conductive leads and / or conductive features of a semiconductor die and a magnetic assembly 110 (e.g., above). Figures 1-6 Bonding lines 115-119 are used to form the first circuit 161 and the second circuit 162. Figure 13 In the cross-sectional view shown, the interconnection process 1300 includes forming a first bonding wire connector 115 between a first conductive feature of the first semiconductor die 102 and a conductive lead 126, and forming a bonding wire connector 117 between a first conductive feature of the second semiconductor die 106 and a conductive lead 137. In another example, different electrical connections are formed to create a first circuit 161, such as flip-chip processing to interconnect solder balls, conductive pillars, bonding pads, etc., of a structure in the circuit. The electrical interconnection process 1300 couples the first semiconductor die 102, the first winding 111 of the multi-stage laminate structure 112, the first conductive shielding trace 111S of the multi-stage laminate structure 112, and at least one of the first conductive leads 124-131 in the first circuit 161.

[0049] Furthermore, electrical connection process 1300 couples at least one of the following second conductive leads: the second semiconductor die 106, the second winding 109 of the multi-stage laminated structure 112, the second conductive shielding trace 109S, and a set of second conductive leads 132-139 in a second circuit isolated from the first circuit. In one example, electrical connection process 1300 couples the second conductive shielding trace 109S to any included conductive protection trace 113. In one example, electrical connection process 1300 couples the first conductive shielding trace 111S to the ground reference node of the first circuit 161 and couples the second conductive shielding trace 109S to the second ground reference node of the second circuit 162 (e.g., below). Figure 23 Further connections can be made at 714 for specific designs, for example, to form... Figures 1-6 The bonding lines shown are 115-119.

[0050] In one example, wire bonding process 1300 couples a first conductive shielding trace 111S of the multi-stage laminate structure 112 to a first circuit 161. In one embodiment, wire bonding process 1300 couples a second conductive shielding trace 109S of the multi-stage laminate structure 112 to a second circuit 162. Additionally, in one example, wire bonding process 1300 couples a conductive protection trace 113 to the second conductive shielding trace 109S of the multi-stage laminate structure 112. In another example, different electrical connections are formed to create the first circuit 161, such as flip-chip processing to interconnect solder balls, conductive pillars, bonding pads, etc., of the structure in the second circuit. In some examples, a support structure may be used to perform wire bonding or other interconnection processes at 714 to provide mechanical structural support for one or more features of the magnetic assembly 110 during wire bonding. In one example, one or both of the core structures 114 and 121 may be supported by a custom wire bonding clamping tool (not shown) during wire bonding operations. In one example, the bonding wire clamping tool may include a cavity for supporting the laminated bonding pad area that extends beyond the supported magnetic core structure.

[0051] Method 700 continues to form the final package structure 120 at 716. In one example, the package at 716 includes performing a molding process (not shown) to form the package structure 120 to encapsulate portions of dies 102 and 106, conductive die attachment pads 104 and 108, support structure 122, magnetic assembly 110, electrical connections (e.g., bonding wires 115-119), and conductive leads 124-139. Figures 1-6 Shown in Figure 7 An example molded plastic encapsulation structure 120 is formed at position 716. In another example, a ceramic encapsulation structure can be formed at position 716. Figure 7At point 718, further back-end processing, such as lead forming and trimming, can be performed.

[0052] Figures 14-18 Further details of the example multi-level laminated structure 112 are shown. Figure 14 A bottom view of a multi-stage laminated structure 112 with a first winding, a second winding, and conductive protective traces is shown. Figure 15 A bottom view of the magnetic assembly 110 is shown, in which a multi-layered laminate structure 112 and corresponding upper magnetic core 114 and lower magnetic core 121 are attached. Figures 16-18 Show along Figure 15 Partial cross-sectional end views of three different embodiments of the magnetic assembly 110 cut from 16-16 lines. The multi-layered laminated structure 112 is a multi-layered structure having patterned conductive features 109, 109S, 111, 111S, and 113 forming portions of a transformer. In one example, a first patterned conductive feature 111 forms the primary winding of the transformer, and a second patterned conductive feature 109 forms the secondary winding of the transformer. In another example, additional patterned conductive features form one or more secondary windings, one or more conductive (e.g., Faraday) shields, one or more sensing coils, and one or more conductive shielding traces and conductive protection traces 113.

[0053] In one example, the patterned conductive features have components on multiple levels (e.g., layers) of the multilevel laminate structure 112, but this is not required in all possible implementations. In one example, the patterned winding turns of the respective primary and / or secondary windings extend on different layers of the multilevel laminate structure 112, but this is not required in all possible implementations. Example patterned winding features include multiple turns of wire in a spiral pattern on the respective layers of the multilevel laminate structure 112, but other implementations are also possible, such as single-turn winding structures on the respective layers. Example patterned conductive features forming transformer windings 109 and 111, shields 109S and 111S, and protective traces 113 include conductive end connection features that allow the windings to interconnect to pins or semiconductor dies of device 100, such as for bonding wire connectors 115-119 or other conductive interconnect types (e.g., solder balls, not shown) in packaged electronics 100. Semiconductor dies 102 and 106 include pillars, solder bumps, conductive pads, or other conductive features (e.g., bonding pads), which can be electrically interconnected to other structures using bonding wires 115-119 or by direct soldering using any suitable electrical interconnection technology (e.g., wire bonding, flip chip attachment, etc.).

[0054] Figures 16-18 The external portion of an example embodiment of the multi-level laminated structure 112 is shown; the internal or central portions are omitted for clarity. Figures 16-18As shown, the multi-level laminated structure 112 has a first side 141 and an opposing second side 142 spaced apart from each other along the X direction, and a stack of levels (e.g., layers) 1601-1607 along the Z direction. The multi-level laminated structure 112 has a third side 1613 attached to the magnetic core 121 and a fourth side 1614 attached to the magnetic core 114 and spaced apart from the third side 1613 along the Z direction. A first patterned conductive feature 111 includes multiple turns in the first layer 1601 to form a first winding, and a second patterned conductive feature 109 has multiple turns in two different layers 1606 and 1607 to form a second winding. In this example, a second conductive shield 109S is formed in the fifth layer 1605, and layers 1603 and 1604 form an isolation barrier between the primary and secondary circuits. Figure 16 In the example, the conductive protective trace 113 and the first conductive shield 111S are formed in the second layer 1602, wherein the conductive protective trace 113 is spaced apart from and located between the first patterned conductive feature 111 and the second side 142 of the multi-level laminated structure 112. Figure 17 Another example is shown, in which a conductive protective trace 113 is formed in a first layer 1601, spaced apart from and located between the first patterned conductive feature 111 and the second side 142 of the multi-level laminated structure 112. Figure 18 In the example, the conductive protection trace 113 is formed in the corresponding first layer 1601 and second layer 1602, and the conductive protection trace 113 is spaced apart from and located between the first patterned conductive feature 111 and the second side 142 of the multi-level laminated structure 112.

[0055] Figures 16-18 In one example, the first conductive shielding trace 111S has multiple turns in a second layer 1602 spaced apart from and located between the first patterned conductive feature 111 and the second patterned conductive feature 109. In these examples, the second conductive shielding trace 109S has multiple turns in another layer 1605 between the first patterned conductive feature 111 and the second patterned conductive feature 109. Furthermore, the second conductive shielding trace 109S is spaced apart from the conductive shielding trace 111S. In an alternative embodiment, the protective trace 113 can be drawn from... Figures 16-18 The example is omitted. Figures 16-18 The embodiments provide a double-shielded implementation for the primary circuit 161 and the secondary circuit 162, with corresponding first shielding 111S and second shielding 109S.

[0056] Also refer to Figures 19-22 It shows several further examples of masking traces. Figure 19 Show along Figure 15A partial cross-sectional end view of the fourth embodiment of the magnetic assembly 110, taken from line 16-16. This example is a single shield, in which a second conductive shielding trace 109S in a second (e.g., secondary) circuit 162 coupled in a fifth layer 1605 is spaced along the Z-direction from and between the turns of the corresponding first conductive trace 109 and second conductive trace 111. In this example, the secondary coil trace 109 extends in corresponding sixth layers 1606 and seventh layers 1607. The second conductive shielding trace 109S has turns in the fifth layer 1605 that are spaced from and extend substantially in common with the secondary coil trace 109.

[0057] Figure 20 Show along Figure 15 An example of double shielding for the magnetic assembly 110 cut from line 16-16 is provided. This example provides double peripheral shielding traces 109S and 111S, and peripheral shielding traces in corresponding layers of the respective first conductive trace 109 and second conductive trace 111. This example further includes a protective trace 113 in a second layer 1602, which may be omitted in another embodiment. Figure 20 In the example, the conductive shielding trace 111S includes turns of wire spaced laterally outward along the X direction from the outermost lateral extent of the first patterned conductive feature 111 in the first layer 1601. Figure 20 As shown, the first conductive trace 109 and the second conductive trace 111 occupy the central portion of the magnetic assembly 110 along a lateral width dimension 2001, and the outermost turns of the conductive shielding traces 109S and 111S are spaced apart from the outermost lateral extent of the patterned conductive features 111 and 109 by a non-zero distance 2002. In this example, the second conductive shielding trace 109S includes turns that are laterally spaced outward from the outermost turns of the second patterned conductive feature 109 in layers 1605 and 1606. In this embodiment, as... Figure 20 As shown, the outer turns of conductive shielding traces 109S and 111S face each other across the dielectrics of layers 1603, 1604, and 1605, forming one or more parasitic capacitors 2000. (See below) Figure 25 As schematically shown, one or more parasitic capacitors 2000 (CP) facilitate EMI reduction by providing capacitive impedance between isolated first circuit 161 and second circuit 162. Furthermore, Figure 20 The example provides an interleaved shielding trace, wherein the second conductive shielding trace 109S in the sixth level 1606 is interleaved with the turns of the second patterned conductive feature 109.

[0058] Figure 21 Show along Figure 15The sixth embodiment of the magnetic assembly 110 cut from line 16-16. This example also provides an interleaved shielded trace configuration in which the turns of both the second patterned conductive feature 109 and the second conductive shielded trace 109S are formed in the fifth level 1605 and the seventh level 1607. Figure 22 The example magnetic assembly 110 provides staggered peripheral shielding, and both the first layer 1601 and the second layer 1602 include turns of a first patterned conductive feature 111 and a first conductive shielding trace 111S. Furthermore, laminated structure layers 1605, 1606, and 1607 each include turns of both a second patterned conductive feature 109 and a second conductive shielding trace 109S. Additionally, as described above... Figure 20 As in the example, conductive shielding traces 111S and 109S each include transversely outwardly spaced wire turns from the outermost wire turns of the corresponding patterned conductive features 111 and 109 in the second layer 1602 and the fifth layer 1605, to provide one or more corresponding parasitic capacitors 2000.

[0059] Figures 23-25 Three example electrical interconnects of the first circuit 161 and the second circuit 162 are shown. Figure 23 A schematic diagram 2300 is provided illustrating an example, in which a first conductive shielded trace 111S is coupled to a first ground reference node of a first circuit 161. (See diagram 2300.) Figure 23 As schematically shown, the first conductive shielding trace 111S extends between the first conductive feature 111 and the second conductive feature 109 that form the primary winding and secondary winding of the transformer. Figure 23Schematic diagram 2300 also shows example circuit components of the first circuit 161 and the second circuit 162. In this embodiment, an input voltage source 2302 provides an input voltage VIN to an input node 2304 of a ground reference node 2306 of the first circuit 161. An input capacitor CI is coupled between the input node 2304 and the first ground reference node 2306. A pair of cross-coupled PMOS transistors 2311 and 2312 have sources coupled to the input node 2304 and drains coupled to the opposite end of the primary winding 111 (the end of the first patterned conductive feature 111). Switching NMOS transistors 2313 and 2314 are coupled between the drains of the respective transistors 2311 and 2312 and the first ground reference node 2306, respectively. The secondary circuit 162 provides an output voltage VO at an output terminal 2324 of a second ground reference node 2326 of the second circuit 162. An output capacitor CO is coupled between terminals 2324 and 2326. The second circuit 162 also includes a pair of cross-coupled PMOS transistors 2331 and 2332, each coupled between the output node 2324 and the corresponding end of the secondary winding 109 (the second patterned conductive feature 109). NMOS transistors 2333 and 2334 are each coupled between the drain of the corresponding PMOS transistors 2331 and 2332 and the second ground reference node 2326.

[0060] Figure 24 Show Figures 1-6 A schematic diagram 2400 of another embodiment of the packaged electronic device, wherein a second conductive shielding trace 109S is coupled to a second ground reference node 2326 of a second circuit 162. Figure 23 and Figure 24 A single-shielded interconnect for a first circuit 161 and a second circuit 162 is provided, having a ground-referenced shield between the primary winding 111 and the secondary winding 109 for EMI control or reduction. In a simulation example, a single-shielded interconnect for EMI control or reduction is provided. Figure 23 or Figure 24 A single-sided Faraday shield can provide 3-5 dB of EMI reduction.

[0061] Figure 25 Show Figures 1-6 A schematic diagram 2500 of a double-shielded embodiment of a packaged electronic device shows a first conductive shielding trace 111S and a second conductive shielding trace 109S located between a primary winding 111 and a secondary winding 109. Furthermore, Figure 25 The double-shielded traces 111S and 109S in the middle provide parasitic capacitors CP (e.g., above) coupled to the respective first ground reference node 2306 and second ground reference node 2326 of the first circuit 161 and the second circuit 162. Figure 20 and Figure 22(Capacitor 2000 in the circuit). In this embodiment, the first conductive shielding trace 111S is coupled to the ground reference node 2306 of the first circuit 161, and the second conductive shielding trace 109S is coupled to the second ground reference node 2326 of the second circuit 162. In a simulation example, Figure 25 The double Faraday shielding provides approximately 10-12 dB of EMI radiation reduction.

[0062] The described examples provide integrated magnets for packaged electronics with integrated EMI reduction features without increasing cost or requiring external circuitry or components for isolating DC-DC converters or other applications. Furthermore, since no additional board-level circuitry is required, EMI reduction is independent of the end-user's design expertise. In various embodiments, conductive shielding traces are patterned on one or more layers of the multi-layer laminate 112, and during wire bonding or other electrical interconnection processes in manufacturing, they can be connected to associated first or second circuitry, such as to their ground reference node. Various embodiments provide single-layer shielding between transformer coils, double shielding located between or around the transformer coils, for example, to create one or more parasitic capacitors, and staggered shielding. In operation, the staggered shielding example provides a temporary option between the optimal EMI reduction performance of the double-shielded configuration and the single-shielded example providing high coupling. In some examples, the shielding coils may be positioned around the power supply coils. In other embodiments, the conductive shielding traces provide block capacitor shielding. Block capacitor shielding is formed in capacitor plates at different levels, these plates being separated by one or more dielectric layers, wherein the respective capacitor plates are connected to corresponding circuits in the first and second circuits, and the capacitor plate structure may, but does not need to, form turns around the power coil in order to increase capacitance (e.g., above). Figure 20 and Figure 22 The described examples also provide package-level solutions for electromagnetic interference (EMI) and can be used alone or in combination with external circuit components and / or silicon-based solutions such as SSMs. Furthermore, the described examples provide integrated EMI solutions independent of silicon process nodes and / or system-level board designs.

[0063] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A packaged electronic device, comprising: The first conductive lead is at least partially exposed outside the package structure; A second conductive lead is at least partially exposed outside the package structure; The multi-level lamination structure in the encapsulation structure includes: A first patterned conductive feature portion having a plurality of turns in a first level to form a first winding coupled to at least one first conductive lead in the first circuit; A second patterned conductive feature portion having multiple turns at different levels to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit; and A conductive shielding trace having a plurality of turns in a second level spaced apart from and located between the first patterned conductive feature and the second patterned conductive feature, the conductive shielding trace being coupled in the first circuit; The multi-level laminated structure includes a second conductive shielding trace having multiple turns in another level between the first patterned conductive feature and the second patterned conductive feature, the second conductive shielding trace being coupled in the second circuit, and the second conductive shielding trace being spaced apart from the conductive shielding trace to create one or more parasitic capacitors therebetween.

2. The packaged electronic device according to claim 1, further comprising: A first semiconductor die, which is at least partially attached to a first die attachment pad in the package structure; A second semiconductor die, which is at least partially attached to a second die attachment pad in the package structure; A first set of electrical connectors, which couples the first semiconductor die, the first patterned conductive feature, the conductive shielding trace, and at least one of the first conductive leads in the first circuit. as well as The second set of electrical connectors is coupled to at least one of the second conductive leads in the second semiconductor die, the second patterned conductive feature, and the second conductive lead in the second circuit.

3. The packaged electronic device according to claim 1, wherein: The conductive shielding trace is coupled to the ground reference node of the first circuit; and The second conductive shielding trace is coupled to the second ground reference node of the second circuit.

4. The packaged electronic device according to claim 1, wherein: The conductive shielding traces include transversely spaced turns of wire extending laterally outward from the outermost transverse extent of the first patterned conductive feature in the first layer; and The second conductive shielding trace includes turns of wire spaced laterally outward from the outermost turn of the second patterned conductive feature in the different layers.

5. The packaged electronic device according to claim 4, wherein: The conductive shielding traces intersect with the coils of the first patterned conductive feature portion in the first layer; and The second conductive shielding trace intersects with the wire turns of the second patterned conductive feature in the different layers.

6. The packaged electronic device according to claim 1, wherein: The conductive shielding traces intersect with the coils of the first patterned conductive feature portion in the first layer; and The second conductive shielding trace intersects with the wire turns of the second patterned conductive feature in the different layers.

7. The packaged electronic device of claim 1, wherein the conductive shielding trace comprises turns of wire spaced laterally outward from the outermost lateral extent of the first patterned conductive feature in the first layer.

8. The packaged electronic device according to claim 1, wherein the conductive shielding traces intersect with the wire turns of the first patterned conductive feature portion in the first layer.

9. The packaged electronic device according to claim 1, wherein: The first conductive lead is positioned along a first side of the package structure; and The second conductive lead is positioned along different second sides of the package structure.

10. The packaged electronic device of claim 1, further comprising a magnetic core structure attached to one side of the laminated structure adjacent to the first layer.

11. The packaged electronic device of claim 10, further comprising a second magnetic core structure attached to a different second side of the laminated structure adjacent to the different layers.

12. The packaged electronic device according to claim 1, further comprising a conductive protection trace, the conductive protection trace being spaced apart from the first patterned conductive feature and located between the outermost turn of the first patterned conductive feature and one side of the multi-level laminated structure.

13. The packaged electronic device of claim 1, further comprising a second conductive shielding trace having a plurality of turns in another layer between the first patterned conductive feature and the second patterned conductive feature.

14. The packaged electronic device of claim 12, further comprising a second conductive shielding trace having a plurality of turns in another layer between the first patterned conductive feature and the second patterned conductive feature.

15. The packaged electronic device of claim 14, wherein the second conductive shielding trace is coupled to the conductive protection trace.

16. The packaged electronic device of claim 1, further comprising one or more structures for facilitating the formation of a magnetic circuit with the first patterned conductive feature.

17. The packaged electronic device of claim 1, further comprising a magnetic core structure attached to a first side of the multi-layer laminated structure.

18. The packaged electronic device of claim 1, further comprising a magnetic core structure attached to a second side of the multi-layer laminated structure.

19. The packaged electronic device of claim 1, further comprising a first magnetic core structure attached to a first side of the multi-level laminated structure and a second magnetic core structure attached to a second side of the multi-level laminated structure.

20. The packaged electronic device of claim 19, wherein the first magnetic core structure and the second magnetic core structure are of the same size.

21. The packaged electronic device of claim 19, wherein the first magnetic core structure and the second magnetic core structure have different dimensions.

22. The packaged electronic device of claim 19, wherein the first magnetic core structure, the second magnetic core structure, and the multi-level laminate structure constitute a magnetic assembly.

23. The packaged electronic device according to claim 2, further comprising a first magnetic core structure attached to a first side of the multi-level laminated structure and a second magnetic core structure attached to a second side of the multi-level laminated structure.

24. The packaged electronic device of claim 23, wherein the first magnetic core structure and the second magnetic core structure are of the same size.

25. The packaged electronic device of claim 23, wherein the first magnetic core structure and the second magnetic core structure have different dimensions.

26. The packaged electronic device of claim 23, wherein the first magnetic core structure, the second magnetic core structure, and the multi-level laminate structure constitute a magnetic assembly.

27. The packaged electronic device of claim 26, wherein the magnetic assembly is attached to a support structure, the support structure being integrated with the second die attachment pad.

28. The packaged electronic device of claim 26, wherein the magnetic assembly is attached to a support structure, the support structure being separated from and spaced apart from the first die attachment pad and the second die attachment pad.

29. The packaged electronic device of claim 1, wherein the first circuit is associated with a first voltage domain and the second circuit is associated with a second voltage domain.

30. The packaged electronic device of claim 29, wherein the first voltage domain is a high-voltage primary circuit of an integrated power supply device, and the second voltage domain is an isolated low-voltage circuit.

31. A multi-stage laminated structure, comprising: First side; The second side is spaced apart from the first side along the first direction; The third side; The fourth side is spaced apart from the third side along a second direction, the second direction being perpendicular to the first direction; A first patterned conductive feature portion having multiple turns in a first level to form a first winding; The second patterned conductive feature has multiple turns in different layers to form a second winding; A conductive shielding trace having a plurality of turns in a second level spaced apart from and located between the first patterned conductive feature and the second patterned conductive feature, the conductive shielding trace being coupled to one of the first patterned conductive feature and the second patterned conductive feature; as well as A second conductive shielding trace has multiple turns in another level between the first patterned conductive feature and the second patterned conductive feature, the second conductive shielding trace being coupled to another of the first patterned conductive feature and the second patterned conductive feature, wherein the second conductive shielding trace is spaced apart from the conductive shielding trace to create one or more parasitic capacitors therebetween.

32. The multi-stage laminated structure according to claim 31, wherein: The conductive shielding traces include transversely spaced turns of wire extending laterally outward from the outermost transverse extent of the first patterned conductive feature in the first layer; and The second conductive shielding trace includes turns of wire spaced laterally outward from the outermost turn of the second patterned conductive feature in the different layers.

33. The multi-stage laminated structure according to claim 31, wherein: The conductive shielding traces intersect with the coils of the first patterned conductive feature portion in the first layer; and The second conductive shielding trace intersects with the wire turns of the second patterned conductive feature in the different layers.

34. The multi-layered laminated structure according to claim 31, wherein the conductive shielding traces comprise turns of wire spaced laterally outward from the outermost lateral extent of the first patterned conductive feature in the first layer.

35. The multi-layered laminated structure according to claim 31, wherein the conductive shielding traces intersect with the wire turns of the first patterned conductive feature portion in the first layer.

36. A method for manufacturing an electronic device, the method comprising: Attach magnetic assemblies with multi-level laminated structures to the support structure; Attach the first semiconductor die to the first die attachment pad; Attach the second semiconductor die to the second die attachment pad; An electrical connection process is performed, wherein the electrical connection process couples the first semiconductor die, the first winding of the multi-layered structure, the first conductive shielding trace of the multi-layered structure, and at least one first conductive lead from a set of first conductive leads in the first circuit, and couples the second semiconductor die, the second winding of the multi-layered structure, the second conductive shielding trace of the multi-layered structure, and at least one second conductive lead from a set of second conductive leads in the second circuit isolated from the first circuit, wherein the electrical connection process couples the first conductive shielding trace to a ground reference node of the first circuit and couples the second conductive shielding trace to a second ground reference node of the second circuit, wherein the second conductive shielding trace is spaced apart from the first conductive shielding trace to create one or more parasitic capacitors therebetween; as well as A molding process is performed to encapsulate portions of the magnetic assembly, the first die attachment pad, the second die attachment pad, the first semiconductor die, the second semiconductor die, the first conductive lead, and the second conductive lead within a package structure. The first conductive lead and the second conductive lead are at least partially exposed to the outside of the magnetic assembly. The first winding is located in a first layer of the multi-stage laminated structure, the second winding is located in a different second layer of the multi-stage laminated structure, the first conductive shielding trace is located in a different third layer spaced apart from and between the first and second layers, and the second conductive shielding trace is located in a different fourth layer spaced apart from and between the first and second layers.

37. A packaged electronic device, comprising: The first conductive peripheral pad is at least partially exposed to the outside of the package structure; The second conductive peripheral pad is at least partially exposed to the outside of the package structure; The multi-level lamination structure in the packaging structure includes: A first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one first conductive peripheral pad in the first circuit; A second patterned conductive feature having multiple turns in different levels to form a second winding coupled to at least one second conductive peripheral pad in a second circuit isolated from the first circuit; A conductive shielding trace having multiple turns in a second level, the second level being spaced apart from and located between the first and second patterned conductive features, the conductive shielding trace being coupled in the first circuit; and The second conductive shielding trace has multiple turns in another layer between the first patterned conductive feature and the second patterned conductive feature. The second conductive shielding trace is coupled in the second circuit and is spaced apart from the conductive shielding trace to create one or more parasitic capacitors between them.

38. The packaged electronic device according to claim 37, further comprising: A first semiconductor die, which is at least partially attached to a first die attachment pad in the package structure; A second semiconductor die, which is at least partially attached to a second die attachment pad in the package structure; The first set of electrical connectors couples the first semiconductor die, the first patterned conductive feature, the conductive shielding trace, and at least one of the first conductive peripheral pads in the first circuit. as well as The second set of electrical connectors couples the second semiconductor die, the second patterned conductive feature, and at least one of the second conductive peripheral pads in the second circuit.

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