Analog computer with variable gain

Abstract

Improved performance of the analog computer is achieved by reducing the gain of a gain element present in the analog computer as appropriate. When there is a previous output of the circuit (if any), the gain of the gain element is reduced to a level low enough that the input signal cannot propagate through the circuit. Then, the input signal is changed to a new value or set of values ​​while the gain of the gain element remains reduced. Finally, the gain of the gain element is increased to a level high enough to allow the input signal to propagate through the circuit, thereby producing an output that is a solution to the problem represented by the analog computer.

Description

[0001] This application claims priority to Provisional Application No. 62 / 812,202 filed on February 28, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates generally to analog computers and, more particularly, to analog computers with variable gain. Background Art

[0003] An analog computer is a type of computer that uses continuously variable aspects of some physical phenomenon (such as electrical quantities, mechanical quantities, or hydraulic forces) to model the problem being solved. In contrast, digital computers represent varying quantities symbolically and by discrete values ​​of both time and amplitude. The slide rule is one of the simplest analog computers. Although digital computers have replaced analog computers in many applications, some problems are still solved advantageously with analog computers.

[0004] The present method is directed to electrical analog computers that model problems in the electrical domain. Such analog computers are based on components with gain, usually operational amplifiers ("op-amps") that conventionally have high gain. For example, the solution of a complex equation such as the Schrödinger equation can be modeled in the electrical components of an analog computer.

[0005] The principle is that the differential Schrödinger equation, which may involve time, can be solved by mapping it into its electrical analog (i.e., Kirchhoff's current law for a circuit using equivalent constraints as the solution to the problem). When one or more inputs are applied to the constrained network that models the problem, the simulated voltages and currents within the analog computer change as the network arrives at a solution that represents the solution to the problem.

[0006] The network of analog computers may be static, where the solution is obtained when the electrical parameters converge to a static result, or dynamic, where the solution is provided by periodic steady states of the electrical parameters.

[0007] One problem that arises with such electrical analog computers is the response of the network to input modifications. When changes are made to the inputs, the analog voltages and currents in the computer must be changed again to solve the problem again, now using the new input parameters. As is known in the art, the time it takes to establish a new solution is finite and depends on the gain-bandwidth product of the high-gain element and the feedback around the high-gain element (if any). This can result in a transient between the "old" solution (i.e., the solution for the previous input) and the "new" solution for the new input.

[0008] This transient exists in the configuration of the gain elements that form the analog computer as it adapts to new inputs, whether the network is static or dynamic. A transient event in a static network is the time it takes for the electrical parameters to converge again to the new static results. A transient event in a dynamic network is the time it takes to move between two periodic steady-state solutions: the periodic steady-state solution for the previous input state and a new periodic steady-state solution for the current input state.

[0009] In some cases, the delay of the transient can be significant. Therefore, it is desirable to reduce the length of the transient so that the analog computer can provide a faster solution to the desired problem represented by the network of computer elements. Summary of the invention

[0010] This application describes apparatus and methods for improving the performance of analog computers.

[0011] One embodiment describes a method of operating an analog computer, the analog computer including a plurality of gain elements configured to operate on a total input signal to provide a solution to a predetermined problem, the gain of each of the plurality of gain elements being capable of varying between a level sufficient to propagate the signal input to the element and a level insufficient to propagate the signal input to the element, the method comprising: reducing the gain of each of the plurality of gain elements to a level insufficient to propagate the signal input to the gain element; changing the total input signal while the gain of the gain element is at the reduced level; and increasing the gain of each of the plurality of gain elements to a level sufficient to propagate the signal input to the gain element at a time no earlier than the time at which the input signal changes.

[0012] Another embodiment describes a variable gain element for an analog computer, comprising: a first transistor and a second transistor, each transistor having a gate, a source and a drain, the gate of the first transistor being configured to receive an input signal, and the gate of the second transistor being connected to a reference point; a first resistor and a second resistor, the first resistor being connected to the drain of the first transistor and to one side of a voltage source, the second resistor being connected to the drain of the second transistor and to the voltage source; a current source connected to the sources of both the first transistor and the second transistor, the current source being configured to provide currents of different levels in response to a control signal; an amplifier having an input terminal and an output terminal, the input terminal being connected to the drains of the first transistor and the second transistor and the reference point, the output terminal providing an output of the gain element; and a control circuit configured to provide a control signal based on a preselected condition.

[0013] Another embodiment describes a variable gain element for an analog computer, comprising: a first amplifier configured to receive a signal at a first end and to generate an amplified signal at a second end; a first resistor element having a first end configured to receive an input signal of the variable gain element and a second end connected to the first end of the first amplifier; a second resistor element having a first end connected to the first end of the first amplifier and a second end connected to the second end of the first amplifier; a switch having a first end connected to the first end of the first amplifier, a second end connected to the second end of the first amplifier, and a switch port configured to receive a control signal, the switch being in an open position or a closed position depending on the control signal; control logic configured to provide a control signal to open or close the switch based on a preselected condition; and a second amplifier configured to receive a signal at a first end and to generate an amplified signal at a second end, the first end of the second amplifier being connected to the second end of the first amplifier, and the second end of the second amplifier being configured to generate an output signal from the variable gain element.

[0014] Yet another embodiment describes an analog computer comprising: a plurality of gain elements configured to operate on a total input signal to provide a solution to a predetermined problem, the gain of each gain element being capable of varying between a level sufficient to propagate the signal input to the element and a level insufficient to propagate the input signal; a gain control device configured to switch the gain of the gain element between a level sufficient to propagate the input signal and a level insufficient to propagate the input signal based on a control signal; and a logic device configured to generate a control signal that causes the gain control device to switch the gain of the gain element to a level insufficient to propagate the input signal before the total input signal changes, and to switch the gain of the gain element to a level sufficient to propagate the input signal no earlier than the time when the input signal changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A gain element with variable gain is shown according to one embodiment.

[0016] Figure 2a and Figure 2b It is shown Figure 1 A graph of the gain characteristics of a gain element.

[0017] Figure 3 is a diagram showing a plurality of gain elements (eg Figure 1 Block diagram of a circuit having multiple gain elements as shown.

[0018] Figure 4 is responsive to new input both in the prior art and in embodiments of the methods described herein Figure 3 Timing diagram of the output of the circuit.

[0019] Figure 5 In one embodiment Figure 3 Graphs of multiple random simulations of the operation of a circuit.

[0020] Figure 6 is a block diagram illustrating an example of a simulated neural network known in the art.

[0021] Figures 7 to 9 yes Figure 6 An example graph of one of the outputs of a simulated neural network.

[0022] Fig.10 A block diagram of one embodiment is shown, as well as a block diagram of a prior art circuit providing similar functionality.

[0023] Fig.11 and Fig.12 yes Fig.10 A diagram of the comparative speeds of the circuits.

[0024] Fig.13 is a diagram of an inverter circuit illustrating certain aspects of the methods described herein.

[0025] Fig.14 The results show that the control signal Fig.13 A graph of the results of a series of examples of inverter circuits sending logic signals.

[0026] Fig.15 is a circuit diagram of one embodiment of a differential circuit according to one embodiment.

[0027] Fig.16 is a circuit diagram of a circuit according to one embodiment in which an amplifier is used Fig.15 The differential circuit is used as an element of an analog computer.

[0028] Fig.17 is a circuit diagram of a circuit according to one embodiment in which a Fig.16 Multiple instances of the circuit are used to implement analog computers.

[0029] Fig.18 is a circuit diagram of a circuit according to one embodiment, in which: Fig.15 The amplifier can be turned into any type of two-input gate.

[0030] Fig.19 is a flow chart of a method of operating a simulation computer according to one embodiment of the present method. DETAILED DESCRIPTION

[0031] Described herein are apparatus and methods for improving the performance of analog computers. The apparatus and methods described utilize a measured reduction in the gain of high gain elements present in an analog computer, either globally (i.e., across all instances of the high gain element) or in a meaningful block or subset of the high gain elements.

[0032] Those skilled in the art will appreciate that in an analog computer, conventional solutions to the problems being solved are determined by simplifying assumptions of high gain in the operational amplifiers configured within the analog computer.

[0033] As described above, there is a transient of some finite duration between the "old" solution for an input (or set of inputs) and the "new" solution for a new input. However, rather than waiting for this finite duration to obtain a new solution, according to the present method, empirical observations indicate that if the gain elements of the simulation computer are all reduced to a gain that is insufficient to propagate the solution within the computer network, then the simulation computer does not need to perform the transient response from the old input to the new input.

[0034] Specifically, the method of the present invention is illustrated by a series of steps:

[0035] First, the gain of the computational elements within the simulated computer is reduced to a level that is insufficient for the gain elements to propagate the signal while the old input state is present on the computer. This will cause the solution for the current input to degenerate: in the limit where the gain approaches zero, the voltages and currents within the computer will be reduced to mere thermal perturbations. Thus, the signal that is assumed to still be present at the computer input cannot propagate through the computational elements, and will "disappear" in elements that are sufficiently far away from the input (in terms of connectivity).

[0036] Next, while the analog computer is in this degraded state with insufficient gain, the input (or set of inputs) is adjusted to a new input value (or set of values). This has little effect on the computer, because the effect of the first step above is that the gain is too low to solve the new problem.

[0037] Finally, the gain of the computational element is then restored slightly after or while the new input is applied to a gain level sufficient to allow the gain element of the analog computer to propagate the signal, thereby solving the problem now presented by the new input.

[0038] The benefit of this process is that even in the presence of these three steps, the time taken to respond to a new input is shorter than would result if the gain did not decrease when the input changed. This is contrary to what one would expect. For example, reducing the power supply to a complementary metal oxide semiconductor (CMOS) logic chip would generally reduce speed rather than increase it; for example, a computer processor would slow down in response to a reduction in available power, so performance would be slower rather than faster.

[0039] This process can be viewed as changing the system's "noise margin." As is known in the art, to be detectable and useful, a signal must exceed the noise that necessarily accompanies it by a sufficient amount so that the signal can be distinguished from the noise; the noise margin is the ratio by which the signal exceeds the minimum acceptable amount.

[0040] In analog computers, the signal must exceed the noise to a tolerable error rate. Since noise has a Gaussian distribution and is theoretically infinite in amplitude, the noise tolerance can be thought of as the number of standard deviations of the mean noise that the signal must exceed to meet a given error rate. For example, a signal with an amplitude of three standard deviations of the mean noise will be exceeded by noise about 0.3% of the time, while a signal with an amplitude of six standard deviations of the mean noise will be exceeded by noise only 0.0000002% of the time.

[0041] Using the concept of noise tolerance, the method described herein can be described as allowing the noise tolerance of the previous input state of the analog computer to degrade to the point where the signal is indistinguishable from the noise, i.e., the noise tolerance is zero. A new input is then applied, and the noise tolerance is increased. All signals then begin to break away from the noise and converge to a new solution. Converging from noise to a new state is faster than the time required to transition from the old state to the new state across the noise tolerance in existing known systems.

[0042] Thus, the described method speeds up the analog computer by defining a non-propagating, noise-limited state as an intermediate state between two solutions. Furthermore, in addition to making the analog computer run faster, as will be appreciated by those skilled in the art based on the teachings herein, this speedup can translate into reduced power operation of the analog computer.

[0043] A certain analogy that can help understand the present method is the problem of placing grocery items on supermarket shelves. A store employee has a shopping cart full of items and places the items on the shelf in a certain order, such as alphabetically. After the task is completed, the manager decides that this is not the best arrangement and asks the employee to rearrange the items on the shelf so that the items are placed by food type rather than alphabetically.

[0044] The employee now has to take the items off the shelves and rearrange them. This is time consuming for several reasons; the employee must remove each "wrongly" placed item from its location and then place it in a new location. But that new location may already be occupied by another item that was placed in the previous sequence. Therefore, the employee must move the other item first, and so on.

[0045] In this context, the method can be thought of as a switch for all shelves, or individual switches for individual shelves in a group of shelves. When the switch is activated, the switch throws all items back into the shopping cart. The employee must then start over, taking out each item again, this time arranging the items on the shelf by food type. However, since no items are still in their previous locations, the employee never has to remove an item from the "wrong" location, and the new placement of an item is not blocked by previously placed items, so the process is faster.

[0046] Before the items in the cart are put on the shelves, the items are randomly put into the cart; therefore, there is no order and the "noise tolerance" of the items is zero. Order is applied when the employee puts the items on the shelves, so now there is a noise tolerance. In this example, it is faster to return to a disordered state by throwing all the items off the shelf between the first alphabetical shelving operation and the second shelving by food type than to actually move all the items directly from alphabetical order to food type arrangement.

[0047] Figure 1 A type of gain element that can be used, for example, in an analog computer is shown. Circuit 100 will be recognized by those skilled in the art as a type of differential amplifier known as a long-tailed pair circuit with a resistive load and an additional current source I1. Circuit 100 includes two N-type metal oxide semiconductor field effect transistors (MOSFETs) M1 and M2, two resistors R1 and R2 connected between a power supply VDD and the drains of transistors M1 and M2, respectively, an amplifier U, and a current source I1.

[0048] In this case, amplifier U is a voltage-controlled voltage source with a gain of 1 and transmits the voltage difference between the resistive loads R1 and R2 to the output Out and hence to the next circuit. Point REF is ground, which sets a threshold for whether the input signal is a high or low level signal and allows amplifier U to output a signal compatible with the next similar gain element.

[0049] However, while the amplifier has a gain of 1, the circuit 100 may have a gain greater than or less than 1. In the present approach, the current source I1 is capable of providing different levels of current in response to a switch or control circuit (as further described below). Figure 2a and Figure 2b The change characteristics of the circuit 100 when the current through the current source I1 changes from 2 μA to 8 μA in a step of 2 microamperes (μA) are shown. Within a certain input range (here +400 millivolts), when the current through the current source I1 is 2 μA, the change of the output (y-axis) relative to the input (x-axis) is less than 1, and the gain is greater than 1 when the current is 8 μA.

[0050] This is because when the current level through current source I1 is low enough, the transconductance of transistors M1 and M2 drops and there is no current between the source and drain of the transistors, so no current flows through resistors R1 and R2, and there is no output from circuit 100. Therefore, by reducing the current through current source I1, the gain of circuit 100 is reduced.

[0051] Therefore, Figure 1 One way to increase the gain of a gain element such as circuit 100 from a level insufficient to propagate a signal to a level required to propagate a signal is to add a switch or other element that increases the current through current source I1 and control logic that causes the switch or other element to do so at the appropriate time (i.e., shortly before or simultaneously with a change in the input of circuit 100). Fig.10 Another example of a method of reducing element gain is described.

[0052] If the gain is to be increased after a change in the input signal, some type of detection and control circuitry or logic may be used to determine that a change in the input has occurred, and in response, increase the gain of the gain element. For example, a differential amplifier circuit may be sufficient to detect even a small change in the input, and then generate a control signal to increase the gain of the gain element; after a time sufficient for the analog computer to propagate the input signal and reach the output, the gain is reduced again. In some cases, the gain of the gain element may be increased to a level sufficient to propagate the input signal at the same time as the input changes; for example, if the input changes at regular intervals, a timing circuit may be used to increase the gain based on preselected conditions corresponding to the timing of the expected input signal (i.e., at preselected times or intervals when the input signal is expected to change), and then reduce the gain again to a level insufficient to propagate the signal after a known period of time when the analog computer can propagate the signal and derive a new output solution. Note that in this case, increasing the gain "at the same time" as the input changes may even include increasing the gain slightly before the input signal actually changes, if the gain increase precedes the input change by too short a time for the gain element to respond quickly enough to operate on the previous input signal (if any). Alternatively, as will be appreciated by those skilled in the art from the teachings herein, the problem of slightly premature input signals may be addressed by using logic elements, such as inverters, unity gain operational amplifiers, or similar devices that introduce a predictable short delay.

[0053] Now consider when something like Figure 1 Figure 1 shows what happens when multiple gain elements of circuit 100 are connected in series. Figure 3is a block diagram of a circuit 300 showing such an arrangement of gain elements; the gain element is designated U1 and the number 64 indicates that there are 64 such gain elements connected in series. The first total input A is applied to the first gain element whose output is output X; this output x becomes the input A of the next gain element, and so on, until the output of the last gain element is considered the total output Y.

[0054] With the gain elements connected in series in this way, it is then possible to compare the time taken to obtain a solution Y to the problem represented by the total input A in two different cases. In this example, it is assumed that there is no problem to be solved, but that the output of the circuit simply replicates the input, regardless of which time delay is inherent in either the conventional method or the method described herein.

[0055] In one case, conventional technology, the previous input and solution are replaced by the new input and solution, as described above, transients occur in conventional analog computers, so the solution is reached only after the new total input A has propagated through all 64 active gain elements to determine the solution Y. In the second case, under the present method described herein, the gain of the gain element has been reduced to zero and then increased at a specific point in time.

[0056] Figure 4 In both cases, Figure 3 A graph of the results of a Simulation Program for Integrated Circuit Emphasis (“SPICE”) simulation of circuit 300 .

[0057] The input signal, a rectangular clock signal, is Figure 4 The output signal is shown by curve A in FIG. Figure 4 Curve C in indicates the gain variation of the gain element.

[0058] like Figure 4 As shown in curve C of FIG. 3 , by increasing the current through current source I1 from 2 μA to 8 μA, the gain of the gain element in circuit 300 increases at a time of 65.01 nanoseconds (nS). As described above, before this, the gain of the gain element is very low, so no signal propagates from the input, and thus the output is zero as shown in curve B.

[0059] Once the gain of the gain element increases at 65.01 nS, the circuit is able to propagate the input signal. Note that in this case, none of the gain elements have a previous state because the gain of the gain element was previously zero. Therefore, when the gain is first increased, the circuit 300 operates according to the present method. Figure 4 As shown in curve B of FIG. 3 , the output reflects the input at a time of 65.12 nS; in other words, it takes 0.11 nanoseconds or 110 picoseconds (pS) for circuit 300 to reach the output from the disordered state of zero gain.

[0060] Now, with the gain high and not subsequently reduced, circuit 300 will continue to operate, but now in a conventional manner, i.e., with a transient between the output produced by the input and the next output produced by the changed input. The first change in input after the gain is increased is the falling edge of the rectangular signal at 71.01 nS; the output changes at 72.14 nS in response to the change in input. Thus, the transition time from the previous output to the new output is 1.13 nS, more than 10 times the 0.11 nS change described above without the previous output.

[0061] As the input signal continues, the next change in the input is the rising edge of the rectangular signal at 81.01 nS. Since the gain remains high, the circuit 300 operates again in the conventional manner of the prior art. The output changes at 81.71 nS in response to the rising edge of the input signal, thus resulting in a transition time of 0.7 nS. Although this is shorter than the transition time in the falling edge case (this asymmetry caused by different rise and fall times is not uncommon), it is still more than six times the case without the previous state.

[0062] In addition to faster processing times, the described approach has an additional benefit; when operating without gain, circuit 300 uses significantly less power than when operating in a conventional manner.

[0063] In normal operation, all 64 gain elements of circuit 300 will require 8 μA of continuous current through Il, for a total current of 512 μA. In contrast, when operated in the manner described herein, each gain element will require only 2 μA or 128 μA, except for the period of time during which circuit 300 must respond to changes in input, i.e., approximately 110 pS for each input change (again allowing for different rise and fall times). It can therefore be seen that if the gain of the gain element is increased when an input change is applied, and then decreased after the new output is obtained, the total current consumed will be only slightly more than one quarter of the current consumed in normal operation.

[0064] Figure 5 yes Figure 3 Graph of 16 random simulations of operation of circuit 300 using the present method described herein. As can be observed by line 502, the input is provided while the gain is increasing (at 65 nS in this example). Figure 5The shaded area 504 in FIG. 5 is the profile of all responses in the 16 simulations. In the best case, as observed at point 506, circuit 300 reaches the output before a time of 65.1 nS (i.e., less than 100 pS), and in the worst case, as observed at point 508, the output reaches a valid level before a time of 65.5 nS (i.e., less than 500 pS), even given the random variations in the configuration of the gain element. This is still less than half the time of 1.13 nS found in idealized simulations of the circuit operating in a conventional manner (as discussed above with respect to FIG. 5 ). Figure 4 discussed), thus demonstrating the benefit of the present approach even in the presence of random manufacturing errors.

[0065] One area that may benefit from this approach is the design of simulated artificial intelligence (AI) processing units. A simulated AI computer may be implemented using a T-model of AI networks known in the art by, for example, Figure 1 The circuit 100 is composed of multiple circuits.

[0066] As is well known, AI neural networks have "layers." The higher the number of layers, the greater the benefit that the present method can provide, because the benefit of the present method increases as the number of layers that the input signal must propagate through increases.

[0067] Figure 6 600 is a block diagram showing an analog neural network 600 known in the art. As shown, the neural network 600 has eight layers, each layer includes elements Xn, and thus produces eight outputs. Each element Xn has 8 neurons in a vertical column, each neuron has 8 resistors, and thus each element Xn has 64 weights; since there are 8 elements Xn in the horizontal direction, there are a total of 64 neurons and 512 weights.

[0068] Figures 7 to 9 It also shows Figure 6 Comparison of one of the eight outputs of the AI ​​neural network 600 in two different situations (one is the conventional method of the prior art and the other is the method of the current invention described herein). Figures 7 to 9 In the graph 702, the gain of the gain element of the AI ​​neural network 600 increases simultaneously with a change in the input mode at 30 nS; in the graph 704, the gain increases simultaneously with another change in the input mode at 40 nS.

[0069] When the input mode changes from low to high at 40nS, the AI ​​neural network 600 is in normal operation because the gain has been high since 30nS, so there is a previous output state and transition time as described above. The solid line 702 shows that the output switches from its low level (approximately -300mV) to its high level (+300mV), and as Figure 8 As can be seen in more detail in FIG. 1 , a high level is reached at 46.61 nS at point 706.

[0070] When the gain increases at 40 nS (while the input changes from low to high), the AI ​​neural network 600 operates using the method of the present invention and has no previous state (the previous output is zero). The dashed line 704 shows that although the output begins to go negative in the wrong direction at first at portion 708, the output is still at 45.16 nS at point 710 ( Figure 8 ) reaches its high level faster. Therefore, using the method of the present invention, the high level output is reached after 5.16nS at point 708 compared to 6.61nS at point 710 in conventional operation, i.e., about 30% faster than conventional operation.

[0071] Figures 7 to 9 It is also shown that even when the input mode switches in the other direction, the present method results in the output being reached in a shorter time, i.e., allowing for asymmetry in the rise and fall times. When the gain increases at 30 nS as the input mode changes, the AI ​​neural network 600 again operates through the method of the present invention, since again there is no previous state (the previous output was zero). Here, the output reaches its low level at 3.28 nS at point 712.

[0072] However, when the input mode changes at 50 nS, the AI ​​neural network 600 operates in a conventional manner because the gain of the gain element is not reduced. The output returns to its low level at 54.37 nS (i.e., 4.37 nS later at point 714). Therefore, switching the input mode from high to low results in the low level output being reached after 3.28 nS using the method of the present invention rather than at 4.37 nS using conventional operation, which is still about 30% faster.

[0073] Fig.10 A block diagram showing one embodiment of the present method compared to a prior art circuit providing somewhat similar functionality but not using the method of the present invention. Fig.10 Simulations performed on a circuit of provide additional evidence of the speed improvements obtained by using the described method over the prior art.

[0074] Fig.10Each circuit 1002, 1004, and 1006 in includes a first amplifier U1 and a second amplifier U2, feedback components R1 and R2, and a capacitor C1. Amplifier U1 has a gain of, for example, -10,000, and those skilled in the art will appreciate that amplifier U1 will therefore operate as a high gain stage with a signal gain defined by feedback components R1 and R2 (i.e., gain -R1 / R2), while second amplifier U2 operates as a signal inverter such that the output of circuit 1002 is not inverted and the overall gain of circuit 1002 is R1 / R2. Capacitor C1 defines a finite bandwidth for the gain of each circuit so that the delay of each circuit can be accurately compared, which is otherwise not necessary for the function of circuits 1002, 1004, and 1006.

[0075] In this example, each circuit 1002, 1004, and 1006 is connected in a chain of 1000 such circuits, as indicated by the bracketed symbols 1002

[1000] , 1004

[1000] , and 1006

[1000] . In contrast, the wires to the left of R2 and to the right of U2 have a bus width of 1000 when emerging from each repeating instance of the circuit, and therefore are different in each repeating instance of the circuit.

[0076] The thousand elements on the bus to the left of R2 are made up of the following: first the input line In at the least significant bit (LSB) position, then elements 998 through 0 from the output bus Out of the previous circuit. This nomenclature results in the series connection of 1,000 instances of X1, as In enters element 0 of R2 and the signal appears on element 0 of bus Out. Element 0 of the bus is then connected to the next LSB, the first instance of the repeating circuit, whose output is in turn the first element of the output Out of the first instance of the circuit, which is connected to the second instance of the circuit, and so on. The desired result of all one thousand X1s being connected in series is achieved through this nomenclature and the use of the bus.

[0077] Using buses and iteration instances in this way allows for reasonable representation of complex circuits when (as in this description) it is assumed that each iteration instance may be different. It is this difference in iteration instances that allows for variations in circuits and the implementation of networks expressed in code similar to the methods commonly used in the field of AI development.

[0078] Fig.10 Circuit 1002 is an embodiment of the method of the present invention. As described above, the method of the present invention has a means for reducing the gain of the gain element; in circuit 1002, such means is shown as a switch S1 having a control port receiving a control signal C driven by control logic 1008 that determines the state of the control signal C.

[0079] If control signal C is active, switch S1 is closed, significantly reducing the gain because closing switch S1 shorts resistor R1, reducing R1 / R2 to nearly zero. Note that control signal C is common to and received by all 1000 instances of circuit 1002, as indicated by the fact that the wire from C to repeating element 1002 is not a bus but has a width of 1. If R1 equals R2, the nominal gain of circuit 1002 is 1.

[0080] Fig.10 Circuit 1006 is an example of a linear amplifier used for analog computing, which does not benefit from the present method because circuit 1006 does not include a means to reduce its gain. As with circuit 1002, if R1 is equal to R2, the nominal gain of circuit 1006 is 1.

[0081] Circuit 1004 is a logic gate model known in the art. In circuit 1004, the value of R1 is much higher than the value of R1 in circuits 1002 or 1006. Therefore, the gain of circuit 1004 from R2 input to U2 output is higher than circuits 1002 or 1006. However, the gain is limited by back-to-back diodes D1 and D2. The result is that circuit 1004 operates in a mode similar to a logic gate, that is, there is a high gain region near the nominal zero input point, but the output is limited to a limited range by some means (usually the power supply rail in the case of CMOS).

[0082] By individually connecting 1000 instances of each of circuits 1002, 1004, and 1006 in series, a test bench can be created to simultaneously compare three different approaches for signal processing.

[0083] In this example, all resistors R1 and R2 are set to values ​​of 10 kΩ, except for resistor R1 in circuit 1004, which is set to 100 kΩ. Therefore, the gain of circuit 1004 from R2 input to U2 output is nominally 10, rather than 1 as in the case of circuits 1002 and 1006.

[0084] Fig.11 and Fig.12 yes Fig.10 1002, 1004, and 1006. As a test, the input signal In of each series circuit 1002, 1004, and 1006 is initially set to -0.5V and switched to +0.5V at a time of 1nS. The signal C used as a control in circuit 1002 is initially set to 1V, keeping switch S1 closed and keeping circuit 1002 in a low gain, non-propagating state. At a time of 4nS (i.e., 3nS after the input change), signal C changes to 0V, opening switch S1 and increasing the gain in circuit 1002, thereby allowing the signal to propagate. The In and C signals are shown in Figure 10. Fig.11As shown in curve A.

[0085] Fig.11 Curve B shows the responses of various circuits. As shown in curve 1104, Fig.10 The serial digital logic circuit 1004 of FIG. 1 has switched at about 1.4 microseconds (μS). Curve 1106 shows that the Fig.10 The linear circuit 1006 of FIG. 1 has switched at about 1 μS. Thus, even without the benefit of the method of the present invention, a chain of linear amplifiers, each having the same gain bandwidth product as a logic gate, will respond faster than a series of logic gates. Note that in two of these circuits, the output must change from a low value due to the existence of the previous state.

[0086] Using this method Fig.10 Circuit 1002 shows the fastest response. Before the gain change at time 0 on the x-axis, circuits 1004 and 1006 were in the previous state, as shown by curves 1104 and 1106, respectively. However, circuit 1002 is in the zero state (like the next gate in the chain), but now there is no noise margin, only thermal variation. Once the input signal and gain change, all three circuits begin to respond. If the output signal of 100mV is an acceptable margin, as shown in Figure 1, Fig.11 As shown in curve 1102, the output of series circuit 1002 rises from a zero state to a level starting at approximately 800nS, which is again significantly faster than the other circuits 1004 or 1006 which reach this output level at approximately 1.4μS and 1.1μS respectively, and approaches its final value faster than circuits 1004 or 1006.

[0087] Another comparison between a series linear amplifier circuit 1002 that benefits from the present method and a series linear amplifier circuit 1006 that does not benefit from this method is shown in FIG. Fig.12 It is assumed here that the output cannot be presumed valid until the output reaches half its value, or approximately 220mV, as Fig.11 shown.

[0088] Fig.12 is a graph of the position in the chain of components in the series circuits 1002 and 1006 versus the percentage of digital delay. Curve 1202 shows the Fig.10 Curve 1206 shows the results of the series linear amplifier circuit 1006 without the benefit of the present method.

[0089] Fig.12 The X-axis is logarithmic and indicates where in the series circuit the delay comparison is made. The Y-axis is the position of the series circuit relative to Fig.10 The percentage of speed improvement of digital circuit 1004.

[0090] As observed in curve 1206, as the number of connected elements increases, the series circuit 1006 asymptotically approaches a 25% reduction in delay compared to the series logic gates. The series circuit 1002 using the present method shows a greater speed improvement up to about 500 circuits connected in series. In the typical case of using up to 20 layers in a neural network, the present method can increase the speed by about 28%.

[0091] Note that these results also greatly underestimate the advantages of analog computers over digital computers in certain applications, because complex calculations can be performed in analog computers with only a few equivalent gate delays. For example, an analog computer configured to solve the Fourier transform of a signal over 128 packets would require 8 layers of analog processing units. Fig.12 As shown, these 8 cells will operate approximately 70% of the time as 8 series logic gates.

[0092] However, almost nothing can be accomplished in a digital processor in 8 logic gate delays; in a digital computer, a Fourier transform may require thousands of gate delay equivalents. Thus, in certain types of applications, analog computations may be thousands of times faster than digital equivalents, and even faster by using the present method.

[0093] Fig.13 is a diagram of circuit 1300, Fig.13 Certain aspects of the method are shown, namely the increase in speed and control mechanisms that can be achieved when the noise margin is reduced.

[0094] Element U3 in circuit 1300 is a conventional inverter known in the art. R1 and R2 are ideal resistors, and the resistance of R1 can be adjusted in response to a voltage applied at port C, which is used as a control signal. Control logic 1302, which can be a detection of a timing circuit as above, determines what voltage is applied at port C. For the sake of argument, R1 can be a macromodel, i.e., a code model of an electrical device. An example of a code model describing R1 is:

[0095] AR1 AB i=V(A,B) / (10k+V(C)*40k)(Equation 1)

[0096] This indicates that adjustable resistor 1 has a current flowing between terminals A and B of R1, which varies based on the voltage V(C) applied at port C, corresponding to a resistance of 10 kilo-ohms when V(C) is 0 volts, 50 kilo-ohms when V(C) is 1 volt, 540 kilo-ohms when V(C) is 10 volts, and so on (the choice of the 40 kilo-ohm value in equation 1 is arbitrary). Therefore, when a control signal of up to 1 volt can be provided, R1 can be adjusted between 10 kilo-ohms and 50 kilo-ohms. In this case, an appropriate value for R2 is 10 kilo-ohms.

[0097] Circuit 1300 also includes buffers U1 and U2, which do not change the voltage applied to them but are used to reduce the voltage gain of inverter U3. Buffer U1 prevents the current flowing through R1 from forming a load on the output of inverter U3, and buffer U2 prevents any component driving the input port from being loaded by resistor R2. It is assumed that the input node of inverter U3 is high impedance and is therefore not affected by the presence of resistors R1 and R2 on the input node.

[0098] As is known in the art, the gain of circuit 1300 is limited by the feedback loop and has the highest gain of R1 / R2. Therefore, in the limit that V(C) tends to infinity, circuit 1300 looks like a conventional inverter of the prior art. The input signal of inverter U3 arrives through input port X, buffer U2 and resistor R2. The output signal appears on port Y, and since V(C) is assumed to be a high voltage, R1 has a high impedance and has no effect on the input signal arriving via R2. In addition, the presence of R1 has no effect on the output of inverter U3 because buffer U1 removes the resistive load.

[0099] Even a relatively high voltage, V(C), does not significantly limit the gain of the inverter. For example, if V(C) is 10 volts, the value of R1 is 540 kilo-ohms. Since the value of R2 is 10 kilo-ohms, the gain of inverter U3 is again limited by resistors R1 and R2 to R1 / R2, or 54; however, this is typically higher than the inherent gain or "self-gain" of inverter U3. Therefore, the signal passing from input port X to output port Y is unaffected and is not affected by any of the variable gain aspects of the present method.

[0100] However, as the control signal voltage V(C) decreases, the inverter gain begins to be limited. As mentioned above, when V(C) is 1 volt, the value of R1 is actually 50 kilo-ohms, so R1 / R2=5, and the inverter gain is limited to 5. Fig.13 The circuit 1300 can therefore be used as a "test bench" that can apply varying values ​​of V(C) and thus various different gains to the inverter U3.

[0101] Fig.14 The results show that the control signal V(C) is transmitted through 32 Fig.13 A graph of the results of a series connection example of circuit 1300 sending a logic signal from a low level (zero) to a high level (one). Fig.14 The rightmost curve 10 is for V(C)=IOv and corresponds to the known art where the inverter gain is essentially unlimited, without the benefit of the present method. The Y-axis shows the output of the series circuit.

[0102] Fig.14The x-axis of shows the time it takes for the series circuit to change its output from low to high, and is labeled to show that the delay of the series circuit 1300 operating as in the prior art is nominally zero. Fig.14 As can be seen from the other curves of , as the voltage V(C) decreases, the input signal can propagate faster through the series circuit.

[0103] This demonstrates one aspect of the present approach: the delay of a chain of events (whether it be a logic delay in this example or an analog signal through a chain of amplifiers) is affected by the gain that each element has. This is contrary to what one might expect from a person skilled in the art, who might expect delay to increase with decreasing gain rather than the decreasing delay seen here.

[0104] One possible conclusion from this effect is that if a certain signal-to-noise ratio is required, the signal amplitude must exceed the noise in the circuit by an amount that can be calculated. As the gain of each component decreases, the signal amplitude also decreases: this can be seen in Fig.14 As can be seen in FIG. 1 , where the highest and lowest levels of the waveform change as the gain is reduced. In other words, the noise margin, i.e., the degree to which the signal exceeds the noise, is reduced. In certain configurations that are the subject of the present method, reducing the noise margin allows for higher speeds.

[0105] It may be argued that Fig.14 The results, while interesting and demonstrating the tradeoff between noise margin and speed, suggest that the approach is not practical. First, the gain reduction in the prior art inverter is achieved by limiting its output swing through feedback. As is well known, this significantly increases gate power dissipation (because the outputs of CMOS logic gates, if held at a voltage between the power supply rails, result in DC current flowing through both N-type metal oxide semiconductor ("NMOS") and P-type metal oxide semiconductor ("PMOS") devices).

[0106] Secondly, depending on the bit error rate (BER) requirement, a reduced noise margin, i.e., a reduction in the signal-to-noise ratio, will be considered unacceptable. For example, if one error per billion bits is required, the signal-to-noise ratio in the logic (or analog) circuit must be very high, which means that the noise margin must be relatively large. The noise margin required to meet the ideal very low BER will not result in a reduction in latency. Nevertheless, Fig.14 It is shown that this method can speed up the performance of a circuit by using a control signal (in this example, V(C)) that dynamically controls the circuit gain.

[0107] However, the noise margin does not have to remain at the final noise margin for the entire operating time. At the beginning of a computation interval (i.e., when the circuit first begins to compute a new result), the noise margin may be low and the delays short, as described above. As the computation interval unfolds, the noise margin rises so that at the end of the computation interval, the noise margin is large enough to support the required BER.

[0108] Certain internal calculations required to calculate the final output (e.g., changes in electrical parameters such as voltages on logic gates, outputs of operational amplifiers, or similar items in analog computers) evolve in the first part of the calculation interval when the noise margin is low, and therefore benefit from the reduced delay. Due to the fact that some of these calculations occur during low noise margins (the higher speed environment of the first part of the calculation interval), the overall time to reach the desired bit error rate is reduced. This is another benefit of the present method.

[0109] Likewise, those skilled in the art will recognize that many means of reducing noise margin (e.g., reducing the supply voltage of a CMOS logic circuit or an operational amplifier) ​​do not result in an increase in speed. However, as described above, the present method is one case where a reduced noise margin does result in an increase in speed, such as Fig.14 Of course, for Fig.13 For the circuit 1300, there are still some issues to consider.

[0110] As mentioned above, the first problem is that a certain noise margin is required to meet a given BER; also as mentioned above, the noise margin is variable within the calculation interval, and the required noise margin is reached before the end of the interval. The second problem is Fig.13 The circuit 1300 consumes significantly more power in the low noise margin, high speed state. Therefore, Fig.13 The speed-power product of circuit 1300 may not be as good as a circuit that does not benefit from the present approach.

[0111] There are many techniques known in the art for speeding up computers; for example, by pushing the process to sub-10 nanometer dimensions, or by paralleling (increasing the width) CMOS devices, the gate size can be changed to provide more current during transition. It is well known that these all lead to a certain speed-power product: at this point in the technology roadmap, the speed-power product has a specific value. The current approach, if it reduces noise margins and increases speed at the expense of consuming more power, may be a less useful innovation. However, the present approach can also improve the speed-power product.

[0112] The embodiments of the method now described alleviate Fig.13Specifically, the embodiment exploits the observation that a computing device, whether a chain of asynchronous logic gates (e.g., a known set of a few gates forming a seven-segment decoder, or a very large number of gates forming a digital multiplier) or a set of interconnected analog computing elements (e.g., operational amplifiers configured to solve differential equations) has a finite operating time and the accuracy (i.e., no significant BER) depends on the final result of the above-mentioned noise margin.

[0113] Note that in each example of this method, there is a Fig.13 There is at least one control signal for the signal V(C) at node C of the circuit 1300. The control signal will cause the noise margin to change during the computation interval of the system benefiting from the present method.

[0114] Fig.15 is a circuit diagram of one embodiment of a differential circuit 1500 using the present method that can be used in an analog computer.

[0115] Similar to Figure 1 In the differential circuit 100, in the circuit 1500, the differential amplifier is composed of transistors M6 and M11 receiving a non-inverting input signal In and a transistor M6 receiving an inverting input signal "Inb" or "In-bar" (as is common in the art, Fig.15 An inverted output signal “Outb” (similarly shown as “Out” with a line over it) appears from the common drain connection of transistors M6 and M10, and a non-inverted output signal “Out” appears from the common drain of transistors M7 and M11.

[0116] These nodes Out and Outb are fed back to the transistors M2, M3, M4 and M5 and transistors M12, M13, M14 and M15 (the latter in Fig.15 The bias control device formed by the sub-circuit 1502 is equivalent to Figure 1 The current source I1 in the circuit 100 of FIG. 1 is not sensitive to the normal mode output voltage (ie, the voltage difference between Out and Outb), but is responsive to the common mode output voltage (the average of the voltages on Out and Outb).

[0117] It will be seen that, as shown here, transistors M10 to M15 are NMOSFETs, while transistors M2 to M7 are PMOSFETs and mirror images of transistors M10 to M15. The transistors in circuit 1500 operate with a source-drain voltage lower than the source-gate voltage, and the amplifier does not consume any current other than the current flowing through the input device. Therefore, circuit 1500 efficiently utilizes current when operating during a calculation interval, which is a small portion of time, as will be described below.

[0118] Circuit 1500 utilizes a control node K, which can disconnect transistors M2 to M15 from the power supply DVcc. When the voltage on node K is high, the PMOS device M1 is turned off and no current flows from the power supply. Node K is also connected to transistors M8 and M9, which are NMOS devices. Therefore, when the power supply is disconnected due to the signal on node K going high, the output terminal is short-circuited to the input terminal through transistors M8 and M9. This is done to prevent an unknown voltage from being output and becoming the input of the next series circuit.

[0119] Those skilled in the art will note that this connection of the node K to the turn-off device transistor M1 and the short-circuit device transistors M8 and M9 need not be as Fig.15 Two separate control lines can be used, one for the power-off and the other for the short-circuiting device; this will allow the timing of the two actions to be different, which may be advantageous in some circumstances. For example, separate control of the power-off and short-circuiting devices can reduce calculation errors due to device parameter mismatch (which may be nominally fixed or vary with source-drain current).

[0120] This is because the improved speed-power product of this embodiment is achieved by reducing the amplifier current to zero and using a virtual ground configuration when in the active state (i.e., during the computation interval). The virtual ground configuration discussed below does not create an ideal virtual ground because the mismatch in the threshold voltages may make it inaccurate. When the amplifier is powered up to the active state, this virtual ground error voltage can be stored on a capacitor (as described below) and achieved by first powering up the circuit and then removing the shorting device after a short delay. This is an example where separate control of the power-off device and the shorting device may be advantageous.

[0121] Those skilled in the art will appreciate that if the input common-mode voltage can be a fixed value (such as can be achieved by using capacitors surrounding circuit 1500 as shown below), the bias control device 1502 formed by transistors M12, M13, M14 and M15 can be omitted, and the sources of M10 and M11 can be directly connected to the ground terminal DGnd.

[0122] Fig.16 A circuit 1600 is shown in the simplest configuration of components of an analog computer utilizing the present method, wherein: Fig.15 The components of are used as amplifier U1. Those skilled in the art will recognize circuit 1600 as a virtual ground configuration, which is a configuration known in the art except for the specific implementation of amplifier U1.

[0123] As mentioned above Fig.15As discussed above with respect to circuit 1500 of FIG. 1 , when the control signal at node K is high, both the power-off device and the short-circuit device within amplifier U1 are active, so circuit 1600 is in a quiescent state. Capacitors C1 and C2 are short-circuited by the internal short-circuit device of amplifier U1. Switches S1 and S2 connect capacitors C2 and C4 to input signal nodes In and Inb. This state may persist as long as necessary; no computation is performed and no power is consumed.

[0124] When the control signal on node K goes low, the computation interval begins. At this point, the gain elements within amplifier U1 are energized and the shorting device is removed. (As discussed above, by using separate control of the shorting and deenergizing devices, the removal of the shorting device may be slightly delayed. In this case, there will be an interval in which the offset voltage of the amplifier is stored across capacitors C1 and C3. This is what is understood by those skilled in the art as "switched capacitor auto-zeroing.")

[0125] At the same time as powering amplifier U1, switches S1 and S2 now connect the left side of capacitors C2 and C4 to ground (this is Fig.16 , as is conventional in the art for a virtual ground configuration). Due to the time spent connected to the input signals In and Inb, capacitors C2 and C4 carry a charge. This charge is transferred to capacitors C1 and C3 and appears as an output voltage. When this voltage appears, the computation interval is complete, and the circuit can be returned to a quiescent state by driving the control signal on node K high again. Fig.16 Circuit 1600 is an example of one implementation of the present method, but circuit 1600 itself appears to accomplish something seemingly trivial, namely, circuit 1600 transmits the input voltage difference between In and Inb to output terminals Out and Outb during a calculation interval, possibly with a gain or attenuation determined by the ratio of the capacitors as is known in the art. However, the actions of circuit 1600 are still the basis for potentially more complex calculations.

[0126] Fig.17 The circuit 1700 shows how you can use Fig.16 Multiple instances of circuit 1600 are used to implement an analog computer capable of performing complex calculations while retaining the advantages of the present approach, namely, faster speed and reduced power consumption.

[0127] Circuit 1700 can be viewed as Fig.16 A two-dimensional array of multiple instances of circuit 1600. Fig.17 As shown, circuit 1700 has four such instances, as shown by the four amplifiers U1 to U4; again, each amplifier U1 to U4 includes Fig.15The four instances of circuit 1600 in circuit 1700 are arranged in a two-dimensional array having two rows and two columns, namely a first column having amplifiers U1 and U2 and a second column having amplifiers U3 and U4, a first row having amplifiers U1 and U3 and a second row having amplifiers U2 and U4. In a given configuration, the array may have any desired number of such instances of circuit 1500, and therefore any desired number of rows and columns.

[0128] Each amplifier U1 to U4 includes the above Fig.15 The circuit 1500 described in FIG. 17 is a shutdown and short-circuit device, and all receive the same control signal discussed above. However, for ease of representation, the node K receiving the control signal and the signal line providing the control signal to each amplifier U1 to U4 are not shown in the circuit 1700.

[0129] Connecting multiple instances of circuit 1600 in this manner allows for some changes in the implementation of each instance of circuit 1600. First, each amplifier in the first column, i.e., amplifiers U1 and U2, can receive different input signals. In addition, multiple inputs of a single amplifier can be used by adding capacitors between the multiple input terminals and the amplifier; thus, for example, in addition to Fig.16 In addition to the capacitors C2 and C4 shown, the additional capacitors C5 and C6 allow additional inputs to the amplifier U1 and, by selecting different values ​​for the capacitors, also allow these inputs to have different weights. The use of such additional capacitors can be applied to applications such as Fig.17 All amplifiers U1 to U4 are shown; however, although Fig.17 All amplifiers U1 to U4 are shown having the same number of inputs, but this is not required and in a given circuit each amplifier may have a different number of weighted inputs where appropriate.

[0130] In addition, if Fig.17 As shown, in the case where the inputs to the amplifiers in the second column come from the outputs of the amplifiers in the first column, switches S1 and S2 are not required in the second row because the positions of the switches connecting the first column amplifiers U1 and U2 to the input signals are also operated by the control signal K described above.

[0131] Those skilled in the art will appreciate that the arrangement of columns and rows described herein and shown in the figures is similar to the arrangement of neurons in layers in a neural network. Fig.17As with the first column in , the first layer of the neural network includes some number of switches that sample the input voltage, and subsequent layers are directly connected to the output of the previous layer. Because a given amplifier can have any number of inputs, the connections between layers can be arbitrarily complex. In addition, as with the differences in the values ​​of the capacitors in circuit 1700, the sum of the voltages entering each neuron in the neural network can be arbitrarily weighted.

[0132] Fig.17 Circuit 1700 is a simple circuit used to demonstrate how to use the present method to utilize Fig.15 Multiple amplifiers of the type shown in circuit 1500 are arranged in layers and connectivity for use in a neural network. In practice, a useful case for the present method may have 4000 or more such amplifiers in each column or layer, and up to 100 or more such layers. Connectivity between layers would be achieved by using capacitors of different values ​​to create the required signal weights.

[0133] When the global control signal goes low as described above, the charge on the capacitors connected to the inputs (e.g., capacitors C2, C4, C5, and C6 in circuit 1700) is pushed into the amplifiers of the first layer (e.g., amplifiers U1 and U2 of circuit 1700). This causes the output of the first layer to push charge into the second layer, which in turn pushes the output of the second layer into the third layer (if present). This is a transient state, i.e., a computational interval as described above.

[0134] In Fig.17 At a much more complex level, you will see that the computation interval is the time it takes for charge to flow from the input to the various nodes of the network. Fig.17 The circuit of and all such similar circuits can be viewed as "charge redistribution networks" that manipulate charge similar to the problem that the network is designed to solve. The amplifier only needs to remain active while the charge redistribution is occurring; once that activity subsides, the network output ( Fig.17 The voltage on the output signal lines Out1 and Out2) can be sampled as known in the art, and the control signal of the entire network can be returned to a high level, thereby shutting off the power as described above. Note that the output sampling can be completed by a second instance of a complex network using the present method. Therefore, many such complex networks can be cascaded, each of which can contain thousands of amplifier elements described in the present invention.

[0135] An example of a problem that can be solved by a network as described above is the Fast Fourier Transform (FFT). Simulations have shown that a network containing just under 800 amplifier elements (e.g. Fig.15A circuit with a circuit 1500 of the type shown in FIG. 1500 and associated capacitors of appropriate values ​​can compute an FFT in significantly less than 1 nS, which is many times faster than a digital computer and typically consumes one thousandth of the power of a digital equivalent. This improvement in speed and power is an effect of the present invention.

[0136] Those skilled in the art will note that the above description relates primarily to use in devices such as analog computers where each amplifier element is identical, so functionality is primarily created by using differently weighted elements around a set of identical elements described as amplifiers. However, the invention has other uses.

[0137] Fig.18 is a circuit diagram of a circuit 1800, in which, by defining which signal is considered to be an inverted signal, Fig.15 The amplifier can be turned into any type of two-input gate, so that AND, OR, NAND, or NOR gates can all be built using the same circuit.

[0138] Circuit 1800 adds transistors M16 through M21. The inputs can now be treated as logic signals, and the series / parallel arrangement of transistors M6, M16, M10, and M20 on one side and transistors M7, M19, M21, and M11 on the other side creates a two-input gate. This two-input gate can be replicated multiple times and then connected directly without capacitors to form a digital network as is known in the art. Thus, circuit 1800 is similar to Fig.13 Circuit 1300 in FIG. 1 will operate at a lower power than circuit 1300 because it operates faster than an equivalent digital network; however, unlike circuit 1300 , circuit 1800 will operate at a lower power, as circuit 1300 consumes more power than is achievable with known techniques.

[0139] Those skilled in the art may wonder whether the Fig.12 The speed increase resulting from the method shown is significant enough to justify the additional complexity and circuitry required to change the circuit gain as described above.

[0140] However, as above, in some embodiments, reducing the gain of the amplifier circuit also reduces power consumption (although this is Fig.10 This is not the case in the circuit 1002 because the current in the amplifier U1 is not reduced by short-circuiting the resistor R1 of the circuit 1002). Figure 6 In the discussion of , it is noted that operation using the present method in this case results in a reduction in power consumption of nearly 75%.

[0141] Consider also the application of the present method to the calculation of the Fourier transform of a signal. The required repetition rate of the Fourier transform may be, for example, one million calculations per second. However, each such calculation may only take 10nS or less to perform. Therefore, the gain element only needs to be active about 1% of the time, requiring higher power. In this case, the full benefit of the present method can be seen, because the operation is faster, often even faster than a few logic gates, and uses much lower power, because high power is only required during the actual calculation.

[0142] Fig.19 is a flow chart of a method 1900 of operating a simulation computer according to one embodiment of the method as described above.

[0143] At optional step 1902, the input is applied to a plurality of gain elements having variable gain, such as circuits 100 and 1002 above, which are placed in an appropriate circuit configuration of an analog computer to solve a predetermined, desired problem. For example, the gain elements may be such as Figure 1 2, with the addition of circuitry for reducing the current from current source I1, or circuit 1002 of FIG. 2. The gain element may be formed as Figure 6 The neural network shown, or may be placed in a different configuration to perform Fourier transforms or other operations. Step 1902 is considered optional because in the case where input is first applied to the analog computer, there will be no previous input.

[0144] At step 1904, when the previous output of the circuit (if any) exists, the gain of the gain element is reduced to a level low enough that the input signal cannot propagate through the circuit. As described above, this can be done in Figure 1 The circuit 100 reduces the current through the current source I1 or closes Fig.10 This is achieved by the switch S1 in the circuit 1002.

[0145] At step 1906, the input signal is changed to a new value or set of new values ​​while the gain of the gain element remains decreased.

[0146] Finally, at step 1908, the gain of the gain element is increased to a level high enough to allow the input signal to propagate through the circuit, thereby producing an output that is a solution to the problem represented by the analog computer. This can be done in contrast to the gain reduction in step 1904. Figure 1 The circuit 100 increases the current through the current source I1 or disconnects Fig.10 This is achieved by the switch S1 in the circuit 1002.

[0147] As described above, in some embodiments, the gain of the gain element may be increased simultaneously with the change in the input signal, rather than after the change in the input signal.

[0148] Compared with the prior art, according to the present method, an analog computer can be constructed from series gain elements with faster operation and lower power consumption. According to the teachings herein, those skilled in the art will understand that an analog computer can be constructed according to these principles.

[0149] The disclosed system and method have been described above with reference to several embodiments. Other embodiments will be apparent to those skilled in the art from this disclosure. Certain aspects of the described methods and devices may be easily implemented using configurations other than those described in the above embodiments or in combination with elements other than or different from the above elements.

[0150] For example, as is well known to those skilled in the art, various options will be apparent to those skilled in the art. In addition, the illustrations of transistors, other circuits and associated feedback loops, resistors, etc. are exemplary; those skilled in the art will be able to select the appropriate number of transistors and related components suitable for a particular application.

[0151] It is intended that the present disclosure cover these and other variations on the embodiments, the present disclosure being limited only by the following claims.

Claims

1. A method of operating an analog computer, the analog computer comprising a plurality of gain elements, the plurality of gain elements being configured to operate on a total input signal to provide a solution to a predetermined problem, the gain of each of the plurality of gain elements being variable between a level sufficient to propagate the signal input to the element and a level insufficient to propagate the signal input to the element, the method comprising: reducing a gain of each of the plurality of gain elements to a level insufficient to propagate the signal input to the gain element; changing the total input signal when the gain of the gain element is at the reduced level; as well as The gain of each of the plurality of gain elements is increased to a level sufficient to propagate the signal input to the gain element no earlier than a time when the input signal changes.

2. The method according to claim 1, wherein: The time to increase the gain of the gain element is after a change in the total input signal.

3. The method according to claim 1, wherein: The gain of the gain element is increased at a time that is simultaneous with the change in the total input signal.

4. A variable gain element for use in an analog computer, comprising: a first transistor and a second transistor, each transistor having a gate, a source, and a drain, the gate of the first transistor being configured to receive an input signal, and the gate of the second transistor being connected to a reference point; a first resistor connected to the drain of the first transistor and to one side of a voltage source and a second resistor connected to the drain of the second transistor and to the voltage source; a current source connected to sources of both the first transistor and the second transistor, the current source being configured to provide different levels of current in response to a control signal; an amplifier having an input connected to the drains of the first transistor and the second transistor and the reference point, and an output providing an output of the gain element; a control circuit configured to provide a control signal based on a preselected condition; switch; as well as control logic for placing the switch in a first position when the input signal changes and placing the switch in a second position when the output of the gain element changes, The current source is configured to provide current when the switch is in the first position and not provide current when the switch is in the second position.

5. The variable gain element according to claim 4, wherein: The first transistor and the second transistor are n-type metal oxide semiconductor field effect transistors.

6. A variable gain element for use in an analog computer, comprising: a first transistor and a second transistor, each transistor having a gate, a source, and a drain, the gate of the first transistor being configured to receive an input signal, and the gate of the second transistor being connected to a reference point; a first resistor connected to the drain of the first transistor and to one side of a voltage source and a second resistor connected to the drain of the second transistor and to the voltage source; a current source connected to sources of both the first transistor and the second transistor, the current source being configured to provide different levels of current in response to a control signal; an amplifier having an input terminal connected to the drains of the first transistor and the second transistor and the reference point, and an output terminal providing an output of the gain element; a control circuit configured to provide a control signal based on a preselected condition; switch; as well as Control logic is used to place the switch in the first position and the second position at preselected intervals.

7. A variable gain element for use in an analog computer, comprising: a first amplifier configured to receive a signal at a first end and produce an amplified signal at a second end; a first resistor element having a first end and a second end, the first end being configured to receive an input signal of the variable gain element, the second end being connected to the first end of the first amplifier; A second resistance element having a first end and a second end, the first end being connected to the first end of the first amplifier, and the second end being connected to the second end of the first amplifier; a switch having a first end, a second end, and a switch port, the first end being connected to the first end of the first amplifier, the second end being connected to the second end of the first amplifier, the switch port being configured to receive a control signal, the switch being in an open position or a closed position depending on the control signal; control logic configured to provide the control signal to open or close the switch based on a preselected condition; as well as a second amplifier configured to receive a signal at a first end and to generate an amplified signal at a second end, the first end of the second amplifier being connected to the second end of the first amplifier, and the second end of the second amplifier being configured to generate an output signal from the variable gain element, Therein, the preselected condition is to change the position of the switch when the input changes and when an output signal appears at the output port of the second amplifier.

8. A variable gain element for use in an analog computer, comprising: a first amplifier configured to receive a signal at a first end and produce an amplified signal at a second end; a first resistor element having a first end and a second end, the first end being configured to receive an input signal of the variable gain element, the second end being connected to the first end of the first amplifier; A second resistance element having a first end and a second end, the first end being connected to the first end of the first amplifier, and the second end being connected to the second end of the first amplifier; a switch having a first end, a second end, and a switch port, the first end being connected to the first end of the first amplifier, the second end being connected to the second end of the first amplifier, the switch port being configured to receive a control signal, the switch being in an open position or a closed position depending on the control signal; control logic configured to provide the control signal to open or close the switch based on a preselected condition; as well as a second amplifier configured to receive a signal at a first end and to generate an amplified signal at a second end, the first end of the second amplifier being connected to the second end of the first amplifier, and the second end of the second amplifier being configured to generate an output signal from the variable gain element, Wherein, the preselected condition is to change the position of the switch at a preselected interval.

9. An analog computer comprising: a plurality of gain elements configured to operate on the total input signal to provide a solution to the predetermined problem, the gain of each gain element being variable between a level sufficient to propagate the signal input to the element and a level insufficient to propagate the input signal; a gain control device configured to switch the gain of the gain element between a level sufficient to propagate the input signal and a level insufficient to propagate the input signal based on a control signal; as well as a logic device configured to generate a control signal so that the gain control device switches the gain of the gain element to a level insufficient to propagate the input signal before the total input signal changes, and switches the gain of the gain element to a level sufficient to propagate the input signal no earlier than the time when the input signal changes.

10. The simulation computer according to claim 9, wherein: The gain element comprises a transistor and the gain control means is a current source that reduces the current in the transistor below the point at which the transistor conducts current.

11. The simulation computer according to claim 9, wherein: The gain element includes a resistive feedback loop, and the gain control means is a switch that shorts the feedback resistor and reduces the gain of the gain element to approximately zero.

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