Analog computer chip

Abstract

The invention relates to the technical field of artificial intelligence, and discloses an analog computer chip. The analog computer chip comprises an input layer, N addition layers and an output layer; each addition layer comprises a plurality of adders; each input interface in the input layer is connected with each summator in the first addition layer through different arithmetic units; in the N addition layers, each summator in the upper addition layer is connected with each summator in the lower addition layer through different arithmetic units; each arithmetic unit has a transfer function corresponding to node parameters of the arithmetic unit; the plurality of adders in the Nth layer of adders are connected with the plurality of output interfaces in the output layer in a one-to-one correspondence manner; the arithmetic unit and the summator are formed by analog devices. In the scheme, the analog computer chip is used as an artificial intelligence chip, so that the size of the artificial intelligence chip can be reduced, the speed of the artificial intelligence chip is increased, and the power consumption of the artificial intelligence chip is reduced.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to an analog computer chip. Background Art

[0002] With the rise of artificial intelligence technology, artificial intelligence chips that can realize certain specific functions have received widespread attention and application.

[0003] However, artificial intelligence chips in the prior art are generally digital computer chips, which are usually composed of a graphics processor, a field programmable gate array, and other module circuits. However, since the computing units of the graphics processors in the prior art all use digital operations, a single computing unit requires tens of thousands to hundreds of thousands of transistors, so that a single graphics processor in the prior art usually has only a few thousand computing units. At this time, if tens of thousands or even hundreds of millions of data are to be calculated simultaneously, more graphics processors must be used for parallel processing. This results in the prior art using digital computer chips as artificial intelligence chips being larger in size, slower in speed, and having higher power consumption. Summary of the Invention

[0004] In view of this, the present application provides an analog computer chip to solve the problems of large size, slow speed and high power consumption of digital computer chips used as artificial intelligence chips. The technical solution is as follows.

[0005] In a first aspect, an analog computer chip is provided, comprising an input layer, N addition layers, and an output layer; The input layer includes multiple input interfaces; each addition layer includes multiple adders; each input interface in the input layer is connected to each adder in the first addition layer through a different operation unit; in the N addition layers, each adder in the previous addition layer is connected to each adder in the next addition layer through a different operation unit; each operation unit has a transfer function corresponding to its node parameter; Furthermore, the multiple adders in the Nth layer of adders are connected to the multiple output interfaces in the output layer in a one-to-one correspondence; and the arithmetic units and adders are both constructed using analog devices.

[0006] In a possible implementation, the operation unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a first operational amplifier; The input terminal of the operation unit is connected to the non-inverting input terminal of the first operational amplifier through the second resistor; the non-inverting input terminal of the first operational amplifier is grounded through the first resistor; The inverting input terminal of the first operational amplifier is connected to the first voltage terminal through a third resistor; the inverting input terminal of the first operational amplifier is also connected to the input terminal of the first operational amplifier through a fourth resistor; the output terminal of the first operational amplifier is connected to the output terminal of the operation unit.

[0007] In a possible implementation, the first resistor, the second resistor, the third resistor, and the fourth resistor are all adjustable resistors; or, the first resistor and the fourth resistor are adjustable resistors; or, the second resistor and the third resistor are adjustable resistors.

[0008] In a possible implementation, the resistance of the first resistor is equal to the resistance of the fourth resistor; and the resistance of the second resistor is equal to the resistance of the third resistor.

[0009] In a possible implementation, the transfer function of the operation unit is:

[0010] Wherein, x is the input value of the transfer function; y is the output value of the transfer function; W is the node parameter, , R3 is the resistance of the third resistor, R4 is the resistance of the fourth resistor, and A11 is the gain of the first operational amplifier.

[0011] In a possible implementation, the operation unit includes a fifth resistor, a sixth resistor, and a second operational amplifier; The non-inverting input terminal of the second operational amplifier is grounded through the fifth resistor; the non-inverting input terminal of the second operational amplifier is also connected to the first voltage terminal through the sixth resistor; the inverting input terminal of the second operational amplifier is connected to the input terminal of the operation unit; and the output terminal of the second operational amplifier is connected to the output terminal of the operation unit.

[0012] In a possible implementation, at least one of the fifth resistor and the sixth resistor is an adjustable resistor.

[0013] In a possible implementation, the transfer function of the operation unit is:

[0014] Wherein, x is the input value of the transfer function; y is the output value of the transfer function; B is the node parameter, , R5 is the resistance of the fifth resistor, R6 is the resistance of the sixth resistor, and A22 is the gain of the second operational amplifier.

[0015] In a second aspect, a regulating circuit is provided, wherein the regulating circuit is used to regulate the above-mentioned analog computer chip; The regulating circuit includes an input terminal, a digital-to-analog conversion module and a decoding module; The input end is used to receive model parameters and generate model parameter data from the model parameters through a digital-to-analog conversion module; the model parameter data is used to adjust the node parameters of the computing unit of the analog computer chip; The decoding module is used to receive a parameter address corresponding to a model parameter, and determine a calculation unit corresponding to the model parameter data according to the parameter address.

[0016] In a possible implementation, the decoding module includes a connection subcircuit, an execution subcircuit, and an address subcircuit; The address subcircuit is used to determine the operation unit to be adjusted according to the parameter address, and connect the operation unit to be adjusted with the execution subcircuit through the connection subcircuit; The execution subcircuit is used to adjust the node parameters of the to-be-adjusted operation unit according to the model parameter data.

[0017] In a possible implementation, the adjustment circuit is provided outside the analog computer chip to adjust the node parameters of each computing unit during the production process of the analog computer chip.

[0018] In a possible implementation, the adjustment circuit is disposed inside the analog computer chip so as to adjust the node parameters of each computing unit in the analog computer chip according to the model parameters when the model parameters are received.

[0019] In a third aspect, an operation unit is provided, which is arranged in the above-mentioned analog computer chip, and each adjustable resistor in the operation unit is a non-volatile storage unit; the node parameters of the operation unit are related to the storage data of the non-volatile storage unit.

[0020] In a fourth aspect, an application circuit is provided, comprising a front-end device, a back-end device, and the above-mentioned analog computer chip; The front-end device is used to generate analog electrical signals and transmit them to the analog computer chip; the analog computer chip is used to process the analog electrical signals and transmit them to the back-end device to realize corresponding functions.

[0021] The technical solution provided by this application may have the following beneficial effects: The present application provides an analog computer chip and its regulating circuit. The computing units of the analog computer chip are all composed of analog devices, so that a single computing unit of the analog computer chip only requires a very small number of analog devices to perform operations. Usually, a single computing unit only requires dozens or even a few transistors. Therefore, this single analog computer chip can perform calculations on tens of thousands or even hundreds of millions of data simultaneously. Therefore, when the analog computer chip is used as an artificial intelligence chip, the size of the artificial intelligence chip can be reduced, the speed of the artificial intelligence chip can be increased, and the power consumption of the artificial intelligence chip can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 The figure is a schematic structural diagram of an analog computer chip according to an exemplary embodiment.

[0024] Figure 2 A schematic diagram showing an application circuit of the analog computer chip in this application is shown.

[0025] Figure 3 A schematic diagram showing the circuit structure of the first arithmetic unit in an embodiment of the present application is shown.

[0026] Figure 4 A schematic diagram showing the circuit structure of the second operation unit in an embodiment of the present application is shown.

[0027] Figure 5 The diagram shows the regulating circuit and connection structure of the computing unit in this application.

[0028] Figure 6 A structural diagram of a decoding module in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0030] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.

[0031] Figure 1 FIG. 1 is a schematic diagram showing the structure of an analog computer chip according to an exemplary embodiment. Figure 1 As shown, the analog computer chip includes an input layer, N addition layers, and an output layer; The input layer includes multiple input interfaces; each addition layer includes multiple adders; each input interface in the input layer is connected to each adder in the first addition layer through a different operation unit; in the N addition layers, each adder in the previous addition layer is connected to each adder in the next addition layer through a different operation unit; each operation unit has a transfer function corresponding to its node parameter; Furthermore, the multiple adders in the Nth layer of adders are connected to the multiple output interfaces in the output layer in a one-to-one correspondence; the operation unit and the adder are both constructed by analog devices.

[0032] In an embodiment of the present application, the number of input interfaces, the number of first-layer adders, the number of second-layer adders, and even the number of n-layer adders may be the same or different. At the same time, the number of n-layer adders is the same as the number of output interfaces.

[0033] like Figure 1 As shown, the input layer includes several input interfaces (including in1, in2, in3...), and external data is input into the analog computer chip through these input interfaces; Afterwards, the external data inputted from each input interface is inputted into each adder of the first layer connected to each arithmetic unit through each arithmetic unit connected to each input interface (each adder of the first layer includes adder 11, adder 12, adder 13, etc.), wherein the adder Figure 1 The arrows in represent the various operation units; Then, the data obtained by the adders in the first layer are input into the adders in the second layer connected to the adders in the first layer (the adders in the second layer include adder 21, adder 22, adder 23, etc.) through the operation units connected to the output ends of the adders in the first layer. After the connection is made in this way, the final data obtained by the adders in the nth layer (the adders in the nth layer include adder n1, adder n2, adder n3, etc.) are connected to the output interfaces (including out1, out2, out3, etc.) of the output layer. That is, at this time, the output interfaces of the output layer output the final data obtained by the operation of the simulated computer chip.

[0034] Figure 2 A schematic diagram of an application circuit of the analog computer chip in the present application is shown, wherein the analog computer chip is connected to a front-end device and a back-end device, the front-end device is used to generate an analog electrical signal and transmit it to the analog computer chip; the analog computer chip is used to process the analog electrical signal and transmit it to the back-end device to realize the corresponding function.

[0035] For example, the front-end device can be a graphic input device such as a camera or a sound input device such as a recording system. The front-end device converts the graphic signal or sound signal into an analog electrical signal and directly inputs it into an analog computer chip. After rapid calculation, the analog computer chip outputs the calculated analog electrical signal to the back-end device. The back-end device can be a display device or a control device, etc. After the back-end device calculates and analyzes the analog electrical signal output by the analog computer chip, it obtains the output signal required by the application circuit (the required output signal includes but is not limited to specific display signals such as graphics and sounds, or abstract control signals such as "no" and "no").

[0036] Specifically, the embodiments of the present application can be based on Figure 2 The data signal input by the front-end device in the training process is used to train the artificial intelligence model using an external computer, wherein the connection structure of the artificial intelligence model is the same as Figure 1 The structure of the analog computer chip shown is the same, and an external computer is used to train the artificial intelligence model to obtain the parameters of each node in the model, and the parameters of each node correspond to the node parameters of the operation unit in the analog computer chip, and changing the node parameters of each operation unit will change the transfer function of each operation unit.

[0037] Therefore, after the external computer completes the training of the artificial intelligence model, the node parameters of the computing units in the analog computer chip can be modified accordingly according to the parameters of each node in the model. That is, the transfer function of each computing unit in the analog computer chip can be changed, so that the analog computer chip can achieve the same or similar functions as the artificial intelligence model.

[0038] Please refer to Figure 3 , which shows a schematic diagram of the circuit structure of the first arithmetic unit in the embodiment of the present application. Figure 3 As shown, the operation unit includes a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier A1; The input terminal of the operation unit is connected to the non-inverting input terminal of the first operational amplifier through the second resistor; the non-inverting input terminal of the first operational amplifier is grounded through the first resistor; The inverting input terminal of the first operational amplifier A1 is connected to the first voltage terminal through a third resistor; the inverting input terminal of the first operational amplifier A1 is also connected to the input terminal of the first operational amplifier through a fourth resistor; the output terminal of the first operational amplifier A1 is connected to the output terminal of the operation unit.

[0039] Optionally, the first resistor, the second resistor, the third resistor and the fourth resistor are all adjustable resistors; Alternatively, the first resistor and the fourth resistor are adjustable resistors; or, the second resistor and the third resistor are adjustable resistors.

[0040] Optionally, the resistance value R1 of the first resistor is equal to the resistance value R4 of the fourth resistor; and the resistance value R2 of the second resistor is equal to the resistance value R3 of the third resistor.

[0041] Assume that the voltage VIN at the input terminal of the operation unit is the independent variable x of the function, the voltage VOUT at the output terminal of the operation unit is the dependent variable y of the function, the first voltage terminal is connected to a fixed voltage VR, and the fixed voltage VR is the constant c of the function. Therefore, it can be seen that when the resistance value R1 of the first resistor is equal to the resistance value R4 of the fourth resistor, the resistance value R2 of the second resistor is equal to the resistance value R3 of the third resistor, and the gain of the first operational amplifier A1 is represented by A11, Figure 3 In the first arithmetic unit circuit structure shown , where VOUT is the output voltage of the operation unit; VIN is the input voltage of the operation unit; VR is the voltage of the first voltage terminal; A11 is the gain of the first operational amplifier A1; that is, at this time, After being expressed by W, w is the node parameter, and the transfer function is , at this time, x is the input value of the transfer function; y is the output value of the transfer function; .

[0042] Please refer to Figure 4 , which shows a schematic diagram of the second arithmetic unit circuit structure in the embodiment of the present application. Figure 4 As shown, the operation unit includes a fifth resistor, a sixth resistor and a second operational amplifier A2; The non-inverting input terminal of the second operational amplifier A2 is grounded through the fifth resistor; the non-inverting input terminal of the second operational amplifier A2 is also connected to the first voltage terminal through the sixth resistor; the inverting input terminal of the second operational amplifier A2 is connected to the input terminal of the operation unit; and the output terminal of the second operational amplifier A2 is connected to the output terminal of the operation unit.

[0043] Optionally, at least one of the fifth resistor and the sixth resistor is an adjustable resistor.

[0044] at this time, Figure 4In the second arithmetic unit circuit structure shown in FIG, , where VOUT is the output voltage of the operation unit; VIN is the input voltage of the operation unit; VR is the voltage of the first voltage terminal; R5 is the resistance value of the fifth resistor; R6 is the resistance value of the sixth resistor; A22 is the gain of the second operational amplifier A2.

[0045] At this time, After being expressed by B, B is the node parameter, and the transfer function is ; In this case, x is the input value of the transfer function; y is the output value of the transfer function; .

[0046] At the same time, since the first operation unit circuit structure and the second operation unit circuit structure are both composed of an operational amplifier, the output terminal voltage VOUT of the first operation unit circuit structure and the second operation unit circuit structure should be between the positive input power supply and the negative input power supply of the operational amplifier. Generally speaking, the positive input power supply of the operational amplifier is a conventional power supply such as 5V or 3.3V, and the negative input power supply is GND, that is, 0V. At this time, assuming that the positive input power supply is 5V, it can be further obtained that the accurate transfer function of the first operation unit circuit structure is: , the accurate transfer function of the second arithmetic unit circuit structure is ; It can be seen from this that a single computing unit of the analog computer chip in this application only requires a very small number of analog devices to perform operations.

[0047] Furthermore, the operation units involved in the embodiments of the present application are all circuit structures composed of analog devices. Specifically, the operational amplifiers (including the first operational amplifier A1 or the second operational amplifier A2) in the operation units can adopt operational amplifiers with non-infinite gain, and the gain of the operational amplifiers can be obtained by calculation or measurement.

[0048] Furthermore, an embodiment of the present application also provides a regulating circuit, which can be used to adjust the node parameters of the computing unit in the analog computer chip. Figure 5 The figure shows the regulation circuit of the computing unit in the present application and its connection structure. The regulation circuit includes an input terminal, a digital-to-analog conversion (DAC) module and a decoding module. The input terminal is used to receive model parameters and generate model parameter data from the model parameters through the digital-to-analog conversion module; the model parameter data is used to adjust the node parameters of the computing unit of the analog computer chip; The decoding module is used to receive a parameter address corresponding to a model parameter, and determine an operation unit corresponding to the model parameter data according to the parameter address.

[0049] Specifically, the parameter address is input into the decoding module through the input terminal, and the model parameter is input into the DAC module through the input terminal. After the decoding module finds each operation unit corresponding to the model parameter according to the parameter address, it adjusts the corresponding node parameters in each operation unit according to the analog signal (i.e., model parameter data) output by the DAC module; Input the parameter address at the input end. You can use one of the following two methods: (1) The input parameter address includes the address data corresponding to the parameters of each node. The decoding module finds the position of the parameters of each node according to the address data corresponding to the parameters of each node, and then adjusts the node parameters of the operation unit corresponding to the position of the parameters of each node to the parameters of each node in the input model parameters; (2) Although the error rate of parameter adjustment in the first method is low, it will result in a large amount of input data. Therefore, the input parameter address can be designed as the address of the parameter of the first node in the input model parameters. At this time, after the decoding module adjusts the node parameters of the first operation unit according to the address, the decoding module directly adjusts the node parameters of the operation unit with the first address in the order after the address to the parameters of the second node in the order after the first node in the input model parameters, and so on, the adjustment is performed one by one until the adjustment of the node parameters of the operation unit with the last address is completed; From the above analysis, we can see that Figure 5 The input end needs to input the parameters of each node of the artificial intelligence model obtained by computer training and the address of the parameters of each node; At this time, the model parameters and parameter addresses in the artificial intelligence model obtained by computer training are all digital signals. The decoding module can directly receive digital signals. Therefore, the parameter address can be directly input into the decoding module. Since the computing units of the analog computer chip in this application are all composed of analog devices, it is necessary to use the DAC module to convert the model parameters of the digital signal into model parameter data of the analog signal. The converted analog signal is input into the decoding module. The decoding module adjusts the node parameters of each computing unit according to the parameter address and model parameter data, thereby obtaining the transfer function required by the artificial intelligence model, and finally generating the artificial intelligence model obtained by computer training in the analog computer chip; Therefore, at this time, in a possible implementation method, the adjustment circuit can be set inside the analog computer chip, so that when the model parameters are received, the node parameters of each operation unit in the analog computer chip are adjusted according to the model parameters. The parameters of the transfer function of the operation unit of the artificial intelligence model generated in the analog computer chip can be modified arbitrarily, thereby making the application field of the analog computer chip wider, but at the same time it will also cause the chip size to be larger.

[0050] In another possible implementation, the adjustment circuit may also be provided outside the analog computer chip to adjust the node parameters of each computing unit during the production process of the analog computer chip.

[0051] For example, during the wafer manufacturing process of the analog computer chip, the node parameters of each computing unit in the analog computer chip are directly adjusted to the required data through an external adjustment circuit. At this time, the node parameters of the computing unit are the parameters of the transfer function required by the artificial intelligence model. Since the analog computer chip does not require an integrated adjustment circuit, the analog computer chip is smaller in size. However, it also causes the artificial intelligence model generated in the analog computer chip to be unable to be modified, and the chip application field is single.

[0052] Please refer to Figure 6 , which shows a structural diagram of a decoding module in an embodiment of the present application.

[0053] like Figure 6 As shown, the decoding module includes a connection subcircuit, an execution subcircuit and an address subcircuit; The address subcircuit is used to determine the operation unit to be adjusted according to the parameter address, and connect the operation unit to be adjusted with the execution subcircuit through the connection subcircuit; The execution subcircuit is used to adjust the node parameters of the to-be-adjusted operation unit according to the model parameter data.

[0054] Figure 6 The working principle of the decoding module shown is as follows: The various operation units are arranged in a certain order in the address subcircuit. The address subcircuit finds the operation unit that needs to be adjusted according to the input parameter address. At this time, the address subcircuit connects the operation unit that needs to be adjusted to the execution subcircuit through the connection subcircuit. The execution subcircuit adjusts the node parameters in the operation unit according to the model parameter data output by the DAC module. In a possible implementation of the embodiment of the present application, each adjustable resistor in the operation unit is a non-volatile storage unit; and the node parameters of the operation unit are related to the storage data of the non-volatile storage unit.

[0055] At this time, by Figure 3 It can be seen that its transfer function is , so at this time, changing the value of W (i.e. node parameter) can adjust the transfer function. Therefore, changing Figure 3 The resistance of the first resistor and the fourth resistor in Figure 3 The resistance of the second resistor and the third resistor in Figure 3By adjusting the resistance values ​​of all resistors in the circuit, the transfer function can be adjusted. Therefore, non-volatile memory cells can be used as resistors. That is, the first, second, third, and fourth resistors are all formed using non-volatile memory cells. In this case, the resistance values ​​of the non-volatile memory cells can be changed by adjusting the stored data in the non-volatile memory cells (e.g., the floating gate charge of the MOS transistor of the non-volatile memory cell). Therefore, the two non-volatile memory cells forming the first and fourth resistors, or the two non-volatile memory cells forming the second and third resistors, are used as adjustment nodes corresponding to the node parameters and connected to the address sub-circuit. When the transfer function parameters corresponding to a certain operation unit need to be changed, the address sub-circuit finds the two non-volatile memory cells corresponding to the operation unit. The execution sub-circuit adjusts the stored data in the non-volatile memory cells based on the model parameter data output by the DAC module (e.g., charging and discharging the floating gates of the MOS transistors of the two non-volatile memory cells to change their resistance values). This adjusts the node parameters corresponding to the operation unit to obtain the transfer function required by the operation unit. Similarly, by Figure 4 It can be seen that its transfer function is , so at this time, changing the value of B (i.e. node parameter) can adjust the transfer function. Therefore, changing Figure 5 The resistance of the fifth resistor R5 in the Figure 5 The resistance of the sixth resistor R6 in the Figure 5 By adjusting the resistance values ​​of all resistors in the CMOS module, the transfer function can be adjusted. Therefore, in this case, non-volatile memory cells can be used as resistors. That is, both the fifth resistor and the sixth resistor are formed using non-volatile memory cells. In this case, by adjusting the stored data in the non-volatile memory cells (such as the floating gate charge of the MOS transistor of the non-volatile memory cells), the resistance value can be changed. Therefore, the non-volatile memory cells forming the fifth resistor or the sixth resistor can be connected to the address sub-circuit. When the parameters of the transfer function corresponding to a certain operation unit need to be changed, the address sub-circuit finds the non-volatile memory cell corresponding to the operation unit. The execution sub-circuit adjusts the stored data in the non-volatile memory cell based on the model parameter data output by the DAC module (such as charging and discharging the floating gate of the MOS transistor of the non-volatile memory cell to change its resistance value), thereby changing the node parameters corresponding to the operation unit to obtain the transfer function required by the operation unit.

[0056] In summary, the present application provides an analog computer chip and its regulating circuit. The computing units of the analog computer chip are all composed of analog devices, so that a single computing unit of the analog computer chip only requires a very small number of analog devices to perform calculations. Usually, a single computing unit only requires dozens or even a few transistors. Therefore, this single analog computer chip can perform calculations on tens of thousands or even hundreds of millions of data simultaneously. Therefore, at this time, when the analog computer chip is used as an artificial intelligence chip, the size of the artificial intelligence chip can be reduced, the speed of the artificial intelligence chip can be increased, and the power consumption of the artificial intelligence chip can be reduced.

[0057] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0058] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An analog computer chip, characterized in that: The analog computer chip includes an input layer, N addition layers and an output layer; The input layer includes a plurality of input interfaces; each addition layer includes a plurality of adders; each input interface in the input layer is connected to each adder in the first addition layer through different operation units; in the N addition layers, each adder in the previous addition layer is connected to each adder in the next addition layer through different operation units; each operation unit has a transfer function corresponding to its node parameter; And the multiple adders in the Nth layer of adders are connected to the multiple output interfaces in the output layer in a one-to-one correspondence; the operation units and adders are both composed of analog devices.

2. The analog computer chip according to claim 1, characterized in that: The operation unit includes a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier; The input end of the operation unit is connected to the non-inverting input end of the first operational amplifier through the second resistor; the non-inverting input end of the first operational amplifier is grounded through the first resistor; The inverting input terminal of the first operational amplifier is connected to the first voltage terminal through a third resistor; the inverting input terminal of the first operational amplifier is also connected to the input terminal of the first operational amplifier through a fourth resistor; the output terminal of the first operational amplifier is connected to the output terminal of the operation unit.

3. The analog computer chip according to claim 2, characterized in that: The first resistor, the second resistor, the third resistor and the fourth resistor are all adjustable resistors; or, the first resistor and the fourth resistor are adjustable resistors; or, the second resistor and the third resistor are adjustable resistors.

4. The analog computer chip according to claim 3, characterized in that: The resistance value of the first resistor is equal to the resistance value of the fourth resistor; the resistance value of the second resistor is equal to the resistance value of the third resistor.

5. The analog computer chip according to claim 4, characterized in that: The transfer function of the arithmetic unit is: Wherein, x is the input value of the transfer function; y is the output value of the transfer function; W is the node parameter, , R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, and A11 is the gain of the first operational amplifier.

6. The analog computer chip according to claim 1, characterized in that: The operation unit includes a fifth resistor, a sixth resistor and a second operational amplifier; The non-inverting input terminal of the second operational amplifier is grounded through the fifth resistor; the non-inverting input terminal of the second operational amplifier is also connected to the first voltage terminal through the sixth resistor; the inverting input terminal of the second operational amplifier is connected to the input terminal of the operation unit; and the output terminal of the second operational amplifier is connected to the output terminal of the operation unit.

7. The analog computer chip according to claim 6, characterized in that: At least one of the fifth resistor and the sixth resistor is an adjustable resistor.

8. The analog computer chip according to claim 7, characterized in that: The transfer function of the arithmetic unit is: Wherein, x is the input value of the transfer function; y is the output value of the transfer function; B is the node parameter, , R5 is the resistance value of the fifth resistor, R6 is the resistance value of the sixth resistor, and A22 is the gain of the second operational amplifier.

9. A regulating circuit, characterized in that: The regulating circuit is used to regulate the analog computer chip as claimed in any one of claims 1 to 8; The regulating circuit includes an input terminal, a digital-to-analog conversion module and a decoding module; The input end is used to receive model parameters, and generate model parameter data from the model parameters through a digital-to-analog conversion module; the model parameter data is used to adjust the node parameters of the computing unit of the analog computer chip; The decoding module is used to receive a parameter address corresponding to a model parameter, and determine a calculation unit corresponding to the model parameter data according to the parameter address.

10. The regulating circuit according to claim 9, characterized in that: The decoding module includes a connection subcircuit, an execution subcircuit and an address subcircuit; The address subcircuit is used to determine the to-be-adjusted operation unit according to the parameter address, and connect the to-be-adjusted operation unit with the execution subcircuit through the connection subcircuit; The execution subcircuit is used to adjust the node parameters of the to-be-adjusted operation unit according to the model parameter data.

11. The regulating circuit according to claim 9, characterized in that: The regulating circuit is arranged outside the analog computer chip to regulate the node parameters of each computing unit during the production process of the analog computer chip.

12. The regulating circuit according to claim 9, characterized in that: The regulating circuit is arranged inside the analog computer chip, so as to adjust the node parameters of each computing unit in the analog computer chip according to the model parameters when receiving the model parameters.

13. A computing unit, characterized in that: The operation unit is arranged in an analog computer chip as described in any one of claims 3-5 or 7-8, and each adjustable resistor in the operation unit is a non-volatile storage unit; the node parameters of the operation unit are related to the storage data of the non-volatile storage unit.

14. An application circuit, characterized in that: The application circuit comprises a front-end device, a back-end device and an analog computer chip as claimed in any one of claims 1 to 8; The front-end device is used to generate analog electrical signals and transmit them to the analog computer chip; the analog computer chip is used to process the analog electrical signals and transmit them to the back-end device to realize corresponding functions.

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