field effect transistor

Abstract

The present disclosure provides a field effect transistor. A field effect transistor includes a substrate, a source electrode and a drain electrode over the substrate and spaced apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has an end portion that contacts the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a field effect transistor including a channel formed of a two-dimensional (2D) material. BACKGROUND

[0002] A transistor is a semiconductor device that performs electrical switching and is used in various integrated circuit devices including memory, driver IC, and logic device. To increase integration of the integrated circuit device, the space occupied by the transistor provided in the integrated circuit device is greatly reduced. Accordingly, research has been conducted to reduce the size of the transistor while maintaining performance.

[0003] When the channel length is reduced as the size of the transistor is reduced, a short channel effect can occur. For example, problems can include threshold voltage variation, carrier velocity saturation, and subthreshold characteristic degradation. Accordingly, a method of limiting the short channel effect and effectively reducing the channel length has been sought. SUMMARY

[0004] A field effect transistor including a channel formed of a two-dimensional (2D) material is provided.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and / or can be learned by practice of the presented embodiments of the disclosure.

[0006] According to an example embodiment, a field effect transistor includes a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has two ends respectively contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

[0007] In some embodiments, each of the plurality of channel layers can include two edges extending in a third direction perpendicular to the first direction and the second direction. The two edges can respectively contact the source electrode and the drain electrode.

[0008] In some embodiments, each of the plurality of channel layers can include two contact regions respectively in planar contact with the source electrode and the drain electrode.

[0009] In some embodiments, the plurality of channel layers can include a first channel layer and a second channel layer having different lengths in the first direction.

[0010] In some embodiments, the first channel layer and the second channel layer can be arranged on the substrate in order of decreasing length in the first direction.

[0011] In some embodiments, the first channel layer and the second channel layer can have different thicknesses from each other.

[0012] In some embodiments, the first channel layer and the second channel layer can have different widths in a third direction perpendicular to each of the first direction and the second direction.

[0013] In some embodiments, the first channel layer and the second channel layer can be arranged on the substrate in an order of decreasing width in the third direction.

[0014] In some embodiments, the gate insulating film can contact the plurality of channel layers and have a shape that encloses each of the plurality of channel layers in a closed path having an axis in the first direction.

[0015] In some embodiments, the gate electrode can be spaced apart from the plurality of channel layers and have a shape that encloses each of the plurality of channel layers in another closed path having an axis in the first direction.

[0016] In some embodiments, the gate insulating film can have a shape that extends to an area between the gate electrode and the source electrode and an area between the gate electrode and the drain electrode.

[0017] In some embodiments, the 2D semiconductor material can include graphene, black phosphorus, phosphorene, and / or a transition metal chalcogenide.

[0018] In some embodiments, the transition metal chalcogenide can include a metal element and a chalcogen element. The metal element can include Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, Pb, or a combination thereof. The chalcogen element can include S, Se, Te, or a combination thereof.

[0019] In some embodiments, the 2D semiconductor material can be doped with a conductive dopant.

[0020] In some embodiments, the plurality of channel layers can include the same 2D semiconductor material.

[0021] In some embodiments, the gate insulating film can include a high-k dielectric material and / or a ferroelectric material.

[0022] In some embodiments, the plurality of channel layers can include a first channel layer and a second channel layer. A length of the first channel layer in the first direction can be different from a length of the second channel layer in the first direction, and a thickness of the first channel layer in the second direction is different from a thickness of the second channel layer in the second direction.

[0023] In some embodiments, at least one of the plurality of channel layers has a thickness in the second direction that is greater than 0 nm and less than or equal to about 5 nm.

[0024] In some embodiments, at least one of the plurality of channel layers has a thickness in the second direction that is greater than 0 nm and less than or equal to about 1 nm.

[0025] In some embodiments, at least one of the plurality of channel layers has a length in the first direction that is greater than 0 nm and less than or equal to about 3 nm.

[0026] According to an example embodiment, a field effect transistor includes a source electrode and a drain electrode spaced apart from each other in a first direction; a plurality of channel layers between the source electrode and the drain electrode; a gate insulating film surrounding each of the plurality of channel layers; and a gate electrode surrounding the gate insulating film. The plurality of channel layers can be spaced apart from each other in a second direction. The second direction intersects the first direction. The plurality of channel layers can include a 2D semiconductor material. The plurality of channel layers can each have a first end contacting the source electrode and a second end contacting the drain electrode.

[0027] In some embodiments, the plurality of channel layers can include a first channel layer and a second channel layer having different lengths in the first direction.

[0028] In some embodiments, the first channel layer and the second channel layer can have different thicknesses from each other.

[0029] In some embodiments, the 2D semiconductor material can include graphene, black phosphorus, phosphorene, and / or a transition metal dichalcogenide.

[0030] In some embodiments, at least one of the plurality of channel layers has a thickness in the second direction that is greater than 0 nm and less than or equal to about 5 nm. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other aspects, features, and effects of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the following drawings, in which:

[0032] Figure 1 is a perspective view of a schematic structure of a field effect transistor according to an embodiment;

[0033] Figure 2 is Figure 1 is a cross-sectional view of the field effect transistor of

[0034] Figure 3 is Figure 1 is a cross-sectional view of the field effect transistor of

[0035] Figure 4 It is a graph illustrating the concept that the minimum channel length due to the short-channel effect depends on the change in channel thickness;

[0036] Figures 5A-5E yes Figure 1 A schematic cross-sectional view of a method for manufacturing a field-effect transistor;

[0037] Figure 6 This is a schematic cross-sectional view of the structure of a field-effect transistor according to another embodiment;

[0038] Figure 7 This is viewed from another cross-section. Figure 6 A cross-sectional view of a field-effect transistor;

[0039] Figure 8 This is a schematic cross-sectional view of the structure of a field-effect transistor according to another embodiment;

[0040] Figure 9 This is a view from another cross-section. Figure 8 A cross-sectional view of a field-effect transistor;

[0041] Figure 10 This is a schematic cross-sectional view of the structure of a field-effect transistor according to another embodiment;

[0042] Figure 11 This is viewed from another cross-section. Figure 10 A cross-sectional view of a field-effect transistor;

[0043] Figure 12A and Figure 12B It is shown Figures 1-3 A cross-sectional view of a variant of a transistor;

[0044] Figure 13A and Figure 13B It is shown Figures 6-7 A cross-sectional view of a variant of a transistor;

[0045] Figure 14A and Figure 14B It is shown Figures 8-9 A cross-sectional view of a variant of the transistor; and

[0046] Figure 14C and Figure 14D It is shown Figures 8-9 A cross-sectional view of a variant of a transistor. Detailed Implementation

[0047] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding the list of one or more members, modify the entire list of members and do not modify the individual members of the list.

[0048] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding the list of one or more members, modify the entire list of members and do not modify the individual members of the list.

[0049] In the layer structure, when a constituent element is disposed "on" or "over" another constituent element, the constituent element can be directly on the other constituent element or over the other constituent element in a non-contact manner.

[0050] The terms such as "first" and "second" are used herein only to describe various constituent elements, but the constituent elements are not limited by these terms. Such terms are used only for the purpose of distinguishing one constituent element from another. The terms do not limit the materials or the structures of the constituent elements to be different from each other.

[0051] Expressions used herein in singular form also encompass their plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0052] In addition, the terms such as "part," "unit," "module," and "block" stated in the specification can represent a unit for processing at least one function or operation and can be embodied by hardware, software, or a combination of hardware and software.

[0053] When the terms "about" or "substantially" are used in the present description in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operational tolerances around the stated numerical value (e.g., ±10%). Moreover, when the words "typically" and "substantially" are used in connection with a geometric shape, it is intended that precision of the geometric shape is not required but rather a range of choices of the shape is within the scope of the present disclosure. Moreover, whether or not a numerical value or shape is modified by "about" or "substantially", it will be understood that these values and shapes should be interpreted to include manufacturing or operational tolerances around the numerical value or shape (e.g., ±10%).

[0054] The use of the terms "a" and "the" and "this" and similar referents in the context of describing the disclosure are to be interpreted as encompassing both the singular and the plural unless otherwise indicated herein.

[0055] Moreover, all of the steps of the methods described herein can be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by context. The present disclosure is not limited to the order of the steps described. Furthermore, the use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed.

[0056] Figure 1 is a perspective view of a schematic structure of a field effect transistor 100 according to an embodiment. Figure 2 is Figure 1 is a cross-sectional view of the field effect transistor 100 of Figure 3 is Figure 1 is a cross-sectional view of the field effect transistor 100 of

[0057] Referring to Figures 1-3 , the field effect transistor 100 can include a plurality of channel layers including a first channel layer 121 and a second channel layer 122 disposed on a substrate 110, a source electrode 180 and a drain electrode 190 contacting the first channel layer 121 and the second channel layer 122, and a gate electrode 160 disposed spaced apart from the first channel layer 121 and the second channel layer 122.

[0058] The substrate 110 can be an insulating substrate or a semiconductor substrate having an insulating layer formed on a surface thereof. The semiconductor substrate can include, for example, Si, Ge, SiGe, or a III-V semiconductor material. The substrate 110 can be, for example, a silicon substrate having a silicon oxide formed on a surface thereof, but the present disclosure is not limited thereto.

[0059] The source electrode 180 and the drain electrode 190 can be provided on the substrate 110 so as to be spaced apart from each other in a first direction, and the first channel layer 121 and the second channel layer 122 can be provided between the source electrode 180 and the drain electrode 190 so as to be spaced apart from each other in a second direction. The first direction can be an X direction, and the second direction can be a Z direction.

[0060] The gate insulating film 140 can be provided so as to surround each of the first channel layer 121 and the second channel layer 122. The gate electrode 160 can be provided so as to surround the gate insulating film 140.

[0061] As shown in FIG. 1A, the gate insulating film 140 can contact the first channel layer 121 and the second channel layer 122, and can have a shape that surrounds each of the first channel layer 121 and the second channel layer 122 in a closed path having an axis in the first direction (X direction). The gate electrode 160 can be spaced apart from the first channel layer 121 and the second channel layer 122 with the gate insulating film 140 between the gate electrode 160 and the first channel layer 121 and the second channel layer 122, and can have a shape that surrounds each of the first channel layer 121 and the second channel layer 122 in a closed path having an axis in the first direction (X direction). Figure 3 The gate insulating film 140 can insulate between the first channel layer 121 and the gate electrode 160 and between the second channel layer 122 and the gate electrode 160 as above, thereby limiting a leakage current. The gate insulating film 140 can also extend toward regions between the gate electrode 160 and the source electrode 180 and between the gate electrode 160 and the drain electrode 190, and can insulate between the gate electrode 160 and the source electrode 180 and between the gate electrode 160 and the drain electrode 190.

[0062] The contact between each of the first channel layer 121 and the second channel layer 122 and the source electrode 180 and the drain electrode 190 can have a fringe contact form. The fringe contact form can denote a state in which a side surface (or an edge portion) of a 2D semiconductor material (e.g., graphene) contacts a surface of the source electrode 180 and / or the drain electrode 190. In the fringe contact form, the side surface (or the edge) of the 2D semiconductor material (e.g., graphene) can directly contact the surface of the source electrode 180 and / or the drain electrode 190.

[0063] As shown in FIG. 1A, both ends of the first channel layer 121 are provided with edges extending in a third direction (Y direction), and the edges can contact the source electrode 180 and the drain electrode 190, respectively. The second channel layer 122 contacts the source electrode 180 and the drain electrode 190 in the same manner.

[0064] Figure 2 As shown in FIG. 1A, both ends of the first channel layer 121 are provided with edges extending in a third direction (Y direction), and the edges can contact the source electrode 180 and the drain electrode 190, respectively. The second channel layer 122 contacts the source electrode 180 and the drain electrode 190 in the same manner.

[0065] ​The field effect transistor 100 according to an embodiment can have a multi-bridge shape because both ends of each of the first and second channel layers 121 and 122 are in contact with the source and drain electrodes 180 and 190 and the first and second channel layers 121 and 122 are stacked apart from each other in a direction away from the substrate 110. The multi-bridge shape of the channel can reduce a short channel effect and also reduce an area occupied by the source / drain, which can be advantageous for high integration. Furthermore, because a source / drain junction capacitance can remain constant regardless of the position of the channel, a high-speed and highly reliable device can be obtained. Although the multi-bridge channel is shown as having two channel layers, this is merely an example, and the present disclosure is not limited thereto. The field effect transistor 100 according to an embodiment can include a plurality of channel layers, in which more than three channel layers are stacked.

[0066] The field effect transistor 100 according to an embodiment can employ a two-dimensional (2D) semiconductor material as a material of the first and second channel layers 121 and 122. The 2D semiconductor material can denote a semiconductor material having a 2D crystal structure and can have a single-layer or multi-layer structure. Each layer constituting the 2D semiconductor material can have an atomic level of thickness. The thickness of each of the first and second channel layers 121 and 122 can be about 10 nm or less. However, the present disclosure is not limited thereto, and the thickness of each of the first and second channel layers 121 and 122 can be further reduced in order to achieve a short channel length CL.

[0067] The field effect transistor 100 according to an embodiment can include a relatively short channel length CL because a 2D semiconductor material is used for the first and second channel layers 121 and 122. The channel length CL can denote a length of each of the first and second channel layers 121 and 122 between the source and drain electrodes 180 and 190, that is, a length in a first direction (X direction) as shown in FIG. 1A. The channel length CL is related to the thickness of each of the first and second channel layers 121 and 122, and the channel length CL can be set to a minimum length determined by the thickness of each of the first and second channel layers 121 and 122. The thickness can denote a thickness in a stacking direction, that is, a second direction (Z direction). Figure 2

[0068] The thickness of each of the first and second channel layers 121 and 122 can be 5 nm or less and greater than 0 nm. The thickness of each of the first and second channel layers 121 and 122 can be 1 nm or less. The channel length CL of each of the first and second channel layers 121 and 122 can be 3 nm or less.

[0069] ​2D semiconductor materials have excellent electrical properties and maintain high mobility without many changes in properties even when the thickness is reduced to the nanometer level, and thus can be applied to various devices.

[0070] The 2D semiconductor material can include at least one of, for example, graphene, black phosphorus, and a transition metal dichalcogenide (TMD). Graphene is a material having a hexagonal honeycomb structure because carbon atoms are two-dimensionally bonded and has advantages of having high electrical mobility and excellent thermal properties (compared to silicon (Si)), being chemically stable, and having a large surface area. Black phosphorus is a material in which black phosphorus atoms are two-dimensionally bonded.

[0071] The TMD can include, for example, one transition metal element of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re, and one chalcogen element of S, Se, and Te. The TMD can be represented by, for example, MX2, where M represents the transition metal element and X represents the chalcogen element. For example, M can include Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, etc., and X can include S, Se, Te, etc. Thus, for example, the TMD can include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, etc. Alternatively, the TMD can not be represented by MX2. In this case, for example, the TMD can include CuS, which is a compound of the transition metal element Cu and the chalcogen element S. The TMD can be a chalcogenide material including a non-transition metal element. The non-transition metal element can include, for example, Ga, In, Sn, Ge, Pb, etc. In this case, the TMD can include a compound of the non-transition metal element Ga, In, Sn, Ge, Pb, etc. and the chalcogenide element S, Se, Te, etc. For example, the TMD can include SnSe2, GaS, GaSe, GaTe, GeSe, In2Se3, InSnS2, etc.

[0072] As described above, the TMD can include one metal element of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and one chalcogen element of S, Se, and Te. However, the above-described materials are merely examples, and other different materials can be used as the TMD material.

[0073] The 2D semiconductor material can be doped with a p-type dopant or an n-type dopant to adjust the mobility. For example, a p-type dopant and an n-type dopant for graphene, carbon nanotubes (CNT), etc. can be used as the p-type dopant and the n-type dopant. The p-type dopant or the n-type dopant can be doped using an ion implantation method or a chemical doping method.

[0074] The first channel layer 121 and the second channel layer 122 can include the same 2D semiconductor material and have the same thickness. However, the present disclosure is not limited thereto, and the first channel layer 121 and the second channel layer 122 can include different types of 2D semiconductor material or can include different thicknesses from each other.

[0075] Each of the source electrode 180 and the drain electrode 190 can include a metal material having excellent electrical conductivity. For example, each of the source electrode 180 and the drain electrode 190 can include a metal such as magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), or the like, or an alloy thereof.

[0076] The gate electrode 160 can include a metal material or a conductive oxide. The metal material can include, for example, at least one selected from the group consisting of Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. The conductive oxide can include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like. The gate electrode 160 can include the same material as the source electrode 180 and the drain electrode 190.

[0077] The gate insulating film 140 can include a high-k dielectric material, which is a material having a high dielectric constant, for example, a dielectric constant higher than that of silicon dioxide. The gate insulating film 140 can include, for example, aluminum oxide, hafnium oxide, zirconium hafnium oxide, lanthanum oxide, or the like. However, the present disclosure is not limited thereto.

[0078] The gate insulating film 140 can include a ferroelectric material. The ferroelectric material has a spontaneous electric dipole because the charge distribution in a unit cell in a crystalline material structure is non-centrosymmetric, that is, a spontaneous polarization. Thus, the ferroelectric material has a remnant polarization caused by the dipole when there is no external electric field. In addition, the polarization direction caused by an external electric field can be switched in units of domains. The ferroelectric material can include, for example, an oxide of at least one selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr, but this is merely an example. In addition, the ferroelectric material can further include a dopant as needed.

[0079] When the gate insulating film 140 includes a ferroelectric material, the field effect transistor 100 can be applied to, for example, a logic device, a memory device, or the like. When the gate insulating film 140 includes a ferroelectric material, a subthreshold swing (SS) can be reduced by a negative capacitance effect, and thus, the performance of the field effect transistor 100 can be improved despite a reduction in the size thereof.

[0080] The gate insulating film 140 can have a multilayer structure including a high-k material and a ferroelectric material. Since the gate insulating film 140 includes a charge trapping layer such as silicon nitride or the like, the field effect transistor 100 can operate as a memory transistor having a storage property.

[0081] The field effect transistor 100 according to an embodiment can reduce a short channel effect by employing a 2D semiconductor material as a channel material, thereby realizing a short channel length.

[0082] The short channel effect can represent a phenomenon of a performance limitation that occurs when a channel length is reduced, that is, for example, a threshold voltage variation, a carrier velocity saturation, or a degradation of a subthreshold characteristic.

[0083] The short channel effect can be related to a channel thickness. Figure 4 is a graph illustrating a concept that a minimum channel length due to the short channel effect depends on a channel thickness variation. As illustrated in the graph, as the channel thickness is reduced, the minimum channel length that can be realized is reduced. Therefore, in order to realize an ultra-compact transistor to increase integration, the channel length can be effectively reduced by reducing the channel thickness.

[0084] When the channel thickness is reduced by using a typical bulk material such as a silicon-based material, the channel thickness is reduced to several nanometers or less, and thus the number of carriers in the silicon-based material is reduced, thereby reducing electron mobility. In contrast, in the field effect transistor 100 according to an embodiment, since each of the first channel layer 121 and the second channel layer 122 includes a 2D semiconductor material, even when the thickness of each of the first channel layer 121 and the second channel layer 122 is reduced to several nanometers or less, high electron mobility can be maintained. Therefore, the minimum channel length due to the short channel effect can be set to be short, and in addition, excellent performance can be obtained.

[0085] According to Figure 4 a graph in which a silicon material is used for a channel, the minimum channel length has a value greater than 10 nm. However, since the field effect transistor 100 according to an embodiment uses a 2D semiconductor material for the first channel layer 121 and the second channel layer 122, a relatively short channel length can be realized. For example, the channel thickness can be set to 1 nm or less, in which case the channel length can be reduced to about 3 nm.

[0086] Figures 5A-5E is a schematic cross-sectional view of a manufacturing method of the field effect transistor 100 according to Figure 1

[0087] Referring to Figure 5A ​First, the support layer 170 and the channel material layer 120 are repeatedly stacked on the substrate 110 a plurality of times. As shown in the drawing, the support layer 170 and the channel material layer 120 can be sequentially and alternately deposited a plurality of times.

[0088] The support layer 170 supporting the channel material layer 120 is a sacrificial layer which is removed after another structure for supporting the channel material layer 120 is formed. The support layer 170 supports the channel material layer 120, and in addition, the support layer 170 can include a material having a different etching rate from the channel material layer 120 so as to be selectively removed. The support layer 170 can be formed by, for example, a chemical vapor deposition (CVD) method.

[0089] The channel material layer 120 can include a 2D semiconductor material formed by a method such as a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, etc. The channel material layer 120 can have a single-layer or multi-layer structure including the 2D semiconductor material. The thickness of the channel material layer 120 can be 10 nm or less, 5 nm or less, or 1 nm or less. The thickness of the channel material layer 120 can be set in consideration of a channel length to be formed.

[0090] The channel material layer 120 can include a 2D semiconductor material doped with a specific conductive dopant. The 2D semiconductor material of the channel material layer 120 can be doped with a p-type dopant or an n-type dopant. For example, a p-type dopant and an n-type dopant for graphene, CNT, etc. can be used as the p-type dopant and the n-type dopant. The p-type dopant or the n-type dopant can be doped using an ion implantation method or a chemical doping method.

[0091] The source of the p-type dopant can include, for example, an ionic liquid such as NO2BF4, NOBF4, NO2SbF6, etc., an acidic compound such as HC1, H2PO4, CH3COOH, H2SO4, HNO3, etc., or an organic compound such as dichlorodicyanobenzoquinone (DDQ), oxone, dimyristoyl phosphatidylcholine (DMPI), trifluoromethanesulfonimide, etc. Alternatively, the source of the p-type dopant can include HPtCl4, AuCl3, HAuCl4, silver trifluoromethanesulfonate (AgOTf), AgNO3, H2PdCl6, Pd(OAc)2, Cu(CN)2, etc.

[0092] The source of the n-type dopant can include, for example, a reduction product of a substituted or unsubstituted nicotinamide; a reduction product of a compound chemically bound to a substituted or unsubstituted nicotinamide; and a compound including at least two pyridine groups in which a nitrogen atom of at least one of the pyridine groups is reduced. For example, the source of the n-type dopant can include nicotinamide mononucleotide-H (NMNH), nicotinamide adenine dinucleotide-H (NADH), nicotinamide adenine dinucleotide phosphate-H (NADPH), or a violet base. Alternatively, the source of the n-type dopant can include a polymer such as polyethyleneimine (PEI). Alternatively, the n-type dopant can include an alkali metal such as K, Li, and the like. The above-described p-type dopant material and n-type dopant material are examples, and various other materials can be used as dopants.

[0093] Thus, after forming a structure in which the support layers 170 and the channel material layers 120 are alternately stacked, the structure can be patterned by a photolithography process.

[0094] Referring to Figure 5B , a structure including the support layers 170, the first channel layer 121, the support layers 170, the second channel layer 122, and the support layers 170 can be formed by patterning using a photolithography process. Further, a source electrode 180 and a drain electrode 190 having a specific shape contacting the first channel layer 121 and the second channel layer 122 can be formed.

[0095] Next, the support layers 170 can be removed. To remove the support layers 170, an etching gas selectively etching only the support layers 170 can be used. An etching process is performed until the first channel layer 121 and the second channel layer 122 are exposed to a specific space H1, and as Figure 5C indicated, a structure in which the first channel layer 121 and the second channel layer 122 are supported in the form of a bridge between the source electrode 180 and the drain electrode 190 is formed.

[0096] Next, as Figure 5D indicated, a gate insulating film 140 surrounding each of the first channel layer 121 and the second channel layer 122 is formed. The gate insulating film 140 can be formed by depositing a specific insulating material on the surface of the first channel layer 121 and the surface of the second channel layer 122 using a method such as CVD, ALD, physical vapor deposition (PVD), or the like. The gate insulating film 140 can surround each of the first channel layer 121 and the second channel layer 122, for example, as Figure 3 indicated. Figure 5D

[0097] ​Furthermore, the gate insulating film 140 can extend onto the surfaces of the source electrode 180 and the drain electrode 190. The deposition process of the gate insulating film 140 can be performed such that a specific space H2 for forming the gate electrode is left.

[0098] Next, as Figure 5E As shown, a gate electrode 160 is formed by depositing electrode material in space H2. The gate electrode 160 may surround the gate insulating film 140, for example, as shown in the figure. Figure 3 (It is in relation to) Figure 5E (See the cross-sectional views in different directions).

[0099] about Figures 5A-5E The described manufacturing method is illustrative, and this disclosure is not limited thereto. (Used to form...) Figures 1-3 Other methods of the transistor structure shown can be used.

[0100] Figure 6 This is a schematic cross-sectional view of the structure of a field-effect transistor 101 according to another embodiment. Figure 7 This is viewed from another cross-section. Figure 6 A cross-sectional view of the field-effect transistor 101.

[0101] The field-effect transistor 101 may include a first channel layer 125 and a second channel layer 126 stacked vertically on a substrate 110 and spaced apart from each other, a source electrode 181 and a drain electrode 191 contacting the first channel layer 125 and the second channel layer 126, and a gate electrode 161 arranged spaced apart from the first channel layer 125 and the second channel layer 126.

[0102] A gate insulating film 141 is formed around each of the first channel layer 125 and the second channel layer 126. A gate electrode 161 is provided around the gate insulating film 141.

[0103] like Figure 7 As shown, the gate insulating film 141 may contact the first channel layer 125 and the second channel layer 126 and may have a shape that surrounds each of the first channel layer 125 and the second channel layer 126 in a closed path having an axis in a first direction (X direction). The gate electrode 161 may be spaced apart from each of the first channel layer 125 and the second channel layer 126 such that the gate insulating film 141 is between the gate electrode 161 and the first channel layer 125 and the second channel layer 126, and may have a shape that surrounds each of the first channel layer 125 and the second channel layer 126 in a closed path having an axis in the first direction (X direction).

[0104] The field-effect transistor 101 according to this embodiment differs from that of the one described above in terms of the shape in which the first channel layer 125 and the second channel layer 126 contact the source electrode 181 and the drain electrode 191.Figures 1-3 The field effect transistor 100 is described.

[0105] The first channel layer 125 can include two contact regions in planar contact with the source electrode 181 and the drain electrode 191, and the second channel layer 126 is in planar contact with the source electrode 181 and the drain electrode 191 in a similar manner.

[0106] The channel length CL is defined as a length of a region of the first channel layer 125 and the second channel layer 126 between the source electrode 181 and the drain electrode 191, as shown in the drawing. The channel length CL can be set to a minimum value defined by a thickness (that is, a thickness in the stacking direction (Z direction)) of each of the first channel layer 125 and the second channel layer 126. The thickness of each of the first channel layer 125 and the second channel layer 126 can be 10 nm or less, or 5 nm or less, or 1 nm or less. When the thickness of each of the first channel layer 125 and the second channel layer 126 is 1 nm or less, the channel length CL can be 3 nm or less.

[0107] Figure 8 is a schematic cross-sectional view of a structure of a field effect transistor 102 according to another embodiment. Figure 9 is a cross-sectional view of the field effect transistor 102 viewed from another cross section. Figure 8 of the field effect transistor 102.

[0108] The field effect transistor 102 can include a first channel layer 131, a second channel layer 132, and a third channel layer 133 vertically stacked on the substrate 110 to be spaced apart from each other, a source electrode 182 and a drain electrode 192 contacting the first channel layer 131, the second channel layer 132, and the third channel layer 133, and a gate electrode 162 arranged to be spaced apart from the first channel layer 131, the second channel layer 132, and the third channel layer 133.

[0109] The gate insulating film 142 can be provided to surround each of the first channel layer 131, the second channel layer 132, and the third channel layer 133. The gate electrode 162 can be provided to surround the gate insulating film 142.

[0110] As Figure 9As shown, the gate insulating film 142 can contact the first channel layer 131, the second channel layer 132, and the third channel layer 133 and can have a shape that surrounds each of the first channel layer 131, the second channel layer 132, and the third channel layer 133 in a closed path having an axis in the first direction (X direction). The gate electrode 162 can be spaced apart from each of the first channel layer 131, the second channel layer 132, and the third channel layer 133 with the gate insulating film 142 between the gate electrode 162 and the first channel layer 131, the second channel layer 132, and the third channel layer 133, and can have a shape that surrounds each of the first channel layer 131, the second channel layer 132, and the third channel layer 133 in a closed path having an axis in the first direction (X direction).

[0111] In the present embodiment, the first channel layer 131, the second channel layer 132, and the third channel layer 133 can have different channel lengths CL1, CL2, and CL3, respectively. The first channel layer 131, the second channel layer 132, and the third channel layer 133 can be arranged on the substrate 110 in order of decreasing channel length.

[0112] As described above, the channel length can be set to a minimum length that can be achieved depending on the thickness of the channel layer, and thus the first channel layer 131, the second channel layer 132, and the third channel layer 133 can have different thicknesses from each other. For example, the first channel layer 131 having the longest channel length CL1 can be the thickest, and then the thickness of the channel layer can be set in order of the second channel layer 132 and the third channel layer 133. The thickness of the third channel layer 133 having the shortest channel length CL3 can be, for example, 1 nm or less, and the channel length CL3 can be 3 nm or less. However, this is an example, and the thicknesses of the first channel layer 131, the second channel layer 132, and the third channel layer 133 can be the same as each other.

[0113] Although Figure 8 and Figure 9 Three channel layers are shown, but the present disclosure is not limited thereto, and the field effect transistor 102 can have a shape of a plurality of channel layers having two or more different channel lengths.

[0114] Figure 10 is a schematic cross-sectional view of a structure of a field effect transistor 103 according to another embodiment. Figure 11 is a cross-sectional view of the field effect transistor 103 viewed from another cross section. Figure 10 of the field effect transistor 103.

[0115] The field-effect transistor 103 can include: a first channel layer 135, a second channel layer 136, and a third channel layer 137, which are vertically stacked on the substrate 110 to be spaced apart from each other; a source electrode 183 and a drain electrode 193, which contact the first channel layer 135, the second channel layer 136, and the third channel layer 137; and a gate electrode 163, which is provided to be spaced apart from the first channel layer 135, the second channel layer 136, and the third channel layer 137.

[0116] The gate insulating film 143 can be provided to surround each of the first channel layer 135, the second channel layer 136, and the third channel layer 137. The gate electrode 163 can be provided to surround the gate insulating film 143.

[0117] The field-effect transistor 103 according to the present embodiment is similar to the field-effect transistor 102 described with respect to FIGS. 1A to 1C in that the first channel layer 135, the second channel layer 136, and the third channel layer 137 each have a channel length CL1, CL2, and CL3, but is different from the field-effect transistor 102 in that, as shown in FIG. 3B, widths in a third direction (Y direction) perpendicular to the channel length direction are different from each other. Figure 8 Figure 9 The field-effect transistor 103 according to the present embodiment is similar to the field-effect transistor 102 described with respect to FIGS. 1A to 1C in that the first channel layer 135, the second channel layer 136, and the third channel layer 137 each have a channel length CL1, CL2, and CL3, but is different from the field-effect transistor 102 in that, as shown in FIG. 3B, widths in a third direction (Y direction) perpendicular to the channel length direction are different from each other. Figure 11

[0118] The first channel layer 135, the second channel layer 136, and the third channel layer 137 can be arranged on the substrate 110 in order of decreasing width. Although Figure 11 each of the first channel layer 135, the second channel layer 136, and the third channel layer 137 is shown to have a width in the third direction that is shown to be different from each other, this is an example, and two or more channel layers can have widths that are different from each other.

[0119] Figure 12A and Figure 12B are cross-sectional views showing variations of the transistor of Figures 1-3

[0120] Referring to Figure 12A and Figure 12B , Figure 12A and Figure 12B , the transistor 100' in Figures 1-3 is similar to the transistor 100 in except that there are two channel layers 122a and 122b in the transistor 100' in place of the channel layer 122 in the transistor 100. The two channel layers 122a and 122b can be the same two-dimensional material to provide a thicker channel layer. Alternatively, the two channel layers 122a and 122b can include different two-dimensional materials. One or both of the two channel layers 122a and 122b can include a dopant.

[0121] Figure 13A and Figure 13B ​​​is a cross-sectional view illustrating a modification of the transistor of Figures 6-7

[0122] Figure 13A and Figure 13B The transistor 101' in Figures 6-7 is similar to the transistor 101 in except that two channel layers 126a and 126b are present in the transistor 101' instead of the single channel layer 126 in the transistor 101. The two channel layers 126a and 126b can be the same two-dimensional material to provide a thicker channel layer. Alternatively, the two channel layers 126a and 126b can include different two-dimensional materials from each other. One or both of the two channel layers 126a and 126b can include a dopant.

[0123] Figure 14A and Figure 14B is a cross-sectional view illustrating a modification of the transistor of Figures 8-9

[0124] Referring to Figure 14A and Figure 14B , Figure 14A and Figure 14B The transistor 102' in Figures 8-9 is similar to the transistor 102 in except that two channel layers 132a and 132b are present in the transistor 102' instead of the channel layer 132 in the transistor 102 and that three channel layers 131a, 131b, and 131c are present in the transistor 102' instead of the channel layer 131 in the transistor 102. The two channel layers 132a and 132b can be the same two-dimensional material to provide a thicker channel layer. Alternatively, the two channel layers 132a and 132b can include different two-dimensional materials from each other. One or both of the two channel layers 132a and 132b can include a dopant.

[0125] The three channel layers 131a, 131b, and 131c can be the same two-dimensional material to provide a thicker channel layer. Alternatively, two or three of the channel layers 131a, 131b, and 131c can include different two-dimensional materials from each other. At least one of the channel layers 131a, 131b, and 131c can include a dopant.

[0126] Although not illustrated, the transistor 102' in Figure 14A and Figure 14B may be further modified by making the width of the channel layer in the Y direction different. For example, similar to the transistor 103 in Figures 10-11 , Figure 14A and Figure 14BThe transistor 102' in the middle can be changed so that the width of the channel layers 132a and 132b in the Y direction is greater than the width of the channel layer 133 in the Y direction and less than the width of the channel layers 131a to 131c in the Y direction.

[0127] Figure 14C and Figure 14D It is shown Figures 8-9 A cross-sectional view of a variant of a transistor.

[0128] Reference Figure 14C and Figure 14D , Figure 14C and Figure 14D The transistor 102 in the middle is similar to Figures 8-9 The transistor 102 in the transistor 102” has two channel layers 132a and 132b in place of channel layer 132 in transistor 102”, and three channel layers 133a, 133b and 133c in place of channel layer 133 in transistor 102”. The two channel layers 132a and 132b can be the same two-dimensional material to provide a thicker channel layer. Alternatively, the two channel layers 132a and 132b can include two different two-dimensional materials. One or both of the two channel layers 132a and 132b can include a dopant.

[0129] The three channel layers 133a, 133b, and 133c can be the same two-dimensional material to provide a thicker channel layer. Alternatively, two or three of the channel layers 133a, 133b, and 133c can include different two-dimensional materials from each other. At least one of the channel layers 133a, 133b, and 133c can include a dopant.

[0130] Although not shown, Figure 14C and Figure 14D The transistor 102 in the middle can be further modified by making the width of the channel layer different in the Y direction. For example, similar to Figures 10-11 Transistor 103 in the middle, Figure 14C and Figure 14D The transistor 102 in the middle can be changed so that the width of the channel layers 132a and 132b in the Y direction is smaller than the width of the channel layer 131 in the Y direction and larger than the width of the channel layers 133a to 133c in the Y direction.

[0131] Because the field-effect transistors 100, 100', 101, 101', 102, 102', 102" and 103 described above exhibit excellent electrical performance and have an ultra-compact structure, they can be applied to integrated circuit devices and achieve miniaturization, low power and high performance.

[0132] The above-described field effect transistor can include a multi-bridge shaped channel and employ a 2D material as a channel material, thereby effectively reducing a channel length.

[0133] Since the above-described field effect transistor has an ultra-compact size and excellent electrical performance, the above-described field effect transistor can be suitable for an integrated circuit device having a high integration degree.

[0134] It should be understood that the implementations described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each implementation should typically be considered as being applicable in other implementations as well. While one or more implementations have been described with reference to the attached drawings, it will be apparent to those of ordinary skill in the art that various changes in form and detail can be made therein without departing from the spirit and scope as defined by the following claims.

[0135] This application claims the benefit of Korean Patent Application No. 10-2020-0033310, filed on March 18, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A field effect transistor comprising: a substrate; a source electrode and a drain electrode spaced apart from each other on the substrate in a first direction; a plurality of channel layers on the substrate, each of the plurality of channel layers having two ends respectively contacting the source electrode and the drain electrode, the plurality of channel layers being spaced apart from each other in a second direction away from the substrate, and the plurality of channel layers comprising a 2D semiconductor material; a gate insulating film surrounding each of the plurality of channel layers; and a gate electrode surrounding the gate insulating film, wherein the 2D semiconductor material comprises a transition metal chalcogenide, a thickness of at least one of the plurality of channel layers in the second direction is greater than 0 nm and less than or equal to 1 nm, a length of at least one of the plurality of channel layers in the first direction is greater than 0 nm and less than or equal to 3 nm, wherein the plurality of channel layers comprises a first channel layer and a second channel layer having different lengths in the first direction, the first channel layer and the second channel layer have different widths in a third direction perpendicular to each of the first direction and the second direction.

2. The field effect transistor of claim 1, wherein each of the plurality of channel layers comprises two edges extending in the third direction, the two edges respectively contacting the source electrode and the drain electrode.

3. The field effect transistor of claim 1, wherein each of the plurality of channel layers comprises two contact areas in plane contact with the source electrode and the drain electrode, respectively.

4. The field effect transistor of claim 1, wherein the first channel layer and the second channel layer are arranged on the substrate in an order of decreasing length in the first direction.

5. The field effect transistor of claim 1, wherein the first channel layer and the second channel layer have different thicknesses from each other.

6. The field effect transistor of claim 1, wherein the first channel layer and the second channel layer are arranged on the substrate in an order of decreasing width in the third direction.

7. The field effect transistor of claim 1, wherein the gate insulating film contacts the plurality of channel layers and has a shape surrounding each of the plurality of channel layers in a closed path having an axis in the first direction.

8. The field effect transistor of claim 7, wherein the gate electrode is spaced apart from the plurality of channel layers and has a shape surrounding each of the plurality of channel layers in another closed path having an axis in the first direction.

9. The field effect transistor of claim 7, wherein the gate insulating film has a shape extending to an area between the gate electrode and the source electrode and an area between the gate electrode and the drain electrode.

10. The field effect transistor of claim 1, wherein the transition metal chalcogenide comprises a metal element and a chalcogen element, the metal element comprises Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, Pb, or a combination thereof, and the chalcogen element comprises S, Se, Te, or a combination thereof. The chalcogen includes S, Se, Te, or a combination thereof.

11. The field-effect transistor of claim 1, wherein the 2D semiconductor material is doped with a conductive dopant.

12. The field-effect transistor of claim 1, wherein the plurality of channel layers comprise the same 2D semiconductor material.

13. The field-effect transistor of claim 1, wherein the gate insulating film comprises a high-k dielectric material and / or a ferroelectric material.

14. The field-effect transistor of claim 1, wherein wherein a length of the first channel layer in the first direction is set to a minimum length determined by a thickness of the first channel layer in the second direction.

15. A field-effect transistor, comprising: a source electrode and a drain electrode spaced apart from each other in a first direction; a plurality of channel layers between the source electrode and the drain electrode, the plurality of channel layers being spaced apart from each other in a second direction, the second direction intersecting the first direction, the plurality of channel layers comprising a 2D semiconductor material, each of the plurality of channel layers having a first end contacting the source electrode and a second end contacting the drain electrode; a gate insulating film surrounding each of the plurality of channel layers; and a gate electrode surrounding the gate insulating film, wherein the 2D semiconductor material comprises a transition metal chalcogenide, a thickness of at least one of the plurality of channel layers in the second direction is greater than 0 nm and less than or equal to 1 nm, a length of at least one of the plurality of channel layers in the first direction is greater than 0 nm and less than or equal to 3 nm, wherein the plurality of channel layers comprise a first channel layer and a second channel layer having different lengths in the first direction, the first channel layer and the second channel layer have different widths in a third direction perpendicular to each of the first direction and the second direction.

16. The field-effect transistor of claim 15, wherein the first channel layer and the second channel layer have different thicknesses from each other. ​

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