Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate; a dielectric layer located on the substrate; a first opening and a second opening located in the dielectric layer, the first opening being located at the top of the second opening, the angle between the sidewall surface of the first opening and the top surface of the dielectric layer being an obtuse angle; and a gate structure located in the first opening and the second opening. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the characteristic size of MOS transistors is getting smaller and smaller. In order to reduce the parasitic capacitance of the gate of the MOS transistor and improve the device speed, a gate stack structure of a high-K (dielectric constant greater than 3.9) gate dielectric layer and a metal gate is introduced into the MOS transistor. In order to avoid the influence of the metal material of the metal gate on other structures of the transistor, the gate stack structure of the metal gate and the high-K gate dielectric layer is usually manufactured using a "gate last" process.

[0003] However, the existing gate-last process still needs to be improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the existing gate-last process.

[0005] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a dielectric layer located on the substrate; a first opening and a second opening located in the dielectric layer, wherein the first opening is located at the top of the second opening, and the angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle; and a gate structure located in the first opening and the second opening.

[0006] Optionally, the substrate includes a base and a fin structure located on the base; and the gate structure spans across the fin structure.

[0007] Optionally, the depth of the second opening ranges from 100 angstroms to 200 angstroms.

[0008] Optionally, the obtuse angle ranges from 120° to 150°.

[0009] Optionally, it further includes: a side wall located on the side wall of the second opening, and the top of the side wall is located at the bottom of the first opening.

[0010] Optionally, the material of the sidewall spacer includes a dielectric material, and the dielectric material includes silicon nitride.

[0011] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0012] Optionally, the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

[0013] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a pseudo gate structure on the substrate; forming an initial sidewall on the sidewall of the pseudo gate structure; forming a dielectric layer on the substrate, the dielectric layer being located on the sidewall surface of the initial sidewall; removing part of the initial sidewall to form the sidewall, and forming an initial first opening located at the top of the sidewall in the dielectric layer, the initial first opening exposing part of the sidewall surface of the dielectric layer; removing part of the sidewall of the dielectric layer exposed by the initial first opening, forming a first opening in the dielectric layer, the angle between the sidewall surface of the first opening and the top surface of the dielectric layer being an obtuse angle; after forming the first opening, removing the pseudo gate structure to form a second opening connected to the first opening.

[0014] Optionally, the depth of the second opening ranges from 100 angstroms to 200 angstroms.

[0015] Optionally, the obtuse angle ranges from 120° to 150°.

[0016] Optionally, the substrate includes a base and a fin structure located on the base; and the gate structure spans across the fin structure.

[0017] Optionally, the process of removing a portion of the dielectric layer sidewall exposed by the initial first opening includes an isotropic dry etching process.

[0018] Optionally, the process of removing part of the initial sidewall spacer includes a free radical etching process.

[0019] Optionally, the free radical etching process includes a first step and a second step: the first step includes: using activated ions to perform an ion activation reaction with the initial side wall to generate a modified layer; the second step includes: using a free radical reaction to remove the modified layer.

[0020] Optionally, the ions of the ion activation reaction include hydrogen ions; the free radicals of the free radical reaction include free radicals containing a mixed gas of NF3, CH4, H2, Ar and He.

[0021] Optionally, the material of the initial spacer includes a dielectric material, and the dielectric material includes silicon nitride.

[0022] Optionally, the method for removing the dummy gate structure includes: removing part of the dummy gate structure to form a transition structure; and removing the transition structure until the substrate surface is exposed to form the second opening.

[0023] Optionally, the process of removing part of the dummy gate structure includes a dry etching process.

[0024] Optionally, the dry etching process includes a free radical plasma etching process.

[0025] Optionally, the process of removing the transition structure includes a dry etching process.

[0026] Optionally, the dry etching process includes a free radical plasma etching process.

[0027] Optionally, after forming the second opening, a gate structure is formed in the first opening and the second opening; the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] In the semiconductor structure of the technical solution of the present invention, the angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle, so that the top width of the first opening is greater than the top width of the second opening. Therefore, when a gate structure is formed in the second opening and the first opening, the material of the gate structure is easily filled to the bottom of the second opening, thereby being able to form a gate structure with a dense material structure, thereby improving the performance of the semiconductor structure.

[0030] In the method for forming a semiconductor structure of the technical solution of the present invention, a first opening is formed in a dielectric layer, and the angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle, so that the top width of the first opening is greater than the top width of the second opening. Therefore, when a gate structure is subsequently formed in the second opening and the first opening, the material of the gate structure is easily filled to the bottom of the second opening, and a gate structure with a dense material structure can be formed, thereby improving the performance of the semiconductor structure.

[0031] Furthermore, the process of removing part of the initial sidewall spacer includes a free radical etching process, which has a large etching selectivity ratio for the sidewall material silicon nitride, thereby being able to accurately remove part of the initial sidewall spacer while causing less damage to other structures of the device.

[0032] Furthermore, the process of removing the dummy gate structure includes a free radical plasma etching process, which has a large etching selectivity ratio for the material of the dummy gate structure, thereby being able to completely remove the dummy gate structure while causing less damage to other structures of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 to 8 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, the existing gate-last process needs to be improved.

[0035] Specifically, the gate-last process needs to first form a dummy gate structure, then form a dielectric layer, then remove the dummy gate structure to form a gate opening in the dielectric layer, and finally form a metal gate in the gate opening. With the further reduction of semiconductor technology nodes, the size of the gate structure is getting smaller and smaller, so the depth-to-width ratio of the gate opening is getting larger and larger. When forming a gate structure in the gate opening, a vapor deposition process is used to deposit the material of the gate structure in the gate opening. Since the depth-to-width ratio of the gate opening is relatively large, it is difficult for the reaction gas to reach the bottom of the gate opening and it is preferentially deposited at the top of the gate opening, so that the formed gate structure is loose and has voids, thereby affecting the performance of the formed semiconductor structure.

[0036] In order to solve the above problems, the technical solution of the present invention proposes a semiconductor structure and a method for forming a semiconductor structure, by forming a first opening in a dielectric layer, the angle between the side wall surface of the first opening and the top surface of the dielectric layer is an obtuse angle, and the first opening exposes the top of the second opening, so that the top width of the first opening is greater than the top width of the second opening, so that when a gate structure is subsequently formed in the second opening and the first opening, the material of the gate structure is easily filled to the bottom of the second opening, and a gate structure with a dense material structure can be formed, thereby improving the performance of the semiconductor structure.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 1 to 8 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in an embodiment of the present invention.

[0039] Please refer to Figure 1 , providing a substrate.

[0040] In this embodiment, the substrate includes: a base 100; a fin structure 101 located on the base 100; an isolation layer (not shown) located on the surface of the base 100 and the sidewall surfaces of several fin structures 101, and the top surface of the isolation layer is lower than the top surface of the fin structure 101.

[0041] In this embodiment, the material of the substrate 100 is single crystal silicon; the material of the fin structure 101 includes single crystal silicon.

[0042] In other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator; the fin structure may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator.

[0043] The material of the isolation layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. In this embodiment, the material of the isolation layer includes silicon oxide.

[0044] In other embodiments, the substrate is a planar substrate.

[0045] Please refer to Figure 2 , a dummy gate structure 102 is formed on the substrate, and the dummy gate structure crosses the fin structure 101.

[0046] The dummy gate structure 102 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) located on the dummy gate dielectric layer.

[0047] The method for forming the pseudo gate structure 102 includes: forming a pseudo gate dielectric material layer (not shown) on a substrate; forming a pseudo gate material layer (not shown) on the pseudo gate dielectric material layer; forming a patterned mask layer (not shown) on the pseudo gate material layer; and etching the pseudo gate material layer and the pseudo gate dielectric material layer using the patterned mask layer as a mask until the substrate surface is exposed to form the pseudo gate structure 102.

[0048] The material of the dummy gate dielectric layer includes silicon oxide or a low-K (K is less than 3.9) material; the material of the dummy gate layer includes polysilicon.

[0049] Please continue to refer to Figure 2 , an initial spacer 103 is formed on the sidewall of the dummy gate structure 102 .

[0050] The method for forming the initial sidewall spacer 103 includes: forming a sidewall material layer (not shown) on the substrate surface, the top surface and the sidewall surface of the dummy gate structure 102; etching back the sidewall material layer until the substrate surface is exposed, and forming an initial sidewall spacer 103 on the sidewall of the dummy gate structure 102.

[0051] The material of the initial spacer 103 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and silicon carbon nitride oxynitride.

[0052] In this embodiment, the material of the initial spacer 103 includes silicon nitride.

[0053] Please continue to refer to Figure 2 , a dielectric layer 104 is formed on the substrate, wherein the dielectric layer 104 is located on the sidewall surface of the initial spacer 103 , and the surface of the dielectric layer 104 exposes the top surface of the dummy gate structure 102 and the top surface of the initial spacer 103 .

[0054] The method for forming the dielectric layer 104 includes: forming a dielectric material layer (not shown) on the substrate, the top surface of the dummy gate structure 102 and the sidewalls of the initial spacer 103; and planarizing the dielectric material layer until the top surface of the dummy gate structure 102 is exposed to form the dielectric layer 104.

[0055] The material of the dielectric layer 104 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride and silicon carbon nitride. The process of forming the dielectric material layer includes a chemical vapor deposition process, a heat treatment process or an atomic layer deposition process.

[0056] In this embodiment, the material of the dielectric layer 104 includes silicon oxide; and the process of forming the dielectric material layer includes a chemical vapor deposition process.

[0057] Next, a portion of the initial spacer 103 is removed to form a spacer, and an initial first opening located at the top of the spacer is formed in the dielectric layer 104 , wherein the initial first opening exposes a portion of the sidewall surface of the dielectric layer 104 .

[0058] In this embodiment, the process of removing a portion of the initial spacer 103 includes a radical etching process.

[0059] The free radical etching process includes a first step and a second step. The first step includes: using activated ions to perform ion activation reaction with the initial sidewall 103 to generate a modified layer; the second step includes: using free radical reaction to remove the modified layer. For the specific process of the first step and the second step, please refer to Figure 3 and Figure 4 .

[0060] In other embodiments, the process of removing a portion of the initial spacer includes a combination of one or more of a dry etching process and a wet etching process.

[0061] Please refer to Figure 3 Activated ions are used to perform ion activation reaction with part of the initial sidewall 103 to generate a modified layer 105 .

[0062] The ions of the ion activation reaction include hydrogen ions.

[0063] The hydrogen ions react with silicon nitride to generate a modified layer 105 , and the modified layer 105 can be fully removed in a subsequent free radical reaction while causing little damage to other structures of the device.

[0064] Please refer to Figure 4 The modified layer 105 is removed by a free radical reaction to form a sidewall 106 , and an initial first opening 107 located at the top of the sidewall 106 is formed in the dielectric layer 104 , wherein the initial first opening 107 exposes a portion of the sidewall surface of the dielectric layer 104 .

[0065] The free radicals of the free radical reaction include free radicals containing NF3, CH4, H2, Ar and He mixed gas.

[0066] The free radical etching process has a large etching selectivity ratio for silicon nitride, which is the material of the initial spacer 103 , so that it can accurately remove a portion of the initial spacer 103 while causing little damage to other structures of the device.

[0067] Please refer to Figure 5 , remove part of the side wall of the dielectric layer 104 exposed by the initial first opening 107, and form a first opening 108 in the dielectric layer 104, wherein the top dimension of the first opening 108 is larger than the bottom dimension, and the angle between the side wall surface of the first opening 108 and the top surface of the dielectric layer 104 is an obtuse angle.

[0068] The process of removing a portion of the sidewall of the dielectric layer 104 exposed by the initial first opening 107 includes one or more combinations of an isotropic dry etching process and a wet etching process.

[0069] In this embodiment, the process of removing part of the side wall of the dielectric layer 104 exposed by the initial first opening 107 includes an isotropic dry etching process; the reaction gas of the isotropic dry etching process includes a mixed gas of CF4, CHF3, CH2F2 and O2, and the mixed gas has a large etching selectivity for the material of the dielectric layer 104, thereby being able to form the first opening 108 within the angle range with less damage to other structures of the device.

[0070] The obtuse angle ranges from 120° to 150°.

[0071] The sidewall surface of the first opening 108 within the angle range makes it easy for the material of the gate structure to be filled to the bottom of the second opening when the gate structure is subsequently formed in the second opening and the first opening 108, so that a gate structure with a dense material structure can be formed. If the angle is too small, i.e., less than 120°, the filling effect of the gate structure material cannot be greatly improved; if the angle is too large, i.e., greater than 150°, after the gate structure is subsequently formed, the size of the gate structure in the first opening 108 and the size in the second opening are greatly different, and the reliability of the semiconductor structure will be affected.

[0072] Next, after forming the first opening 108 , the dummy gate structure 102 is removed to form a second opening, wherein the first opening exposes the top of the second opening.

[0073] In this embodiment, a portion of the dummy gate structure 102 is first removed to form a transition structure; and then the transition structure is removed to form the second opening. For a detailed process of forming the second opening, please refer to Figure 6 and Figure 7 .

[0074] Please refer to Figure 6 , removing part of the dummy gate structure 102 to form a transition structure 109 .

[0075] The process of removing part of the dummy gate structure 102 includes a dry etching process, and the dry etching process includes a radical plasma etching process.

[0076] In this embodiment, the process of removing part of the dummy gate structure 102 includes a free radical plasma etching process. The free radicals of the free radical plasma etching process include: free radical plasma of a mixed gas containing NF3, H2, NH3 and Ar.

[0077] The radical plasma etching process has a large etching selectivity ratio for the material of the dummy gate structure 102 , so that the dummy gate structure 102 can be removed while causing little damage to other structures of the device.

[0078] Please refer to Figure 7 , removing the transition structure 109 until the substrate surface is exposed, thereby forming a second opening 110 .

[0079] The method of removing the transition structure 109 includes a combination of one or more of a wet etching process and a dry etching process.

[0080] In this embodiment, the process of removing the transition structure 109 includes a dry etching process, and the dry etching process includes a free radical plasma etching process.

[0081] The second opening 110 has a depth ranging from 100 angstroms to 200 angstroms.

[0082] The second opening 110 within the depth range avoids the situation where the depth of the second opening 110 is too small, i.e., less than 100 angstroms, so that when removing the dummy gate structure, the etching process will damage the fin structure 101; and also avoids the situation where the depth of the second opening 110 is too large, so that the dummy gate structure is difficult to remove.

[0083] In other embodiments, the dummy gate structure can be removed at one time to form the second opening.

[0084] In other embodiments, the process of removing the dummy gate structure includes a dry etching process, and the dry etching process includes a radical plasma etching process.

[0085] Please refer to Figure 8 , a gate structure 111 is formed in the first opening 108 and the second opening 110 .

[0086] The gate structure 111 includes a gate dielectric layer (not shown) and a gate layer (not labeled) located on the gate dielectric layer.

[0087] In this embodiment, the gate structure 111 further includes a work function layer (not shown) located on the gate dielectric layer, and the gate layer is located on the surface of the work function layer.

[0088] The method for forming the gate structure 111 includes: forming a gate dielectric material layer (not shown) on the surface of the dielectric layer 104, the inner wall surface of the first opening 108 and the inner wall surface of the second opening 110; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate material layer (not shown) on the surface of the work function material layer; planarizing the gate material layer, the work function material layer and the gate dielectric material layer until the surface of the dielectric layer 104 is exposed, and forming the gate structure 111 in the first opening 108 and the second opening 110.

[0089] The material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0090] The process for forming the gate dielectric material layer includes an atomic layer deposition process, a chemical vapor deposition process or a heat treatment process; the process for forming the work function material layer includes an atomic layer deposition process, a chemical vapor deposition process or a heat treatment process; the process for forming the gate material layer includes a physical vapor deposition process or an atomic layer deposition process.

[0091] In this embodiment, the process of forming the gate dielectric material layer includes an atomic layer deposition process; the process of forming the work function material layer includes an atomic layer deposition process; and the process of forming the gate material layer includes a physical vapor deposition process.

[0092] Since the top dimension of the first opening 108 is larger than the bottom dimension, and the angle between the sidewall surface of the first opening 108 and the top surface of the dielectric layer 104 is an obtuse angle, the top width of the first opening 108 is larger than the top width of the second opening 110. Therefore, when a gate structure 111 is subsequently formed in the second opening 110 and the first opening 108, the material of the gate structure 111 is easily filled to the bottom of the second opening 110, and a gate structure 111 with a dense material structure can be formed, thereby improving the performance of the semiconductor structure.

[0093] In other embodiments, the gate structure is located in the second opening.

[0094] The method for forming the gate structure includes: forming an initial gate structure in a first opening and a second opening; planarizing the dielectric layer, the first area of ​​the sidewall and the initial gate structure until the top surface of the second area of ​​the sidewall is exposed, and forming a gate structure in the second opening.

[0095] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please refer to Figure 8 ,include:

[0096] substrate;

[0097] A dielectric layer 104 located on the substrate;

[0098] A first opening (not shown) and a second opening (not shown) located in the dielectric layer 104, wherein the first opening is located at the top of the second opening, the top size of the first opening is larger than the bottom size, and the angle between the sidewall surface of the first opening and the top surface of the dielectric layer 104 is an obtuse angle;

[0099] The gate structure 111 is located in the first opening and the second opening.

[0100] In this embodiment, the substrate includes a base 100 and a fin structure 101 located on the base 100 ; the gate structure 111 spans across the fin structure 101 .

[0101] In this embodiment, the obtuse angle ranges from 120° to 150°.

[0102] In this embodiment, it further includes: a side wall 106 located on the side wall of the second opening, and the top of the side wall 106 is located at the bottom of the first opening.

[0103] In this embodiment, the material of the spacer 106 includes a dielectric material, and the dielectric material includes silicon nitride.

[0104] In this embodiment, the gate structure 111 includes a gate dielectric layer (not shown) and a gate layer (not labeled) located on the gate dielectric layer.

[0105] In this embodiment, the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

[0106] In the semiconductor structure, the top size of the first opening is larger than the bottom size, and the angle between the sidewall surface of the first opening and the top surface of the dielectric layer 104 is an obtuse angle, so that the top width of the first opening is larger than the top width of the second opening. Therefore, when the gate structure 111 is formed in the second opening and the first opening, the material of the gate structure 111 is easily filled to the bottom of the second opening, so that the gate structure 111 with a dense material structure can be formed, thereby improving the performance of the semiconductor structure.

[0107] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dummy gate structure on the substrate; forming an initial spacer on the sidewall of the dummy gate structure; forming a dielectric layer on the substrate, wherein the dielectric layer is located on the sidewall surface of the initial sidewall spacer; A portion of the initial sidewall is removed to form a sidewall, and an initial first opening is formed on the top of the sidewall, wherein the initial first opening exposes a portion of the sidewall surface of the dielectric layer, and the process of removing the portion of the initial sidewall includes a free radical etching process, wherein the free radical etching process includes a first step and a second step: the first step includes: using activated ions to perform an ion activation reaction with the initial sidewall to generate a modified layer; the second step includes: using a free radical reaction to remove the modified layer; Removing part of the dielectric layer sidewall exposed by the initial first opening to form a first opening in the dielectric layer, wherein the angle between the sidewall surface of the first opening and the top surface of the dielectric layer is an obtuse angle, and the angle between the top surface of the sidewall and the sidewall surface of the first opening is an obtuse angle; The dummy gate structure is removed to form a second opening connected to the first opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: The depth of the second opening is in the range of 100 angstroms to 200 angstroms.

3. The method for forming a semiconductor structure according to claim 1, wherein: The obtuse angle ranges from 120° to 150°.

4. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes a base and a fin structure located on the base; the gate structure spans across the fin structure.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing a portion of the dielectric layer sidewall exposed by the initial first opening includes an isotropic dry etching process.

6. The method for forming a semiconductor structure according to claim 1, wherein: The ions of the ion activation reaction include hydrogen ions; the free radicals of the free radical reaction include free radicals containing a mixed gas of NF3, CH4, H2, Ar and He.

7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the initial spacer includes a dielectric material, and the dielectric material includes silicon nitride.

8. The method for forming a semiconductor structure according to claim 1, wherein: The method for removing the dummy gate structure includes: removing part of the dummy gate structure to form a transition structure; removing the transition structure until the substrate surface is exposed to form the second opening.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process of removing part of the dummy gate structure includes a dry etching process.

10. The method for forming a semiconductor structure according to claim 9, wherein: The dry etching process includes a free radical plasma etching process.

11. The method for forming a semiconductor structure according to claim 8, wherein: The process of removing the transition structure includes a dry etching process.

12. The method for forming a semiconductor structure according to claim 11, wherein: The dry etching process includes a free radical plasma etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: After forming the second opening, a gate structure is formed in the first opening and the second opening; the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

14. A semiconductor structure formed by the forming method according to any one of claims 1 to 13, characterized in that: include: substrate; a dielectric layer disposed on the substrate; A first opening and a second opening are located in the dielectric layer, wherein the first opening is located at the top of the second opening, and an angle between a sidewall surface of the first opening and a top surface of the dielectric layer is an obtuse angle; A side wall located on the side wall of the second opening, the top of the side wall is located at the bottom of the first opening, and the angle between the top surface of the side wall and the side wall surface of the first opening is an obtuse angle; A gate structure is located in the first opening and in the second opening.

15. The semiconductor structure according to claim 14, wherein: The substrate includes a base and a fin structure located on the base; the gate structure spans across the fin structure.

16. The semiconductor structure according to claim 14, wherein: The depth of the second opening is in the range of 100 angstroms to 200 angstroms.

17. The semiconductor structure according to claim 14, wherein: The obtuse angle ranges from 120° to 150°.

18. The semiconductor structure according to claim 14, wherein: The material of the spacer includes a dielectric material, and the dielectric material includes silicon nitride.

19. The semiconductor structure according to claim 14, wherein: The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

20. The semiconductor structure according to claim 19, wherein: The material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

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