A lithium battery protection circuit

Abstract

The invention discloses a lithium battery protection circuit, which comprises a reference voltage generating circuit, a reference voltage generating circuit, a reference current generating circuit, an overcharge detection comparator, an over-discharge detection comparator, a charge over-current detection comparator, a discharge over-current detection comparator, a logic control circuit, an oscillator and counter circuit, a short-circuit protection detection circuit, a CS open-circuit protection circuit, an OD driving circuit, and an OC level conversion circuit. The invention can realize the protection of lithium batteries.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a lithium battery protection circuit. Background Art

[0002] Lithium-ion batteries (often referred to as lithium batteries) are secondary batteries (rechargeable batteries) that rely mainly on the movement of lithium ions between the positive and negative electrodes to work. Lithium-ion batteries have the advantages of high voltage, long cycle life, fast charging, and a wide operating temperature range. Therefore, rechargeable lithium-ion batteries are the most widely used batteries in modern digital products such as mobile phones and laptops. However, if lithium-ion batteries are overcharged, over-discharged, or discharged with overcurrent during use, they will cause irreversible damage to the lithium batteries and even cause serious safety accidents such as explosions and fires. Therefore, lithium-ion batteries must be used in conjunction with lithium battery protection boards during use. A typical lithium battery protection board circuit is as follows: Figure 1 As shown, it is composed of resistors, capacitors, power MOS tubes and lithium battery protection chips, among which the lithium battery protection chip is the core component of the protection board.

[0003] Figure 1 In the figure, MN1 and MN2 are power MOS tubes, which are turned on and off by the lithium battery protection chip and are used to open / cut off the charge and discharge circuit of the lithium battery. D1 and D2 are parasitic body diodes of the power MOS tubes MN1 and MN2. The voltage between the power pin VDD and the ground pin VSS of the lithium battery protection chip is the voltage of the lithium battery. After voltage division, the battery voltage is compared with multiple reference detection voltages. When the battery voltage is higher than the overcharge protection voltage and lasts longer than the overcharge protection delay, the chip controls the charging protection MOS tube MN2 to turn off, cutting off the charging circuit between the charger and the battery; similarly, when the voltage division value between VDD and VSS is less than the over-discharge detection voltage, the chip will control MN1 to turn off, cutting off the discharge circuit between the lithium battery and the load. When the lithium battery is discharging to the load, the discharge current forms a voltage drop on the internal resistance of MN1 and MN2, and the CS pin voltage polarity is positive (relative to the VSS pin). During the charging process, the charging current forms a negative voltage drop on MN1 and MN2, and the CS pin voltage polarity is negative. R1 and C1 form a low-pass filter circuit to filter out high-frequency interference on the chip VDD pin.

[0004] exist Figure 1 In the lithium battery protection chip, the reference voltage generation circuit inside the chip generates a reference voltage for the entire chip. The reference voltage circuit is used to generate a reference voltage for the comparator inside the chip. The oscillator and divider circuits are used to generate detection delays. OD and OC are the gate control pins of the discharge MOS and charge MOS tubes, respectively. Figure 1It can be seen that OD and OC are not directly driven by the logic control circuit. Since the power MOS tube has a large gate parasitic capacitance, a drive circuit needs to be inserted between the logic control circuit inside the chip and the OD / OC pins to provide sufficient drive capability to prevent the OD and OC from being turned off / on for too long. It is also important to note that in addition to the drive circuit, a level conversion circuit needs to be added between the logic control circuit and OC. This is because during the charging process of the lithium battery, CS is a negative voltage. When the lithium battery is overcharged or over-currented, in order to completely shut down the charging MOS tube MN2, that is, to make the V GS =0V, the output voltage of the OC pin must be equal to V CS Obviously, the low level output by the internal logic control circuit of the chip can only be VSS, so VSS to V must be added between the logic control circuit and OC. CS The level conversion circuit. Figure 1 It can also be seen that when the chip is overcharged or overcurrent protected, MN2 is turned off, and the voltage between the VDD and CS pins is equal to the charger open circuit voltage V CH , so V OC =V CS =VDD-V CH The open circuit voltage of mainstream chargers on the market currently ranges from 5V to 30V, while the overcharge protection voltage of lithium battery protection chips is generally around 3.6 to 4.5V. Therefore, the OC pin needs to be able to withstand a negative high voltage of around -25V. Therefore, the level conversion circuit of the OC pin needs to take into account the performance requirements of driving capability, level conversion, and negative high voltage resistance.

[0005] In the prior art, the driving circuit of the charging MOS tube mainly has the following two structures: 1. A structure of a level conversion circuit plus an output inverter using a thick gate oxide BCD process; 2. An output inverter structure using a large resistor as a pull-down device. As mentioned above, the first type of existing OC level conversion circuit is as follows Figure 2 As shown: cout is the control signal of the module, inverter INV1, high-voltage PMOS tubes PM1 and PM2, high-voltage NMOS tubes NM1 and NM2 constitute a level conversion circuit (level-shifter), high-voltage MOS tubes PM3 and NM3 constitute an output inverter, R1 is the current-limiting resistor of the OC pin, and constitutes an electrostatic discharge protection circuit (ESDProtector) with NM4.

[0006] Figure 2 In the example, cout is the control signal given by the internal logic control circuit of the chip. When the voltage and current of the lithium battery are normal, cout outputs a high level. At this time, PM1 is turned on and PM2 is turned off. The gate potential of NM2 is equal to VDD, so V GS,NM2 =VDD-VCS , because the voltage of the CS pin is close to VSS in normal working state, the NM2 tube is turned on, which makes the gate potential of the NM1 tube equal to V CS , then its V GS,NM1 = 0, so NM1 is completely turned off, and PM3's V GS =VDD-V CS , PM3 is turned on, OC outputs high level, and the charging MOS tube is turned on; when the battery is overcharged or overcurrent occurs, the logic control circuit flips the cout signal to a low level. At this time, PM2 is turned on, and NM1 is turned on, making the gate potential of NM2 equal to V CS , its V GS，NM2 =0, so NM2 is completely turned off, and PM2 is turned on, which makes NM3's V GS，NM3 =VDD-V CS , then NM3 is turned on, so the OC pin output voltage is equal to the CS pin voltage, thus completing the internal logic low level VSS of the chip to the OC pin low level V CS The level conversion function.

[0007] The second existing charging MOS pin driving circuit is as follows Figure 3 As shown: coutb and Figure 2 The cout in is a pair of inverted signals. PM1 and R1 form an output inverter structure. PM2 is an ESD protection tube with a GDPMOS (gate connected to power supply PMOS) structure, and resistor R2 is a current limiting resistor. Its working principle is: when the chip is working normally, coutb outputs a low level, at this time PM1 tube is turned on, and the voltage V OC =VDD*[R1 / (R1+R on,PM1 )],R on,PM1 is the on-resistance of PM1, which is much smaller than R1. Therefore, the output voltage of OC pin is approximately equal to VDD. The larger the resistance of R1, the smaller the difference between OC pin voltage and VDD. When overcharging and overcurrent occur, the logic control circuit controls coutb to flip to high level. At this time, PM1 is turned off, and the OC pin and CS pin are connected through resistor R1. After stabilization, the output voltage of OC pin is equal to the voltage of CS pin, thus completing the internal low level VSS of the chip to the low level V of OC pin. CS conversion.

[0008] The prior art has the following problems:

[0009] 1. In the common lithium battery protection chips on the market, the OC pin level conversion circuit has high process requirements and cannot balance performance and cost: As mentioned above, when the chip is overcharged and charged overcurrent protection occurs, the OC pin needs to output a negative level equal to the CS pin potential, so that the V GS = 0V, making it completely shut down. Figure 2 In the level conversion circuit shown in the figure, when the four tubes NM1-NM4 are protected, V GS Need to withstand the negative high voltage of VDD-VCS, which requires the chip to use thick gate process to increase V GS The thick gate process requires additional mask manufacturing and photolithography steps, which increases the production cost of the chip. Figure 3 The OC level conversion circuit shown in the figure avoids the use of thick gate oxide process. However, this solution has a fatal flaw. In order to prevent the static current passing through PM1 from being too large when the chip is working normally, the resistance of resistor R1 must reach the megohm level. This results in the OC pin being turned off when the protection is about to occur. Figure 1 The gate parasitic capacitance of the medium power MOS tube MN2 is Figure 3 R1 constitutes a time constant of millisecond level, so the discharge time of the gate voltage of MN2 from VDD to CS will reach millisecond level, which will seriously affect the reliability of charging overcurrent protection.

[0010] 2. In the lithium battery protection chips commonly found on the market, the reference voltage of the internal comparator of the chip is usually generated by a circuit structure of a bandgap reference plus a voltage regulator divider. Although the bandgap reference circuit has good temperature characteristics, the design of the bandgap reference circuit needs to be applied to operational amplifiers and bipolar transistors, and the voltage regulator divider circuit also needs to be applied to operational amplifiers. Both of them need to occupy a large layout area and generate considerable static current. The lithium battery protection chip is directly powered by the lithium battery. The static power consumption of the chip is an important performance indicator. The static power consumption of the internal circuit of the chip should be minimized during design.

[0011] 3. Currently, there is no special CS open circuit protection circuit designed in the common lithium battery protection chips on the market. The CS pin is used to detect the charging and discharging current of the lithium battery. A resistor RCS with a resistance of about 1k ohm needs to be added between the CS pin and the source of the charging MOS MN2 to limit the current passing through the CS pin. However, during the production and use of the lithium battery protection board, it is inevitable that RCS will be cold-soldered, leaked or damaged. When RCS fails, the CS pin will not be able to detect the source voltage of MN2. At this time, the overcurrent and short-circuit protection functions of the chip will be completely ineffective. Summary of the invention

[0012] Therefore, it is necessary to provide a lithium battery protection circuit to solve the lithium battery charging protection problem.

[0013] To achieve the above-mentioned purpose, the inventor provides a lithium battery protection circuit, including a reference voltage generating circuit, a reference voltage generating circuit, a reference current generating circuit, an overcharge detection comparator, an over-discharge detection comparator, a charging over-current detection comparator, a discharging over-current detection comparator, a logic control circuit, an oscillator and a counter circuit, a short-circuit protection detection circuit, a CS open-circuit protection circuit, an OD driving circuit, and an OC level conversion circuit. The input end of the reference voltage generating circuit is connected to the VDD end, the output end of the reference voltage generating circuit is connected to the reference voltage generating circuit and the reference current generating circuit respectively, the output end of the reference voltage generating circuit is connected to an input end of the overcharge detection comparator and an input end of the over-discharge detection comparator, and the overcharge detection comparator is connected to the over-discharge detection comparator. The other input end of the comparator is connected to a voltage divider circuit of VDD, the other input end of the over-discharge detection comparator is connected to another voltage divider circuit of VDD, the output end of the over-charge detection comparator is connected to the logic control circuit, the output end of the over-discharge detection comparator is connected to the logic control circuit, the oscillator and counter circuit are connected to the logic control circuit, the output end of the short-circuit protection detection circuit and the output end of the CS open-circuit protection circuit are connected to the logic control circuit, the input end of the short-circuit protection detection circuit and the input end of the CS open-circuit protection circuit are connected to the CS end, the logic control circuit is connected to the input end of the OD drive circuit and the input end of the OC level conversion circuit, the output end of the OD drive circuit is connected to the OD end, and the output end of the OC level conversion circuit is connected to the OC end.

[0014] Furthermore, the OC level conversion circuit includes a current mirror and an output inverter composed of a high-voltage PMOS tube PM3 and a high-voltage NMOS tube NM1. The current mirror is used to obtain a bias current according to the current of the reference current generating circuit. The bias current is connected to the source of the PMOS tube PM5. The gate of the PMOS tube PM5 is connected to the control signal cout of the logic control circuit. The source of the PMOS tube PM3 is connected to the VDD terminal. The gate of the PMOS tube PM3 is connected to the inverted control signal coutb. The drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM1. The gate of the NMOS tube NM1 is connected to the drain of the PMOS tube PM5 and one end of the resistor R1. The source of the NMOS tube NM1 is connected to one end of the resistor R2. The other end of the resistor R1 and the other end of the resistor R2 are connected to the CS terminal.

[0015] Furthermore, when the NMOS tube NM1 is turned on, V GS It is determined by the product of the current mirror current and the crossover resistance between the gate and source of the NMOS tube NM1, and the product is less than the power supply voltage VDD.

[0016] Furthermore, the reference voltage generating circuit adopts the principle of mutual compensation of the temperature coefficients of the threshold voltages of the depletion-mode MOS tube and the enhancement-mode MOS tube.

[0017] Furthermore, the reference voltage generating circuit performs resistor voltage division on the reference voltage VREF of the reference voltage generating circuit to generate a reference voltage required by the internal circuit of the chip.

[0018] Furthermore, the CS open circuit protection circuit includes a pull-up current source I1, a pull-up current source I2, a current switch MP1, an inverter INV1, and a NAND gate NAND1, wherein the output end of the inverter INV1 is connected to an input end of the NAND gate NAND1, the output end of the NAND gate NAND1 is connected to the gate of the current switch MP1, the source of the current switch MP1 is connected to the pull-up current source I1, the drain of the current switch MP1 is connected to one end of the resistor RVMD, the other end of the resistor RVMD is connected to the CS end, the pull-up current source I2 is connected to the drain of the current switch MN1, and the source of the current switch MN1 is connected to the CS end through the resistors R11 and R12.

[0019] Furthermore, in the CS open circuit protection circuit, when the CS pin is floating, the CS pin potential will be pulled up by the pull-up current source I2, so that the chip enters the short-circuit protection state, and then the pull-up current source I1 starts to charge the parasitic capacitance of the CS pin. When the CS pin is open, the CS pin voltage will be charged to above the short-circuit protection detection voltage before the discharge overcurrent protection state is released, and enter the short-circuit protection state again, so that the OD pin always outputs a low level; when the CS is not open, the CS cannot be charged to above the load short-circuit protection voltage before the discharge overcurrent protection is released, and will not enter the charging overcurrent protection state.

[0020] Furthermore, in the CS open circuit protection circuit, when the CS pin is open, the OD pin always outputs a low level, so that the discharge MOS tube is in a turned-off state, thereby cutting off the discharge path between the battery and the load circuit.

[0021] The present invention provides a lithium battery protection chip, wherein the lithium battery protection chip comprises the lithium battery protection circuit described in any one embodiment of the present invention.

[0022] Different from the prior art, the above technical solution has the following advantages:

[0023] (1) The lithium battery protection circuit and chip designed by the present invention adopt a new type of level conversion circuit. The level conversion circuit has no static power consumption under normal working conditions of the chip. When the chip is in overcharge protection or charging overcurrent protection, it can quickly pull down the OC pin potential to be equal to the CS pin potential, and completely shut down the charging MOS after a delay time of microseconds, and the overcharge protection and charging overcurrent protection are highly reliable.

[0024] (2) The lithium battery protection circuit and chip designed by the present invention adopt a new level conversion circuit. The level conversion circuit avoids the use of high V GS The voltage-resistant thick-gate oxide MOS tube reduces the process requirements for the design of lithium battery protection chips, has good process versatility, and at the same time reduces the photolithography costs of mask production and chip production, resulting in low chip manufacturing costs and good economy.

[0025] (3) The lithium battery protection circuit and chip designed by the present invention designs a new reference voltage generating circuit, which uses two types of devices, depletion-type and enhancement-type MOS devices, to generate reference voltage, without the need for operational amplifiers and bipolar transistors, thereby greatly saving chip area and power consumption.

[0026] (4) The lithium battery protection circuit and chip shown in the present invention are designed with a new reference voltage generation circuit, which can directly divide the reference voltage from the output end to generate multiple reference voltages inside the chip, without the need to additionally design a voltage regulator divider circuit, further saving chip area and power consumption.

[0027] (5) The lithium battery protection circuit and chip shown in the present invention are designed with a CS open circuit protection circuit. This circuit can make the OD pin of the chip always output a low level when the CS port resistor RCS and the chip pin are open, thereby cutting off the discharge circuit between the lithium battery and the load, and can effectively prevent lithium battery safety accidents caused by CS current detection failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A typical circuit of the lithium battery protection board described in the background technology;

[0029] Figure 2 The first charging MOS tube driving circuit described in the background technology;

[0030] Figure 3 The second charging MOS pin driving circuit described in the background technology;

[0031] Figure 4 This is a schematic diagram of a lithium battery protection chip circuit according to an embodiment of the present invention;

[0032] Figure 5 The OC level conversion circuit of the embodiment of the present invention;

[0033] Figure 6 A reference voltage generating circuit according to an embodiment of the present invention;

[0034] Figure 7 This is a CS open circuit detection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0036] See also Figures 4 to 7 This embodiment provides a lithium battery protection circuit, and its circuit schematic diagram is as follows Figure 4 As shown. The lithium battery protection circuit can not only be packaged as a lithium battery protection chip separately, but also can be used in a chip where the protection chip and the MOS tube are co-sealed, as well as a lithium battery protection chip without peripheral circuits. The lithium battery protection chip circuit includes: a reference voltage generation circuit, a reference voltage generation circuit, a reference current generation circuit, an overcharge detection comparator, an over-discharge detection comparator, a charge overcurrent detection comparator, a discharge overcurrent detection comparator, a logic control circuit, an oscillator & counter circuit, a short circuit protection / CS open circuit detection circuit, and an OC level conversion circuit. The basic working principle of the chip is:

[0037] When the chip detects that the lithium battery voltage is higher than the overcharge protection voltage, the overcharge detection comparator flips, and the oscillator & counter circuit starts working. When the flip duration of the overcharge detection comparator is greater than the overcharge protection delay time, the logic control circuit will turn off the MOS tube connected to the OC pin through the OC level conversion circuit to cut off the charging circuit; when the charging current of the lithium battery is too large, the chip will detect that the CS pin voltage is less than or equal to the charging overcurrent detection protection voltage, and the charging overcurrent comparator flips. When the flip duration is greater than the charging overcurrent protection delay time, the logic control circuit controls the OC level conversion circuit to turn off the OC pin MOS.

[0038] When the chip detects over-discharge, discharge over-current and load short-circuit, and the duration is greater than the protection detection delay time, the logic control circuit will drive the OD drive circuit to output a low level and turn off the OD pin MOS.

[0039] Figure 4 The circuit schematic diagram of the OC level conversion circuit is as follows Figure 5 As shown: I1 is the current generated by the reference current generation circuit inside the chip, and PM1 and PM2 form a pair of current mirrors to obtain the bias current I1`. I1`=N*I1, N is the channel width ratio of PM1 and PM2. cout and coutb are a pair of inverting control signals, which control the switch tubes PM3 and PM5 respectively. PM3 and NM1 form an output inverter. R2 is a current limiting resistor, which is used to protect the source of NM1 from static electricity breakdown. R3 and PM4 form an ESD protection circuit. Among them, PM1 and PM2 use low-voltage MOS tubes; PM3, PM4, PM5 and NM1 use V DS High voltage MOS tube. The V of the NMOS tube of the output inverterGS Controlled by the current switch: When the current switch is turned on, the output current of the current mirror flows through the resistor connected between the gate and source of the NMOS tube, generating a voltage drop, causing the NMOS tube to turn on; when the current switch is turned off, the gate and source of the NMOS tube are short-circuited by the resistor, completing the shutdown.

[0040] When the lithium battery is charged and discharged normally, cout = VDD, PM5 is turned off, I1` = 0, and the voltage drop on R1 is equal to V CS , that is, V GS，NM1 =0, so NM1 is turned off. coutb = VSS, PM3 is turned on, and OC is pulled up to output VDD. When the lithium battery is overcharged or overcurrent occurs, cout = VSS, coutb = VDD, PM3 is turned off, and PM5 is turned on. Current I1` flows through resistor R1 to form a voltage drop. At this time, V GS，NM1 =I1`*R1, as long as I1`*R1 is greater than the conduction threshold V of NM1 TH，NM1 , NM1 can be turned on (since PM3 is turned off, no static current flows through NM1 and R2, and there is no need to consider the voltage drop on R2). At this time, the OC pin voltage is pulled down to V CS , turning off the charging MOS.

[0041] Through the above analysis, we can know that the value range of I1`*R1 is as follows:

[0042] V TH,NM1 < I1`*R1 <VDD-V dsat,PM2 -V DS,PM5 (1)

[0043] In the above formula, V dsat,PM2 The minimum V for PM2 to work in saturation region DS Voltage, V DS,PM5 is the conduction voltage drop of PM5.

[0044] The fall time of the OC pin is:

[0045] V OC (t) = V OC,1 +(V OC,final -V OC,1 )*[1-exp(-T fall / τ OC )] (2)

[0046] In the above formula, V OC,1 is the battery voltage, V OC,final V when the OC pin is turned off CS Voltage, V OC V after the OC pin is turned off OC Voltage. τ OCis the time constant of the OC terminal, τ OC =R OC *C P,OC =(R2+R3+R on，NM1 )*C P,OC , R on,NM1 is the on-resistance of NM1, C P,OC is the gate parasitic capacitance of the charging MOS. From formulas (1) and (2), we can see that the larger the aspect ratio of PM5, the greater the V dsat,PM2 The smaller the value, the larger the value of I1`*R1 can take, and the V GS，NM1 The larger the value, the smaller the on-resistance of NM1, the smaller the time constant of the OC terminal, and the faster the fall time of the OC pin.

[0047] The output inverter in the OC level conversion circuit, the PMOS tube is controlled by internal logic, without V GS High voltage resistance requirement; when the product is less than the power supply voltage VDD, the NMOS tube has no V GS Therefore, the high-voltage MOS tubes used in the circuit of the present invention have no V exceeding the voltage VDD. GS The voltage resistance requirement is met, and there is no need to use the BCD process with thick gate oxide. The process has good versatility, low chip manufacturing cost and good economy.

[0048] Compared with the MOS tube driving circuit structure in the prior art, the MOS tube driving circuit of the present design does not require the use of a high-cost thick gate oxide process; the resistor occupies a smaller area; no static current is generated when the chip is working normally, and the power consumption is low; and the OC pin has a short fall time and high reliability.

[0049] The reference voltage generation circuit schematic is as follows: Figure 6 As shown, Mp1, Mp2 and Mn8 are switch tubes, and their gate signals are controlled by pd signals. When the chip is working normally, pd is at a low level, Mp1 and Mp2 are turned on, and Mn8 is turned off; when the chip enters a dormant state, pd is at a high level, Mp1 and Mp2 are turned off, and Mn8 is turned on, so that the overall working current of the circuit is reduced to 0. The specific working principle of the circuit is as follows:

[0050] The gate-source voltages of Mn3 and Mn4 are:

[0051]

[0052] Where V THE is the threshold voltage of the enhancement mode NMOS tube, V THD is the threshold voltage of the depletion-type NMOS tube, μ E and μ Dare the mobility of the enhancement mode NMOS tube and the depletion mode NMOS tube respectively, K1, K3, K4 and K5 are the width to length ratios of the Mn1, Mn2, Mn4 and Mn5 tubes respectively. Then the voltage V1 is expressed as:

[0053]

[0054] From formula (3), we can conclude that if The component related to mobility in the V1 expression can be offset, and V1 can be expressed as: Its temperature coefficient is only related to the threshold voltage of the enhancement mode NMOS tube, and the temperature coefficient is negative.

[0055] Mn6 and Mn7 are depletion-type NMOS tubes, V GS7 The expression is as follows:

[0056]

[0057] When the width-to-length ratio of Mn6 is smaller than that of Mn7, V GS7 Has a negative temperature coefficient. The chip's reference voltage V ref It can be expressed as:

[0058]

[0059] V ref The temperature coefficient is:

[0060]

[0061] It can be concluded from formula (6) that by setting a reasonable ratio of the width-to-length ratio of Mn6 and Mn7, and a ratio of R1 to R2, the temperature coefficient of the reference voltage Vref can be made 0. The reference voltage generating circuit of the present invention can generate a reference voltage with low temperature drift. Compared with the traditional bandgap reference circuit, the operational amplifier and the bipolar transistor are eliminated, and the layout area and current consumption of the reference voltage generating circuit are greatly reduced. Figure 6 Medium V sip is the short-circuit detection voltage, V dip is the discharge overcurrent detection voltage, V cip is the over-current detection voltage. The switch Mn9 is controlled by the signals td_cip and doutb at the same time. When the chip enters the over-current protection state, td_cip is high, which connects CS to V cip With V ref The above detection voltages are directly from V ref The voltage is divided, and there is no need to design a separate voltage regulator voltage divider circuit. Compared with the traditional reference voltage generation circuit, the use of an operational amplifier is omitted, the current consumption is further reduced, and the circuit layout area is reduced, thereby reducing the chip manufacturing cost.

[0062] The reference voltage generation circuit designed by the present invention is composed of only an enhancement type NMOS tube, a depletion type NMOS tube and a resistor. By setting reasonable device parameters, a reference voltage V with low temperature drift and stable output can be obtained. REF Compared with the traditional bandgap reference circuit, there is no need to use operational amplifiers and triodes, which greatly saves the chip area and has lower power consumption. The reference voltage generation circuit designed by the present invention can directly use resistor voltage division from the reference voltage output end to generate reference voltages for multiple comparators inside the chip, without the need to design a separate voltage regulator voltage division circuit, further reducing the circuit area overhead and reducing the overall current consumption of the chip.

[0063] CS open circuit detection circuit schematic diagram Figure 7 As shown: I1 is the current source generated by the reference current circuit, I2 is the current source in the reference voltage generation circuit, V ref The signal is the reference voltage generated by the reference voltage generation circuit. MP1 is a high-voltage PMOS tube, which is controlled by short and V RVMS Signal control. short is the output signal of the short circuit detection circuit, V RVMS It is the control signal of the pull-down resistor RVMS at the CS terminal. MN1 is a low-voltage NMOS tube, which is controlled by the td_cip and doutb signals. td_cip is the control signal for the overcurrent protection of charging, and doutb is the control signal for the OD output. The basic working principle of the detection circuit is:

[0064] (1) When the chip is in normal working state, td_cip and doutb are both low level, then MN1 is turned on. RVMS The signals are all low level, at this time NAND1 outputs high level, MP1 is turned off, MN2 is turned off, and the CS pin potential is not affected by I1 and RVMS;

[0065] (2) When the chip is connected to a load for discharge and enters the discharge overcurrent or load short circuit protection state, the td_cip signal remains at a low level, and the doutb signal becomes a high level. At this time, MN1 is turned off. RVMS and short signals are both high level, MP1 is still off. After the load is removed, the CS pin voltage is pulled down to VSS by RVMS, and after the discharge overcurrent protection release delay time T DIPR After some time, V RVMS becomes low level, so MN2 is turned off and RVMS is disconnected. Due to the load short circuit protection release delay time T shortR Greater than T DIPR, short is still high, so the output of NAND1 becomes low, MP1 turns on, and I1 starts to charge the parasitic capacitance of the CS pin. Since I1 is a tiny current of nA level, and the CS pin is connected to the source of the power MOS tube MN3, its total source parasitic capacitance C SS Large (hundreds of pF), the voltage on the CS pin is shortR After the time is up, it is still much lower than the chip's short-circuit protection voltage V sip , at this time, the short signal becomes low level, MP1 is turned off, and the chip will return to normal working state;

[0066] (3) When RCS is suddenly disconnected from the CS pin due to some reason (soldering problem or device failure), the CS pin is quickly pulled up to V by I2. SIP Above, after the load short circuit protection delay time T sip After T, short becomes high, OD becomes low, doutb becomes high, MN1 is turned off, and the chip enters the load short circuit protection state. dip -T sip After time, where T dip is the discharge overcurrent protection delay time, V RVMS The signal becomes high level, MP1 is turned off, MN2 is turned on, CS is pulled down to VSS, and after the discharge overcurrent protection release delay time T DIPR After some time, V RVMS becomes low, RVMS is disconnected, the output of NAND1 becomes low, MP1 is turned on, and I1 starts to charge the parasitic capacitance of the CS pin. At this time, since RCS is open, the parasitic capacitance Cp of the CS pin is only at the fF level, and the CS voltage will be quickly pulled up to V sip Above, at this time due to T shortR Greater than T DIPR , when RVMS is disconnected, the Short signal has not yet returned to a low level, and the chip enters the load short-circuit protection state again. When RCS is open, the above state will be repeated continuously, and the chip will be locked in the load short-circuit protection state, OD will always output a low level, and the discharge circuit will be cut off. When RCS is connected normally, the chip will exit the load short-circuit protection state, and OD will return to a high level. The CS open circuit protection circuit of the present invention can ensure that when the CS pin is open, the OD pin always outputs a low level, so that the discharge MOS tube is in the off state, cutting off the discharge path between the battery and the load circuit, and the lithium battery cannot discharge to the load. In this way, damage to the lithium battery caused by current detection failure due to CS open circuit can be prevented, thereby avoiding safety accidents.

[0067] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A lithium battery protection circuit, characterized in that: The invention comprises a reference voltage generating circuit, a reference voltage generating circuit, a reference current generating circuit, an overcharge detection comparator, an over-discharge detection comparator, a charge over-current detection comparator, a discharge over-current detection comparator, a logic control circuit, an oscillator and a counter circuit, a short circuit protection detection circuit, a CS open circuit protection circuit, an OD driving circuit, and an OC level conversion circuit. The input end of the reference voltage generating circuit is connected to the VDD end, the output end of the reference voltage generating circuit is connected to the reference voltage generating circuit and the reference current generating circuit respectively, the output end of the reference voltage generating circuit is connected to one input end of the overcharge detection comparator and one input end of the over-discharge detection comparator, the other input end of the overcharge detection comparator is connected to the VD D is connected, the other input end of the over-discharge detection comparator is connected to another voltage-dividing circuit of VDD, the output end of the over-charge detection comparator is connected to the logic control circuit, the output end of the over-discharge detection comparator is connected to the logic control circuit, the oscillator and counter circuit are connected to the logic control circuit, the output end of the short-circuit protection detection circuit and the output end of the CS open-circuit protection circuit are connected to the logic control circuit, the input end of the short-circuit protection detection circuit and the input end of the CS open-circuit protection circuit are connected to the CS end, the logic control circuit is connected to the input end of the OD driving circuit and the input end of the OC level conversion circuit, the output end of the OD driving circuit is connected to the OD end, and the output end of the OC level conversion circuit is connected to the OC end; The OC level conversion circuit includes a current mirror and an output inverter composed of a high-voltage PMOS tube PM3 and a high-voltage NMOS tube NM1. The current mirror is used to obtain a bias current according to the current of the reference current generating circuit. The bias current is connected to the source of the PMOS tube PM5. The gate of the PMOS tube PM5 is connected to the control signal cout of the logic control circuit. The source of the high-voltage PMOS tube PM3 is connected to the VDD terminal. The gate of the high-voltage PMOS tube PM3 is connected to the inverted control signal coutb. The drain of the high-voltage PMOS tube PM3 is connected to the drain of the high-voltage NMOS tube NM1. The gate of the high-voltage NMOS tube NM1 is connected to the drain of the PMOS tube PM5 and one end of the resistor R1. The source of the high-voltage NMOS tube NM1 is connected to one end of the resistor R2. The other end of the resistor R1 and the other end of the resistor R2 are connected to the CS terminal. The reference voltage generation circuit adopts the principle of mutual compensation of the temperature coefficients of the threshold voltages of the depletion-type MOS tube and the enhancement-type MOS tube; When the chip detects that the lithium battery voltage is higher than the overcharge protection voltage, the overcharge detection comparator flips, and the oscillator and counter circuit start working. When the flip duration of the overcharge detection comparator is greater than the overcharge protection delay time, the logic control circuit will turn off the MOS tube connected to the OC pin through the OC level conversion circuit to cut off the charging circuit; when the charging current of the lithium battery is too large, the chip will detect that the CS pin voltage is less than or equal to the charging overcurrent detection protection voltage, and the charging overcurrent comparator flips. When the flip duration is greater than the charging overcurrent protection delay time, the logic control circuit controls the OC level conversion circuit to turn off the OC pin MOS.

2. A lithium battery protection circuit according to claim 1, characterized in that: When NMOS tube NM1 is turned on, V GS It is determined by the product of the current mirror current and the crossover resistance between the gate and source of the NMOS tube NM1, and the product is less than the power supply voltage VDD.

3. A lithium battery protection circuit according to claim 1, characterized in that: The reference voltage generating circuit performs resistor voltage division on the reference voltage VREF of the reference voltage generating circuit to generate the reference voltage required by the internal circuit of the chip.

4. A lithium battery protection circuit according to claim 1, characterized in that: The CS open circuit protection circuit includes a pull-up current source I1, a pull-up current source I2, a current switch MP1, an inverter INV1, and a NAND gate NAND1. The output end of the inverter INV1 is connected to an input end of the NAND gate NAND1, the output end of the NAND gate NAND1 is connected to the gate of the current switch MP1, the source of the current switch MP1 is connected to the pull-up current source I1, the drain of the current switch MP1 is connected to one end of the resistor RVMD, the other end of the resistor RVMD is connected to the CS end, the pull-up current source I2 is connected to the drain of the current switch MN1, and the source of the current switch MN1 is connected to the CS end through the resistors R11 and R12.

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