Processing circuit

Abstract

The processing circuit disclosed in the present invention has an input circuit, and the input circuit includes a delay element coupled between the control terminal of the first transistor and the second connection terminal of the first transistor. In this way, the delay element is intentionally inserted between the control terminal and the connection terminal of an input transistor to fix the hold time violation in the normal mode or the test mode. Compared with the traditional hold time fixed buffer or delay unit, since the delay element does not have a transistor switching operation, leakage and power loss can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a processing circuit. Background Art

[0002] Setup and hold time checks are the most common type of timing checks used in timing verification of integrated circuit layout designs. For example, synchronous inputs have setup and hold time specifications with respect to clock inputs. These checks specify that the data inputs must remain stable for a specified period of time before and after the clock edge. The time before the clock edge is called the setup time. The period of time immediately after the clock edge is called the hold time. When the timing verification of the integrated circuit layout design indicates a timing violation (e.g., setup time violation and / or hold time violation), the integrated circuit layout design needs to be appropriately modified to meet the timing requirements (e.g., setup time constraints and / or hold time constraints).

[0003] In the digital design field, physical designers usually use hold time fixed buffers or delay cells to make the timing meet the hold time constraint or limit. However, inserting the hold time fixed buffer or delay cell to delay the data input will consume a lot of leakage and power. Therefore, an innovative circuit design is needed that can meet the hold time constraint with less leakage and power loss. Summary of the invention

[0004] In view of this, the present invention provides a processing circuit to solve the above problems. The processing circuit of the present invention uses a delay element (e.g., a capacitive element) coupled between a control terminal (e.g., a gate) and a connection terminal (e.g., a drain) of an input transistor to prevent or exempt from hold time violation immunity.

[0005] According to a first aspect of the present invention, a processing circuit is disclosed, comprising:

[0006] An input circuit, comprising: a first transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the first transistor is arranged to receive a data signal; a second transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the second transistor is coupled to the second connection terminal of the first transistor, and the control terminal of the second transistor is arranged to receive a first non-data signal; and a delay element coupled between the control terminal of the first transistor and the second connection terminal of the first transistor; and

[0007] A follower circuit is arranged to receive a data input from the input circuit and generate a data output according to the data input, wherein the data input is received at an input node of the follower circuit and the input node of the follower circuit is coupled to the second connection terminal of the second transistor.

[0008] According to a second aspect of the present invention, a processing circuit implemented as a trigger is disclosed, comprising:

[0009] An input circuit includes: a first transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the first transistor is arranged to receive a data signal; a second transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the second transistor is coupled to the second connection terminal of the first transistor, and the control terminal of the second transistor is arranged to receive a first non-data signal; a third transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the third transistor is arranged to receive the second data signal; a fourth transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the fourth transistor is coupled to the second connection terminal of the third transistor, and the control terminal of the second transistor is arranged to receive a second non-data signal that is inverted to the first non-data signal; a fifth transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the fourth transistor is coupled to the second connection terminal of the third transistor, and the control terminal of the second transistor is arranged to receive a second non-data signal that is inverted to the first non-data signal a control terminal, wherein the control terminal of the first transistor is arranged to receive the second data signal; a sixth transistor, having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the sixth transistor is coupled to the second connection terminal of the fifth transistor, and the control terminal of the second transistor is arranged to receive the second non-data signal; a seventh transistor, having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the seventh transistor is arranged to receive the second data signal; an eighth transistor, having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the eighth transistor is coupled to the second connection terminal of the seventh transistor, and the control terminal of the eighth transistor is for receiving the first non-data signal; and at least one delay element, coupled between the control terminal and the second connection terminal of at least one of the first transistor, the third transistor, the fifth transistor and the seventh transistor; and

[0010] a follower circuit arranged to receive a data input from the input circuit and to generate a data output in accordance with the data input, wherein the data input is received at an input node of the follower circuit and the follower circuit is coupled to the second connection terminal of the second transistor, the second connection terminal of the fourth transistor, the second connection terminal of the sixth transistor and the second connection terminal of the eighth transistor;

[0011] Among them, one of the first data signal and the second data signal is a normal mode data input of the trigger, and the other of the first data signal and the second data signal is a test mode data input of the trigger.

[0012] The processing circuit of the present invention has an input circuit, and the input circuit includes a delay element coupled between the control terminal of the first transistor and the second connection terminal of the first transistor. In this way, the delay element is intentionally inserted between the control terminal and the connection terminal of an input transistor to fix the hold time violation in the normal mode or the test mode. Compared with the conventional hold time fixed buffer or delay unit, since the delay element does not have a transistor switching operation, leakage and power loss can be greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing a processing circuit according to a first embodiment of the present invention.

[0014] Figure 2 is a diagram showing a hold rise constraint that can be satisfied by a processing circuit using the proposed hold time fixing technique.

[0015] Figure 3 is a diagram showing a hold fall constraint that can be satisfied by a processing circuit using the proposed hold time fixation technique.

[0016] Figure 4 is a diagram showing a processing circuit according to a second embodiment of the present invention.

[0017] Figure 5 is a diagram showing a processing circuit according to a third embodiment of the present invention.

[0018] Figure 6 is a diagram showing a processing circuit according to a fourth embodiment of the present invention.

[0019] Figure 7 is a graph showing enhanced input capacitance achieved via a capacitive element that is added to fix hold time violations.

[0020] Figure 8 is a diagram showing an example of using a pure capacitor as a hold time fixing element without an additional active device.

[0021] Fig. 9is a diagram showing an example of using a metal-oxide-metal (MOM) capacitor as a retention time fixing element without an additional active device.

[0022] Fig.10 is a diagram showing an example of using a metal-oxide-semiconductor (MOS) capacitor as a retention time fixing element with an additional active device.

[0023] Fig.11 is a diagram showing another example of using a MOS capacitor as a retention time fixed element with an additional active device.

[0024] Fig.12 is a diagram showing an example of using a varactor diode as a retention time fixed element with an additional active device. DETAILED DESCRIPTION

[0025] Certain terms are used throughout the specification and the appended claims to refer to specific components. As will be appreciated by those skilled in the art, manufacturers may refer to components by different names. This document does not intend to distinguish between components that differ in name but function the same. In the following description and claims, the terms "include" and "comprising" are used in an open-ended manner and should be interpreted to mean "including but not limited to..." Similarly, the term "coupled" is intended to mean an indirect or direct electrical connection. Thus, if one device is electrically connected to another device, the connection may be a direct electrical connection or an indirect electrical connection through other devices and connections.

[0026] Figure 1 1 is a diagram showing a processing circuit according to a first embodiment of the present invention. The processing circuit 100 includes an input circuit 102 and a follower circuit 104. In order to better understand the technical features of the present invention, it is assumed below that the processing circuit 100 is implemented as a flip-flop. However, this is only for illustrative purposes and does not mean a limitation of the present invention. In fact, any semiconductor circuit using the proposed hold time fixing technology falls within the scope of the present invention. The processing circuit can be in an integrated circuit.

[0027] The input circuit 102 includes a plurality of transistors M1, M2, M3, M4, M5, M6, M7, and M8. In this embodiment, the transistors M1, M2, M5, and M6 are p-channel metal oxide semiconductor (PMOS) transistors, each having a control terminal (i.e., gate) and two connection terminals (i.e., drain and source), and the transistors M3, M4, M7, and M8 are n-channel metal oxide semiconductor (NMOS) transistors, each having a control terminal (i.e., gate) and two connection terminals (i.e., drain and source).

[0028] Transistors M1 and M3 are used as input transistors in a normal mode. The source of transistor M1 is coupled to a reference voltage (e.g., power supply voltage VDD), and the gate of transistor M1 is used as a data input terminal for receiving a data signal D. The source of transistor M2 is coupled to the source of transistor M1. The drain of transistor M1 and the gate of transistor M2 are used as a test-enable terminal for receiving a non-data signal TE, and the drain of transistor M2 is coupled to an input node N1 of a subsequent circuit 104. The source of transistor M3 is coupled to another reference voltage (e.g., ground voltage VSS), and the gate of transistor M3 is used as a data input terminal for receiving a data signal D. The source of transistor M4 is coupled to the drain of transistor M3, the gate of transistor M4 is used as a test-enable terminal for receiving another non-data signal TE' (which is the inversion of the non-data signal TE), and the drain of transistor M4 is coupled to the input node N1 of the subsequent circuit 104.

[0029] Transistors M5 and M7 are used as input transistors of the test mode (scan mode). The source of transistor M5 is coupled to a reference voltage (e.g., power supply voltage VDD), and the gate of transistor M5 is used as a data input terminal for receiving another data signal TD. The source of transistor M6 is coupled to the drain of transistor M5, the gate of transistor M6 is used as a test enable terminal for receiving a non-data signal TE', and the drain of transistor M6 is coupled to the input node N1 of the follow-up circuit 104. The source of transistor M7 is coupled to another reference voltage (e.g., ground voltage VSS), and the gate of transistor M7 is used as a data input terminal for receiving a data signal TD. The source of transistor M8 is coupled to the drain of transistor M7, the gate of transistor M8 is used as a test enable terminal for receiving a non-data signal TE, and the drain of transistor M8 is coupled to the input node N1 of the follow-up circuit 104.

[0030] The data signal D is a normal mode data input of the processing circuit (e.g., a flip-flop) 100. The data signal TD is a test mode (scan mode) data input of the processing circuit (e.g., a flip-flop) 100. The configuration of the transistors M1, M2, M3, and M4 is similar to a tri-state inverter, and the signal inversion is performed only when the non-data signal TE is at a logic low level and the non-data signal TE' is at a logic high level. In addition, the configuration of the transistors M5, M6, M7, and M8 is similar to a tri-state inverter, and the signal inversion is performed only when the non-data signal TE is at a logic high level and the non-data signal TE' is at a logic low level. Therefore, when the non-data signal TE is set to a logic low level and the non-data signal TE' is set to a logic high level, the processing circuit (e.g., a flip-flop) 100 operates in a normal mode, for example, deriving the data input S received at the input node N1 of the follower circuit 104 from the data signal D. When the non-data signal TE is set to a logic high level and the non-data signal TE′ is set to a logic low level, the processing circuit (eg, flip-flop) 100 operates in a test mode (scan mode) such that the data input S received at the input node N1 of the subsequent circuit 104 is derived from the data signal TD.

[0031] The follower circuit 104 is arranged to receive the data input S from the input circuit 102 and generate the data output Q according to the data input S. Figure 1As shown, the follower circuit 104 includes transistors M9, M1, M11, M12, M13, M14, inverters INV1, INV3 and tri-state inverters INV2, INV4. In this embodiment, transistors M9, M11 and M13 are PMOS transistors, and transistors M10, M12 and M14 are NMOS transistors. A transmission gate is composed of transistors M9 and M10 and is controlled by clock signals CK and CK', wherein the clock signal CK' is the inversion of the clock signal CK. Another transmission gate is composed of transistors M11 and M12 and is controlled by clock signals CK and CK'. Inverter INV1 and tri-state inverter INV2 (controlled by clock signals CK and CK') form a latch circuit. Inverter INV3 and tri-state inverter INV4 (controlled by clock signals CK and CK') form another latch circuit. Transistors M13 and M14 form an inverter arranged to output data output Q. Since the present invention focuses on the design of hold time violation immunity (or exemption from hold time violation) of the input circuit 102, further description of the principle of the follower circuit 104 is omitted for the sake of brevity. It should be noted that the configuration of the follower circuit 104 can be adjusted according to actual design considerations.

[0032] The processing circuit (e.g., flip-flop) 100 needs to meet certain timing requirements, including hold time constraints. Hold time constraints may include, for example, Figure 2 The hold-up constraints shown and Figure 3 The hold-down constraint shown in the figure, wherein the hold-up constraint is applied under the condition that the input data has a rising edge and the output data has a falling edge, and the hold-down constraint is applied under the condition that the input data has a falling edge of the clock edge and the output data has a rising edge after the clock edge. According to the proposed hold time fixed design, the delay element DE is coupled between the gate and the drain of the transistor M1 to fix the hold rise constraint violation or the hold time in the normal mode of the processing circuit (e.g., flip-flop) 100, so as to fix, for example, the time interval between the data signal and the non-data signal (e.g., clock signal) (refer to Figure 2 and Figure 3As shown, a hold time rise constraint and a hold time fall constraint may be included). For example, the delay element DE may be simply implemented by a capacitive element having a well-defined capacitance, wherein the well-defined capacitive element may refer to a capacitive element whose capacitance value is known and whose capacitance value is fixed. In order to insert a hold time fixed buffer or delay unit, the proposed hold time fixed design may use a capacitor to cause more delay to meet the hold time constraints (e.g., a hold rise constraint and / or a hold fall constraint). The use of the proposed hold time fixed design may make it easier for the processing circuit (e.g., a trigger) 100 to meet the hold time requirements without consuming a large amount of leakage and power. Since the input circuit 102 has four input transistors M1, M3, M5, and M7, the same hold time fixing technique may be applied to any input transistor that requires the hold time violation to be fixed.

[0033] Figure 4 4 is a diagram showing a processing circuit according to a second embodiment of the present invention. The processing circuit 400 includes an input circuit 402 and the aforementioned follower circuit 104. As an example and not a limitation, the processing circuit 400 can be implemented in a flip-flop. The main difference between the input circuits 102 and 402 is that the input circuit 402 has a delay element DE coupled between the gate and drain of the transistor M3 to fix a hold fall constraint violation or a hold time in a normal mode of the processing circuit (e.g., flip-flop) 400.

[0034] Figure 5 5 is a diagram showing a processing circuit according to a third embodiment of the present invention. The processing circuit 500 includes an input circuit 502 and the aforementioned follower circuit 104. As an example and not a limitation, the processing circuit 500 can be implemented in a flip-flop. The main difference between the input circuits 102 and 502 is that the input circuit 502 has a delay element DE coupled between the gate and drain of the transistor M5 to fix the hold rise constraint violation or hold time in the test mode (scan mode) of the processing circuit (e.g., flip-flop) 400.

[0035] Figure 6 6 is a diagram showing a processing circuit according to a fourth embodiment of the present invention. The processing circuit 600 includes an input circuit 602 and the aforementioned follower circuit 104. As an example and not a limitation, the processing circuit 600 can be implemented in a flip-flop. The main difference between the input circuits 102 and 602 is that the input circuit 602 has a delay element DE coupled between the gate and the drain of the transistor M7 to fix the hold-down constraint violation or the hold time in the test mode (scan mode) of the processing circuit (e.g., flip-flop) 400. In the embodiment of the present invention, a plurality of delay elements DE can also be provided, for example, in Figure 6In the embodiment, it can be as follows Figure 1 As shown, a delay element is further connected between the gate and drain of the transistor M1, or Figure 6 In the embodiment, it can be as follows Figure 4 As shown, another delay element is connected between the gate and drain of the transistor M3, and so on; providing a plurality of delay elements DE can more flexibly adjust the holding time.

[0036] Figure 1 and Figure 2 The delay element DE shown in FIG. 1 can be configured to include: A capacitive element with a well-defined capacitance can be used to implement Figure 1 and Figure 4-6 . It should be noted that the capacitive element with well-defined capacitance (rather than parasitic capacitance) is intentionally inserted to resolve the hold time violation. In addition to resolving the hold time violation, the capacitive element intentionally coupled between the gate and drain of one input transistor can further increase the input capacitance. Figure 7 is a graph showing the enhanced input capacitance achieved via a capacitive element that is added to fix a hold time violation. Assume that the capacitive element intentionally inserted to resolve the hold time violation has a predefined capacitance C and the voltage gain Av of the input transistor is –u. Miller capacitance emphasizes the effective input capacitance from C to C(1+u).

[0037] In some embodiments of the present invention, Figure 1 and Figure 2 The delay element DE shown may be configured to include: Figure 1 and Figure 4-6 The capacitive element may be implemented as a pure capacitor. Figure 8 8 is a diagram showing an example of using a pure capacitor 802 as a retention time fixing element without additional active devices. For example, the pure capacitor 802 is composed of two conductive plates separated by a dielectric.

[0038] In some embodiments of the present invention, Figure 1 and Figure 2 The delay element DE shown may include one or more. Figure 1 and Figure 4-6 The capacitive element may be implemented by a metal-oxide-metal (MOM) capacitor. Fig. 9It is a figure showing an example of using MOM capacitor 902 as a holding time fixed element in the absence of additional active devices. For some semiconductor processes, MOM capacitor 902 can be realized by poly-MD (metal-to-diffusion layer, metal-diffusion layer) coupling capacitance. In the present embodiment, MOM capacitor is adopted to have a larger capacitance value, so the time of delay can be increased to be applicable to the circuit design requiring larger delay.

[0039] In some embodiments of the present invention, Figure 1 and Figure 2 The delay element DE shown may be configured to include: Figure 1 and Figure 4-6 The capacitive element may be implemented by a metal oxide semiconductor (MOS) capacitor. Fig.10 1002 is a diagram showing an example of using a MOS capacitor as a retention time fixed element with an additional active device. The MOS capacitor 1002 is implemented by a MOS transistor CM1 having a control terminal (i.e., gate) and two connection terminals (i.e., drain and source). The control terminal of the MOS transistor CM1 is coupled to the control terminal (i.e., gate) of the input transistor, one of the connection terminals of the MOS transistor CM1 is coupled to the connection terminal (i.e., drain) of the input transistor, and the other connection terminal of the MOS transistor CM1 is floating or may also be connected to a power supply voltage VDD or the like. Fig.11 1 is a diagram showing another example of using a MOS capacitor as a retention time fixed element with an additional active device. MOS capacitor 1102 is implemented by a MOS transistor CM2 having a control terminal (i.e., a gate) and two connection terminals (i.e., a drain and a source). The control terminal of MOS transistor CM2 is coupled to the control terminal (i.e., the gate) of the input transistor, and both connection terminals of MOS transistor CM2 are coupled to the connection terminal (i.e., the drain) of the input transistor. The use of MOS capacitors in this embodiment can have a simpler architecture, and the design of the circuit is also simpler. At the same time, multiple MOS capacitors can be used in series or in parallel (for example, MOS capacitor 1102 has multiple MOS capacitors, which are connected in series or in parallel), and the connection method of the connection terminals of the MOS capacitors can also be more flexible to suit different circuit requirements.

[0040] In some embodiments of the present invention, Figure 1 and Figure 2 The delay element DE shown in FIG. 1 may include: Figure 1 and Figure 4-6 The capacitive element may be implemented by a varicap diode. Fig.12 1 is a diagram showing an example of using a varactor diode 1202 as a retention time fixing element with additional devices. Figure 8-11 In contrast to the configuration shown in the embodiment with fixed capacitance, Fig.12 The embodiment shown in is configured to have an adjustable capacitance. Therefore, the capacitance required to keep the time fixed can be set by appropriately adjusting the varactor diode 1202. The use of the varactor diode in this embodiment can have a simpler architecture, the circuit design is also simpler, and the varactor diode has an adjustable capacitance, and the capacitance value can be freely determined according to the required delay time, which is more flexible.

[0041] To summarize briefly, a delay element (e.g., a capacitive element) DE is intentionally inserted between a control terminal (e.g., a gate) and a connection terminal (e.g., a drain) of an input transistor to fix a hold time violation in a normal mode or a test mode (scan mode). Compared to a typical hold time fixed buffer or delay cell, since the delay element (e.g., a capacitive element) DE does not have a transistor switching operation, leakage and power loss can be greatly reduced. In addition, the amount of delay applied by the delay element (e.g., a capacitive element) DE can be set by using a capacitance value with fine granularity. Therefore, the delay element (e.g., a capacitive element) DE can provide a fine-grained delay that is less than one gate delay.

[0042] With respect to the digital design flow, the hardware description language (HDL) layout may be further processed in the auto place and route (APR) stage. In some embodiments, the trigger cell defined in the HDL design and the proposed trigger cell (which uses the delay element DE to fix the hold time violation) available in the APR stage may have the same footprint. In this way, a cell exchange command may be executed in the APR stage to replace the trigger cell in the HDL design (which does not meet the hold time constraint) with the proposed trigger cell (which solves the hold time violation). In addition, multiple proposed trigger cells having the same cell size but different delay amounts (i.e., different hold time fixing capabilities) may be used in the APR stage, and one of the proposed trigger cells may be appropriately selected to replace at least one trigger cell in the HDL design to solve the hold time conflict problem. The use of the proposed trigger cell is compatible with existing implementations. That is, the existing digital design flow is unchanged.

[0043] Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. A processing circuit, characterized in that: include: An input circuit, comprising: a first transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the first transistor is arranged to receive a data signal; a second transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the second transistor is coupled to the second connection terminal of the first transistor, and the control terminal of the second transistor is arranged to receive a first non-data signal; and a delay element coupled between the control terminal of the first transistor and the second connection terminal of the first transistor; and A follower circuit is arranged to receive a data input from the input circuit and generate a data output according to the data input, wherein the data input is received at an input node of the follower circuit and the input node of the follower circuit is coupled to the second connection terminal of the second transistor.

2. The processing circuit according to claim 1, characterized in that The delay element is a capacitive element.

3. The processing circuit according to claim 2, characterized in that The capacitive element is a pure capacitor; or the capacitive element is a metal oxide metal capacitor; or the capacitive element is a varactor diode.

4. The processing circuit according to claim 2, characterized in that The capacitive element is a metal oxide semiconductor capacitor implemented by a metal oxide semiconductor transistor, a control terminal of the metal oxide semiconductor transistor is coupled to the control terminal of the first transistor, and a first connection terminal of the metal oxide semiconductor transistor is coupled to the second connection terminal of the first transistor.

5. The processing circuit according to claim 4, characterized in that The second connection terminal of the metal oxide semiconductor transistor is coupled to the second connection terminal of the first transistor.

6. The processing circuit according to claim 1, characterized in that The processing circuit is implemented in a flip-flop.

7. The processing circuit according to claim 6, characterized in that The data signal is a normal mode data input of the trigger; or the data signal is a test mode data input of the trigger.

8. The processing circuit according to claim 1, characterized in that The input circuit also includes: a third transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the third transistor is arranged to receive the data signal; and A fourth transistor has a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the fourth transistor is coupled to the second connection terminal of the third transistor, the control terminal of the fourth transistor is arranged to receive a second non-data signal that is inverted with the first non-data signal, and the second connection terminal of the fourth transistor is coupled to the input node of the follower circuit.

9. The processing circuit according to claim 8, characterized in that The first connection terminal of the first transistor is arranged to receive a first reference voltage, and the first connection terminal of the third transistor is arranged to receive a second reference voltage lower than the first reference voltage; or the first connection terminal of the third transistor is arranged to receive a second reference voltage higher than the first reference voltage.

10. The processing circuit according to claim 9, characterized in that When the second transistor is turned on by the first non-data signal and the fourth transistor is turned on by the second non-data signal, the data input of the follower circuit is derived from the data signal.

11. The processing circuit according to claim 10, characterized in that When the processing circuit operates in a normal mode, the second transistor and the fourth transistor are turned on.

12. The processing circuit according to claim 10, characterized in that When the processing circuit operates in the test mode, the second transistor and the fourth transistor are turned on.

13. A processing circuit, characterized in that: The processing circuit is implemented as a trigger, and the processing circuit includes: An input circuit includes: a first transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the first transistor is arranged to receive a first data signal; a second transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the second transistor is coupled to the second connection terminal of the first transistor, and the control terminal of the second transistor is arranged to receive a first non-data signal; a third transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the third transistor is arranged to receive the first data signal; a fourth transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the fourth transistor is coupled to the second connection terminal of the third transistor, and the control terminal of the fourth transistor is arranged to receive a second non-data signal that is inverted to the first non-data signal; a fifth transistor having a first connection terminal, a second connection terminal and a control terminal. and a control terminal, wherein the control terminal of the fifth transistor is arranged to receive a second data signal; a sixth transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the sixth transistor is coupled to the second connection terminal of the fifth transistor, and the control terminal of the sixth transistor is arranged to receive the second non-data signal; a seventh transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the control terminal of the seventh transistor is arranged to receive the second data signal; an eighth transistor having a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal of the eighth transistor is coupled to the second connection terminal of the seventh transistor, and the control terminal of the eighth transistor is for receiving the first non-data signal; and at least one delay element coupled between the control terminal and the second connection terminal of at least one of the first transistor, the third transistor, the fifth transistor and the seventh transistor; and a follower circuit arranged to receive a data input from the input circuit and to generate a data output in accordance with the data input, wherein the data input is received at an input node of the follower circuit and the follower circuit is coupled to the second connection terminal of the second transistor, the second connection terminal of the fourth transistor, the second connection terminal of the sixth transistor and the second connection terminal of the eighth transistor; Among them, one of the first data signal and the second data signal is a normal mode data input of the trigger, and the other of the first data signal and the second data signal is a test mode data input of the trigger.

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