Switching circuits, mixers and electronic equipment

Abstract

Embodiments of the present application disclose a switching circuit, a mixer, and an electronic device. The switching circuit includes a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor. The gates of the first MOS transistor and the fourth MOS transistor are both connected to a first port, and the gates of the second MOS transistor and the third MOS transistor are both connected to a second port. The length of the lead between the gate of the first MOS transistor and the first port, the length of the lead between the gate of the second MOS transistor and the second port, the length of the lead between the gate of the third MOS transistor and the second port, and the length of the lead between the gate of the fourth MOS transistor and the first port are all equal. The switching circuit has high linearity.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a switching circuit, a mixer and an electronic device. Background Art

[0002] In electronic communications systems, mixers are core circuits responsible for spectrum shifting within transceivers. They are widely used in microwave wireless communications, radar, and measurement systems. Key technical specifications for mixers include IF / RF bandwidth, conversion gain, noise figure, linearity, port-to-port isolation, port standing wave ratio, and power consumption.

[0003] Because mixers in receivers are located at locations where RF signal amplitudes are high and many interfering signals are not effectively suppressed, linearity is a very important (if not the most important) specification. The input second-order intercept point (IIP2) is one of the key metrics for measuring mixer linearity. IIP2 quantifies the linearity of second-order distortion caused by nonlinearities in circuits such as amplifiers and mixers. Currently, mixer linearity is poor, and research is needed to develop mixers with improved linearity. Summary of the Invention

[0004] The embodiments of the present application provide a switching circuit, a mixer, and an electronic device to improve the linearity of the device.

[0005] In a first aspect, an embodiment of the present application provides a switching circuit, comprising a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, wherein the gate of the first MOS transistor and the gate of the fourth MOS transistor are both connected to a first port, and the gate of the second MOS transistor and the gate of the third MOS transistor are both connected to a second port; the length of a lead wire between the gate of the first MOS transistor and the first port, the length of a lead wire between the gate of the second MOS transistor and the second port, the length of a lead wire between the gate of the third MOS transistor and the second port, and the length of a lead wire between the gate of the fourth MOS transistor and the first port are all equal.

[0006] In the embodiment of the present application, the gate wiring of each MOS transistor in the switch circuit has the same length, so that the gate parasitic capacitance of each MOS transistor is the same and the linearity is high.

[0007] In an optional implementation, a first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through a first position, and a second lead between the gate of the second MOS transistor and the gate of the third MOS transistor passes through a second position, and the first position and the second position are the same position on different layers in the switch circuit; the length of the lead from the gate of the first MOS transistor to the first position, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, and the length of the lead from the gate of the fourth MOS transistor to the first position are equal.

[0008] In this implementation, the lengths of leads from the gates of the MOS transistors in the switch circuit to the same position on different layers in the switch circuit are equal, so that the parasitic capacitances of the gates of the MOS transistors are the same and the linearity is high.

[0009] In an optional implementation, the first MOS transistor and the third MOS transistor are aligned left-right and symmetrical along a first symmetric axis, the second MOS transistor and the fourth MOS transistor are aligned left-right and symmetrical along the first symmetric axis, the first MOS transistor and the second MOS transistor are aligned front-to-back and symmetrical along a second symmetric axis, the third MOS transistor and the fourth MOS transistor are aligned front-to-back and symmetrical along the second symmetric axis, and the first symmetric axis and the second symmetric axis are perpendicular to each other.

[0010] In this implementation, the MOS transistors in the switch circuit are symmetrically arranged, which can make the parasitic capacitances of the MOS transistors compatible, thereby improving the linearity of the mixer.

[0011] In an optional implementation, one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to the second port; the third position and the fourth position are symmetrical along the first symmetry axis; and the switching circuit is symmetrical along the first symmetry axis.

[0012] In this implementation, the third lead and the fourth lead are symmetrical along the first symmetry axis, so that the routing of the gates of the MOS transistors can be symmetrical.

[0013] In an optional implementation, the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected to form the second lead, and the first lead and the second lead are both straight lines.

[0014] In this implementation, the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead and reduce the cost.

[0015] In an optional implementation, a portion of the third lead is located on one side of the first symmetry axis, and another portion of the third lead is located on the other side of the first symmetry axis; a portion of the fourth lead is located on one side of the first symmetry axis, and another portion of the fourth lead is located on the other side of the first symmetry axis; the third lead passes through the fifth position, and the fourth lead passes through the sixth position, and the fifth position and the sixth position are the same position in different layers in the switching circuit.

[0016] In this implementation, the gate wiring of each MOS transistor is strictly symmetrical, so that the parasitic capacitance of the gate of each MOS transistor is consistent.

[0017] In an optional implementation, the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the switching circuit, the second portion of the third lead is parallel to the first axis of symmetry, the third portion of the third lead is located on both sides of the first axis of symmetry, and the fourth portion of the third lead is parallel to the first axis of symmetry; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the switching circuit, the second portion of the fourth lead is parallel to the first axis of symmetry, the third portion of the fourth lead is located on both sides of the first axis of symmetry, and the fourth portion of the fourth lead is parallel to the first axis of symmetry; the third portion of the third lead passes through the fifth position, and the third portion of the fourth lead passes through the sixth position.

[0018] In this implementation, the first part of the third lead and a part of the second lead are located at the same position on different layers in the switching circuit, and the first part of the fourth lead and a part of the first lead are located at the same position on different layers in the switching circuit, which can effectively reduce the mutual influence between the leads.

[0019] In an optional implementation, the third lead is located on one side of the first symmetry axis, and the fourth lead is located on the other side of the first symmetry axis; the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the switching circuit, and the second portion of the third lead is parallel to the first symmetry axis; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the switching circuit, and the second portion of the fourth lead is parallel to the first symmetry axis.

[0020] In this implementation, the third lead and the fourth lead are directly connected to the first port and the second port without crossing each other, which simplifies wiring.

[0021] In an optional implementation, the third position and the first position are the same position, and the fourth position and the second position are the same position.

[0022] In a second aspect, an embodiment of the present application provides another switching circuit, which includes a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, wherein the gate of the first MOS transistor and the gate of the fourth MOS transistor are both connected to the first port, and the gate of the second MOS transistor and the gate of the third MOS transistor are both connected to the second port; the lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor and the lead between the gate of the second MOS transistor and the gate of the third MOS transistor both pass through the same position on different layers in the switching circuit.

[0023] In the embodiment of the present application, the lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor, and the lead between the gate of the second MOS transistor and the gate of the third MOS transistor all pass through the same position on different layers in the switching circuit; the linearity of the switching circuit can be improved.

[0024] In an optional implementation, the length of the lead between the gate of the first MOS transistor and the first port, the length of the lead between the gate of the second MOS transistor and the second port, the length of the lead between the gate of the third MOS transistor and the second port, and the length of the lead between the gate of the fourth MOS transistor and the first port are all equal.

[0025] In this implementation, the gate wiring of each MOS transistor in the switch circuit has the same length, so that the gate parasitic capacitance of each MOS transistor is the same, and the linearity is high.

[0026] In an optional implementation, a first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through a first position, and a second lead between the gate of the second MOS transistor and the gate of the third MOS transistor passes through a second position, and the first position and the second position are the same position on different layers in the switch circuit; the length of the lead from the gate of the first MOS transistor to the first position, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, and the length of the lead from the gate of the fourth MOS transistor to the first position are equal.

[0027] In this implementation, the lengths of leads from the gates of the MOS transistors in the switch circuit to the same position on different layers in the switch circuit are equal, so that the parasitic capacitances of the gates of the MOS transistors are the same and the linearity is high.

[0028] In an optional implementation, the first MOS transistor and the third MOS transistor are aligned left-right and symmetrical along a first symmetric axis, the second MOS transistor and the fourth MOS transistor are aligned left-right and symmetrical along the first symmetric axis, the first MOS transistor and the second MOS transistor are aligned front-to-back and symmetrical along a second symmetric axis, the third MOS transistor and the fourth MOS transistor are aligned front-to-back and symmetrical along the second symmetric axis, and the first symmetric axis and the second symmetric axis are perpendicular to each other.

[0029] In this implementation, the MOS transistors in the switch circuit are symmetrically arranged, which can make the parasitic capacitances of the MOS transistors compatible, thereby improving the linearity of the mixer.

[0030] In an optional implementation, one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to the second port; the third position and the fourth position are symmetrical along the first symmetry axis; and the switching circuit is symmetrical along the first symmetry axis.

[0031] In this implementation, the third lead and the fourth lead are symmetrical along the first symmetry axis, so that the routing of the gates of the MOS transistors can be symmetrical.

[0032] In an optional implementation, the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected to form the second lead, and the first lead and the second lead are both straight lines.

[0033] In this implementation, the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead.

[0034] In an optional implementation, a portion of the third lead is located on one side of the first symmetry axis, and another portion of the third lead is located on the other side of the first symmetry axis; a portion of the fourth lead is located on one side of the first symmetry axis, and another portion of the fourth lead is located on the other side of the first symmetry axis; the third lead passes through the fifth position, and the fourth lead passes through the sixth position, and the fifth position and the sixth position are the same position in different layers in the switching circuit.

[0035] In this implementation, the gate wiring of each MOS transistor is strictly symmetrical, so that the parasitic capacitance of the gate of each MOS transistor is consistent.

[0036] In an optional implementation, the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the switching circuit, the second portion of the third lead is parallel to the first axis of symmetry, the third portion of the third lead is located on both sides of the first axis of symmetry, and the fourth portion of the third lead is parallel to the first axis of symmetry; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the switching circuit, the second portion of the fourth lead is parallel to the first axis of symmetry, the third portion of the fourth lead is located on both sides of the first axis of symmetry, and the fourth portion of the fourth lead is parallel to the first axis of symmetry; the third portion of the third lead passes through the fifth position, and the third portion of the fourth lead passes through the sixth position.

[0037] In this implementation, the first part of the third lead and a part of the second lead are located at the same position on different layers in the switching circuit, and the first part of the fourth lead and a part of the first lead are located at the same position on different layers in the switching circuit, which can effectively reduce the mutual influence between the leads.

[0038] In an optional implementation, the third lead is located on one side of the first symmetry axis, and the fourth lead is located on the other side of the first symmetry axis; the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the switching circuit, and the second portion of the third lead is parallel to the first symmetry axis; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the switching circuit, and the second portion of the fourth lead is parallel to the first symmetry axis.

[0039] In this implementation, the third lead and the fourth lead are directly connected to the first port and the second port without crossing each other, which simplifies wiring.

[0040] In an optional implementation, the third position and the first position are the same position, and the fourth position and the second position are the same position.

[0041] In a third aspect, an embodiment of the present application provides a mixer, comprising a first metal oxide semiconductor (MOS) transistor group; the first MOS transistor group comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the gates of the first MOS transistor and the fourth MOS transistor are both connected to a first local oscillator port, and the gates of the second MOS transistor and the third MOS transistor are both connected to a second local oscillator port; the length of a lead wire between the gate of the first MOS transistor and the first local oscillator port, the length of a lead wire between the gate of the second MOS transistor and the second local oscillator port, the length of a lead wire between the gate of the third MOS transistor and the second local oscillator port, and the length of a lead wire between the gate of the fourth MOS transistor and the first local oscillator port are all equal.

[0042] In the embodiment of the present application, the gate wiring of each MOS transistor in the mixer has the same length, so that the gate parasitic capacitance of each MOS transistor is the same, and the linearity is high.

[0043] In an optional implementation, the first local oscillator port and the second local oscillator port are both local oscillator ports that receive a driving voltage; the source of the first MOS transistor and the source of the second MOS transistor are both connected to the first input port, and the source of the third MOS transistor and the source of the fourth MOS transistor are both connected to the second input port; the drain of the first MOS transistor and the drain of the third MOS transistor are both connected to the first output port, and the drain of the second MOS transistor and the drain of the fourth MOS transistor are both connected to the second output port.

[0044] In an optional implementation, a first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through a first position, and a second lead between the gate of the second MOS transistor and the gate of the third MOS transistor passes through a second position, and the first position and the second position are the same position on different layers in the mixer; the length of the lead from the gate of the first MOS transistor to the first position, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, and the length of the lead from the gate of the fourth MOS transistor to the first position are equal.

[0045] In this implementation, the lengths of leads from the gates of the MOS transistors in the mixer to the same position on different layers in the mixer are equal, so that the parasitic capacitances of the gates of the MOS transistors are the same and the linearity is high.

[0046] In an optional implementation, the first MOS transistor and the third MOS transistor are aligned left-right and symmetrical along a first symmetric axis, the second MOS transistor and the fourth MOS transistor are aligned left-right and symmetrical along the first symmetric axis, the first MOS transistor and the second MOS transistor are aligned front-to-back and symmetrical along a second symmetric axis, the third MOS transistor and the fourth MOS transistor are aligned front-to-back and symmetrical along the second symmetric axis, and the first symmetric axis and the second symmetric axis are perpendicular to each other.

[0047] In this implementation, the MOS transistors in the mixer are symmetrically arranged, which can make the parasitic capacitances of the MOS transistors compatible, thereby improving the linearity of the mixer.

[0048] In an optional implementation, one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first local oscillator port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to the second local oscillator port; the third position and the fourth position are symmetrical along the first symmetry axis; and the mixer is symmetrical along the first symmetry axis.

[0049] In this implementation, the third lead and the fourth lead are symmetrical along the first symmetry axis, so that the routing of the gates of the MOS transistors can be symmetrical.

[0050] In an optional implementation, the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected to form the second lead, and the first lead and the second lead are both straight lines.

[0051] In this implementation, the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead.

[0052] In an optional implementation, a portion of the third lead is located on one side of the first symmetry axis, and another portion of the third lead is located on the other side of the first symmetry axis; a portion of the fourth lead is located on one side of the first symmetry axis, and another portion of the fourth lead is located on the other side of the first symmetry axis; the third lead passes through a fifth position, and the fourth lead passes through a sixth position, and the fifth position and the sixth position are the same position on different layers in the mixer.

[0053] In this implementation, the gate wiring of each MOS transistor is strictly symmetrical, so that the resistance and parasitic capacitance of the gate of each MOS transistor are consistent.

[0054] In an optional implementation, the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, the second portion of the third lead is parallel to the first axis of symmetry, the third portion of the third lead is located on both sides of the first axis of symmetry, and the fourth portion of the third lead is parallel to the first axis of symmetry; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, the second portion of the fourth lead is parallel to the first axis of symmetry, the third portion of the fourth lead is located on both sides of the first axis of symmetry, and the fourth portion of the fourth lead is parallel to the first axis of symmetry; the third portion of the third lead passes through the fifth position, and the third portion of the fourth lead passes through the sixth position.

[0055] In this implementation, the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, and the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, which can effectively reduce mutual influence between the leads.

[0056] In an optional implementation, the third lead is located on one side of the first symmetry axis, and the fourth lead is located on the other side of the first symmetry axis; the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, and the second portion of the third lead is parallel to the first symmetry axis; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, and the second portion of the fourth lead is parallel to the first symmetry axis.

[0057] In this implementation, the third lead and the fourth lead are directly connected to the first local oscillator port and the second local oscillator port without crossing, which simplifies wiring.

[0058] In an optional implementation, the third position and the first position are the same position, and the fourth position and the second position are the same position.

[0059] In this implementation, it is possible to ensure that the gate wiring of each MOS transistor is strictly symmetrical.

[0060] In an optional implementation, the first input port and the second input port are both connected to a low-noise amplifier, and the first output port and the second output port are both connected to a transimpedance amplifier.

[0061] In a fourth aspect, an embodiment of the present application provides another mixer, comprising a first metal oxide semiconductor (MOS) transistor group and a second MOS transistor group; the first MOS transistor group comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the gates of the first MOS transistor and the fourth MOS transistor are both connected to a first local oscillator port, and the gates of the second MOS transistor and the third MOS transistor are both connected to a second local oscillator port; the length of the lead between the gate of the first MOS transistor and the first local oscillator port, the length of the lead between the gate of the second MOS transistor and the second local oscillator port, the length of the lead between the gate of the third MOS transistor and the second local oscillator port, and the length of the lead between the gate of the fourth MOS transistor and the first local oscillator port are all equal.

[0062] In the embodiment of the present application, the gate wiring of each MOS transistor in the mixer has the same length, so that the gate parasitic capacitance of each MOS transistor is the same, and the linearity is high.

[0063] In an optional implementation, the first MOS transistor group and the second MOS transistor group are aligned left to right and symmetrical along a reference symmetry axis.

[0064] In this implementation, the first MOS transistor group and the second MOS transistor group are symmetrically placed, so that the parasitic capacitances of the two MOS transistor groups can be consistent, thereby improving the linearity of the mixer.

[0065] In an optional implementation, a first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through a first position, and a second lead between the gate of the second MOS transistor and the gate of the third MOS transistor passes through a second position, and the first position and the second position are the same position on different layers in the mixer; the length of the lead from the gate of the first MOS transistor to the first position, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, and the length of the lead from the gate of the fourth MOS transistor to the first position are equal.

[0066] In this implementation, the lengths of leads from the gates of the MOS transistors in the mixer to the same position on different layers in the mixer are equal, so that the parasitic capacitances of the gates of the MOS transistors are the same and the linearity is high.

[0067] In an optional implementation, the first MOS transistor and the third MOS transistor are aligned left-right and symmetrical along a first symmetric axis, the second MOS transistor and the fourth MOS transistor are aligned left-right and symmetrical along the first symmetric axis, the first MOS transistor and the second MOS transistor are aligned front-to-back and symmetrical along a second symmetric axis, the third MOS transistor and the fourth MOS transistor are aligned front-to-back and symmetrical along the second symmetric axis, and the first symmetric axis and the second symmetric axis are perpendicular to each other.

[0068] In this implementation, the MOS transistors in the mixer are symmetrically arranged, which can make the parasitic capacitances of the MOS transistors compatible, thereby improving the linearity of the mixer.

[0069] In an optional implementation, one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to the second port; the third position and the fourth position are symmetrical along the first symmetry axis; and the mixer is symmetrical along the first symmetry axis.

[0070] In this implementation, the third lead and the fourth lead are symmetrical along the first symmetry axis, so that the routing of the gates of the MOS transistors can be symmetrical.

[0071] In an optional implementation, the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected to form the second lead, and the first lead and the second lead are both straight lines.

[0072] In this implementation, the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead.

[0073] In an optional implementation, a portion of the third lead is located on one side of the first symmetry axis, and another portion of the third lead is located on the other side of the first symmetry axis; a portion of the fourth lead is located on one side of the first symmetry axis, and another portion of the fourth lead is located on the other side of the first symmetry axis; the third lead passes through a fifth position, and the fourth lead passes through a sixth position, and the fifth position and the sixth position are the same position on different layers in the mixer.

[0074] In this implementation, the gate wiring of each MOS transistor is strictly symmetrical, so that the resistance and parasitic capacitance of the gate of each MOS transistor are consistent.

[0075] In an optional implementation, the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, the second portion of the third lead is parallel to the first axis of symmetry, the third portion of the third lead is located on both sides of the first axis of symmetry, and the fourth portion of the third lead is parallel to the first axis of symmetry; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, the second portion of the fourth lead is parallel to the first axis of symmetry, the third portion of the fourth lead is located on both sides of the first axis of symmetry, and the fourth portion of the fourth lead is parallel to the first axis of symmetry; the third portion of the third lead passes through the fifth position, and the third portion of the fourth lead passes through the sixth position.

[0076] In this implementation, the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, and the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, which can effectively reduce mutual influence between the leads.

[0077] In an optional implementation, the third lead is located on one side of the first symmetry axis, and the fourth lead is located on the other side of the first symmetry axis; the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, and the second portion of the third lead is parallel to the first symmetry axis; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, and the second portion of the fourth lead is parallel to the first symmetry axis.

[0078] In this implementation, the third lead and the fourth lead are directly connected to the first local oscillator port and the second local oscillator port without crossing, which simplifies wiring.

[0079] In an optional implementation, the third position and the first position are the same position, and the fourth position and the second position are the same position.

[0080] In this implementation, it is possible to ensure that the gate wiring of each MOS transistor is strictly symmetrical.

[0081] In an optional implementation, the first MOS transistor group and the second MOS transistor group are placed on different deep N wells.

[0082] In this implementation, the isolation between the first MOS transistor group and the second MOS transistor group is relatively high.

[0083] In an optional implementation, the first input port and the second input port are both connected to a low-noise amplifier, and the first output port and the second output port are both connected to a transimpedance amplifier.

[0084] In a fifth aspect, an embodiment of the present application provides another mixer, which includes a first metal oxide semiconductor (MOS) tube group and a second MOS tube group, wherein the first MOS tube group and the second MOS tube group are placed on different deep N wells.

[0085] Optionally, the circuit structure of the second MOS tube group is the same as the circuit structure of the first MOS tube group.

[0086] In the embodiment of the present application, the two MOS transistor groups are placed on different deep N wells, which can improve the isolation between the two MOS transistor groups.

[0087] In an optional implementation, the first MOS transistor group includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the gates of the first MOS transistor and the fourth MOS transistor are both connected to the first port, and the gates of the second MOS transistor and the third MOS transistor are both connected to the second port; the length of the lead between the gate of the first MOS transistor and the first port, the length of the lead between the gate of the second MOS transistor and the second port, the length of the lead between the gate of the third MOS transistor and the second port, and the length of the lead between the gate of the fourth MOS transistor and the first port are all equal.

[0088] In this implementation, the lengths of the gate wirings of the MOS transistors in the mixer are the same, so that the gate parasitic capacitances of the MOS transistors are the same, resulting in higher linearity.

[0089] In an optional implementation, the first MOS transistor group and the second MOS transistor group are aligned left to right and symmetrical along a reference symmetry axis.

[0090] In this implementation, the first MOS transistor group and the second MOS transistor group are symmetrically placed, so that the parasitic capacitances of the two MOS transistor groups can be consistent, thereby improving the linearity of the mixer.

[0091] In an optional implementation, a first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through a first position, and a second lead between the gate of the second MOS transistor and the gate of the third MOS transistor passes through a second position, and the first position and the second position are the same position on different layers in the mixer; the length of the lead from the gate of the first MOS transistor to the first position, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, and the length of the lead from the gate of the fourth MOS transistor to the first position are equal.

[0092] In this implementation, the lengths of leads from the gates of the MOS transistors in the mixer to the same position on different layers in the mixer are equal, so that the parasitic capacitances of the gates of the MOS transistors are the same and the linearity is high.

[0093] In an optional implementation, the first MOS transistor and the third MOS transistor are aligned left-right and symmetrical along a first symmetric axis, the second MOS transistor and the fourth MOS transistor are aligned left-right and symmetrical along the first symmetric axis, the first MOS transistor and the second MOS transistor are aligned front-to-back and symmetrical along a second symmetric axis, the third MOS transistor and the fourth MOS transistor are aligned front-to-back and symmetrical along the second symmetric axis, and the first symmetric axis and the second symmetric axis are perpendicular to each other.

[0094] In this implementation, the MOS transistors in the mixer are symmetrically arranged, which can make the parasitic capacitances of the MOS transistors compatible, thereby improving the linearity of the mixer.

[0095] In an optional implementation, one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to the second port; the third position and the fourth position are symmetrical along the first symmetry axis; and the mixer is symmetrical along the first symmetry axis.

[0096] In this implementation, the third lead and the fourth lead are symmetrical along the first symmetry axis, so that the routing of the gates of the MOS transistors can be symmetrical.

[0097] In an optional implementation, the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected to form the second lead, and the first lead and the second lead are both straight lines.

[0098] In this implementation, the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead.

[0099] In an optional implementation, a portion of the third lead is located on one side of the first symmetry axis, and another portion of the third lead is located on the other side of the first symmetry axis; a portion of the fourth lead is located on one side of the first symmetry axis, and another portion of the fourth lead is located on the other side of the first symmetry axis; the third lead passes through a fifth position, and the fourth lead passes through a sixth position, and the fifth position and the sixth position are the same position on different layers in the mixer.

[0100] In this implementation, the gate wiring of each MOS transistor is strictly symmetrical, so that the resistance and parasitic capacitance of the gate of each MOS transistor are consistent.

[0101] In an optional implementation, the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, the second portion of the third lead is parallel to the first axis of symmetry, the third portion of the third lead is located on both sides of the first axis of symmetry, and the fourth portion of the third lead is parallel to the first axis of symmetry; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, the second portion of the fourth lead is parallel to the first axis of symmetry, the third portion of the fourth lead is located on both sides of the first axis of symmetry, and the fourth portion of the fourth lead is parallel to the first axis of symmetry; the third portion of the third lead passes through the fifth position, and the third portion of the fourth lead passes through the sixth position.

[0102] In this implementation, the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, and the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, which can effectively reduce mutual influence between the leads.

[0103] In an optional implementation, the third lead is located on one side of the first symmetry axis, and the fourth lead is located on the other side of the first symmetry axis; the first portion of the third lead and a portion of the second lead are located at the same position on different layers in the mixer, and the second portion of the third lead is parallel to the first symmetry axis; the first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the mixer, and the second portion of the fourth lead is parallel to the first symmetry axis.

[0104] In this implementation, the third lead and the fourth lead are directly connected to the first port and the second port without crossing each other, which simplifies wiring.

[0105] In an optional implementation, the third position and the first position are the same position, and the fourth position and the second position are the same position.

[0106] In this implementation, it is possible to ensure that the gate wiring of each MOS transistor is strictly symmetrical.

[0107] In an optional implementation, the first input port and the second input port are both connected to a low-noise amplifier, and the first output port and the second output port are both connected to a transimpedance amplifier.

[0108] In a sixth aspect, an embodiment of the present application provides an electronic device, which includes the mixer in the third to fifth aspects and any optional implementation manner.

[0109] The electronic device may be a receiver, a transceiver, or a radio frequency chip in a terminal (eg, a mobile phone, a base station, etc.), or may be a terminal or other device. BRIEF DESCRIPTION OF THE DRAWINGS

[0110] Figure 1 A schematic diagram of the structure of the front and rear stages of a mixer in a receiver;

[0111] Figure 2 The figure is a circuit diagram of a mixer;

[0112] Figure 3 It is a traditional mixer layout structure;

[0113] Figure 4 The present invention is a layout structure of a group of switching circuits in a mixer;

[0114] Figure 5 A circuit schematic diagram of a switching circuit;

[0115] Figure 6 A layout structure of a mixer provided in an embodiment of the present application;

[0116] Figure 7 Provide a layout structure of a switch circuit for an embodiment of the present application;

[0117] Figure 8 Another switch circuit layout structure provided in an embodiment of the present application;

[0118] Figure 9A It is a traditional mixer layout structure;

[0119] Figure 9B A mixer layout structure is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0120] In order to enable people in this technical field to better understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0121] The terms "first," "second," and "third," etc. in the specification, embodiments, claims, and figures of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, for example, including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the process, method, product, or apparatus.

[0122] In electronic communications systems, mixers are core circuits in transceivers, responsible for spectrum shifting. They are widely used in microwave wireless communications, radar, and measurement systems. A receiver typically consists of amplifiers, filters, and mixers, amplifying and filtering the analog input signal, performing several frequency shifts or conversions. The analog-to-digital converter (ADC) then samples the signal and transmits the resulting digital signal to a computer or digital signal processor for further processing. Mixers are located in receivers where RF signal amplitudes are high and many interfering signals are not effectively suppressed. Therefore, linearity is a very important (if not the most important) mixer specification. Figure 1 This is a schematic diagram of the structure of the front and rear stages of a mixer in a receiver. Figure 1 As shown, 101 is a low-noise amplifier, 102 is a mixer, and 103 is a transimpedance amplifier; the mixer 102 is located at the post-stage of the low-noise amplifier 101, and the transimpedance amplifier 103 is located at the post-stage of the mixer 102; the low-noise amplifier 101 amplifies the received weak signal through low-noise processing and inputs orthogonal RF signals to the two input ends of the mixer 102; the mixer 102 mixes the RF signal at its input end with the local oscillator signal (i.e., frequency shifts) to obtain an intermediate frequency signal; the transimpedance amplifier 103 converts the received intermediate frequency signal into a voltage signal. Figure 1 This is only an example provided in this application. The mixer can be applied in a variety of circuits, and this application does not limit the front and back stages of the mixer.

[0123] Figure 2 This is a circuit diagram of a mixer. Figure 2As shown, the dotted box on the left is the first switch circuit, and the dotted box on the right is the second switch circuit; the first switch circuit is composed of M1 to M4, M1 to M4 are all metal oxide semiconductor (MOS) tubes, the gate of M1 and the gate of M4 are both connected to the input port LOP1, the gate of M2 and the gate of M3 are both connected to the input port LON1, the source of M1 and the source of M2 are both connected to the input port RFIP, the source of M3 and the source of M4 are both connected to the input port RFIN, and the output ports of the first switch circuit are IFIP and IFIN; the second switch circuit is composed of M5 to M8, M5 to M8 are all MOS tubes, the gate of M5 and the gate of M8 are both connected to the input port LOP2, the gate of M6 and the gate of M7 are both connected to the input Port LON2, the source of M5 and the source of M6 are both connected to the input port RFIP, the source of M7 and the source of M8 are both connected to the input port RFIN, and the output ports of the second switch circuit are IFQP and IFQN; the first switch circuit and the second switch circuit are connected in parallel and are both driven by orthogonal local oscillator signals, outputting two intermediate frequency signals I and Q, forming an orthogonal Gilbert mixer; wherein, the signal input to the input port LOP1 and the signal input to the input port LON1 are orthogonal signals, and the signal input to the input port LOP2 and the signal input to the input port LON2 are orthogonal signals. Figure 2 This is only an example of a circuit diagram of a mixer provided in this application. Different types of mixers have different circuit diagrams, and this application does not limit the circuit diagram of the mixer. Figure 2 It can be seen that the mixer includes two groups of switching circuits with the same structure. The gates of M1 and M4 are both connected to the input port LOP1, the gates of M2 and M3 are both connected to the input port LON1, the gates of M5 and M8 are both connected to the input port LOP2, and the gates of M6 and M7 are both connected to the input port LON2. Both groups of switching circuits are driven by orthogonal local oscillator signals, one group outputs the I intermediate frequency signal, and the other group outputs the Q intermediate frequency signal.

[0124] The mixer's layout structure includes two groups of symmetrically arranged switching circuits. The gates of the four MOS transistors in each group of switching circuits are each connected to a lead; two gate leads are connected to one output port of the LO, and the other two gate leads are connected to the other output port of the LO. Figure 3 This is a traditional mixer layout structure. Figure 3 As shown, M1 to M8 correspond to Figure 2 M1 to M8, Figure 3 The layout structure of the middle left half corresponds to Figure 2 The switch circuit in the dotted box on the left, Figure 3 The layout structure in the middle right half corresponds to Figure 2The switch circuit in the dotted line on the right; the gate of M1 and the gate of M4 are connected to the input port LOP1 of LO, the gate of M2 and the gate of M3 are connected to the output port LON1 of LO, the gate of M5 and the gate of M8 are connected to the output port LOP2 of LO, the gate of M6 and the gate of M7 are connected to the output port LON2 of LO; the drain of M1 and the drain of M3 are connected to the output port IFIP, the drain of M2 and the drain of M4 are connected to the output port IFIN, the drain of M5 and the drain of M7 are connected to the output port IFQP, the drain of M6 and the drain of M8 are connected to the output port IFQN; the source of M1 and the source of M2 are connected to the input port RFIP, the source of M3 and the source of M4 are connected to the input port RFIN; the source of M5 and the source of M6 are connected to the input port RFIP, the source of M7 and the source of M8 are connected to the input port RFIN. Figure 3 As shown, since the layout structures of the two groups of switch circuits are arranged symmetrically, in order to more conveniently describe the layout structure of each group of switch circuits in the layout structure of the mixer, only the layout structure of one group of switch circuits is described below. Figure 4 This is the layout structure of a set of switch circuits in the mixer. Figure 4 As shown, M1 to M4 correspond to Figure 2 Among M1~M4, the gate of M1 and the gate of M4 are connected to the input port LOP1 of LO, the gate of M2 and the gate of M3 are connected to the output port LON1 of LO, the drain of M1 and the drain of M3 are connected to the output port IFIP, the drain of M2 and the drain of M4 are connected to the output port IFIN, the source of M1 and the source of M2 are connected to the same input port RFIP, and the source of M3 and the source of M4 are connected to another input port RFIN. Figure 5 for Figure 4 The circuit schematic diagram corresponding to the layout structure in . Figure 5 M1 to M4 correspond to Figure 4 Among M1 to M4, the gate of M1 and the gate of M4 are connected to the input port LOP1, the gate of M2 and the gate of M3 are connected to the input port LON1, the source of M1 and the source of M2 are connected to the input port RFIP, the source of M3 and the source of M4 are connected to the input port RFIN, and the output ports of the first switch circuit are IFIP and IFIN. Figure 4 It can be seen that with this layout structure, the gate routing lengths of the four MOS transistors are inconsistent, which results in inconsistent gate parasitics. This directly destroys the symmetry of the MOS transistor routing and affects the linearity of the mixer. Therefore, it is necessary to solve the problem of MOS transistor routing asymmetry in the traditional mixer layout structure so that the parasitics of the gates of the four MOS transistors are consistent, thereby improving the linearity of the mixer.

[0125] The following describes a layout structure of a mixer provided by an embodiment of the present application, in which the parasitics of the gate of the MOS tube are consistent. The circuit schematic diagram corresponding to the layout structure of the mixer provided by the present application is a mixer circuit including two sets of switch circuits, Figure 1 This is an example of a circuit schematic corresponding to the layout structure. Figure 6 This application provides a mixer layout structure. Figure 6 As shown, M1 to M8 correspond to Figure 2 M1 to M8, Figure 6 The layout structure of the middle left half corresponds to Figure 2 The first switch circuit in the dotted box on the left (corresponding to the first MOS tube group), Figure 6 The layout structure in the middle right half corresponds to Figure 2 The second switch circuit in the dotted line on the right (corresponding to the second MOS tube group); the gate of M1 and the gate of M4 are directly connected through the first lead (601 in the figure), and the first lead is connected to one end of the third lead (603 in the figure), and the other end of the third lead is connected to the output port LOP1 of LO; the gate of M2 and the gate of M3 are directly connected through the second lead (602 in the figure), and the second lead is connected to one end of the fourth lead (604 in the figure), and the other end of the fourth lead is connected to the output port LON1 of LO; M The gate of M5 and the gate of M8 are directly connected through a lead, and the lead is connected to the output port LOP2 of LO through another lead. The gate of M6 and the gate of M7 are directly connected through a lead, and the lead is connected to the output port LON2 of LO through another lead. The drain of M1 and the drain of M3 are both connected to the output port IFIP, the drain of M2 and the drain of M4 are both connected to the output port IFIN, the drain of M5 and the drain of M7 are both connected to the output port IFQP, and the drain of M6 and the drain of M8 are both connected to the output port IFQN. Optionally, the first lead and the third lead are located on the same layer, and the second lead and the fourth lead are located on the same layer. It can be understood that Figure 6 The left half of the figure corresponds to the first layout area of ​​the first switch circuit (corresponding to the first MOS tube group). Figure 6 The right half of the figure corresponds to the second layout area of ​​the second switch circuit (corresponding to the second MOS tube group), and the first layout area and the second layout area are aligned left and right and symmetrical along the reference symmetry axis. Figure 6 and Figure 3 It can be seen that the main difference between the layout structure of the mixer provided in the embodiment of the present application and the layout structure of the traditional mixer is that the gate wiring lengths of the four MOS tubes in each group of switching circuits are consistent, which makes the parasitics of the gates of the MOS tubes the same. Figure 6In the layout structure of the mixer, the first lead between the gates of M1 and M4 and the second lead between the gates of M2 and M3 are located on different layers of the layout structure. In other words, the first lead and the second lead do not intersect. In the layout structure of the mixer provided in the embodiment of the present application, the layout structures of the two groups of switch tubes are symmetrical. To more conveniently describe the layout structure of each group of switch circuits in the layout structure of the mixer, the layout structure of one group of switch circuits is specifically described below.

[0126] Figure 7 A layout structure of a switch circuit provided in an embodiment of the present application, the circuit diagram corresponding to the layout structure is as follows Figure 5 shown. Figure 7 The layout structure of the switch circuit in FIG is an example of the layout structure of the first MOS tube group. Figure 7 As shown, the layout structure of the switch circuit includes a first MOS tube (ie Figure 7 M1 in), the second MOS tube (ie Figure 7 M2 in), the third MOS tube (ie Figure 7 M3 in) and the fourth MOS tube (i.e. Figure 7The gate of M1 and the gate of M4 are directly connected through a first lead (701 in the figure) and the first lead is connected to one end of a third lead (703 in the figure), and the other end of the third lead is connected to the input port LOP1 (corresponding to the first port) of LO; the gate of M2 and the gate of M3 are directly connected through a second lead (702 in the figure) and the second lead is connected to one end of a fourth lead (704 in the figure), and the other end of the fourth lead is connected to the output port LON1 (corresponding to the second port) of LO; M1 and M3 are aligned left and right and symmetrical along a first symmetry axis, M2 and M4 are aligned left and right and symmetrical along the first symmetry axis, M1 and M2 are aligned front and back and symmetrical along a second symmetry axis, M3 and M4 are aligned front and back and symmetrical along the second symmetry axis, and the first symmetry axis and the second symmetry axis are perpendicular to each other; the first lead (701 in the figure) between the gate of M1 and the gate of M4 passes through a first position, the gate of M2 and the gate of M3 The second lead (702 in the figure) between the gates passes through the second position, and the first position and the second position are the same position in different layers of the layout structure; the length of the lead from the gate of M1 to the first position, the length of the lead from the gate of M2 to the second position, the length of the lead from the gate of M3 to the second position, and the length of the lead from the gate of M4 to the first position are equal; one end of the third lead (703 in the figure) is connected to the third position of the first lead, and the other end is connected to the first port (i.e., the input port LOP1 in the figure); one end of the fourth lead (i.e., 704 in the figure) is connected to the fourth position of the second lead, and the other end is connected to the second port (i.e., the input port LON1 in the figure); the third position and the fourth position are symmetrical along the first symmetry axis; the layout structure is symmetrical along the first symmetry axis; the first lead and the second lead are located at different layers of the layout structure, and the third lead and the fourth lead are located at different layers of the layout structure. Optionally, the first position is the midpoint of the first lead, the second position is the midpoint of the second lead, and the first position, the second position, and the intersection of the first symmetry axis and the second symmetry axis are located at the same position in different layers of the layout structure. Optionally, the third position is the midpoint of the first lead, the fourth position is the midpoint of the second lead, and the third position, the fourth position, and the intersection of the first symmetry axis and the second symmetry axis are located at the same position in different layers of the layout structure. Optionally, the third position and the fourth position are not the same position in different layers of the layout structure. Optionally, the third position and the first position are the same position, and the fourth position and the second position are the same position. From Figure 7 It can be seen that the gate wirings of M1 to M4 have the same length, and the third lead and the fourth lead are symmetrical along the first symmetry axis. Thus, the gate parasitic capacitances of M1 to M4 are the same, and the linearity of the switching circuit is high.

[0127] In an optional implementation, if Figure 7As shown, the gates of M1 and M4 are directly connected to form the first lead, and the gates of M2 and M3 are directly connected to form the second lead. Both the first lead and the second lead are straight lines. In this implementation, the direct connection between the gates of M1 and M4, as well as the direct connection between the gates of M2 and M3, can effectively reduce the length of the leads and reduce costs.

[0128] In an optional implementation, if Figure 7 As shown, a portion of the third lead (703 in the figure) is located on one side of the first symmetry axis, while another portion of the third lead is located on the other side of the first symmetry axis. A portion of the fourth lead (704 in the figure) is located on one side of the first symmetry axis, while another portion of the fourth lead is located on the other side of the first symmetry axis. The third lead passes through the fifth position, and the fourth lead passes through the sixth position. The fifth and sixth positions are the same position on different layers in the above layout structure. In this implementation, the gate routing of M1-M4 passes through two crossover leads to the LO port (i.e., input ports LOP1 and LON1 in the figure), making the gate routing of M1-M4 strictly symmetrical, which can further improve the linearity of the switching circuit.

[0129] In an optional implementation, if Figure 7 As shown, the first portion of the third lead (7031 in the figure) and a portion of the second lead (702 in the figure) are located at the same position on different layers in the above-mentioned layout structure, the second portion of the third lead (7032 in the figure) is parallel to the first symmetry axis, the third portion of the third lead (7033 in the figure) is located on both sides of the first symmetry axis, and the fourth portion of the third lead (7034 in the figure) is parallel to the first symmetry axis; the first portion of the fourth lead (symmetrical with 7031 about the first symmetry axis) and a portion of the first lead are located at the same position on different layers in the above-mentioned layout structure, the second portion of the fourth lead (symmetrical with 7032 about the first symmetry axis) is parallel to the first symmetry axis, the third portion of the fourth lead (symmetrical with 7033 about the first symmetry axis) is located on both sides of the first symmetry axis, and the fourth portion of the fourth lead (symmetrical with 7034 about the first symmetry axis) is parallel to the first symmetry axis; the third portion of the third lead passes through the fifth position, and the third portion of the fourth lead passes through the sixth position. Optionally, the third lead and the first lead are located in the same layer of the layout structure, and the second lead and the fourth lead are located in the same layer of the layout structure. In this implementation, the first portion of the third lead and a portion of the second lead are located in the same position on different layers of the layout structure, and the first portion of the fourth lead and a portion of the first lead are located in the same position on different layers of the layout structure, which can effectively reduce the mutual influence between the leads.

[0130] Figure 7 In the layout structure, the gate traces of M1 to M4 pass through two crossover traces to the LO port (i.e., input ports LOP1 and LON1 in the figure). In the mixer layout structure, the gate traces of M1 to M4 can pass through at least one crossover trace to the LO port. Optionally, in the mixer layout structure, the gate traces of M1 to M4 can pass through an even number of crossover traces to the LO port; such a layout structure has better linearity performance. In the switch circuit layout structure, the gate traces of M1 to M4 can pass through a single crossover trace to the LO port. Figure 8 Another switch circuit layout structure provided in the embodiment of the present application, the circuit diagram corresponding to the layout structure is as follows Figure 5 shown. Figure 8 In FIG, 801 is the first lead, 802 is the second lead, 8031 ​​is the first part of the third lead, 8032 is the second part of the first lead, and 804 is the fourth lead. Figure 8 As shown, the first portion (8031) of the third lead and a portion of the second lead are at the same position on different layers of the layout structure, and the second portion (8032) of the third lead is parallel to the first axis of symmetry; the first portion of the fourth lead (symmetrical with 8031 ​​along the first axis of symmetry) and a portion of the first lead are at the same position on different layers of the layout structure, and the second portion of the fourth lead (symmetrical with 8032 along the first axis of symmetry) is parallel to the first axis of symmetry. Optionally, the third lead and the first lead are at the same layer of the layout structure, and the second lead and the fourth lead are at the same layer of the layout structure. Optionally, one end of the third lead is connected to the midpoint of the first lead, and one end of the fourth lead is connected to the midpoint of the second lead. Comparison Figure 7 and Figure 8 It can be seen that Figure 8 The layout structure and Figure 7 The difference in the layout structure is that the gate lines of M1 to M4 can pass through a crossover lead to the LO port. In this implementation, the third and fourth leads do not cross over but directly connect to the LO port, simplifying the routing.

[0131] In one optional implementation, in the mixer layout, the first and second switching circuits are placed in different deep N-wells (DNWs). In a traditional mixer layout, two sets of switching circuits are placed in the same deep N-well, one set corresponding to the I path and the other corresponding to the Q path, resulting in poor isolation between the I and Q paths. Figure 9A This is a traditional mixer layout structure. Figure 9A As shown, the first switch circuit and the second switch circuit are placed on the same deep N-well, resulting in poor isolation between the IQ paths. Figure 9BA mixer layout structure is provided in the embodiment of the present application. Figure 9B As shown, the first switch circuit is placed on DNW1 and the second switch circuit is placed on DNW2. That is, the first switch circuit and the second switch circuit are placed on different deep N wells to enhance the isolation between the IQ circuits. Figure 9B , Figure 9B The first switch circuit and the second switch circuit are arranged on different deep N wells, the first switch circuit corresponds to the I path, and the second switch circuit corresponds to the Q path, so that the isolation between the I and Q paths can be enhanced.

[0132] The layout structure of the switch circuit provided in the present application is a layout structure with better linearity performance. It is not limited to being applied to the layout structure of the mixer, but can also be applied to other circuits. In the present application, equality is not limited to being completely equal, but a certain deviation is allowed. One purpose of the scheme of the present application is to make the lengths of the wiring of the gates of each MOS as equal as possible, and it is not limited to the lengths of the wiring of the gates of each MOS being completely consistent. The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with the technical field of this application can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A switching circuit, characterized in that: The switch circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, wherein the gates of the first MOS transistor and the fourth MOS transistor are both connected to the first port, and the gates of the second MOS transistor and the third MOS transistor are both connected to the second port; The length of the lead between the gate of the first MOS transistor and the first port, the length of the lead between the gate of the second MOS transistor and the second port, the length of the lead between the gate of the third MOS transistor and the second port, and the length of the lead between the gate of the fourth MOS transistor and the first port are all equal; A first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through a first position, and a second lead between the gate of the second MOS transistor and the gate of the third MOS transistor passes through a second position. The first position and the second position are the same position on different layers in the switch circuit. The length of the lead from the gate of the first MOS transistor to the first position, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, and the length of the lead from the gate of the fourth MOS transistor to the first position are equal. The gates of the first MOS transistor and the fourth MOS transistor are directly connected to form the first lead, and the gates of the second MOS transistor and the third MOS transistor are directly connected to form the second lead. One end of a third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of a fourth lead is connected to the fourth position of the second lead, and the other end is connected to the second port; the third position and the fourth position are symmetrical along a first symmetry axis; the switch circuit is symmetrical along the first symmetry axis; A portion of the third lead is located on one side of the first symmetry axis, and another portion of the third lead is located on the other side of the first symmetry axis; a portion of the fourth lead is located on one side of the first symmetry axis, and another portion of the fourth lead is located on the other side of the first symmetry axis; the third lead passes through the fifth position, and the fourth lead passes through the sixth position, and the fifth position and the sixth position are the same position on different layers in the switching circuit.

2. The switching circuit according to claim 1, wherein: The first MOS transistor and the third MOS transistor are aligned left-right and symmetrical along a first symmetric axis, the second MOS transistor and the fourth MOS transistor are aligned left-right and symmetrical along the first symmetric axis, the first MOS transistor and the second MOS transistor are aligned front-to-back and symmetrical along a second symmetric axis, the third MOS transistor and the fourth MOS transistor are aligned front-to-back and symmetrical along the second symmetric axis, and the first symmetric axis and the second symmetric axis are perpendicular to each other.

3. The switching circuit according to claim 1 or 2, characterized in that: The first lead line and the second lead line are both straight lines.

4. The switching circuit according to claim 1, wherein: The first part of the third lead and a part of the second lead are located at the same position on different layers in the switching circuit, the second part of the third lead is parallel to the first symmetry axis, the third part of the third lead is located on both sides of the first symmetry axis, and the fourth part of the third lead is parallel to the first symmetry axis; the first part of the fourth lead and a part of the first lead are located at the same position on different layers in the switching circuit, the second part of the fourth lead is parallel to the first symmetry axis, the third part of the fourth lead is located on both sides of the first symmetry axis, and the fourth part of the fourth lead is parallel to the first symmetry axis; the third part of the third lead passes through the fifth position, and the third part of the fourth lead passes through the sixth position.

5. The switching circuit according to claim 1, wherein: The third lead is located on one side of the first symmetry axis, and the fourth lead is located on the other side of the first symmetry axis; a first portion of the third lead and a portion of the second lead are located at the same position on different layers in the switch circuit, and a second portion of the third lead is parallel to the first symmetry axis; A first portion of the fourth lead and a portion of the first lead are located at the same position on different layers in the switch circuit, and a second portion of the fourth lead is parallel to the first symmetry axis.

6. The switching circuit according to any one of claims 1, 4 or 5, characterized in that: The third position is the same as the first position, and the fourth position is the same as the second position.

7. A mixer, characterized in that: The switching circuit comprises the switching circuit according to any one of claims 1 to 6.

8. The mixer according to claim 7, wherein: The first port and the second port are both local oscillator ports for receiving a driving voltage; the source of the first MOS transistor and the source of the second MOS transistor are both connected to the first input port, and the source of the third MOS transistor and the source of the fourth MOS transistor are both connected to the second input port; the drain of the first MOS transistor and the drain of the third MOS transistor are both connected to the first output port, and the drain of the second MOS transistor and the drain of the fourth MOS transistor are both connected to the second output port.

9. The mixer according to claim 8, wherein: The first input port and the second input port are both connected to a low noise amplifier, and the first output port and the second output port are both connected to a transimpedance amplifier.

10. A mixer, characterized in that: The mixer includes a first MOS tube group and a second MOS tube group, wherein the circuit structure of the second MOS tube group is the same as that of the first MOS tube group; the first MOS tube group and the second MOS tube group are aligned left and right and symmetrical along a reference symmetry axis; the first MOS tube group includes a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube, wherein the gates of the first MOS tube and the fourth MOS tube are both connected to a first local oscillator port, and the gates of the second MOS tube and the third MOS tube are both connected to a second local oscillator port; The length of the lead between the gate of the first MOS transistor and the first local oscillator port, the length of the lead between the gate of the second MOS transistor and the second local oscillator port, the length of the lead between the gate of the third MOS transistor and the second local oscillator port, and the length of the lead between the gate of the fourth MOS transistor and the first local oscillator port are all equal; A first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through a first position, and a second lead between the gate of the second MOS transistor and the gate of the third MOS transistor passes through a second position. The first position and the second position are the same position on different layers in the mixer. The length of the lead from the gate of the first MOS transistor to the first position, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, and the length of the lead from the gate of the fourth MOS transistor to the first position are equal. The gates of the first MOS transistor and the fourth MOS transistor are directly connected to form the first lead, and the gates of the second MOS transistor and the third MOS transistor are directly connected to form the second lead. One end of a third lead is connected to the third position of the first lead, and the other end is connected to the first local oscillator port; one end of a fourth lead is connected to the fourth position of the second lead, and the other end is connected to the second local oscillator port; the third position and the fourth position are symmetrical along a first symmetry axis; the mixer is symmetrical along the first symmetry axis; A portion of the third lead is located on one side of the first symmetry axis, and another portion of the third lead is located on the other side of the first symmetry axis; a portion of the fourth lead is located on one side of the first symmetry axis, and another portion of the fourth lead is located on the other side of the first symmetry axis; the third lead passes through a fifth position, and the fourth lead passes through a sixth position, and the fifth position and the sixth position are the same position on different layers in the mixer.

11. The mixer according to claim 10, wherein: The first MOS transistor group and the second MOS transistor group are placed on different deep N wells.

12. An electronic device, characterized in that: The mixer comprises the mixer according to any one of claims 7 to 9.

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