Display panel and display device

Abstract

The present invention provides a display panel and a display device, which relate to the field of display technology. Among them, the first and second sides of the display panel are respectively provided with gate driving circuits, and the gate driving circuit includes at least two gate driving sub-circuits, and the gate driving sub-circuits located on the first / second side are respectively connected to the input signal terminal, the power supply terminal, the clock signal terminal, and the pixel circuit of the first / second pixel in the corresponding pixel row close to the first / second side; the gate driving sub-circuit located on the first / second side responds to the input signal, the power supply signal and the clock signal, and outputs a gate signal to the pixel circuit of the first / second pixel in the corresponding pixel row. In an embodiment of the present invention, each gate driving sub-circuit is in a cascade relationship, and there is no cascade relationship between the gate driving sub-circuits. The corresponding pixel row is driven by multiple independent gate driving sub-circuits, which shortens the attenuation path of the cascade signal and improves the life and driving ability of the gate driving circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Nowadays, with the rapid development of display technology, the demand for high-end display products such as ultra-large size, ultra-high resolution and ultra-high refresh rate is more urgent.

[0003] The display panel can output the gate signal through the GOA circuit (Gate on Array, gate drive circuit). As the display time increases, the TFT (Thin Film Transistor) in the GOA circuit will have a positive drift in characteristics, resulting in a decrease in the threshold voltage of the TFT. Due to the cascade carry relationship of each GOA unit inside the GOA circuit, the cascade carry signal inside the GOA circuit will gradually attenuate due to the positive drift of the TFT characteristics. When the signal attenuates to a level that is insufficient to effectively charge the PU point (pull-up node) of the GOA unit, the GOA unit will be unable to output a signal, resulting in an abnormal display. Summary of the invention

[0004] The present invention provides a display panel and a display device to solve the problem of abnormal display caused by attenuation of cascade carry signals inside a GOA circuit in the existing display panel.

[0005] In order to solve the above problem, the present invention discloses a display panel, wherein a gate driving circuit is respectively arranged on a first side and a second side opposite to each other of the display panel, and the display panel further comprises a plurality of pixel rows, wherein the pixel rows comprise a plurality of first pixels close to the first side and a plurality of second pixels close to the second side;

[0006] The gate driving circuit includes at least two gate driving sub-circuits, the gate driving sub-circuits are respectively connected to an input signal terminal, a power supply terminal and a clock signal terminal, the gate driving sub-circuit located on the first side is also connected to a pixel circuit of the first pixel in the corresponding pixel row, and the gate driving sub-circuit located on the second side is also connected to a pixel circuit of the second pixel in the corresponding pixel row;

[0007] The gate driving subcircuit located on the first side is configured to output a gate signal to a pixel circuit of the first pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power terminal, and a clock signal provided by the clock signal terminal;

[0008] The gate driving subcircuit located on the second side is configured to output a gate signal to the pixel circuit of the second pixel in the corresponding pixel row in response to the input signal provided by the input signal terminal, the power signal provided by the power terminal, and the clock signal provided by the clock signal terminal.

[0009] Optionally, the gate driving subcircuit includes a plurality of cascaded shift registers, the shift registers include a plurality of thin film transistors, and the thin film transistors include an oxide channel layer.

[0010] Optionally, the gate driving subcircuit located on the first side is connected to the pixel circuits of the first pixels in the pixel rows of a first preset number of rows, and the first preset number of rows is greater than or equal to 1080 and less than or equal to 2160.

[0011] Optionally, the gate driving subcircuit located on the second side is connected to the pixel circuits of the second pixels of the pixel rows of a second preset number of rows, and the second preset number of rows is greater than or equal to 1080 and less than or equal to 2160.

[0012] Optionally, the gate driving sub-circuit is also connected to a reset signal terminal; the gate driving sub-circuit is also configured to reset the gate driving sub-circuit in response to a reset signal provided by the reset signal terminal and a power signal provided by the power terminal.

[0013] In order to solve the above problem, the present invention further discloses a display device, comprising the above display panel.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] In an embodiment of the present invention, a gate driving circuit is respectively provided on a first side and a second side opposite to each other of the display panel, and the gate driving circuit includes at least two gate driving sub-circuits, and the gate driving sub-circuits are respectively connected to an input signal terminal, a power supply terminal and a clock signal terminal, and the gate driving sub-circuit located on the first side is also connected to a pixel circuit of a first pixel in a corresponding pixel row close to the first side, and the gate driving sub-circuit located on the second side is also connected to a pixel circuit of a second pixel in a corresponding pixel row close to the second side; the gate driving sub-circuit located on the first side is configured to output a gate signal to the pixel circuit of the first pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power supply terminal and a clock signal provided by the clock signal terminal; the gate driving sub-circuit located on the second side is configured to output a gate signal to the pixel circuit of the second pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power supply terminal and a clock signal provided by the clock signal terminal. In an embodiment of the present invention, each gate driving sub-circuit is internally cascaded, but there is no cascade relationship between each gate driving sub-circuit. The corresponding pixel rows are driven by multiple independent gate driving sub-circuits, which shortens the attenuation path of the cascade signal and improves the life and driving capability of the gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 An existing 21T1C GOA circuit diagram is shown;

[0017] Figure 2 A schematic diagram of a gate drive circuit of an existing bilaterally driven 110-inch 8K 120Hz display product is shown;

[0018] Figure 3 An internal cascade schematic diagram of an existing gate drive circuit is shown;

[0019] Figure 4 A schematic diagram for analyzing the Vth characteristic drift of a TFT in an existing GOA circuit is shown;

[0020] Figure 5 Another schematic diagram for analyzing the Vth characteristic drift of a TFT in an existing GOA circuit is shown;

[0021] Figure 6 A life simulation result of an existing GOA circuit is shown;

[0022] Figure 7 Shows the Figure 6 Schematic diagram of output waveform simulation of the 1st to 9th GOA units in the simulation data of 0W hours;

[0023] Figure 8A schematic diagram showing the changing trend of the rise time of the output waveform of each GOA unit at different bias times in an existing GOA circuit is shown;

[0024] Fig. 9 A schematic diagram showing a variation trend of the falling time of the output waveform of each GOA unit at different bias times in an existing GOA circuit is shown;

[0025] Fig.10 A schematic diagram showing a variation trend of the output high level voltage Vmax of the output waveform of each GOA unit at different bias times in an existing GOA circuit is shown;

[0026] Fig.11 A schematic diagram of a display panel according to a first embodiment of the present invention is shown;

[0027] Fig.12 A schematic diagram of a driving architecture of a display panel according to a first embodiment of the present invention is shown;

[0028] Fig.13 A schematic diagram of gate driving timing of the first embodiment of the present invention is shown;

[0029] Fig.14 The figure shows the life simulation result of a gate driving circuit according to the first embodiment of the present invention;

[0030] Fig.15 A schematic diagram showing a change trend of the rise time of the output waveform of each GOA unit at different bias times in a gate driving sub-circuit in the first embodiment of the present invention is shown;

[0031] Fig.16 A schematic diagram showing a variation trend of the falling time of the output waveform of each GOA unit at different bias times in a gate driving sub-circuit in the first embodiment of the present invention is shown;

[0032] Fig.17 A schematic diagram showing a variation trend of an output high-level voltage Vmax of an output waveform of each GOA unit at different bias times in a gate driving sub-circuit in the first embodiment of the present invention is shown. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Embodiment 1

[0035] At present, the super-large display products on the market are mainly 86 inches, 98 inches and other sizes, with low resolution (4K) and low refresh rate (60Hz). At the same time, because the TFT gate adopts COF (Chip On Flex, or Chip On Film) design, the production cost is higher, which is not conducive to the marketization of super-large products.

[0036] In addition, the TFT channel of the current LCD (Liquid Crystal Display) technology route generally adopts a-Si process. The channel mobility of a-Si material itself is low, which further restricts the development of ultra-large size, ultra-high resolution and ultra-high refresh rate. Therefore, oxide channel material with higher mobility can be used to design ultra-large size, ultra-high resolution and ultra-high refresh rate display products. However, oxide material itself has a low affinity to H2O and H + Therefore, the oxide TFT characteristics are prone to positive drift, which leads to a decrease in the threshold voltage Vth of the TFT and a decrease in the on-state current Ion of the TFT channel.

[0037] For the GOA circuit including oxide TFT, the channel width of TFT in the GOA circuit is large and the bias voltage is large. Therefore, the GOA TFT is prone to drift, especially Figure 1 As shown in the figure, the two TFTs M3 and M13 in the GOA circuit of the 21T1C have larger channel widths in the GOA circuit, are subjected to larger bias voltages and longer bias time, and the large current flowing through the TFTs themselves causes serious heating of the TFTs. The excessively high temperature further stimulates the generation of defect states in the TFT channel, further reducing the potential barrier for carrier capture. Therefore, the threshold voltage Vth drift of the TFTs in the GOA is more serious.

[0038] Reference Figure 1 , M3 is mainly responsible for opening the corresponding grid line. The large size and high resolution of the super-large display product result in a heavy load on the grid line. Figure 2 Taking the 110-inch 8K 120Hz display product with double-sided gate drive as an example, the gate line resistance is generally around 5K, the overlap capacitance is generally around 1000pF, the delay of the entire gate line is about 1.25us, and the actual charging time of the pixel is only about 2.45us. The charging time is extremely short. Therefore, the M3 must be designed with a large enough channel width to ensure that M3 can provide sufficient driving capability.

[0039] Reference Figure 1, M13 is mainly responsible for the cascade carry relationship within the GOA circuit. The GOA circuit is composed of several GOA units (i.e., shift registers). Figure 2 Taking the 110-inch 8K 120Hz display product with bilateral gate drive as an example, the resolution is 7680*4320, and there are 4320 vertical rows of pixels. Both sides require 4320 gate lines to control the opening of the pixels in this row, and each gate line must be turned on by the GOA unit connected to the gate line. Therefore, for a single-sided GOA circuit, 4320 GOA units must be designed for driving, plus 12 Dummy GOA units responsible for the reset function of the GOA circuit (used to reset the last few GOA units). A GOA circuit is composed of a total of 4320+12=4332 GOA units.

[0040] Among them, the 4332 GOA units follow a strict carry-reset relationship. Figure 3 , the carry relationship is N→N+5 (5 is just an example), that is, M13 of the Nth GOA unit outputs a high-level signal to the input end of the N+5th GOA unit, charges the PU point of the N+5th GOA unit, and triggers the N+5th GOA unit to start working. Similarly, M13 of the N+5th unit outputs a high-level signal to the input end of the N+10th GOA unit, charges the PU point of the N+10th GOA unit, and triggers the N+10th GOA unit to start working, and so on. Figure 3 , the reset relationship is N+6→N (6 is only an example), that is, the N+6th GOA unit M13 outputs a high level to the reset end of the Nth GOA unit, discharges the PU point of the Nth GOA unit, so as to lower the PU potential and trigger the Nth GOA unit to end the work. Similarly, the Nth GOA unit M13 outputs a high level to the reset end of the N-6th GOA unit, discharges the PU point of the N-6th GOA unit, so as to lower the PU potential and trigger the N-6th GOA unit to end the work.

[0041] 4332 GOA units are arranged in sequence from DPO (Data Pad Opposite) to DP (Data Pad). Figure 3 In a corresponding example, the 1st, 2nd, 3rd, 4th and 5th GOA units are triggered by the GOA circuit trigger signal STV, and the remaining GOA units are triggered only by the internal cascade carry relationship, that is, the output signals of the 1st, 2nd, 3rd, 4th and 5th GOA units are transmitted to the next level GOA unit step by step according to the carry relationship, and the next level GOA unit resets the previous level GOA unit in time. The internal signal of GOA is transmitted from the 1st GOA unit to the 4332nd GOA unit in sequence through the cascade relationship, and finally the row-by-row scan is completed.

[0042] However, as the display time increases, the GOA internal cascade carry signal will gradually attenuate due to the positive drift of the TFT characteristics. When the signal attenuates to a point where it is insufficient to effectively charge the PU point of the GOA unit, the GOA unit will be unable to output a signal, causing the entire GOA circuit to fail.

[0043] The above-mentioned GOA circuit failure analysis is applicable to both a-Si channel layer TFT and oxide channel layer TFT. For a-Si process, TFT characteristics are stable and Vth drift is low, but a-Si process cannot realize the design of ultra-large size, ultra-high resolution and ultra-high refresh rate display products, so the oxide process is needed. However, under the oxide process conditions, TFT characteristics are unstable and Vth drift is serious, which will further accelerate the attenuation of the GOA internal cascade signal, accelerate the failure of the GOA circuit, and cause the life of the display device to drop sharply.

[0044] In the following, the attenuation mechanism of the internal cascade signal of GOA is theoretically explained, and a new display panel solution is proposed for ultra-large size, ultra-high resolution and ultra-high refresh rate display.

[0045] Figure 4 and Figure 5 Two schematic diagrams of analyzing the Vth characteristic drift of the TFT in the GOA circuit (hereinafter referred to as GOA TFT) are shown respectively, referring to Figure 4 As the TFT is affected by the bias time, its characteristics gradually drift, and the Ids-Vgs curve gradually drifts in the positive direction. Usually, the Ion value can be used to measure the conduction ability of the TFT. The larger the Ion, the larger the conduction current of the TFT and the stronger the conduction ability. Generally, the current value corresponding to the TFT Vgs voltage and Vds voltage of 15V is defined as the Ion value. Figure 5 As shown in FIG. 1 , when the characteristics of the TFT drift in the positive direction, the Ion value corresponding to Vgs=Vds=15V decreases. The decrease in the Ion value means that the conduction capability of the TFT decreases.

[0046] Figure 6 The life simulation results of the current GOA circuit are shown, and the GOA unit output waveform after the bias voltage is applied for 0W (10,000), 1W, 2W, 3W, 4W, 4.1W, 4.2W, 4.3W, 4.4W and 4.5W hours is simulated for the current GOA circuit. Figure 6 In the figure, the horizontal coordinates of the 10 sets of data are all time, and the vertical coordinates are all output voltage. Each set of data is obtained by merging the output waveforms of the 1st to 9th GOA units into the same coordinate graph. Figure 7 , Figure 7The 9 output waveforms shown in the figure are the simulation data of 0W hour. The output waveforms of the 1st to 9th GOA units are combined into the same coordinate diagram to obtain Figure 6 The first set of data in .

[0047] Reference Figure 6 In the simulations of 0W, 1W, 2W, 3W, and 4W hours, the output waveforms of the GOA units were all normal. In the simulation of 4.4W hours, the last GOA unit had no output, indicating that the Vth drift attenuated the internal cascade carry signal of the GOA, and eventually made the last GOA unit unable to output. In the simulations of 4.2W, 4.3W, 4.4W, and 4.5W hours, the GOA output waveform became increasingly abnormal. Therefore, the simulated life of the GOA circuit can be determined to be 4W hours.

[0048] Figure 8 , Fig. 9 and Fig.10 The rise time (Tr), fall time (Tf) and output high level voltage Vmax of each GOA unit at 0W, 1W, 2W, 3W, 4W and 4.1W are shown respectively. Figure 8 , Fig. 9 and Fig.10In the simulation of 0W, 1W, 2W and 3W hours, the Tr (in microseconds μs) and Tf (in microseconds μs) of each level of GOA unit are gradually decreasing, and Vmax is basically flat. In the simulation of 0W hours, it is believed that the GOA TFT is not affected by the bias stress, the TFT characteristics are the initial characteristics, and the Ion value level is the highest level. When the GOA circuit is scanned line by line from the DPO side to the DP side, the GOA drive signal such as CLK (clock signal) and other signals gradually increase (the DP side is the PCB bonding side, and the GOA unit close to the DP side is closer to the signal source of the GOA circuit), and the RC load of the CLK signal gradually decreases, and the output capacity of the GOA circuit becomes stronger and stronger. Therefore, when the GOA circuit is scanned line by line from the DPO side to the DP side, the Tr and Tf of the GOA output waveform gradually decrease, which means that the output signal rise Delay (delay) and fall Delay are smaller. This is because the high-level signals actually output by M3 and M13 in the GOA unit are the CLK signals connected to the GOA unit of this row, which are used as the GOA output signal and the GOA internal cascade signal, respectively, for the carry and reset inside the GOA circuit. From the DPO side to the DP side, the CLK signal becomes stronger and stronger, that is, the GOA cascade signal becomes stronger and stronger. Therefore, the output of the GOA unit becomes stronger and stronger, that is, in the process of the GOA circuit scanning from the DPO side to the DP side line by line, the Tr and Tf of the GOA output waveform gradually decrease. In addition, because the high level of the output voltage of the GOA unit close to the DPO side has reached the peak value, the Vmax of the GOA units at all levels remain basically consistent.

[0049] For the three groups of simulation data of 1W, 2W, and 3W hours, in the same group of simulation data, Tr and Tr of different GOA units showed a gradual downward trend, and Vmax showed a flat trend. In addition, in different groups of simulation data, Tr&Tf of the same GOA unit showed a gradual increasing trend, and Vmax showed a flat trend. The above results show that with the increase of bias application time, the output capacity of the GOA circuit is gradually decreasing, but under the same bias application time conditions, Tr and Tf of GOA units at all levels still maintain a downward trend.

[0050] Taking the Nth GOA unit as an example, the corresponding next-level GOA unit is the N+5th GOA unit. The strength of the CLK signal output by the N+5th GOA unit is determined by the following three factors:

[0051] The first aspect is the strength of the carry signal of the N+5th GOA unit, that is, the output signal of the Nth GOA unit;

[0052] The second aspect is that after Vth drifts, the ability of the N+5th GOA unit to output a high level of CLK decreases;

[0053] The third aspect is that the strength of the CLK signal connected to the N+5th GOA unit itself is enhanced.

[0054] The output signal strength of the Nth GOA unit weakens after the Vth drift. This signal serves as the carry signal of the N+5th GOA unit, resulting in the weakening of the gate voltage strength of M3 and M13 of the N+5th GOA unit. Because the N+5th GOA also has a reduced ability to output a high level CLK after the Vth drift, the first and second aspects will result in a reduction in the ability of the GOA circuit to output a high level CLK. However, the CLK signal strength tends to increase, thus forming a competitive relationship between the gradual decrease in the output capacity of the GOA unit and the gradual increase in the CLK signal.

[0055] If the weakening effect of the GOA unit output signal caused by the decrease in the output capacity of the GOA unit is weaker than the strengthening effect of the GOA unit output signal caused by the enhancement of the CLK signal, in this case, the output capacity of the GOA units at all levels will gradually increase. If the weakening effect of the GOA unit output signal caused by the decrease in the output capacity of the GOA unit is stronger than the strengthening effect of the GOA unit output signal caused by the enhancement of the CLK signal, in this case, the output capacity of the GOA units at all levels will gradually weaken.

[0056] Under the bias conditions of 1W, 2W, and 3W hours, although the output capacity of the GOA unit decreases due to Vth drift, it is still at a competitive disadvantage in the above-mentioned competitive relationship, while the gradual increase of the CLK signal from the DPO side to the DP side is at a competitive advantage. Therefore, the enhancement effect of the CLK signal is greater than the decrease effect of the GOA unit output capacity, and ultimately it still reflects the trend of the gradual increase in the output of each level of GOA units from the DPO side to the DP side.

[0057] Under the bias condition of 4W hours, Vth drifts further and the output capacity of the GOA unit is further reduced. However, at this time, the reduction in the output capacity of GOA has become the dominant advantage in the competitive relationship. Therefore, Tr and Tf begin to gradually increase (the output Delay gradually increases), and Vmax begins to show a downward trend, indicating that when the bias is applied for 4W hours, the output from the DPO side to the DP side has gradually decayed inside the GOA circuit. When the bias is applied for 4.1W hours, Vth drifts further, the output capacity of GOA is further reduced, and the reduction effect is more obvious. Tr and Tf increase significantly, and Vmax decreases significantly. The last-level GOA unit cannot output normally (Vmax voltage is 0V). At this time, the corresponding Tr and Tf times cannot be detected, indicating that the GOA circuit has failed and the life of the GOA circuit has ended.

[0058] In summary, after the bias voltage is applied for a certain period of time, when the output capacity of the GOA unit decreases to a certain extent, the output signal of the GOA unit will inevitably decay when scanning from the DPO side to the DP side line by line until the GOA circuit fails. Therefore, by reducing the attenuation of the GOA unit output signal, the life of the GOA circuit can be greatly improved.

[0059] For ultra-large-size, ultra-high-resolution display devices, firstly, the Vth sensitivity of the oxide channel TFT itself is high (Vth drift is prone to occur); secondly, the attenuation path of the GOA circuit is longer, and the attenuation path corresponding to 8K display products is 4320 GOA units, and the attenuation path corresponding to 16K display products will reach 8640 GOA units; thirdly, the heating effect of the thin-film transistors M3 and M13 with larger channel widths will cause Vth to drift further. The combined influence of the above three factors restricts the life of the GOA circuit of large-size display products.

[0060] However, no effective measures have been found to improve the Vth sensitivity of the oxide process itself and the heating effect of thin-film transistors M3 and M13 with larger channel widths. This is because for the high-mobility oxide process, the oxide material itself and the conductive mechanism determine its characteristic sensitivity. At the same time, large-size display products will inevitably develop in the direction of larger size, higher resolution and refresh rate in the future, which means that the driving capability of the GOA circuit will be increasingly required, and the RC Loading (impedance load) of the entire circuit will inevitably increase. Therefore, the channel size of the thin-film transistors M3 and M13 can only be designed to be larger and larger, and the heating effect will only become more and more serious. Therefore, the only measure that can effectively improve the life of the GOA circuit of large-size display products is to reduce the attenuation path of the GOA circuit.

[0061] The inventors conducted an AD (Abnormal Display) failure analysis on the GOA circuit of a 65-inch 8K display device. When the AD level is relatively mild, scanning horizontal stripes appear only on the DP side, indicating that the GOA unit close to the DP side first outputs abnormally, and the DPO side displays normally. From the DPO side to the DP side, the GOA unit output attenuates, which is consistent with the attenuation mechanism proposed above. When the AD level is severe, only some GOA units close to the DPO side can be turned on normally, and the remaining GOA units all output abnormally. The measured abnormal waveform shows Multi Output (many continuous high-level outputs), which is consistent with the simulation results of applying a bias voltage of 4.3W for hours.

[0062] In summary, the output waveform of the GOA circuit gradually decays from the far end of the scan (DPO side) to the near end of the scan (DP side), and the output signal of the GOA unit close to the DP side decays most severely. Therefore, the GOA unit close to the DP side is the first to have output abnormality. As the bias application time increases, the attenuation becomes more serious, and the abnormal display area gradually expands to the DPO side, eventually leading to full-screen display abnormality.

[0063] Fig.11 A schematic diagram of a display panel according to the first embodiment of the present invention is shown. Fig.11 , a gate driving circuit 10 is respectively disposed on a first side A and a second side B opposite to each other of the display panel, and the display panel further comprises a plurality of pixel rows 20, wherein the pixel rows 20 comprise a plurality of first pixels 201 close to the first side A, and a plurality of second pixels 202 close to the second side B;

[0064] The gate driving circuit 10 includes at least two gate driving sub-circuits 11, and the gate driving sub-circuits 11 are respectively connected to an input signal terminal 111, a power terminal 112, and a clock signal terminal 113, and the gate driving sub-circuit 11 located at the first side A is also connected to a pixel circuit 203 of the first pixel 201 in the corresponding pixel row 20, and the gate driving sub-circuit 11 located at the second side B is also connected to a pixel circuit 204 of the second pixel 202 in the corresponding pixel row 20;

[0065] The gate driving sub-circuit 11 located at the first side A is configured to output a gate signal to the pixel circuit 203 of the first pixel 201 in the corresponding pixel row 20 in response to the input signal provided by the input signal terminal 111, the power signal provided by the power terminal 112, and the clock signal provided by the clock signal terminal 113;

[0066] The gate driving subcircuit 11 located on the second side B is configured to output a gate signal to the pixel circuit 204 of the second pixel 202 in the corresponding pixel row 20 in response to the input signal provided by the input signal terminal 111, the power signal provided by the power terminal 112, and the clock signal provided by the clock signal terminal 113.

[0067] For a display panel with ultra-large size, ultra-high resolution and ultra-high frequency, the embodiment of the present invention adopts a bilateral driving method to drive the gate of the pixel circuit, wherein, referring to Fig.11, the gate driving circuit 10 on each side is divided into at least two independent gate driving sub-circuits 11, and each gate driving sub-circuit 11 can be used to drive the pixels in the corresponding pixel row 20. The gate driving sub-circuit 11 located on the first side A of the display panel can be used to drive the first pixel 201 in the corresponding pixel row 20, and the gate driving sub-circuit 11 located on the second side B of the display panel can be used to drive the second pixel 202 in the corresponding pixel row 20. In specific applications, the number of the first pixel 201 and the second pixel 202 can be equal.

[0068] In an embodiment of the present invention, each gate driving sub-circuit 11 is internally cascaded, and each gate driving sub-circuit 11 can be driven independently. Compared with driving all pixel rows through internally cascaded gate driving circuits, driving corresponding pixel rows through multiple independent gate driving sub-circuits 11 shortens the attenuation path of the cascade signal and improves the life and driving capability of the gate driving circuit.

[0069] Optionally, the gate driving subcircuit 11 located at the first side A is connected to the pixel circuit 203 of the first pixel 201 of the pixel row 20 of a first preset number of rows, and the first preset number of rows is greater than or equal to 1080 and less than or equal to 2160.

[0070] Optionally, the gate driving subcircuit 11 located at the second side B is connected to the pixel circuit 204 of the second pixel 202 of the pixel row 20 of a second preset number of rows, and the second preset number of rows is greater than or equal to 1080 and less than or equal to 2160.

[0071] In an embodiment of the present invention, for large-size and ultra-large-size display panels, each gate driving sub-circuit 11 can control pixel circuits of 1080 to 2160 pixel rows 20, thereby shortening the attenuation path of the cascade signal and ensuring the advantages of the cascade relationship itself.

[0072] In an optional embodiment, the gate drive circuit 10 on each side can be divided into 4 independent gate drive sub-circuits 11 for driving. If calculated with 8K resolution (7680*4320), the existing attenuation path in the AA area has 4320 GOA units. After division, the attenuation path corresponding to each gate drive sub-circuit 11 has only 1080 GOA units. The attenuation path is the same as that of FHD (Full High Definition) resolution display products, and the attenuation path is reduced by 75%.

[0073] Fig.12 A schematic diagram of a driving architecture of a display panel according to the first embodiment of the present invention is shown. Fig.12Taking the example that the gate driving circuit 10 on each side is divided into four independent gate driving sub-circuits 11, the four gate driving sub-circuits 11 on a single side are respectively provided by the corresponding input signal terminals 111 with input signals STV1, STV2, STV3 and STV4 to control the input of the first few GOA units in the gate driving sub-circuit 11, and the input control of the subsequent GOA units is realized by the cascaded carry signal.

[0074] Optionally, refer to Fig.11 The gate driving sub-circuit 11 is also connected to the reset signal terminal 114; the gate driving sub-circuit 11 is also configured to reset the gate driving sub-circuit 11 in response to the reset signal provided by the reset signal terminal 114 and the power signal provided by the power terminal 112.

[0075] Reference Fig.12 The four gate driving sub-circuits 11 on one side can be reset by a reset signal STV0 provided by a reset signal terminal 114 to control the reset of the last few GOA units, and the reset control of the previous GOA units is realized by the cascaded reset signal. Of course, all GOA units can also be reset directly by the reset signal STV0, and the embodiment of the present invention does not make specific limitations on this.

[0076] In the embodiment of the present invention, optionally, the power signal provided by the power terminal 112 may specifically include: Figure 1 The VGL, LVGL, VDDO and VDDE (VDDO and VDDE may also be referred to as VDD1 and VDD2) and other signals shown in the figure, the clock signal provided by the clock signal terminal 113 may specifically include a CLK signal, and specific reference may be made to related technologies, which is not specifically limited in the embodiment of the present invention.

[0077] Also optionally, the gate driving subcircuit 11 includes a plurality of cascaded shift registers, the shift registers include a plurality of thin film transistors, and the thin film transistors include an oxide channel layer.

[0078] In the embodiment of the present invention, since the oxide channel layer is sensitive to H2O, H + Therefore, the oxide TFT is prone to positive drift, which leads to a decrease in the threshold voltage Vth of the oxide TFT and a decrease in the on-state current Ion of the oxide channel. The embodiments of the present invention shorten the attenuation path of the cascade signal, thereby improving the life and driving capability of the gate drive circuit of the thin film transistor including the oxide channel.

[0079] Fig.13 A schematic diagram of a gate drive timing sequence of the first embodiment of the present invention is shown. Taking an 8K display product as an example, the 8K display product adopts a 10CLK design. Fig.13 , the phases of the clock signals CLK1-CLK10 are delayed by 1H in sequence, and in the gate drive sub-circuit 11, the 1st to 10th GOA units use CLK1-CLK10 respectively, the 11th to 20th GOA units use CLK1-CLK10 respectively, the 21st to 30th GOA units use CLK1-CLK10 respectively, and so on. Among them, 1H refers to the minimum unit time for charging the pixel.

[0080] STV1-STV4 are used as the start-up signals of the four gate drive sub-circuits 11 on one side. They are pulled high and maintained for 5 hours at the moment 1 hour before the first GOA unit in the four gate drive sub-circuits 11 outputs the corresponding CLK1 high level. The four gate drive sub-circuits 11 are gradually turned on. Each gate drive sub-circuits 11 are cascaded according to the carry reset relationship. There is no cascade relationship between the four gate drive sub-circuits 11. The reset of the four gate drive sub-circuits 11 only requires one reset signal STV0. They are pulled high to a high level 4 times at the moment 1 hour after the last GOA unit in the four gate drive sub-circuits 11 outputs the corresponding CLK10 high level, and each pull-up is maintained for 5 hours.

[0081] Fig.14 The life simulation result of a gate drive circuit of the first embodiment of the present invention is shown, and the output waveform of the GOA unit after bias application of 0W, 1W, 2W, 3W, 4W, 5W, 5.2W and 5.4W hours is simulated for the gate drive circuit. Fig.14 In the figure, the horizontal coordinates of the eight groups of data are all time, and the vertical coordinates are all output voltages, wherein each group of data is obtained by merging the output waveforms of the 1st to 9th GOA units into the same coordinate graph.

[0082] Reference Fig.14 In the simulations of 0W, 1W, 2W, 3W, 4W, 5W and 5.2W hours, the output waveforms of the GOA units were all normal. In the simulation of 5.4W hours, the output waveform of the last GOA unit showed an abnormal output of Multi Output, indicating that the gate drive circuit failed. Therefore, the life of the gate drive circuit simulated by the embodiment of the present invention can be determined to be 5.2W hours. Compared with the existing 4W hour life, the life of the gate drive circuit is increased by 30% without adding any additional cost, effectively extending the life of the oversized Oxide GOA circuit.

[0083] Fig.15 , Fig.16 and Fig.17The rise time (Tr), fall time (Tf) and output high level voltage Vmax of the output waveform of each GOA unit at 0W, 1W, 2W, 3W, 4W, 5W, 5.2W and 5.4W of the embodiment of the present invention are shown respectively. Fig.15 , Fig.16 and Fig.17 , Tr (in microseconds μs) and Tf (in microseconds μs) both increase with the increase of bias time, and Vmax decreases with the increase of bias time. The changing trend is consistent with the attenuation mechanism described above and will not be repeated here.

[0084] In an embodiment of the present invention, a gate driving circuit is respectively provided on a first side and a second side opposite to each other of the display panel, and the gate driving circuit includes at least two gate driving sub-circuits, and the gate driving sub-circuits are respectively connected to an input signal terminal, a power supply terminal and a clock signal terminal, and the gate driving sub-circuit located on the first side is also connected to a pixel circuit of a first pixel in a corresponding pixel row close to the first side, and the gate driving sub-circuit located on the second side is also connected to a pixel circuit of a second pixel in a corresponding pixel row close to the second side; the gate driving sub-circuit located on the first side is configured to output a gate signal to the pixel circuit of the first pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power supply terminal and a clock signal provided by the clock signal terminal; the gate driving sub-circuit located on the second side is configured to output a gate signal to the pixel circuit of the second pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power supply terminal and a clock signal provided by the clock signal terminal. In an embodiment of the present invention, each gate driving sub-circuit is internally cascaded, but there is no cascade relationship between each gate driving sub-circuit. The corresponding pixel rows are driven by multiple independent gate driving sub-circuits, which shortens the attenuation path of the cascade signal and improves the life and driving capability of the gate driving circuit.

[0085] Embodiment 2

[0086] An embodiment of the present invention further discloses a display device, comprising the above-mentioned display panel.

[0087] In an embodiment of the present invention, a gate driving circuit is respectively provided on a first side and a second side opposite to each other of the display panel, and the gate driving circuit includes at least two gate driving sub-circuits, and the gate driving sub-circuits are respectively connected to an input signal terminal, a power supply terminal and a clock signal terminal, and the gate driving sub-circuit located on the first side is also connected to a pixel circuit of a first pixel in a corresponding pixel row close to the first side, and the gate driving sub-circuit located on the second side is also connected to a pixel circuit of a second pixel in a corresponding pixel row close to the second side; the gate driving sub-circuit located on the first side is configured to output a gate signal to the pixel circuit of the first pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power supply terminal and a clock signal provided by the clock signal terminal; the gate driving sub-circuit located on the second side is configured to output a gate signal to the pixel circuit of the second pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power supply terminal and a clock signal provided by the clock signal terminal. In an embodiment of the present invention, each gate driving sub-circuit is internally cascaded, but there is no cascade relationship between each gate driving sub-circuit. The corresponding pixel rows are driven by multiple independent gate driving sub-circuits, which shortens the attenuation path of the cascade signal and improves the life and driving capability of the gate driving circuit.

[0088] For the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the order of the actions described, because according to the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0089] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0090] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0091] The display panel and display device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display panel, characterized in that: A gate driving circuit is disposed on a first side and a second side opposite to the display panel, respectively. The display panel further comprises a plurality of pixel rows, wherein the pixel rows comprise a plurality of first pixels close to the first side and a plurality of second pixels close to the second side; The gate driving circuit includes at least two gate driving sub-circuits, the gate driving sub-circuits are respectively connected to an input signal terminal, a power supply terminal and a clock signal terminal, the gate driving sub-circuit located on the first side is also connected to a pixel circuit of the first pixel in the corresponding pixel row, and the gate driving sub-circuit located on the second side is also connected to a pixel circuit of the second pixel in the corresponding pixel row; The gate driving subcircuit located on the first side is configured to output a gate signal to a pixel circuit of the first pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power terminal, and a clock signal provided by the clock signal terminal; The gate driving subcircuit located on the second side is configured to output a gate signal to a pixel circuit of the second pixel in the corresponding pixel row in response to an input signal provided by the input signal terminal, a power signal provided by the power terminal, and a clock signal provided by the clock signal terminal; The gate driving subcircuit includes a plurality of cascaded shift registers, the shift registers include a plurality of thin film transistors, and the thin film transistors include an oxide channel layer; There is no cascade relationship between each of the gate driving sub-circuits.

2. The display panel according to claim 1, characterized in that: The gate driving subcircuit located on the first side is connected to the pixel circuits of the first pixels in the pixel rows of a first preset number of rows, where the first preset number of rows is greater than or equal to 1080 and less than or equal to 2160.

3. The display panel according to claim 1, characterized in that: The gate driving subcircuit located on the second side is connected to the pixel circuits of the second pixels in the pixel rows of a second preset number of rows, where the second preset number of rows is greater than or equal to 1080 and less than or equal to 2160.

4. The display panel according to any one of claims 1 to 3, characterized in that: The gate driving sub-circuit is also connected to the reset signal terminal; the gate driving sub-circuit is also configured to reset the gate driving sub-circuit in response to the reset signal provided by the reset signal terminal and the power supply signal provided by the power supply terminal.

5. A display device, characterized in that: A display panel comprising any one of claims 1 to 4.

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