Latch circuit, and flip-flop circuit including the same

Abstract

A master latch circuit includes a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series, a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation of the clock signal and the signal of the first node to a second node, wherein a gate of the first p-type transistor is connected to the second node.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a latch circuit, and a flip-flop circuit including the same. BACKGROUND

[0002] A flip-flop is a general-purpose data storage element used in digital electronic circuits. The flip-flop is an important component in digital circuit design. This is because the flip-flop is a clock storage element that can implement sequential and stable logic design. The flip-flop is used to store a logic state, a parameter, or a digital control signal.

[0003] For example, a microprocessor can generally include a plurality of flip-flops, and in order to satisfy the operation of a high-performance microprocessor, the flip-flop is required to provide the maximum logic clock speed by reducing the setup and hold time of the flip-flop and the clock output time. In addition, the flip-flop is also required to reduce power unnecessarily consumed when the flip-flop is not operated, for example, power consumed in a clock buffer. SUMMARY

[0004] A latch circuit and a flip-flop circuit including the same are provided, which operate by internally generating an inverted clock signal even in the absence of a clock buffer, and a semiconductor device is also provided.

[0005] A latch circuit and a flip-flop circuit including the same are also provided, which improve power efficiency by reducing power consumed in a clock buffer when a flip-flop is not operated, and a semiconductor device is also provided.

[0006] It should be noted that the objects of the present disclosure are not limited thereto, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0007] According to an aspect of the disclosure, a master latch circuit includes: a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series between a power terminal and a power ground terminal; a first node connected to a drain terminal of the first p-type transistor and a drain terminal of the first n-type transistor; and a NAND circuit configured to receive a signal of the first node and a clock signal, perform a NAND operation, and output a result of the NAND operation to a second node. Wherein, the NAND circuit includes: a second p-type transistor connected in parallel with a third p-type transistor between the power terminal and the second node and a third n-type transistor connected in series with a fourth n-type transistor between the second node and the power ground terminal. Wherein, a gate of the second p-type transistor and a gate of the fourth n-type transistor are connected to the first node. Wherein, a gate of the first n-type transistor, a gate of the third p-type transistor, and a gate of the third n-type transistor are configured to receive the clock signal. And wherein, a gate of the first p-type transistor is connected to the second node.

[0008] According to an aspect of the disclosure, a master latch circuit includes: a first p-type transistor, a second p-type transistor, and a first n-type transistor connected in series between a power terminal and a power ground terminal; a first node connected to the second p-type transistor and the first n-type transistor; and a NOR circuit configured to receive a signal of the first node and an inverted clock signal, perform a NOR operation, and output a result of the NOR operation to a second node. Wherein, the NOR circuit includes: a third p-type transistor connected in series with a fourth p-type transistor between the power terminal and the second node; a third node connected with the third p-type transistor and the fourth P-type transistor; and a second n-type transistor connected in parallel with a third n-type transistor between the second node and the power ground terminal. Wherein, a gate of the third p-type transistor and a gate of the second n-type transistor are connected to the first node. Wherein, a gate of the third n-type transistor, a gate of the fourth p-type transistor, and a gate of the second p-type transistor are configured to receive the inverted clock signal. And wherein, a gate of the first n-type transistor is connected to the second node.

[0009] According to an aspect of the disclosure, a flip-flop circuit includes a scan multiplexer (MUX) circuit having a MUX output terminal connected to a first node; a first latch circuit connected between the first node and a second node; a second latch circuit connected between the second node and a third node; and an output driving circuit configured to drive and output a signal of the third node. Wherein the first latch circuit includes a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series between a power terminal and a power ground terminal; a NAND circuit configured to receive a signal of the first node and a clock signal, perform a NAND operation, and output a result of the NAND operation to the second node. Wherein the NAND circuit includes a second p-type transistor connected in parallel with a third p-type transistor between the power terminal and the second node; and a third n-type transistor and a fourth n-type transistor connected in series with each other between the second node and the power ground terminal. Wherein a drain terminal of the first p-type transistor and a drain terminal of the first n-type transistor are connected to the first node. Wherein a gate of the second p-type transistor and a gate of the fourth n-type transistor are connected to the first node. Wherein a gate of the first n-type transistor, a gate of the third p-type transistor, and a gate of the third n-type transistor are configured to receive the clock signal. Wherein the first n-type transistor and the second n-type transistor are not turned on at the same time. And wherein a gate of the first p-type transistor is connected to the second node.

[0010] According to an aspect of the disclosure, a multi-bit flip-flop circuit includes a scan inverter circuit configured to invert a scan enable signal to generate an inverted scan enable signal; a clock buffer circuit configured to generate an inverted clock signal from a clock signal; a plurality of first flip-flop circuits electrically connected to the scan inverter circuit or the clock buffer circuit and arranged adjacent in a first direction; and a plurality of second flip-flop circuits electrically connected to the clock buffer circuit and the scan inverter circuit and arranged adjacent in the first direction and adjacent to the plurality of first flip-flop circuits in a second direction. Wherein each flip-flop circuit of the plurality of first flip-flop circuits and the plurality of second flip-flop circuits includes: a first power input line, a second power input line, and a third power input line separated along the first direction; a first row including a scan multiplexer (MUX) circuit, an output driver circuit, and a first inverter circuit disposed between the first power input line and the second power input line; and a second row including a first latch circuit and an AND / OR / Inverter (AOI) circuit disposed between the second power input line and the third power input line. Wherein the first latch circuit includes: a first p-type transistor, a second p-type transistor, and a first n-type transistor connected in series between a first power terminal connected to the third power input line and a first power ground terminal connected to the second power input line; a first node connected to a drain terminal of the second p-type transistor, a drain terminal of the first n-type transistor, and an output terminal of the scan MUX circuit; and a first NOR circuit configured to receive a signal of the first node and the inverted clock signal, perform a first NOR operation, and output a result of the first NOR operation to a second node. Wherein the first NOR circuit includes: a third p-type transistor connected in series with a fourth p-type transistor between the first power terminal and the second node, connected in parallel with a second n-type transistor and a third n-type transistor between the second node and the first power ground terminal, wherein a gate of the third p-type transistor and a gate of the second n-type transistor are connected to the first node. Wherein a gate of the third n-type transistor, the fourth p-type transistor, and the second p-type transistor are configured to receive the inverted clock signal. And wherein a gate of the first n-type transistor is connected to the second node.

[0011] Further details of example embodiments for addressing the above problems are included in the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and other aspects, features, and advantages of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating a flip-flop circuit according to an embodiment;

[0014] Figure 2 is a block diagram illustrating a flip-flop circuit according to an embodiment; Figure 1The timing diagram of the operation of the trigger circuit;

[0015] Figure 3 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0016] Figure 4 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0017] Figure 5 This illustrates an embodiment. Figure 3 The timing diagram of the operation of the trigger circuit;

[0018] Figures 6 to 8 This is a description based on embodiments. Figure 4 A top view of an exemplary embodiment of the layout of the trigger circuit;

[0019] Figure 9 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0020] Figure 10 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0021] Figure 11 It is used to describe the embodiments. Figure 7 A conceptual diagram of the layout of the trigger circuit;

[0022] Figure 12 It is a conceptual diagram used to describe the layout of the trigger circuit according to an embodiment;

[0023] Figures 13 to 15 It is used to describe the embodiments. Figure 8 A top view of an exemplary embodiment of the layout of the trigger circuit;

[0024] Figure 16 and Figure 17 It is a conceptual diagram used to describe the arrangement of functional circuits in a trigger circuit according to an embodiment;

[0025] Figure 18 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0026] Figure 19 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0027] Figure 20 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0028] Figure 21 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0029] Figures 22 to 24 It is used to describe the embodiments.Figure 21 A top view of the layout of the trigger circuit;

[0030] Figure 25 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0031] Figure 26 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0032] Figure 27 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0033] Figure 28 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0034] Figure 29 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0035] Figure 30 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0036] Figure 31 This is a circuit diagram illustrating a trigger circuit according to an embodiment;

[0037] Figure 32 This is a circuit diagram illustrating a trigger circuit according to an embodiment; and

[0038] Figures 33 to 35 This is a top view used to describe the layout of the trigger circuit according to an embodiment. Detailed Implementation

[0039] It should be understood that although terms such as “first” and “second” may be used herein to describe various elements or components, these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, without departing from the scope and spirit of this disclosure, the first element or component described below may be referred to as the second element or component.

[0040] In this specification, a common node refers to the point where one terminal of each of at least two transistors or other components is connected. For example, the common node of a first transistor and a second transistor may refer to the point where the source or drain terminal of the first transistor is connected to the drain or source terminal of the second transistor.

[0041] In the following description, various exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0042] Figure 1 This is a block diagram showing a flip-flop circuit. Figure 2 It is shown Figure 1 The timing diagram of the operation of the trigger circuit.

[0043] Referring to Figure 1 The flip-flop circuit 100 according to some exemplary embodiments can include a scan multiplexer (MUX) circuit 10 which can be referred to as a scan multiplexer, a first latch circuit 20 which can be referred to as a master latch circuit, a second latch circuit 30 which can be referred to as a slave latch circuit, a clock buffer INV1, a clock buffer INV2, and an output driver circuit 40.

[0044] The scan MUX circuit 10 receives a data signal D or a scan input signal SI for a scan operation of a semiconductor circuit (not shown) and outputs one of the data signal D and the scan input signal SI according to a clock signal.

[0045] To this end, when the scan enable signal SE is at a logic high level and the inverted scan enable signal SEN is at a logic low level, the scan MUX circuit 10 inverts the scan input signal SI and outputs the inverted scan input to the first latch circuit 20. On the other hand, when the scan enable signal SE is at a logic low level (L) and the inverted scan enable signal SEN is at a logic high level (H), the scan MUX circuit 10 inverts the data signal D and outputs the inverted data signal D to the first latch circuit 20.

[0046] Meanwhile, the clock buffers INV1 and INV2 receive a clock signal CK and output an inverted clock signal nclk and a re-inverted clock signal bclk. The inverted clock signal nclk is generated by inverting the clock signal CK, and the re-inverted clock signal bclk is generated by inverting the inverted clock signal nclk. The inverted clock signal nclk and the re-inverted clock signal bclk are supplied to the first latch circuit 20 and the second latch circuit 30. For convenience of description, since the re-inverted clock signal bclk has the same phase as the clock signal CK, the re-inverted clock signal bclk will be referred to as a clock signal bclk hereinafter.

[0047] The first latch circuit 20 latches the output signal of the scan MUX circuit 10 based on the clock signal bclk and the inverted clock signal nclk and transmits the latched signal to the second latch circuit 30. The second latch circuit 30 latches the output signal of the first latch circuit 20 based on the clock signal bclk and the inverted clock signal nclk and transmits the latched signal to the output driver circuit 40.

[0048] That is, the first latch circuit 20 can function as a master latch which latches an output signal of the scan MUX circuit 10 and transmits the latched signal to the second latch circuit 30 at a rising edge of a clock signal bclk, and the second latch circuit 30 can function as a slave latch which latches an output signal of the first latch circuit 20 and transmits the latched signal to the output driver circuit 40 at a rising edge of the clock signal bclk.

[0049] The output driver circuit 40 receives an output signal of the second latch circuit 30 and outputs data Q as an output signal to the outside, for example, an element outside the flip-flop circuit 100.

[0050] Referring to Figure 1 and Figure 2 When the clock buffers INV1 and INV2 are used in the flip-flop circuit 100, the clock signal bclk and the inverted clock signal nclk are also transitioned between logic states each time the input clock signal CK is transitioned between logic states. Here, when the data signal D, which is an input signal of the flip-flop circuit 100, is fixed to a logic high level and the flip-flop circuit 100 does not operate (a period P1), undesired power consumption occurs due to the transitions of the clock signal bclk and the inverted clock signal nclk.

[0051] Accordingly, it is necessary to reduce power consumption by enabling the flip-flop circuit 100 to operate without the clock buffers INV1 and INV2.

[0052] Figure 3 is a circuit diagram illustrating a flip-flop circuit according to some exemplary embodiments.

[0053] Referring to Figure 3 , the flip-flop circuit 100 can include a scan MUX circuit 10, a first latch circuit 20, a second latch circuit 30, and an output driver circuit 40.

[0054] The scan MUX circuit 10 includes a plurality of p-type transistors and a plurality of n-type transistors connected between a power terminal and a power ground (VSS) terminal. The scan MUX circuit 10 holds a data signal D and provides the data signal D to a node N1 according to a scan enable signal SE, a clock signal CK, and a scan input signal SI. Here, the scan MUX circuit 10 inverts the data signal D and outputs the inverted signal to the node N1.

[0055] The first latch circuit 20 includes a plurality of p-type transistors and a plurality of n-type transistors connected between the power terminal and the VSS terminal. According to some exemplary embodiments, the first latch circuit 20 can include a transistor MP1 connected between the power terminal and a node N1, transistors MN1 and MN2 connected in series between the node N1 and the VSS terminal, and a NAND circuit 220. According to some exemplary embodiments, the first latch circuit 20 can include the transistor MP1, the transistors MN1 and MN2, and the NAND circuit 220 connected in series between the power terminal and the VSS terminal.

[0056] The gate of the transistor MP1 is connected to a node N2, the clock signal CK is provided to the gate of the transistor MN1, and the gate of the transistor MN1 is connected to a node N3. The transistor MP1, the transistor MN1, and the transistor MN2 receive an output signal of the scan MUX circuit 10 and store the output signal at the node N1 according to the clock signal CK, the clock buffer signal CKb, and the signal S.

[0057] The NAND circuit 220 can include transistors MP2 and MP3 connected in parallel between the power terminal and the node N2, and transistors MN3 and MN4 connected in series between the node N2 and the VSS terminal. The transistor MN3 is connected between the node N2 and the node N3, and the transistor MN4 is connected between the node N3 and the VSS terminal. The gate of each of the transistor MP2 and the transistor MN4 is connected to the node N1, and the clock signal CK can be provided to the gate of each of the transistor MP3 and the transistor MN3.

[0058] The NAND circuit 220 performs a NAND operation on the input signal DN of the node N1 and the clock signal CK and outputs the operation result to the node N2. More specifically, in the NAND circuit 220, when the clock signal CK is at a logic high level (H), the node N2 can be at a logic low level (L) based on a transition of the signal DN of the node N1 (the node N1 transitions from a logic high level (H) to a logic low level (L)), or when the clock signal CK is at a logic low level (L), the node N2 can be at a logic high level (H) based on a transition of the signal DN of the node N1 (the node N1 transitions from a logic low level (L) to a logic high level (H)). In other words, the NAND circuit 220 can operate based on the signal DN of the node N1 such that the clock signal CK is inverted, and can provide the clock buffer signal CKb by connecting the node N2 to each terminal requiring an inverted clock signal nclk during operation.

[0059] Meanwhile, the first latch circuit 20 can include a feedback path. The feedback path can include a path S through which a gate of the transistor MN2 is connected to the node N3. Whether to store the output signal of the scan MUX circuit 10 in the node N1 is determined based on a signal of the node N3 in addition to the clock signal CK and the clock buffer signal CKb.

[0060] As described above with reference to Figure 1 and Figure 2 Although a clock buffer circuit 50 is required to generate an inverted clock signal, in the present disclosure, by generating the clock buffer signal CKb at the node N2 from the clock signal CK without having a clock buffer and connecting the node N2 to an element requiring the inverted clock signal, a clock buffer is not required, for example, as shown in Figure 3 and Figure 4 Accordingly, even in the time period P1 in which the flip-flop circuit does not operate, power consumption due to flipping can be possible.

[0061] The second latch circuit 30 includes a plurality of p-type transistors and a plurality of n-type transistors connected between a power terminal and a VSS terminal. According to some exemplary embodiments, the second latch circuit 30 can include an OR circuit 31 configured to receive the clock signal CK and the signal QI, a NAND circuit 32 configured to output a signal QN by receiving an output signal of the OR circuit and a signal of the node N2, and an inverter circuit 33 configured to invert the output signal QN of the NAND circuit 32 and feed back the inverted signal to an input terminal of the OR circuit 31. According to some exemplary embodiments, the second latch circuit 30 can be implemented as an “OR / AND / inverter (OAI)” circuit in which the OR circuit 31, the AND circuit 32, and the inverter circuit 33 are combined.

[0062] The output driver circuit 40 can drive the output signal QN of the second latch circuit 30 and output the driven signal as the output signal Q of the flip-flop circuit. According to some exemplary embodiments, the output driver circuit 40 can include at least one inverter circuit. In this case, the output driver circuit 40 can invert the signal QN and output the inverted signal as the signal Q.

[0063] When describing the operation of the flip-flop circuit 100 according to some exemplary embodiments, the scan MUX circuit 10 is activated by the clock signal CK and the scan enable signal SE, but outputs the data signal D to the first latch circuit 20 as the next stage only when the scan input signal SI is input. At this time, according to various exemplary embodiments, the scan MUX circuit 10 can output the data signal D as it is, or can invert and output the data signal D. Figure 3The scanning MUX circuit 10 of the exemplary embodiment shown in the diagram inverts the data signal D and outputs the inverted signal to node N1. The first latch circuit 20 holds the signal input to node N1, i.e., the inverted data (DN), through the operation of the NAND circuit 220 according to the transition of the clock signal CK, and inverts the signal of node N1 and outputs the inverted signal to node N2. That is, the inverted data of node N1 is output to node N2 as re-inverted data QI. When a signal is input to node N2, the second latch circuit 30, according to the transition of the clock signal CK, uses the OAI circuit, including the OR circuit 31 and the NAND circuit 32, to re-invert the signal of node N2 and outputs the inverted signal QN to node N4. The output driver circuit 40 inverts the signal of node N4 and outputs the inverted signal Q.

[0064] Based on the above Figure 3 The trigger circuit 100 can be used without Figure 1 In the case of the clock buffer circuit 50 shown, by using a clock buffer signal (which may be referred to as node N2 or clock buffer signal CKb) generated at an internal node of the first latch circuit 20 instead of the inverted clock signal nclk generated by the clock buffer circuit 50, the number of transistors can be reduced, thereby reducing the area of ​​the flip-flop circuit. Furthermore, since the signal from the internal node can be used, the operating frequency of the flip-flop circuit 100 can be adjusted to be the same. Additionally, the power in the clock buffer circuit 50, which would otherwise be consumed to generate the inverted clock signal nclk, may not be needed.

[0065] Figure 4 This is a circuit diagram of a trigger circuit according to some exemplary embodiments. Figure 5 It is shown Figure 3 The timing diagram of the operation of the flip-flop circuit is shown. For ease of description, the main description will be related to... Figure 3 The exemplary embodiments of the present invention differ from those components. Parts not described will be referenced in the references. Figure 3 The descriptions are the same.

[0066] Reference Figure 4 The trigger circuit 100 may include a scan MUX circuit 10, a scan inverter circuit 15, a first latch circuit 20, a second latch circuit 30, and an output driver circuit 40. According to some exemplary embodiments, the scan MUX circuit 10 and the first latch circuit 20 may be implemented as a scan MUX circuit 210 and a NAND circuit 220.

[0067] The scan inverter circuit 15 includes an inverter circuit configured to receive a scan enable signal SE and generate an inverted scan enable signal nse.

[0068] Specifically, the scanning MUX circuit 10 may include transistors MP4 to MP8 and transistors MN5 to MN9, and the feedback circuit of the first latch circuit may include transistors MP1, MN1 and MN2.

[0069] Transistors MP4 and MP5, which are connected in series between the power supply terminal and node N5, are connected in parallel with transistors MP6 and MP7, which are also connected in series between the power supply terminal and node N5.

[0070] Transistors MN5 and MN8, which are connected in series between the VSS terminal and node N6, are connected in parallel with transistors MN6 and MN7, which are also connected in series between the VSS terminal and node N6.

[0071] The gates of transistors MP4 and MN6 each receive the scan enable signal SE, and the gates of transistors MP6 and MN8 each receive the inverted scan enable signal nse. The gates of transistors MP5 and MN5 each receive the data signal D, and the gates of transistors MP7 and MN7 each receive the scan input signal SI.

[0072] Transistor MP8 is connected between node N5 and node N1, and transistor MN9 is connected between node N6 and node N1.

[0073] The gate of transistor MP8 receives the clock signal CK, and the gate of transistor MN9 is connected to node N2 (clock buffer signal CKb). Meanwhile, node N1 can be referred to as the common node connecting transistors MN9 and MP8 in this paper.

[0074] Meanwhile, transistors MN1 and MP8, selected by the clock signal CK, and transistors MP1 and MN9, selected by the clock buffer signal CKb, can be configured as CMOS circuit pairs. These CMOS circuit pairs serve as input control circuits that control the input of data signals on the scan MUX circuit 10 side (transistors MP8 and MN9) and hold the data signals input through the scan MUX circuit 10 on the main latch circuit side (transistors MP1 and MN1). That is, transistors MP8 and MN9 can be referred to as data input control transistors, and transistors MP1, MN1, and MN2 can be referred to as data holding transistors.

[0075] According to some exemplary embodiments, the second latch circuit 30 may include an OAI circuit (e.g., Figure 3 OR circuit 31 and NAND circuit 32) and inverter circuit (e.g., Figure 3The second latch circuit 30 can include transistors MP9 to MP12 and transistors MN10 to MN13. More specifically, the second latch circuit 30 can include a first inverter circuit 31, a second inverter circuit 32, and a third inverter circuit 33.

[0076] The transistors MP9, MN10, and MN11 can be connected in series between the power terminal and the VSS terminal. The transistor MP9 can be connected between the power terminal and a node N4, the transistor MN10 can be connected between the node N4 and a node N9, and the transistor MN11 can be connected between the node N9 and the VSS terminal. The gates of each of the transistor MP9 and the transistor MN11 can be connected to the node N2 and receive the clock buffer signal CKb. The clock signal CK can be applied to the gate of the transistor MN10.

[0077] The transistors MP10, MP11, and MN12 can be connected in series between the power terminal and the node N9. The transistors MP10 and MP11 can be connected in series between the power terminal and the node N4, and the transistor MN12 can be connected between the node N4 and the node N9. The gates of each of the transistor MP10 and the transistor MN12 can be connected to the node N7 and receive the signal QI. The clock signal CK is applied to the gate of the transistor MP11.

[0078] The transistors MP12 and MN13 can be connected in series between the power terminal and the VSS terminal. The transistor MP12 can be connected between the power terminal and the node N7. The transistor MN13 can be connected between the VSS terminal and the node N7. The gates of each of the transistor MP12 and the transistor MN13 can be connected to the node N4 and receive the signal QN. The transistors MP12 and MN13 are the inverter circuit 33, and can invert the signal QN of the node N4 and output the inverted signal as the signal QI of the node N7.

[0079] The output driver circuit 40 can include transistors MP13 and MN14 connected in series between the power terminal and the VSS terminal. The transistor MP13 can be connected between the power terminal and a node N8. The transistor MN14 can be connected between the VSS terminal and the node N8. The gates of each of the transistor MP13 and the transistor MN14 can be connected to the node N4 and receive the signal QN. The transistors MP13 and MN14 are inverter circuits included in the output driver circuit 40, and can invert the signal QN of the node N4 and output the inverted signal as the signal Q of the node N8, i.e., the output signal of the flip-flop circuit 100.

[0080] According to some exemplary embodiments, when describing the operation of the flip-flop circuit, in the scan MUX circuit 10 and the first latch circuit 20, when the scan enable signal SE is at a logic low level (L), in response to the inverted scan enable signal nse, the transistor MP4 is turned on and the transistor MN6 is turned off, and the transistor MP6 is turned off and the transistor MN8 is turned on. When the clock signal CK is at a logic low level (L), the transistor MP8 is turned on, and the signal DN of the node N1 is at a logic high level (H) according to the input data signal D. The transistor MN1 is turned off because the clock signal CK is at a logic low level (L), and the signal DN is stored in the node N1. The NAND circuit 220 receives the clock signal CK at a logic low level (L) and the signal DN at a logic high level (H), and thus the node N2 is at a logic high level (H).

[0081] That is, because the node N1 is at a logic low level (L) and the node N2 is at a logic high level (H), the signal of the node N2 is supplied to the gate of each of the transistor MN9 and the transistor MP1, serving as a clock buffer signal CKb, so that the transistor MP1 is turned off and the transistor MN9 is turned on.

[0082] When the node N3 is at a logic high level (H) and the clock signal CK is at a logic low level (L), the transistor MN3 is turned off, and the transistor MN4 is turned on in response to the signal of the node N1. The node N3 is at a logic low level (L) to turn off the transistor MN2. In other words, the transistor MN2 is not turned on at the same time as the transistor MN3. That is, even when the transistor MP1 and the transistor MN1 are turned on at the same time during a transition of the clock buffer signal CKb or the clock signal CK, the transistor MN2 is turned off so that the signal DN of the node N1 is not leaked to the VSS terminal and is maintained at the node N1.

[0083] In the second latch circuit 30, because the clock signal CK is at a logic low level (L), the transistor MN10 is turned off, and the transistor MP9 and the transistor MN11, which are connected to the gate of the transistor MN10, are turned on. That is, because the signal of the node N2 is not transmitted to the node N4, the first latch circuit 20 can be in a state in which data is stored in the node N2.

[0084] When the clock signal CK transitions from the logic low level (L) to the logic high level (H), in the second latch circuit 30, the transistor MP9 and the transistor MN10 are turned on, and the transistor MN11 is turned off. Therefore, the signal stored in the node N2 is inverted and transmitted to the node N4 as the signal QN, and the transistor MP12 and the transistor MN13 whose gate is connected to the node N4 invert the signal QN and output the inverted signal to the node N7 as the signal QI. Since the transistor MP11 is turned off when the clock signal CK is at the logic high level (H), the signal QN of the node N4 is not connected to the output driver circuit 40, and is stored in the node N7.

[0085] The output driver circuit 40 drives the signal QN generated in the previous operation period and outputs the driven signal, and when the clock signal CK transitions from the logic high level (H) back to the logic low level (L), the transistor MP11 of the second latch circuit 30 is turned on, and therefore, the transistor MP11 and the transistor MN12 are turned on so that the signal QI stored in the node N7 is inverted as the signal QN and is output. Subsequently, the output driver circuit 40 inverts the signal QN stored by the second latch circuit 30 again and outputs the inverted signal as the signal Q.

[0086] Reference Figure 5 When there is a clock buffer including an inverter (for example, the clock buffer circuit 50 in Figure 1 , the inverted clock signal nclk and the re-inverted clock signal bclk are generated based on the input clock signal CK. Even when the flip-flop circuit 100 is not operated after the output data signal D is output as the flip-flop output signal (Q) (the period P2), the inverted clock signal nclk and the re-inverted clock signal bclk are continuously toggled.

[0087] However, in the case of the flip-flop circuit according to the exemplary embodiment described with reference to Figure 3 and Figure 4 , the clock buffer signal CKb of the node N2 is used instead of the inverted clock signal nclk, and after the output signal (Q) of the flip-flop circuit is output, the clock buffer signal CKb is not toggled in the current operation period P2. That is, the flip-flop circuit 100 uses the clock buffer signal through the feedback path S and the node N2, without using the inverted clock signal nclk toggled by the clock buffer circuit 50, and therefore, not only the power consumption can be reduced, but also the operation can be performed more accurately in synchronization with the input clock signal.

[0088] Figures 6 to 8 is a top view for describing one exemplary embodiment of a layout of the flip-flop circuit of Figure 4 . Figure 6is a top view illustrating up to a front-end-of-line (FEOL) of the flip-flop circuit 100 according to some example embodiments. Figure 7 is a top view illustrating up to a middle-of-line (MOL). Figure 8 is a top view illustrating up to a back-end-of-line (BEOL).

[0089] Referring to Figures 6 to 8 The flip-flop circuit 100 can include a plurality of functional circuits arranged in a double-height layout. According to some example embodiments, assuming that the functional circuits are arranged in a plurality of columns, each functional circuit can share an interconnection line of a common signal. The flip-flop circuit 100 can include, in a first row: some of scan MUX circuits 210 and main latches; NAND circuits 220; and OAI circuits including OR circuits 31 and NAND circuits 32 of slave latches. The flip-flop circuit 100 can include, in a second row: some of scan MUX circuits 210 and main latches; scan inverter circuits 15; output driver circuits 40; and inverter circuits 33 of slave latches. For ease of description, the scan inverter circuits 15, the scan MUX circuits 210, the output driver circuits 40, the inverter circuits 33, the first latch circuits 20 (e.g., which can be main latch circuits), and the OAI circuits including the OR circuits 31 and the NAND circuits 32 are referred to as functional circuits.

[0090] Each functional circuit can be formed on a substrate. The substrate can be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate can include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto.

[0091] Each functional circuit can include a first active region Act1, a second active region Act2, and an active region isolation film NACT. The first active region Act1 can be defined along a first direction X. The first active region Act1 can be defined by a deep trench. The first active region Act1 can be a region in which an n-type transistor is formed. For example, the first active region Act1 can include a well region doped with a p-type impurity.

[0092] The second active region Act2 can be defined along the first direction X. The second active region Act2 can be defined as being spaced apart from the first active region Act1 in a second direction Y. The first active region Act1 and the second active region Act2 can be separated by a deep trench. The second active region Act2 can be a region in which a p-type transistor is formed. For example, the second active region Act2 can include a well region doped with an n-type impurity.

[0093] An active region separation film NACT can be formed on the substrate. The active region separation film NACT can pass through a space between the first active region Act1 and the second active region Act2. The active region separation film NACT can extend in the first direction X. The active region separation film NACT can fill a deep trench that separates the first active region Act1 and the second active region Act2. Meanwhile, according to some example embodiments, the first active region Act1 or the second active region Act2 can have various lengths in the second direction Y. For example, the first active region Act1 (R2) can be formed to be longer than the first active region Act1 (R1) in the second direction. For example, the second active region Act2 (R2) can be formed to be longer than the second active region Act2 (R1) in the second direction. Accordingly, the length of the active region separation film NACT in the second direction Y can be changed, and the number of fin patterns (or RX patterns) formed and included in the active region can also be changed. For example, the first active region Act1 (R1) can include two fin patterns, and the first active region Act1 (R2) can include three fin patterns.

[0094] A cell separation film can be formed on the substrate. The cell separation film can fill a deep trench that separates the first active region Act1 and the second active region Act2. The cell separation film can extend in the first direction X along a boundary of each functional circuit. The active region separation film NACT and the cell separation film can each include an insulating material. The functional circuit according to some example embodiments can include a plurality of gate stacks 120 and a plurality of insulating gates 150. The gate stacks 120 and the insulating gates 150 can each extend along the second direction Y. The gate stacks 120 and the insulating gates 150 can be arranged adjacent to each other in the first direction X.

[0095] The gate stacks 120 and the gate stacks 120 or the gate stacks 120 and the insulating gates 150 arranged adjacent to each other in the first direction X can be spaced apart from each other by a contact poly pitch (CPP). As an example, adjacent gate stacks 120 can be spaced apart from each other by a CPP. As another example, adjacent gate stacks 120 and insulating gates 150 can be spaced apart from each other by a CPP. As still another example, adjacent insulating gates 150 can be spaced apart from each other by a CPP.

[0096] The gate stacks 120 and the insulating gates 150 can be respectively disposed above the first active region Act1 and the second active region Act2. The gate stacks 120 and the insulating gates 150 can each extend from the first active region Act1 to the second active region Act2. According to some example embodiments, the gate stacks 120 and the insulating gates 150 can pass through the active region separation film NACT. A portion of the gate stacks 120 and a portion of the insulating gates 150 can each extend above the cell separation film.

[0097] The insulating gate 150 can separate at least a portion of the first active region Act1 from at least a portion of the second active region Act2. When a manufacturing process of forming the insulating gate 150 is considered, at least a portion of the first active region Act1 and at least a portion of the second active region Act2 are removed, and then the portions removed from the first and second active regions Act2 are filled with an insulating material. Accordingly, the insulating gate 150 can be formed. Accordingly, a portion of a sidewall of the insulating gate 150 can be in contact with the first active region Act1 and the second active region Act2. A portion of the sidewall of the insulating gate 150 can be in contact with a semiconductor material film included in the first active region Act1 and the second active region Act2.

[0098] The insulating gate 150 can pass through the active region separation film NACT. The insulating gate 150 can be disposed on the active region separation film NACT. A portion of the insulating gate 150 can be recessed into the active region separation film NACT. A portion of the active region separation film NACT can be removed in a process of forming the insulating gate 150. Accordingly, a portion of the insulating gate 150 can be recessed into the active region separation film NACT. A gate spacer can be disposed on a sidewall of the insulating gate 150. The insulating gate 150 can include, for example, an insulating material.

[0099] The p-type transistor MP can be formed at a location where the gate stack 120 intersects the first active region Act1, and the n-type transistor MN can be formed at a location where the gate stack 120 intersects the second active region Act2.

[0100] Each functional circuit can include a source / drain contact and a gate contact. The source / drain contacts 170, 170-1, and 170-2 can be disposed on the first active region Act1 and the second active region Act2. The source / drain contacts 170, 170-1, and 170-2 can be connected to a semiconductor pattern formed on the first active region Act1 and the second active region Act2. The semiconductor pattern can be formed between adjacent gate stacks 120 and insulating gates 150. The semiconductor pattern can be formed by removing a portion of the active regions Act1 and Act2 to form a recess, and then filling the recess by an epitaxial process.

[0101] The source / drain contacts 170, 170-1, and 170-2 can include normal source / drain contacts 170, 171, and 172, and extended source / drain contacts 170-1 and 170-2. The normal source / drain contacts 170, 171, and 172 can fully overlap the first active region Act1 or the second active region Act2. The normal source / drain contact 170 can overlap the first active region Act1 and the second active region Act2 disposed in one height layout (e.g., between PW1 and PW2 or between PW2 and PW3). The normal source / drain contacts 171 and 172 can be arranged to cross the power line PW2 while overlapping the second active region Act2 and the first active region Act1 arranged in another height layout (e.g., above or below PW2). Some of the extended source / drain contacts 170-1 and 170-2 can extend over the cell isolation film and the cell gate cut pattern. The extended source / drain contacts 170-1 and 170-2 can be connected to the power lines PW1, PW2, and PW3 (in Figure 7

[0102] In addition, the source / drain contact 170 can be formed to have different lengths in the direction of the active region isolation film NACT based on the boundary between the first active region Act1 or the second active region Act2 and the active region isolation film NACT. For example, when comparing the region X1 and the region X2, the source / drain contact 171 in the region X1 can be formed only up to the boundary between the active regions ACT1 and ACT2 and the active region isolation film NACT, while the drain / drain contact 172 in the region X2 can be formed to partially extend to the active region isolation film NACT. The case where the source / drain contact 171 or 172 partially extends to the active region isolation film NACT or the case where the source / drain contact 171 or 172 does not partially extend to the active region isolation film NACT can be determined according to the position (e.g., the first metal line pattern) on which the first metal line is formed.

[0103] The gate contact is formed on the gate stack 120, but not on the insulating gate 150. The gate contact can be connected to the gate stack 120. For example, the gate contact can be electrically connected to the gate electrode of the gate stack 120. The gate contact can be disposed on the first active region Act1 and the second active region Act2. In addition, the gate contact can also be formed on the active region isolation film NACT. In the integrated circuit according to some exemplary embodiments, at least one gate contact can be disposed at a position overlapping one of the first active region Act1 and the second active region Act2.

[0104] ​A functional circuit according to some exemplary embodiments can include source / drain vias VA, gate vias VB, metal lines M1 and M2, and power lines PW1, PW2, and PW3. The gate vias VB can be formed on the gate contacts. The gate vias VB can connect the gate contacts and the metal lines M1 and M2. The source / drain vias VA can be formed on the source / drain contacts 170, 171, 172, 170-1, and 170-2. The source / drain vias VA can be connected to at least some of each of the source / drain contacts 170, 171, 172, 170-1, and 170-2. The source / drain vias VA can include normal vias connecting the normal source / drain contacts 170, 171, and 172 with the metal lines M1 and M2, and power line vias connecting the extended source / drain contacts 170-1 and 170-2 with the power lines PW1, PW2, and PW3.

[0105] The first metal line M1, the third metal line M3, and the power lines PW1, PW2, and PW3 can extend in the first direction X. The power lines PW1, PW2, and PW3 can include power supply lines PW1 and PW3 to which a first voltage is applied and a ground power line PW2 to which a second voltage is applied. The power supply lines PW1 and PW3 can supply power to p-type transistors, and the ground power line PW2 can supply power to n-type transistors.

[0106] The first metal line M1 can be electrically connected to the gate stack 120 or the source / drain contacts 170, 171, 172, 170-1, and 170-2 through the gate via VB or the source / drain via VA. The second metal line M2 can be electrically connected to the first metal line M1 through the first via V1.

[0107] The second metal line M2 can extend in the second direction Y and perpendicularly intersect the first metal line M1. The third metal line M3 can extend in the first direction X, can be spaced apart from and parallel to the first metal line M1 in the third direction Z, and can perpendicularly intersect the second metal line M2.

[0108] Referring to Figures 6 to 8 , some transistors included in the first latch circuit 20 and the second latch circuit 30 of the flip-flop circuit of Figure 4 can be shown. A power ground voltage VSS can be applied to the power supply lines PW1 and PW3, a power voltage VDD can be applied to the power line PW2, the first active region Act1 can be a well region doped with n-type impurities, and the second active region Act2 can be a well region doped with p-type impurities.

[0109] For example, transistors MN1 to MN4 of the first latch circuit 20 can be formed at the intersection of the gate stack 120 and the first active region Act1 of the first row, and transistors MP1 to MP3 can be formed at the intersection of the gate stack 120 and the second active region Act2 of the second row.

[0110] When reference Figures 6 to 8 describe Figure 4 In the circuit, during the feedback passage region of the scanning MUX circuit 210 and the first latch circuit, the gate stack 120 of transistor MN4 is connected to the drain contact 170 of transistor MP1 via the first metal line M1, which corresponds to node N1. The drain contact 170 of transistor MP2, the drain contact of transistor MP3, the gate contact of transistor MP9, and the gate contact of transistor MN11 are connected via the first metal lines M1, N21, and N23 and the second metal line M2, forming node N2. The first and second metal lines of node N2 are electrically connected to the drain contact 170 of transistor MP2, the drain contact of transistor MP3, the gate contact of transistor MP9, and the gate contact of transistor MN11. That is, a clock buffer signal CKb is generated at node N2, which serves as the output line of the NAND circuit 220 in the first latch circuit 20, and node N2 is connected to transistor MP1 and the scanning MUX circuit 10, so the clock buffer signal CKb is provided to the gate of the transistor.

[0111] That is, when an inverted clock signal nclk is needed in the flip-flop circuit 100, it can be transmitted through multiple layers of metal lines via a clock buffer circuit (e.g., Figure 1 The inverted clock signal generated by flipping in the clock buffer circuit 50) is connected to the circuit included in the flip-flop circuit 100, thereby providing the inverted clock signal nclk. However, in the present disclosure, when using the clock buffer signal CKb generated at the output terminal of the first latch circuit 20, a smaller number of first and second metal lines can be used to provide the clock signal without complex metal line wiring, thereby improving the convenience of layout and routing (P / R) design.

[0112] Figure 9 This is a circuit diagram illustrating a trigger circuit according to some exemplary embodiments. For ease of description, the differences between the following exemplary embodiments and the exemplary embodiments described above will be mainly described, and the descriptions of the remaining elements will be the same.

[0113] Reference Figure 9The first latch circuit 20 according to some exemplary embodiments can further include at least one reset transistor configured to reset a node N2, which can be, for example, a data storage node. That is, the first latch circuit 20 can include: a transistor MP1; a transistor MN1; a transistor MN2; a NAND circuit 220; and reset transistors MPR and MNR.

[0114] The first latch circuit 20 can include a reset transistor MPR between a power terminal and a node NR. The reset transistor MPR and the NAND circuit 220 are connected in series between the power terminal and a VSS terminal. Further, the first latch circuit 20 can include a reset transistor MNR between the node N2 and the VSS terminal. A gate of each of the reset transistor MPR and the reset transistor MNR receives a reset signal R.

[0115] The NAND circuit 220 can include a transistor MP2 and a transistor MP3 connected in parallel between a node NR and a node N2, and a transistor MN3 and a transistor MN4 connected in series between the node N2 and the VSS terminal. The transistor MN3 is connected between the node N2 and a node N3, and the transistor MN4 is connected between a node N3 and the VSS terminal. A gate of each of the transistor MP2 and the transistor MN4 is connected to the node N1, and a clock signal CK can be provided to a gate of each of the transistor MP3 and the transistor MN3.

[0116] The first latch circuit 20 can reset data stored in the first latch circuit 20 in response to the reset signal R. According to some exemplary embodiments, the flip-flop circuit 100 can reset the data of the first latch circuit 20 by applying the reset signal R before performing a flip-flop operation. According to some exemplary embodiments, the flip-flop circuit 100 can reset the data stored in the node N2 of the first latch circuit 20 by applying the reset signal R after completing the flip-flop operation. In an embodiment, the flip-flop circuit 100 can periodically or intentionally apply the reset signal R to reset the data of the first latch circuit 20 according to a setting.

[0117] Figure 10 is a circuit diagram illustrating a flip-flop circuit 110 according to some exemplary embodiments. In an embodiment, the flip-flop circuit 110 can correspond to the flip-flop circuit 100. For ease of description, differences between the following exemplary embodiments and the above exemplary embodiments will be mainly described, and descriptions of the remaining elements will be the same.

[0118] Referring to Figure 10 According to some exemplary embodiments, the flip-flop circuit 110 includes a scan MUX circuit 10, a first latch circuit 25, a second latch circuit 30, an output driver circuit 40, and an inverted clock generation circuit 52.

[0119] The inverting clock generation circuit 52 includes an inverter circuit to generate an inverting clock signal nclk based on an input clock signal CK. In the following Figure 10 description, for distinction, the clock buffer signal generated at the node N2 is denoted by CKb, and the inverting clock signal generated by the inverting clock generation circuit 52 is denoted by nclk.

[0120] Unlike the scan MUX circuit in Figures 3 to 6 , the clock signal CK and the clock buffer signal CKb are inverted and input to the scan MUX circuit 10 in Figure 10 . That is, the clock buffer signal CKb is input to the gate of the transistor MP8, and the inverting clock signal nclk is input to the gate of the transistor MN9.

[0121] According to some example embodiments, the first latch circuit 25 includes two p-type transistors MP21 and MP22 and an n-type transistor MN21 connected in series between a power supply terminal and a VSS terminal, and a NOR circuit 250. Specifically, the gate of the transistor MP21 is connected to a node N0 of the NOR circuit 250. The transistor MP22 is connected between a drain terminal of the transistor MP21 and a node N1, and has a gate input of the inverting clock signal nclk. The transistor MN21 is connected between the node N1 and the VSS terminal, and has a gate connected to a node N2.

[0122] The NOR circuit 250 receives a data signal DN of the node N1 and the inverting clock signal nclk, and outputs a NOR operation result signal to the node N2.

[0123] The NOR circuit 250 can include a transistor MP23 and a transistor MP24 connected in series between the power supply terminal and the node N2, and a transistor MN22 and a transistor MN23 connected in parallel between the node N2 and the VSS terminal.

[0124] The gate of each of the transistor MP23 and the transistor MN22 is connected to the node N1, and the inverting clock signal nclk is input to the gate of each of the transistor MP24 and the transistor MN23.

[0125] Even in the case of the NOR circuit 250, the gate of the transistor MP21 is connected to the node N0 to form a feedback path S. The output signal of the scan MUX circuit 10 is determined whether to be stored in the node N1 or not in accordance with the clock buffer signal CKb and the signal S of the node N0. Because the transistor MP21 is connected between the power supply terminal and the source terminal of the transistor MP22 and turned on / off based on the feedback signal S applied to the gate of the transistor MP21, the signal DN stored in the node N1 can remain even by the transition of the inverted clock signal nclk.

[0126] Figure 10 The first latch circuit 25 functions as the NOR circuit 250, but due to the characteristics of the p-type transistor, by generating and using the inverted clock signal nclk in the inverted clock generation circuit 52, the first latch circuit 25 and the second latch circuit 30 can each latch and then transmit the input data signal D in response to the transition of the clock signal CK, similarly to the operation described in Figure 3 and 4 .

[0127] Figure 11 is a conceptual diagram for describing the layout of the flip-flop circuit of Figure 8 .

[0128] A plurality of flip-flop circuits can share one clock buffer circuit and one scan inverter circuit. Figure 11 The example shown in is an example in which the flip-flop circuit is implemented in a double height layout. The term "height layout" used herein refers to between the first power supply metal line and the second power supply metal line. Single height layout refers to the case where the circuit is arranged between the first power supply metal line and the second power supply metal line, and double height layout refers to the case where the circuit is arranged between three power supply metal lines. Based on the same principle, it is assumed that the circuit arranged between three or more power supply metal lines is implemented in a multiple height layout.

[0129] Figure 11In the shown example, the scan inverter circuit 15 is arranged in the middle of the first column of the second flip-flop circuit FF1, and the clock buffer circuit 50 of the clock buffer circuit 50 is arranged between the first flip-flop circuit FF0 and the second flip-flop circuit FF1 in the second column, but according to another exemplary embodiment, both the scan inverter circuit 15 and the clock buffer circuit 50, which can be shared by a plurality of flip-flop circuits, can be provided in the middle of the first flip-flop circuit FF0 and the second flip-flop circuit FF1, and according to still another exemplary embodiment, both can also be arranged in the middle of any one flip-flop circuit. That is, the flip-flop circuit of the present disclosure is not limited to the arrangement of the shown example. Figure 3

[0130] In the shown example, the scan inverter circuit 15 is arranged in the middle of the first column of the second flip-flop circuit FF1, and the clock buffer circuit 50 of the clock buffer circuit 50 is arranged between the first flip-flop circuit FF0 and the second flip-flop circuit FF1 in the second column, but according to another exemplary embodiment, both the scan inverter circuit 15 and the clock buffer circuit 50, which can be shared by a plurality of flip-flop circuits, can be provided in the middle of the first flip-flop circuit FF0 and the second flip-flop circuit FF1, and according to still another exemplary embodiment, both can also be arranged in the middle of any one flip-flop circuit. That is, the flip-flop circuit of the present disclosure is not limited to the arrangement of the shown example. Figure 1

[0131] Figure 12 is a conceptual diagram for describing a layout of a flip-flop circuit according to some exemplary embodiments.

[0132] According to some exemplary embodiments, a flip-flop circuit can be implemented as shown in Figure 12 As shown, the first flip-flop circuit FF0 can be implemented in a double-height layout, and can include the scan inverter circuit SE INV (15), some circuits of the master latch, and two inverters in the first row, and can include the scan MUX circuit, the NOR circuit of the master latch, and the OAI circuit of the slave latch in the second row.

[0133] ​​However, the scan inverter circuit SE INV (15) and the scan out circuit 80 (NAND2 and QI1) in the first row and the clock buffer CK buffer 53 in the second row can be disposed between the first flip-flop circuit FF0 and the adjacent second flip-flop circuit FF1. That is, according to some example embodiments, the adjacent second flip-flop circuit FF1 can be disposed in a symmetrical form with the first flip-flop circuit FF0 as if the scan out circuit 80 (NAND2 and QI1) of the first row and the clock buffer of the second row are flipped.

[0134] In the adjacent second flip-flop circuit FF1, the first row can include a master latch and an inverter (Q1 and QI1) as a part of a slave latch, followed by a scan out circuit (NAND2); the second row can include an OAI circuit, a NOR circuit, and a scan MUX circuit in a slave latch, followed by a clock buffer circuit.

[0135] Figures 13 to 15 is a top view of one example embodiment of a layout of a flip-flop circuit for describing Figure 10 . Figures 13 to 15 is a view of the flip-flop circuit 110 of Figure 10 . Figure 13 is a top view up to the FEOL of the flip-flop circuit 110 according to some example embodiments. Figure 14 is a top view up to the MOL. Figure 15 is a top view up to the BEOL. For ease of description, only the differences in the arrangement of each functional circuit from the arrangement of Figures 6 to 8 will be described. And the description that is repeated from the description of Figures 6 to 8 will be omitted.

[0136] Referring to Figures 13 to 15 , the flip-flop circuit 110 can include a plurality of functional circuits arranged in a double-height layout. The flip-flop circuit 110 can include a scan inverter circuit 15, a scan MUX circuit 10, an inverted clock generation circuit 52 (which can be related to, for example, a clock buffer circuit), an output driver circuit 40, and an inverter circuit 33 of a slave latch in the first row. The flip-flop circuit 110 can include a first latch circuit 25 (which can be a master latch circuit, for example) and an AOI circuit including an OR circuit 31 and a NAND circuit 32 of a slave latch in the second row.

[0137] Referring to Figure 13 , in Figure 10The trigger circuit 110 shows transistors included in the scan MUX circuit 10, the first latch circuit 25, the second latch circuit 30, the output driver circuit 40, and the inverting clock generation circuit 52 (which may be associated with, for example, a clock buffer circuit). Power supply lines PW1, PW2, and PW3 may include power supply lines PW1 and PW3 with a first voltage applied and a ground power supply line PW2 with a second voltage applied. Power supply lines PW1 and PW3 supply power to p-type transistors, while ground power supply line PW2 supplies power to n-type transistors. The first active region Act1 may be a well region filled with p-type impurities, and the second active region Act2 may be a well region filled with n-type impurities.

[0138] For example, transistors MN21 to MN23 and MN9 of the first latching circuit 25 can be formed at the intersection of the gate stack 120 in the second row and the second active region Act2, and transistors MP21 to MP24 and MP8 can be formed at the intersection of the gate stack 120 in the second row and the first active region Act1.

[0139] refer to Figures 13 to 15 Layout, for reference Figure 10 In the first latch circuit 25 shown, the gate stack 120 of transistor MP21 is connected to the drain contact 170 of transistor MP23 via a first metal line M1 (node ​​N0). The drain contact 170 of transistor MN9, the drain contact of transistor MN21, the gate contact of transistor MP23, and the gate contact of transistor MN22 are connected via a first metal line M1 (node ​​N1) and a second metal line M2. The first and second metal lines at node N2 are electrically connected to the drain contacts of transistor MN22, transistor MN23, and transistor MP24. That is, a clock buffer signal CKb is generated at node N2, which serves as the output line of the first latch circuit 25, and node N2 is connected to transistor MP1 and the scan MUX circuit 10, thereby providing the clock buffer signal CKb to the gate of the transistor.

[0140] In other words, when an inverted clock signal is needed in the flip-flop circuit 110, the inverted clock signal generated by toggling in a clock buffer circuit 50 can be connected to the circuitry included in the flip-flop circuit 110 via multiple metal lines across multiple layers, thereby providing the inverted clock signal nclk. However, in the present disclosure, when using the clock buffer signal CKb of node N2 of the first latch circuit 25, a smaller number of first and second metal lines can be used without complex metal wiring, thereby improving design convenience.

[0141] Figure 16 and Figure 17is a conceptual diagram for describing an arrangement of functional circuits in a flip-flop circuit according to some exemplary embodiments.

[0142] Referring to Figure 16 , a scan out circuit Scan out (80), a scan inverter circuit SE INV (15), and a clock buffer circuit CK INV (50) are arranged between and shared by a plurality of flip-flop circuits. That is, a scan out circuit Scan out (80), a scan inverter circuit SE INV (15), and a clock buffer circuit CK INV (50) can be provided in the first column between the first flip-flop circuit FF1 and the second flip-flop, can be provided in the second column between the first flip-flop circuit FF3 and the second flip-flop circuit FF4.

[0143] According to some exemplary embodiments, each flip-flop circuit can be operated simultaneously or separately in one bit unit. According to some exemplary embodiments, each flip-flop circuit can be formed in a single height layout or a multi-height layout. For example, when a flip-flop circuit is implemented in a double height layout as shown in Figures 13 to 15 , the layout of the flip-flop of Figure 16 can be implemented as a 4-bit latch in a four height layout. As another example, when a flip-flop circuit is implemented in a single height layout as shown in Figure 17 , an 8-bit flip-flop layout can be implemented in a four height layout.

[0144] Figure 18 is a circuit diagram showing a flip-flop circuit 110 according to some exemplary embodiments. For ease of description, differences between the following exemplary embodiments and the exemplary embodiments of Figure 10 will be mainly described, and the description of the remaining elements will be the same.

[0145] According to some exemplary embodiments, the flip-flop circuit 110 includes a scan MUX circuit 10, a first latch circuit 25, a second latch circuit 30, an output driver circuit 40, and an inverting clock generation circuit 52. However, unlike the flip-flop circuit 110 of Figure 10 , the flip-flop circuit 110 according to some exemplary embodiments further includes a scan out circuit 80. Figure 18

[0146] The scan out circuit 80 is connected to the feedback terminal of the second latch circuit 30. More specifically, the scan out circuit 80 is connected to the output terminal of the inverter circuit 33. According to some exemplary embodiments, the scan out circuit 80 includes an inverter circuit 81 and a NAND circuit 83. The inverter circuit 81 receives and inverts the output signal QI, and the inverted signal is subjected to NAND operation together with the scan enable signal SE, and the operation result is output as a signal SQ. ​

[0147] The flip-flop circuit 110 of the scan output circuit 80 can be a flip-flop of the last stage in a multi-flip-flop circuit of Figure 18 or Figure 16 . Figure 17

[0148] For example, in Figure 17 , it is assumed that flip-flop circuits are connected in the order of FF0, FF1, FF2, FF3, FF4, FF5, FF6, and FF7. The output of a preceding flip-flop circuit is connected to the input of a succeeding flip-flop circuit. For example, when it is assumed that the input signals of FF0 are D0, SI, SE, and CK, and the output signals of FF0 are Q0 and QI0 (e.g., QI of the second latch circuit 30), FF1 receives QI0 as the input signal SI. SE and CK can be input so that the remaining inputs are the same as the inputs of FF0. D is received according to the scan chain, but QI is received from the flip-flop circuit of the preceding stage (e.g., the output terminal of the output driver circuit 40). The scan chain in which the flip-flop circuits are connected to each other can be implemented, and the flip-flop of the last stage FF7 can include the scan output circuit 80 as shown in Figure 18 .

[0149] Figure 19 is a circuit diagram showing a flip-flop circuit 100 according to some example embodiments. For ease of description, the difference between the following example embodiments and the example embodiments of Figure 4 will mainly be described, and the description of the remaining elements will be the same.

[0150] According to some example embodiments, the second latch circuit 30' can be implemented as shown in Figure 19 : a transistor MPS, a transistor MNS1, and a transistor MNS2 connected in series between a power supply terminal and a VSS terminal; a tri-state circuit 35; and an inverter circuit 36.

[0151] More specifically, in the second latch circuit 30', the transistor MPS, the transistor MNS1, and the transistor MNS2 can be connected in series between the power supply terminal and the VSS terminal. The gate of the transistor MPS is connected to a node N2, and the drain terminal of the transistor MPS can be connected to a node NS, which is an output terminal of the second latch circuit 30'. The transistor MNS1 and the transistor MNS2 are connected in series between the node NS and the VSS terminal.

[0152] The clock signal CK is input to the gate of the transistor MNS1, and the output terminal of the data inverter circuit SINV is connected to the gate of the transistor MNS2.

[0153] ​According to some exemplary embodiments, the first latch circuit 20 can further include a data inverter circuit SINV. That is, the first latch circuit 20 can include the inverter circuit (MP1 and MN1), the transistor MN2, the NAND circuit 220, and the data inverter circuit SINV. The data inverter circuit SINV is connected between the node N1 and the gate of the transistor MNS2 of the second latch circuit 30', and provides a signal nDN obtained by inverting the signal of the node N1 to the gate of the transistor MNS2.

[0154] As described above, since the node N1 is at the logic low level (L) and the node N2 is at the logic high level (H), the signal of the node N2 is used as the clock buffer signal CKb, and the data inverter circuit SINV inverts the signal DN of the node N1 and provides the inverted signal nDN to the transistor MNS2. That is, the non-inverted data signal nDN should be provided to the gate of each of the transistor MPS and the transistor MNS2, and the transistor MPS can be gated by the clock buffer signal CKb of the node N2, in which the signal of the node N1 is inverted, and the transistor MNS2 can be gated by the output signal nDN of the data inverter circuit SINV.

[0155] In an embodiment, Figure 19 The flip-flop circuit 100 can further include the reset transistors MPR and MNR as shown in Figure 9 .

[0156] Figure 20 is a circuit diagram illustrating a flip-flop circuit according to some exemplary embodiments. For ease of description, differences between the following exemplary embodiments and the above-described exemplary embodiments will be mainly described, and the description of the remaining elements will be the same.

[0157] Referring to Figure 20 , the first latch circuit 20" can further include an inverter circuit 230 between the node N1 and the gate of the transistor MN2. The inverter circuit 230 includes a transistor MPI and a transistor MNI. The node N1 is connected to the input terminal of the inverter circuit 230 and the gate of the transistor MN4, and the gate of the transistor MN2 can be connected to the output terminal NI of the inverter circuit 230.

[0158] Because the gate of the transistor MN4 of the NAND circuit 220, the input terminal of the inverter circuit 230, that is, the gate of the transistor MPI and the gate of the transistor MNI, is connected to the node N1, a signal S obtained by inverting the signal DN of the node N1 can be applied to the gate of the transistor MN2.

[0159] Figure 21is a circuit diagram showing a flip-flop circuit according to some exemplary embodiments. For ease of description, differences between the following exemplary embodiments and the above exemplary embodiments will mainly be described, and descriptions of the circuit configurations of the remaining components (e.g., the first latch circuit 20, the second latch circuit 30, and the output driver circuit) will be the same as Figure 4 in the exemplary embodiments described above.

[0160] Reference will be made to Figure 21 , which is different from Figure 4 , the scan MUX circuit 10 can include six p-type transistors connected between the power supply terminal and the node N1, and six n-type transistors connected between the node N1 and the VSS terminal.

[0161] Specifically, in the scan MUX circuit 10, a plurality of p-type transistors MP31, MP32, and MP33 are connected in series between the power supply terminal and the node N1, and a plurality of p-type transistors MP34, MP35, and MP36 are connected in series between the power supply terminal and the node N1. That is, the p-type transistors MP31, MP32, and MP33 and the p-type transistors MP34, MP35, and MP36 are connected in parallel between the power supply terminal and the node N1.

[0162] Further, in the scan MUX circuit 10, a plurality of n-type transistors MN31, MN32, and MN33 are connected in series between the node N1 and the VSS terminal, and a plurality of n-type transistors MN34, MN35, and MN36 are connected in series between the node N1 and the VSS terminal. That is, the transistors MN31, MN32, and MN33 and the transistors MN34, MN35, and MN36 are connected in parallel between the node N1 and the VSS terminal.

[0163] The scan enable signal SE is applied to the gate of each of the transistor MP31 and the transistor MN36, and the clock signal CK is applied to the gate of each of the transistor MP32 and the transistor MP36. The data signal D is applied to the gate of each of the transistor MP33 and the transistor MN32, and the inverted scan enable signal nse is applied to the gate of each of the transistor MP34 and the transistor MN33. The clock buffer signal CKb is applied to the gate of each of the transistor MN31 and the transistor MN34.

[0164] In the scan MUX circuit 10 of the illustrated exemplary embodiments, when the clock signal CK is at a logic low level, the transistors MP32 and MP36 are turned on, and the transistors MN31 and MN34 are turned off, so that one of the scan input signal SI or the data signal D can be output to the node N1 in the same manner as Figure 4 in the exemplary embodiments described above when the scan enable signal SE is enabled.

[0165] Meanwhile, the transistors MP1, MN1, and MN2 can function as holding transistors that hold an input signal of the flip-flop circuit 100 at the node N1, and the transistors MP36, MP32, MN31, and MN34 can function as input control transistors that determine whether the flip-flop circuit 100 receives a data input.

[0166] Figures 22 to 24 is a top view for describing a layout of the flip-flop circuit of Figure 21 For convenience of description, differences between the following layout and the layout of Figures 6 to 8 will be mainly described.

[0167] Unlike the flip-flop of Figures 6 to 8 , the flip-flop of Figures 22 to 24 is implemented in a single height layout. Figure 22 is a top view showing FEOL up to the flip-flop circuit 100 of Figure 21 . Figure 23 is a top view showing up to MOL. Figure 24 is a top view showing up to BEOL.

[0168] In the layout implemented in the single height layout, a plurality of functional circuits can be arranged in the Y direction between two power lines. In the illustrated example, the clock buffer circuit 50, the scan MUX circuit 10, the first latch circuit 20, the second latch circuit 30, and the output driver circuit 40 are sequentially arranged in the X direction between the power supply line PW1 and the ground power supply line PW2. The power supply line PW1 and the ground power supply line PW2 are spaced apart from each other in the Y direction.

[0169] When the first latch circuit 20 is described in detail with reference to Figure 22 , the node N1 is formed above the gate stack 120 of the transistor MN3 and the gate stack of the transistor MN4, the node N2 is formed above the gate stack of the transistor MP1, and the node N3 is formed above the gate stack of the transistor MN2.

[0170] When described by matching Figure 23 with Figure 24 , the node N1 is electrically connected while intersecting the first metal line M1, and the node N2 is electrically connected while intersecting the first metal line from MP3 to MP3 above. The node N3 is electrically connected to the source contact 170 of the transistor MN3, the drain contact 170 of the transistor MP1, and the gate contact of the transistor MN2 through the first metal line, the second metal line, and the third metal line.

[0171] That is, since the clock buffer signal CKb is provided to the scan MUX circuit 10 through the node N2 (i.e., the output node of the NAND circuit), each of the transistor MP1 and the second latch circuit 30, the PnR efficiency from the clock buffer circuit can be increased, and thus, by using the clock buffer signal internally generated during operation, the flip-flop circuit 100 can be more synchronized with the operating frequency of the clock, thereby improving performance.

[0172] Figure 25 is a circuit diagram illustrating a flip-flop circuit according to some exemplary embodiments. For ease of description, differences between the following exemplary embodiments and the above-described exemplary embodiments will be mainly described, and descriptions of the remaining components such as the scan inverter circuit 15, the first latch circuit 25, the second latch circuit 30", and the inverted clock generation circuit 52 will be the same as in the Figure 10 exemplary embodiments.

[0173] Referring to Figure 25 , the flip-flop circuit 100 can include a scan MUX circuit 10', a first latch circuit 25, a second latch circuit 30", and an output driver circuit 40.

[0174] The first latch circuit 25 can be implemented in the same manner as the first latch circuit 25 of Figure 10 . In the scan MUX circuit 10', the transistors are implemented in the same manner as the scan MUX circuit of Figure 21 , but since the NOR circuit has a characteristic that the output is low when all of the inputs are high, the inverted clock signal nclk is input to the gate of each of the transistors MN31 and MN34, and the node N2 (signal CKb) is connected to the gate of each of the transistors MP32 and MP36.

[0175] According to some exemplary embodiments, the second latch circuit 30" can include an AOI circuit including an AND circuit 37 and a NOR circuit 38, and an inverter circuit 33.

[0176] Figure 26 is a circuit diagram illustrating a flip-flop circuit according to some exemplary embodiments.

[0177] Referring to Figure 26 , the flip-flop circuit 100 can include a scan MUX circuit 10, a first latch circuit 20', a second latch circuit 30', and an output driver circuit 40. The scan MUX circuit 10 and the second latch circuit 30' are implemented in the same manner as the scan MUX circuit 10 in Figure 3 or Figure 4 , and the second latch circuit 30' in Figure 19 , and thus descriptions thereof will be omitted.

[0178] The first latch circuit 20' can further include a transistor MPT. The transistor MPT is a p-type transistor connected between the power terminal and the node N3 and having a gate connected to the node N1. The transistor MPT turns on / off in response to the signal DN of the node N1, thereby changing the signal of the node N3, and thus, the transistor MN2 or MNS2 whose gate is connected to the node N3 turns on / off.

[0179] That is, the transistor MPT and the transistor MN4 can function as an inverter circuit which receives and inverts the signal DN of the node N1 and outputs the inverted signal as the signal S through the node N3.

[0180] Further, the node N3 is connected to the gate terminal of the transistor MNS2 together with the drain terminal of the transistor MPT and the gate terminal of the transistor MN2 to operate as a terminal of the signal S input to the second latch circuit 30', and thus, it is possible to prevent glitch from occurring.

[0181] Figure 27 is a circuit diagram illustrating a flip-flop circuit according to some exemplary embodiments.

[0182] Referring to Figure 27 , the flip-flop circuit 100 can include a scan MUX circuit 10', a first latch circuit 20', a second latch circuit 30", and an output driver circuit 40. The first latch circuit 20' and the output driver circuit 40 are the same as those of Figure 26 , and thus the description thereof will be omitted.

[0183] The scan MUX circuit 10' includes a multiplexer 11 configured to select one of a data signal D and a scan input signal SI in response to a scan enable signal SE and an inverted scan enable signal, and transistors MP43, MP41, MN41, and MN43 connected in series between the power terminal and the VSS terminal.

[0184] The transistor MP41 and the transistor MN41 form an inverter circuit 61 to invert the output signal DN of the multiplexer 11. The inverter circuit 61 outputs the output signal DN to the node N1 according to a clock signal CK or a clock buffer signal CKb. The source terminal (node A) of the transistor MP41 is connected to the drain terminal of the transistor MP43, and the source terminal of the transistor MP43 is connected to the power terminal. The source terminal (node B) of the transistor MN41 is connected to the drain terminal of the transistor MN43, and the source terminal of the transistor MN43 is connected to the VSS terminal. The transistor MP43 is gated by the clock signal CK, and the transistor MN43 is gated by the clock buffer signal CKb of the node N2.

[0185] The second latch circuit 30" includes: transistors MPS, MNS1 and MNS2 connected in series between the power supply terminal and the VSS terminal; an inverter circuit 65 connected between the node A and the node B; and the inverter circuit 39.

[0186] The gate of the transistor MPS is connected to the node N2, the clock signal CK is applied to the gate of the transistor MNS1, and the gate of the transistor MNS2 is connected to the node N3. The inverter circuit 65 is connected to each of the node A and the node B of the inverter circuit 61 of the scan MUX circuit 10". That is, the inverter circuit 65 and the inverter circuit 61 share the modified power supply terminal (node A) and the modified power supply ground terminal (node B).

[0187] Figure 28 is a circuit diagram illustrating a flip-flop circuit according to some example embodiments.

[0188] Referring to Figure 28 , the flip-flop circuit 100 can include the scan MUX circuit 10', the first latch circuit 20', the second latch circuit 30', and the output driver circuit 40. The first latch circuit 20', the second latch circuit 30', and the output driver circuit 40 are the same as those of the flip-flop circuit 100 of Figure 27 , and thus a description thereof will be omitted.

[0189] The first latch circuit 20' further includes a reset transistor MPR and a reset transistor MNR. The reset transistor MPR is connected between the power supply terminal and the node NR, and is gated by the reset signal R, and the reset transistor MNR is connected between the node N2 which is an output terminal of the first latch circuit 20' and the VSS terminal, and is gated by the reset signal R.

[0190] The NAND circuit 220 is connected between the node NR and the VSS terminal. That is, the source and drain terminals of the transistor MP2 and the source and drain terminals of the transistor MP3 are connected in parallel between the node NR and the node N2.

[0191] The transistor MPT is connected between the node NR and the node N3, and is gated by the signal of the node N1.

[0192] Figure 29 is a circuit diagram illustrating a flip-flop circuit according to some example embodiments.

[0193] Referring to Figure 29 , the flip-flop circuit 100 can include the D flip-flop circuit 29'10, the first latch circuit 20', the second latch circuit 30", and the output driver circuit 40. The first latch circuit 20', the second latch circuit 30", and the output driver circuit 40 are the same as those of the flip-flop circuit 100 of Figure 30 , and thus a description thereof will be omitted. Figure 28 ​

[0194] The flip-flop circuit can not use the scan MUX circuit. That is, the flip-flop circuit can include a D flip-flop circuit 2910 in the front end of the first latch circuit 20'. The D flip-flop circuit 2910 includes a transistor MP44 connected between a power terminal and a node A, transistors MP51 and MP52 connected in series between the node A and a node N1, and transistors MP53 and MP54 connected in series between the node A and the node N1 and connected in parallel with the transistors MP51 and MP52. In addition, the D flip-flop circuit 2910 can include transistors MN52 and MN53 connected in series between the node N1 and a node B, transistors MN54 and MN51 connected in series between the node N1 and the node B and connected in parallel with the transistors MN52 and MN53, and a transistor MN44 connected between the node B and a VSS terminal. The transistors MP51 and MN51 can be gated by a scan enable signal SE, the transistors MP52 and MN52 can be gated by a data signal D, and the transistors MP53 and MN53 can be gated by an inverted scan enable signal nse. The transistors MP54 and MN54 can be gated by a scan input signal SI. In addition, the transistor MP44 can be gated by a clock signal CK, and the transistor MN44 can be gated by a clock buffer signal CKb.

[0195] In Figure 29 the flip-flop circuit, the D flip-flop circuit 2910 can use fewer transistors than the scan MUX circuit to input data to the first latch circuit 20' based on the data, the scan input signal, the scan enable signal, and the clock signal.

[0196] Figure 30 is a circuit diagram illustrating a flip-flop circuit according to some example embodiments.

[0197] Referring to Figure 30 , the flip-flop circuit 100 can include a scan MUX circuit 10", a first latch circuit 20', a second latch circuit 30", and an output driver circuit 40. Figure 30 The flip-flop circuit 100 of Figure 24 is the same as , and thus a description thereof will be omitted.

[0198] The scan MUX circuit 10' includes transistors MP43, MP41, MN41, and MN43 connected in series between a power terminal and a VSS terminal.

[0199] The transistor MP43 is connected between the power supply terminal and the node A, and includes a gate to which the clock signal CK is applied. The transistor MP41 and the transistor MN41 form an inverter circuit 61 to invert the output signal DN of the multiplexer 11. The inverter circuit 61 outputs the output signal DN to the node N1 in accordance with the clock signal CK or the clock buffer signal CKb. The source terminal (node A) of the transistor MP41 is connected to the drain terminal of the transistor MP43, and the source terminal of the transistor MP43 is connected to the power supply terminal. The source terminal (node B) of the transistor MN41 is connected to the drain terminal of the transistor MN43, and the source terminal of the transistor MN43 is connected to the VSS terminal. The transistor MP43 is gated by the clock signal CK, and the transistor MN43 is gated by the clock buffer signal CKb of the node N2.

[0200] The transistors MPT and MN3 whose drain terminals are connected to the node N3 can function as an inverter that receives a signal of the node N1 and outputs an inverted signal to the node N3, together with the transistor MN4, in place of the data inverter circuit SINV of Figure 16 . That is, the number of transistors can be reduced more than that of the data inverter circuit SINV of Figure 16 .

[0201] Further, in the inverter circuit 65 of the second latch circuit 30", the source terminal of the transistor MP42 is connected to the node A, the source terminal of the transistor MN42 is connected to the node B, and the number of transistors for receiving the clock signal CK in the second latch circuit 30" is reduced, so that the dependency on the slew rate of the clock signal can be reduced. That is, operation can be more efficiently performed even at a low voltage.

[0202] The NAND circuit 220 can include the transistor MPC and the transistor MP2 connected in series between the power supply terminal and the node N2, the transistor MP3 connected between the power supply terminal and the node N2, and the transistor MN3 and the transistor MN4 connected in series between the node N2 and the VSS terminal. The gate of the transistor MPC is connected to the output terminal of the NOR circuit 70, and turns on / off in response to the signal CKC.

[0203] The transistor MN3 is connected between the node N2 and the node N3, and the transistor MN4 is connected between the node N3 and the VSS terminal. The gate of each of the transistor MP2 and the transistor MN4 is connected to the node N1, and the clock signal CK can be supplied to the gate of each of the transistor MP3 and the transistor MN3.

[0204] The first latch circuit 20' can further include the transistor MPT. The transistor MPT is a p-type transistor connected between the power supply terminal and the node N3, and the gate of which is connected to the node N1.

[0205] The NOR circuit 70 receives a signal of the node ND and an output signal QB of the inverter circuit 39, and outputs a signal CKC. The output signal DN of the multiplexer 11 configured to select one of a data signal D and a scan input signal SI according to a scan enable signal SE and an inverted enable signal nse is output to the node ND.

[0206] That is, the inverted output signal QB of the second latch circuit 30" and the inverted input signal DN of the first latch circuit 20' are compared, and only when the two signals are different, the signal CKC gates the transistor MPC and the transistor MNC to operate the NAND circuit 220 so that the signal of the node N2 can be latched to the node NS.

[0207] That is, the case where the two signals QB and DN are the same is a case where the flip-flop circuit 100 does not need to operate, and thus unnecessary power consumption due to the inversion of the clock signal can be reduced.

[0208] Figure 31 is a circuit diagram illustrating a flip-flop circuit according to some exemplary embodiments.

[0209] The first latch circuit 20 can include an inverter circuit 3110, a transistor MN2 connected in series between a power terminal and a VSS terminal, and a NAND circuit 220 configured to receive an output signal of the inverter circuit 3110 and a clock signal CK. For example, the inverter circuit 3110 can include a transistor MP1 and a transistor MN1, and the transistor MN2 can be connected in series between a source terminal of the transistor MN1 and the VSS terminal and can have a gate connected to the node N3.

[0210] The gate of the transistor MP1 is connected to the node N1, the clock signal CK is provided to the gate of the transistor MN1, and the gate of the transistor MN2 is connected to the node N3. The transistor MP1, the transistor MN2, and the transistor MN1 receive the output signal of the scan MUX circuit 10 and store the output signal at the node N1 according to the clock signal CK, the clock buffer signal CKb, and the signal S.

[0211] The transistor MN3 is connected between the node N2 and the node N3, and the transistor MN4 is connected between the node N3 and the VSS terminal. The gate of each of the transistor MP2 and the transistor MN4 is connected to the node N1, and the clock signal CK can be provided to the gate of each of the transistor MP3 and the transistor MN3.

[0212] The first latch circuit 20 can further include a transistor MPT. The transistor MPT is a p-type transistor connected between the node N10 and the node N3 and having a gate connected to the node N1.

[0213] The NAND circuit 220 included in the first latch circuit 20 is connected between the node N10 and the VSS terminal, and performs a NAND operation on the signal of the node N1 and the clock signal, and outputs the operation result to the node N2.

[0214] The node N3 is connected to the source terminal of the transistor MN3, the gate terminal of the transistor MN2, and the gate terminal of the transistor MNS2. The node N10 is connected to the drain terminal of the reset transistor MPR, the source terminal of the transistor MP2, and the source terminal of the transistor MP3.

[0215] The transistor MPT turns on / off in response to the signal DN of the node N1, thereby changing the signal of the node N3, and thus, the transistor MN2 or MNS2 whose gate is connected to the node N3 turns on / off. Therefore, the charge leakage of the transistor MN1 or MNS1 can be prevented from occurring.

[0216] The first latch circuit 20 further includes a reset transistor MPR and a reset transistor MNR. The reset transistor MPR is connected between the power terminal and the node N10 and is gated by a reset signal, and the reset transistor MNR is connected between the node N2 and the VSS terminal and is gated by the reset signal.

[0217] Figure 32 is a circuit diagram illustrating a flip-flop circuit according to some example embodiments.

[0218] Referring to Figure 32 , the flip-flop circuit 100 can include an input circuit 13, a first latch circuit 20', a second latch circuit 30", and an output driver circuit 40. Hereinafter, differences between the input circuit 13 and the scan MUX circuit 10 of the present example embodiment will be mainly described. Figure 31

[0219] The input circuit 13 can include a transistor MPD2, a transistor MND2, and an inverter including a transistor MPD1 and a transistor MND1, which is connected between a node A and a node B. The node A is a drain terminal of the transistor MPD2, and the node B is a drain terminal of the transistor MND2. The input circuit 13 is more simply implemented than other embodiments, e.g., using a smaller number of transistors for the input of the first latch circuit 20'.

[0220] The inverter can output from the node ND to the node N1 when the transistor MPD2 turns on according to the clock signal CK or the transistor MND2 turns on according to the signal CKb. That is, the inverter inverts the data signal D of the node ND as the signal DN of the node N1.

[0221] Figures 33 to 35 ​is a top view for describing a layout of a flip-flop circuit according to some exemplary embodiments. Figure 33 is a top view showing up to the FEOL of the flip-flop circuit 100 according to some exemplary embodiments. Figure 34 is a top view showing up to the MOL. Figure 35 is a top view showing up to the BEOL. For convenience of description, only the difference in the arrangement of each functional circuit from Figures 6 to 8 will be described. Also, the description that is repeated with Figures 6 to 8 will be omitted.

[0222] According to the exemplary embodiments shown in Figures 33 to 35 , the flip-flop circuit can be implemented in a single height layout. The layout shown illustrates the flip-flop circuit of Figure 4 . The scan inverter circuit 15, the scan MUX circuit 10, the inverter circuit 230 of the first latch circuit, the NAND circuit 220, the OAI circuit including the OR circuit 31 of the second latch circuit and the NAND circuit 32, the inverter circuit 33, and the output driver circuit 40 can be arranged in order from left to right.

[0223] Although exemplary embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in various different forms. It will be understood by those of ordinary skill in the art that the present disclosure can be implemented in other specific forms without departing from the technical spirit or essential characteristics of the present disclosure. Therefore, the exemplary embodiments set forth herein should be considered in a descriptive sense only and not for purposes of limitation. Accordingly, the exemplary embodiments set forth herein are illustrative in nature and are provided to more fully describe the disclosure. The embodiments disclosed herein are well suited to achieving the present disclosure along with other contributions to the art. However, other variations of those embodiments can be devised without departing from the spirit or the scope of the present disclosure. Accordingly, the disclosure is not limited to the specific embodiments set forth herein, but includes all changes, modifications, and further applications falling within the spirit and scope thereof as defined in the claims.

Claims

1. A master latch circuit comprising: a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series between a power terminal and a power ground terminal; a first node connected to a drain terminal of the first p-type transistor and a drain terminal of the first n-type transistor; and a NAND circuit configured to receive a signal of the first node and a clock signal, perform a NAND operation, and output a result of the NAND operation to a second node, wherein the NAND circuit comprises a second p-type transistor connected in parallel with a third p-type transistor between the power terminal and the second node, and a third n-type transistor connected in series with a fourth n-type transistor between the second node and the power ground terminal, wherein a gate of the second p-type transistor and a gate of the fourth n-type transistor are connected to the first node, wherein a gate of the first n-type transistor, a gate of the third p-type transistor, and a gate of the third n-type transistor are configured to receive the clock signal, and wherein a gate of the first p-type transistor is connected to the second node. a third node connected to the gates of the third n-type transistor, the fourth n-type transistor, and the second n-type transistor.

2. The master latch circuit of claim 1, wherein, the master latch circuit is connected to a scan multiplexer (MUX) circuit configured to output a data signal or a scan input signal to the first node according to a scan enable signal, the clock signal, and a signal of the second node, 3. The master latch circuit of claim 1, wherein, wherein the scan MUX circuit comprises a first inverter circuit having an output connected to the first node and configured to output the data signal or the scan input signal according to the clock signal or the signal of the second node, a fourth p-type transistor and a fifth p-type transistor connected in series between a first terminal of the first inverter circuit and the power terminal, a sixth p-type transistor and a seventh p-type transistor connected in series between the first terminal of the first inverter circuit and the power terminal, an eighth n-type transistor and a fifth n-type transistor connected in series between a second terminal of the first inverter circuit and the power ground terminal, and a sixth n-type transistor and a seventh n-type transistor connected in series between the second terminal of the first inverter circuit and the power ground terminal, wherein a gate of the fourth p-type transistor and a gate of the sixth n-type transistor are configured to receive the scan enable signal, wherein a gate of the fifth p-type transistor and a gate of the fifth n-type transistor are configured to receive the data signal, wherein a gate of the sixth p-type transistor and a gate of the eighth n-type transistor are configured to receive an inverted scan enable signal, and wherein a gate of the seventh p-type transistor and a gate of the seventh n-type transistor are configured to receive the scan input signal. an output of the master latch circuit is provided to a slave latch circuit, and 4. The master latch circuit of claim 1, wherein, wherein the slave latch circuit comprises an OR / AND / inverter (OAI) circuit configured to store and output a signal of the second node in response to the clock signal. the slave latch circuit further comprises a second inverter circuit configured to invert an output signal of the OAI circuit and provide the inverted output signal to the OAI circuit.

5. The master latch circuit of claim 4, wherein, ​ 6.The master latch circuit of claim 1, further comprising: a p-type reset transistor connected between the power terminal and the source terminal of the second p-type transistor, wherein a gate of the p-type reset transistor is configured to receive a reset signal; and an n-type reset transistor connected between the second node and the power ground terminal, wherein a gate of the n-type reset transistor is configured to receive the reset signal.

7. The master latch circuit of claim 4, wherein, The OAI circuit includes: a ninth p-type transistor, a ninth n-type transistor, and a tenth n-type transistor connected in series between the power terminal and the power ground terminal; a fourth node connected to a drain terminal of the ninth p-type transistor and a drain terminal of the ninth n-type transistor; a fifth node connected to a source terminal of the ninth n-type transistor and a drain terminal of the tenth n-type transistor; a tenth p-type transistor connected in series with the tenth p-type transistor between the power terminal and the fourth node; an eleventh n-type transistor connected between the fourth node and the fifth node; and a third inverter circuit configured to invert a signal of the fourth node and input an inverted signal of the fourth node to gates of each of the tenth p-type transistor and the eleventh n-type transistor, wherein a gate of the ninth p-type transistor is connected to the second node, and wherein a gate of the eleventh p-type transistor and a gate of the ninth n-type transistor are configured to receive a clock signal.

8. The master latch circuit of claim 7, wherein, The gate of the ninth p-type transistor and the gate of the tenth n-type transistor are connected to the second node. 9.The master latch circuit of claim 7, further comprising a fourth inverter circuit SINV configured to invert a signal of the first node, and wherein a gate of the tenth n-type transistor is connected to an output terminal of the fourth inverter circuit. 10.The master latch circuit of claim 1, further comprising a fifth inverter circuit configured to invert a signal of the first node and input an inverted signal of the first node to a gate of the second n-type transistor. 11.A master latch circuit comprising: a first p-type transistor, a second p-type transistor, and a first n-type transistor connected in series between a power terminal and a power ground terminal; a first node connected to the second p-type transistor and the first n-type transistor; and a NOR circuit configured to receive a signal of the first node and an inverted clock signal, perform a NOR operation, and output a result of the NOR operation to a second node, wherein the NOR circuit includes: a third p-type transistor connected in series with a fourth p-type transistor between the power terminal and the second node; a third node connected to the third p-type transistor and the fourth P-type transistor; and a second n-type transistor connected in parallel with a third n-type transistor between the second node and the power ground terminal, wherein a gate of the third p-type transistor and a gate of the second n-type transistor are connected to the first node, wherein a gate of the third n-type transistor, a gate of the fourth p-type transistor, and a gate of the second p-type transistor are configured to receive the inverted clock signal, and wherein a gate of the first n-type transistor is connected to the second node. ​ 12. The master latch circuit of claim 11, wherein, The master latch circuit is connected to a scan multiplexer (MUX) circuit configured to provide a data signal or a scan input signal to a first node in accordance with a scan enable signal, the inverted clock signal, and a signal of a second node, wherein the scan MUX circuit comprises: a first inverter circuit having an output connected to the first node and outputting the data signal or the scan input signal in accordance with an inverted clock signal or a signal of the second node; a fourth p-type transistor and a fifth p-type transistor connected in series between a first terminal of the first inverter circuit and a power terminal; a sixth p-type transistor and a seventh p-type transistor connected in series between the first terminal of the first inverter circuit and the power terminal; a fourth n-type transistor and a fifth n-type transistor connected in series between a second terminal of the first inverter circuit and a power ground terminal; and a sixth n-type transistor and a seventh n-type transistor connected in series between the second terminal of the first inverter circuit and the power ground terminal, wherein a gate of each of the fourth p-type transistor and the sixth n-type transistor is configured to receive the scan enable signal; wherein a gate of the fifth p-type transistor and a gate of the fifth n-type transistor are configured to receive the data signal, wherein a gate of the sixth p-type transistor and a gate of the fourth n-type transistor are configured to receive the inverted scan enable signal, and wherein a gate of the seventh p-type transistor and a gate of the seventh n-type transistor are configured to receive the scan input signal.

13. The master latch circuit of claim 11, wherein, The master latch circuit is connected to a scan multiplexer (MUX) circuit configured to provide a data signal or a scan input signal to a first node in accordance with a scan enable signal, the inverted clock signal, and a signal of a second node, wherein the scan MUX circuit comprises: an eighth p-type transistor, a ninth p-type transistor, and a tenth p-type transistor connected in series between a power terminal and the first node; eleventh, twelfth, and thirteenth p-type transistors connected in series between the power terminal and the first node, respectively; an eighth n-type transistor, a ninth n-type transistor, and a tenth n-type transistor connected in series between the first node and a power ground terminal; and eleventh, twelfth, and thirteenth n-type transistors connected in series between the first node and the power ground terminal, wherein a gate of the eighth p-type transistor is configured to receive the scan enable signal, wherein a gate of the ninth p-type transistor is configured to receive the clock signal, wherein a gate of the tenth p-type transistor is configured to receive the data signal, wherein a gate of the eleventh p-type transistor is configured to receive the inverted scan enable signal, wherein a gate of the twelfth p-type transistor is configured to receive the scan input signal, wherein a gate of the thirteenth p-type transistor is configured to receive the clock signal, wherein a gate of the eighth n-type transistor is configured to receive the signal of the second node, wherein a gate of the ninth n-type transistor is configured to receive the data signal, wherein a gate of the tenth n-type transistor is configured to receive the inverted scan enable signal, wherein a gate of the eleventh n-type transistor is configured to receive a signal of the second node, wherein a gate of the twelfth n-type transistor is configured to receive a scan input signal, and wherein the thirteenth n-type transistor is configured to receive a scan enable signal.

14. The master latch circuit of claim 12, wherein the master latch circuit is included in a flip-flop circuit, and wherein the flip-flop circuit further comprises: an AND / OR / inverter (AOI) circuit configured to store a signal of the second node and output the signal to a fourth node in response to the inverted clock signal; and a second inverter circuit configured to invert and drive a signal of the fourth node.

15. A flip-flop circuit, comprising: a scan multiplexer (MUX) circuit, a MUX output terminal of which is connected to a first node; a first latch circuit connected between the first node and a second node; a second latch circuit connected between the second node and a third node; and an output driving circuit configured to drive and output a signal of the third node, wherein the first latch circuit comprises: a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series between a power terminal and a power ground terminal; a NAND circuit configured to receive a signal of the first node and a clock signal, perform a NAND operation, and output a result of the NAND operation to the second node, wherein the NAND circuit comprises: a second p-type transistor connected in parallel with a third p-type transistor between the power terminal and the second node; and a third n-type transistor and a fourth n-type transistor connected in series with each other between the second node and the power ground terminal, wherein a drain terminal of the first p-type transistor and a drain terminal of the first n-type transistor are connected to the first node, wherein a gate of the second p-type transistor and a gate of the fourth n-type transistor are connected to the first node, wherein a gate of the first n-type transistor, a gate of the third p-type transistor, and a gate of the third n-type transistor are configured to receive the clock signal, wherein the first n-type transistor and the second n-type transistor are not turned on at the same time, and wherein a gate of the first p-type transistor is connected to the second node.

16. The flip-flop circuit of claim 15, wherein the fourth node is connected to gates of the third n-type transistor, the fourth n-type transistor, and the second n-type transistor. the scan MUX circuit comprises:

17. The flip-flop circuit of claim 15, wherein, a first inverter circuit, an inverter output terminal of which is connected to the first node, and which is configured to output a data signal or a scan input signal according to a signal of the second node or a clock signal; a fourth p-type transistor connected in series with a fifth p-type transistor between a first terminal of the first inverter circuit and the power terminal; a sixth p-type transistor connected in series with a seventh p-type transistor between the first terminal of the first inverter circuit and the power terminal; a fifth n-type transistor connected in series with a sixth n-type transistor between a second terminal of the first inverter circuit and the power ground terminal; and an eighth n-type transistor connected in series with a ninth n-type transistor between the second terminal of the first inverter circuit and the power ground terminal, ​ wherein a gate of the fourth p-type transistor and a gate of the seventh n-type transistor are configured to receive a scan enable signal, wherein a gate of the fifth p-type transistor and a gate of the sixth n-type transistor are configured to receive a data signal, wherein a gate of the sixth p-type transistor and a gate of the fifth n-type transistor are configured to receive an inverted scan enable signal, and wherein a gate of the seventh p-type transistor and a gate of the eighth n-type transistor are configured to receive a scan input signal.

18. The flip-flop circuit of claim 15, further comprising: a p-type reset transistor connected between a power terminal and a source terminal of the second p-type transistor, wherein a gate of the p-type reset transistor is configured to receive a reset signal; and an n-type reset transistor connected between the second node and a power ground terminal, wherein a gate of the n-type reset transistor is configured to receive the reset signal.

19. The flip-flop circuit of claim 17, wherein, The second latch circuit includes: a ninth p-type transistor, a ninth n-type transistor, and a tenth n-type transistor connected in series between a power terminal and a power ground terminal; a third node connected to a drain terminal of the ninth p-type transistor and a drain terminal of the ninth n-type transistor; a fifth node connected to a source terminal of the ninth n-type transistor and a drain terminal of the tenth n-type transistor; a tenth p-type transistor and an eleventh p-type transistor connected in series between the power terminal and the third node; an eleventh n-type transistor connected between the third node and the fifth node; and a third inverter circuit configured to invert a signal of the third node and input an inverted signal of the third node to a gate of each of the tenth p-type transistor and the eleventh n-type transistor, wherein a gate of the ninth p-type transistor is connected to the second node, and wherein a gate of the eleventh p-type transistor and a gate of the ninth n-type transistor are configured to receive a clock signal.

20. The flip-flop circuit of claim 18, wherein, The NAND circuit further includes a fourth inverter circuit configured to invert a signal of the first node and provide an inverted signal of the first node to a gate of the tenth n-type transistor.

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