Imaging element, method for manufacturing the same, stacked imaging element, and solid-state imaging device

Abstract

A camera element includes a photoelectric conversion section 23 formed by laminating a first electrode 21, a photoelectric conversion layer 23A formed of an organic material, and a second electrode 22. An inorganic oxide semiconductor material layer 23B is formed between the first electrode 21 and the photoelectric conversion layer 23A, includes a first layer 23C and a second layer 23D from the first electrode side, and satisfies ρ1 ≥ 5.9 g / cm 3 and ρ1 - ρ2 ≥ 0.1 g / cm 3 when an average film density of the first layer 23C within 3 nm from an interface between the first electrode 21 and the inorganic oxide semiconductor material layer 23B is set as ρ1 and an average film density of the second layer 23D is set as ρ2.

Description

TECHNICAL FIELD

[0001] The present application relates to an imaging element, a stacked imaging element, a solid-state imaging device, and an imaging element manufacturing method. BACKGROUND

[0002] In recent years, a stacked imaging element has been attracting attention as an imaging element for constituting an image sensor or the like. The stacked imaging element has a structure in which a photoelectric conversion layer (light receiving layer) is interposed between two electrodes. In addition, the stacked imaging element must have a structure for accumulating and transferring signal charges generated in the photoelectric conversion layer based on photoelectric conversion. In a conventional existing structure, a structure for accumulating and transferring signal charges to a floating drain (FD) electrode must be provided, and high-speed transfer must be performed to avoid delay of the signal charges.

[0003] An imaging element (photoelectric conversion element) for solving the above problem has been disclosed, for example, in Japanese Patent Application Publication No. 2016-63165. The imaging element includes:

[0004] an accumulation electrode formed on the first insulating layer;

[0005] a second insulating layer formed on the accumulation electrode;

[0006] a semiconductor layer formed so as to cover the accumulation electrode and the second insulating layer;

[0007] a collection electrode formed so as to be in contact with the semiconductor layer and separate from the accumulation electrode; a photoelectric conversion layer formed on the semiconductor layer; and

[0008] an upper electrode formed on the photoelectric conversion layer.

[0009] Imaging elements that use organic semiconductor materials in their photoelectric conversion layers can perform photoelectric conversion on specific colors (wavelength bands). Furthermore, due to this characteristic, when these imaging elements are used in solid-state imaging devices, a sub-pixel stacked structure (stacked imaging element) can be obtained—a structure impossible to achieve in conventional solid-state imaging devices where sub-pixels are composed of an on-chip color filter layer (OCCF) and the imaging element arranged in a two-dimensional arrangement (see, for example, Japanese Patent Application Publication No. 2011-138927). Another advantage is that false colors are not generated because de-mosaic processing is not required. In the following description, for convenience, an imaging element including a photoelectric conversion section disposed on or above a semiconductor substrate may be referred to as a "first type imaging element"; for convenience, a photoelectric conversion section constituting a first type imaging element may be referred to as a "first type photoelectric conversion section"; for convenience, an imaging element disposed in a semiconductor substrate may be referred to as a "second type imaging element"; for convenience, a photoelectric conversion section constituting a second type imaging element may be referred to as a "second type photoelectric conversion section".

[0010] Figure 70 An example of the construction of an existing stacked camera element (stacked solid-state camera device) is shown. Figure 70 In the example shown, a third photoelectric conversion unit 343A and a second photoelectric conversion unit 341A are stacked within the semiconductor substrate 370. The third photoelectric conversion unit 343A and the second photoelectric conversion unit 341A are second-type photoelectric conversion units constituting the third imaging element 343 and the second imaging element 341, respectively, as second-type imaging elements. Furthermore, a first photoelectric conversion unit 310A, constituting a first-type photoelectric conversion unit, is provided above the semiconductor substrate 370 (specifically, above the second imaging element 341). Here, the first photoelectric conversion unit 310A includes a first electrode 321, a photoelectric conversion layer 323 formed of an organic material, and a second electrode 322, and the first photoelectric conversion unit 310A constitutes the first imaging element 310, which is a first-type imaging element. In the second photoelectric conversion unit 341A and the third photoelectric conversion unit 343A, for example, blue light and red light can be photoelectricly converted respectively based on the difference in absorption coefficients. Furthermore, in the first photoelectric conversion unit 310A, for example, green light can be photoelectricly converted.

[0011] The charges generated by photoelectric conversion in the second photoelectric conversion section 341A and the third photoelectric conversion section 343A are temporarily accumulated in the second photoelectric conversion section 341A and the third photoelectric conversion section 343A, and then the above-mentioned charges are transferred to a second floating diffusion FD2 and a third floating diffusion FD3, respectively, through a vertical transistor (a gate section 345 is illustrated) and a transfer transistor (a gate section 346 is illustrated), and are further output to an external reading circuit (not illustrated), respectively. These transistors and the floating diffusions FD2 and FD3 are also formed in the semiconductor substrate 370.

[0012] The charges generated by photoelectric conversion in the first photoelectric conversion section 310A are accumulated in a first floating diffusion FD1 formed in the semiconductor substrate 370 via a contact hole section 361 and a wiring layer 362. Further, the first photoelectric conversion section 310A is also connected to a gate section 352 of an amplification transistor for converting a charge amount into a voltage via the contact hole section 361 and the wiring layer 362. In addition, the first floating diffusion FD1 constitutes a part of a reset transistor (a gate section 351 is illustrated). Reference numeral 371 denotes an element separation region, reference numeral 372 denotes an oxide film formed on a surface of the semiconductor substrate 370, reference numerals 376 and 381 denote interlayer insulating layers, reference numeral 383 denotes a protective material layer, and reference numeral 314 denotes an on-chip microlens.

[0013] Patent Application Publication No. 2014-045178 discloses an oxide semiconductor laminated film which is less likely to cause variation in electrical characteristics of a transistor (TFT) and has high stability. That is, the oxide semiconductor laminated film disclosed in Patent Application Publication No. 2014-045178 has the following features:

[0014] The oxide semiconductor laminated film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer each containing indium, gallium, and zinc and laminated in this order;

[0015] The second oxide semiconductor layer has a higher indium content than the first oxide semiconductor layer and the third oxide semiconductor layer;

[0016] The oxide semiconductor laminated film has an absorption coefficient of 3 x 10 -3 / cm or less in an energy range of 1.5 eV or more and 2.3 eV or less, as measured by CPM (constant photoconductivity spectroscopy).

[0017] [LIST OF CITATIONS]

[0018] [PATENT LITERATURE]

[0019] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-063165

[0020] [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-138927

[0021] [Patent Document 3] Japanese Patent Application Laid-Open No. 2014-045178 SUMMARY

[0022] [PROBLEMS TO BE SOLVED BY THE INVENTION]

[0023] However, in the technology disclosed in the above-described Japanese Patent Application Laid-Open No. 2016-63165, there is a limitation that the accumulation electrode and the second insulating layer formed on the accumulation electrode must be formed with the same length, and the interval between the collection electrode and the like is limited to be very fine. This complicates the manufacturing process and can lead to a decrease in manufacturing yield. Further, some of the materials constituting the semiconductor layer have been mentioned, but a more specific composition of the material or the constitution thereof is not mentioned. Further, a correlation formula between the carrier mobility of the semiconductor layer and the accumulated charge has been mentioned. However, matters relating to improvement in charge transport, such as matters relating to the carrier mobility of the semiconductor layer, which is important for transport of generated charges, or matters relating to the energy level relationship between the semiconductor layer and a portion of the photoelectric conversion layer adjacent to the semiconductor layer, and the like, are not mentioned. Further, in the technology disclosed in the above-described Japanese Patent Application Laid-Open No. 2014-045178, which is characterized by changing the composition ratio of each layer to achieve electrical stability, in each layer, in order to achieve a desired characteristic, it is necessary to provide a complicated device configuration in which the composition of each layer is intentionally controlled to establish the function of each layer and the like. Further, although the conductivity or the TFT characteristic is mentioned, there is no mention of matters relating to transport of charges.

[0024] Therefore, an object of the present application is to provide an imaging device, a stacked imaging device, a solid-state imaging apparatus, and an imaging device manufacturing method, in which the transport characteristic of charges accumulated in a photoelectric conversion layer is excellent, although the configuration and structure are simple.

[0025] [TECHNICAL SOLUTION]

[0026] A first aspect of the present application for achieving the above object is a camera element including a photoelectric conversion section formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode. An inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, and includes a first layer and a second layer from the first electrode side. When an average film density of the first layer within 3 nm, preferably 5 nm, more preferably 10 nm from an interface between the first electrode and the inorganic oxide semiconductor material layer is set as p1, and an average film density of the second layer is set as p2, p1 ≥ 5.9 g / cm 3 and p1 - p2 ≥ 0.1 g / cm 3 are satisfied. Preferably, p1 ≥ 6.1 g / cm 3 and p1 - p2 ≥ 0.2 g / cm 3 are satisfied. Note that, although the thickness of the first layer is more preferable to be thinner, it is also necessary to prevent the formation of a discontinuous layer, and therefore the minimum layer thickness of the first layer is set to 3 nm. Further, if the thickness is too thick, the characteristics of the inorganic oxide semiconductor material layer are reduced, and therefore the maximum layer thickness of the first layer is set to 10 nm. The same applies hereinafter.

[0027] A second aspect of the present application for achieving the above object is a camera element including a photoelectric conversion section formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode. An inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, and includes a first layer and a second layer from the first electrode side. The composition of the first layer is the same as that of the second layer. When an average film density of the first layer within 3 nm, preferably 5 nm, more preferably 10 nm from an interface between the first electrode and the inorganic oxide semiconductor material layer is set as p1, and an average film density of the second layer is set as p2, p1 - p2 ≥ 0.1 g / cm 3 is satisfied. Preferably, p1 - p2 ≥ 0.2 g / cm 3 is satisfied.

[0028] The imaging element of the third aspect of the present application for achieving the above object includes a photoelectric conversion section formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode. An inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, and the inorganic oxide semiconductor material layer includes a first layer and a second layer from the first electrode side. When an average oxygen deficiency generation energy of the first layer within 3 nm, preferably 5 nm, more preferably 10 nm from the interface between the first electrode and the inorganic oxide semiconductor material layer is set as E OD-1 , and an average oxygen deficiency generation energy of the second layer is set as E OD-2 , E OD-1 ≥ 2.8 eV and E OD-1 – E OD-2 ≥ 0.2 eV are satisfied. Preferably, E OD-1 ≥ 2.9 eV and E OD-1 – E OD-2 ≥ 0.3 eV are satisfied. Alternatively, the composition of the first layer is the same as that of the second layer, and E OD-1 – E OD-2 ≥ 0.2 eV is satisfied. Preferably, E OD-1 – E OD-2 ≥ 0.3 eV is satisfied.

[0029] The stacked imaging element of the present application for achieving the above object includes at least one of the above-described imaging elements of the first to third aspects of the present application.

[0030] The solid-state imaging device of the first aspect of the present application for achieving the above object includes a plurality of the above-described imaging elements of the first to third aspects of the present application. Further, the solid-state imaging device of the second aspect of the present application for achieving the above object includes a plurality of the above-described stacked imaging elements of the present application.

[0031] The imaging element manufacturing method of the present application for achieving the above object is a method of manufacturing an imaging element including a photoelectric conversion section formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode, and an inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, the inorganic oxide semiconductor material layer including a first layer and a second layer from the first electrode side. The imaging element manufacturing method includes a step of forming the second layer with input power smaller than that used when forming the first layer based on a sputtering method after forming the first layer based on a sputtering method. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a schematic partial cross-sectional view of the imaging element of Example 1.

[0033] Figure 2 is an equivalent circuit diagram of the imaging element of Example 1.

[0034] Figure 3 is an equivalent circuit diagram of the imaging element of Example 1.

[0035] Figure 4 is a schematic layout view of the first electrode and the charge accumulation electrode constituting the imaging element of Example 1 and the transistor constituting the control section.

[0036] Figure 5 is a view schematically showing the potential state of each part during the operation of the imaging element of Example 1.

[0037] Figure 6A , Figure 6B and Figure 6C are equivalent circuit diagrams of the imaging element of Example 1, Example 4, and Example 6 for explaining each part of Figure 5 (Example 1), Figure 20 and Figure 21 (Example 4), and Figure 32 and Figure 33 (Example 6), respectively.

[0038] Figure 7 is a schematic layout view of the first electrode and the charge accumulation electrode constituting the imaging element of Example 1.

[0039] Figure 8 is a schematic perspective view of the first electrode, the charge accumulation electrode, the second electrode, and the contact hole portion constituting the imaging element of Example 1.

[0040] Figure 9 is an equivalent circuit diagram of a modification of the imaging element of Example 1.

[0041] Figure 10 is a schematic layout view of the first electrode and the charge accumulation electrode constituting the modification of the imaging element of Example 1 shown in Figure 9 and the transistor constituting the control section.

[0042] Figure 11 is a schematic partial cross-sectional view of the imaging element of Example 2.

[0043] Figure 12 is a schematic partial cross-sectional view of the imaging element of Example 3.

[0044] Figure 13 is a schematic partial cross-sectional view of a modification of the imaging element of Example 3.

[0045] Figure 14 is a schematic partial cross-sectional view of another modification example of the imaging device of Embodiment 3.

[0046] Figure 15 is a schematic partial cross-sectional view of still another modification example of the imaging device of Embodiment 3.

[0047] Figure 16 is a schematic partial cross-sectional view of a part of the imaging device of Embodiment 4.

[0048] Figure 17 is an equivalent circuit diagram of the imaging device of Embodiment 4.

[0049] Figure 18 is an equivalent circuit diagram of the imaging device of Embodiment 4.

[0050] Figure 19 is a schematic layout view of the first electrode, the transfer control electrode, and the charge accumulation electrode that constitute the imaging device of Embodiment 4, and a transistor that constitutes the control section.

[0051] Figure 20 is a view that schematically shows potential states of the respective parts during operation of the imaging device of Embodiment 4.

[0052] Figure 21 is a view that schematically shows potential states of the respective parts during another operation of the imaging device of Embodiment 4.

[0053] Figure 22 is a schematic layout view of the first electrode, the transfer control electrode, and the charge accumulation electrode that constitute the imaging device of Embodiment 4.

[0054] Figure 23 is a schematic perspective view of the first electrode, the transfer control electrode, the charge accumulation electrode, the second electrode, and the contact hole section that constitute the imaging device of Embodiment 4.

[0055] Figure 24 is a schematic layout view of the first electrode, the transfer control electrode, and the charge accumulation electrode that constitute a modification example of the imaging device of Embodiment 4, and a transistor that constitutes the control section.

[0056] Figure 25 is a schematic partial cross-sectional view of a part of the imaging device of Embodiment 5.

[0057] Figure 26 is a schematic layout view of the first electrode, the charge accumulation electrode, and the charge discharge electrode that constitute the imaging device of Embodiment 5.

[0058] Figure 27is a schematic perspective view of a first electrode, a charge accumulation electrode, a charge discharge electrode, a second electrode, and a contact hole portion that constitute the imaging device of Embodiment 5.

[0059] Figure 28 is a schematic partial cross-sectional view of the imaging device of Embodiment 6.

[0060] Figure 29 is a schematic equivalent circuit diagram of the imaging device of Embodiment 6.

[0061] Figure 30 is a schematic equivalent circuit diagram of the imaging device of Embodiment 6.

[0062] Figure 31 is a schematic layout view of a first electrode and a charge accumulation electrode that constitute the imaging device of Embodiment 6 and a transistor that constitutes a control portion.

[0063] Figure 32 is a diagram that schematically shows potential states of each portion during operation of the imaging device of Embodiment 6.

[0064] Figure 33 is a diagram that schematically shows potential states of each portion during another operation (transfer period) of the imaging device of Embodiment 6.

[0065] Figure 34 is a schematic layout view of a first electrode and a charge accumulation electrode that constitute the imaging device of Embodiment 6.

[0066] Figure 35 is a schematic perspective view of a first electrode, a charge accumulation electrode, a second electrode, and a contact hole portion that constitute the imaging device of Embodiment 6.

[0067] Figure 36 is a schematic layout view of a first electrode and a charge accumulation electrode that constitute a modification example of the imaging device of Embodiment 6 and a transistor that constitutes a control portion.

[0068] Figure 37 is a schematic cross-sectional view of a part of the imaging device (two imaging devices arranged side by side) of Embodiment 7.

[0069] Figure 38 is a schematic layout view of a first electrode and a charge accumulation electrode and the like that constitute the imaging device of Embodiment 7 and a transistor that constitutes a control portion.

[0070] Figure 39 is a schematic layout view of a first electrode and a charge accumulation electrode and the like that constitute the imaging device of Embodiment 7.

[0071] Figure 40is a schematic layout diagram of a modification example of the first electrode and the charge accumulation electrode and the like that constitute the imaging device of Embodiment 7.

[0072] Figure 41 is a schematic layout diagram of a modification example of the first electrode and the charge accumulation electrode and the like that constitute the imaging device of Embodiment 7.

[0073] Figure 42A and Figure 42B is a schematic layout diagram of a modification example of the first electrode and the charge accumulation electrode and the like that constitute the imaging device of Embodiment 7.

[0074] Figure 43 is a schematic cross-sectional view of a part of the imaging device (2 imaging devices arranged side by side) of Embodiment 8.

[0075] Figure 44 is a schematic plan view of a part of the imaging device (2x2 imaging devices arranged side by side) of Embodiment 8.

[0076] Figure 45 is a schematic plan view of a part of a modification example of the imaging device (2x2 imaging devices arranged side by side) of Embodiment 8.

[0077] Figure 46A and Figure 46B is a schematic cross-sectional view of a part of a modification example of the imaging device (2 imaging devices arranged side by side) of Embodiment 8.

[0078] Figure 47A and Figure 47B is a schematic cross-sectional view of a part of a modification example of the imaging device (2 imaging devices arranged side by side) of Embodiment 8.

[0079] Figure 48A and Figure 48B is a schematic plan view of a part of a modification example of the imaging device of Embodiment 8.

[0080] Figure 49A and Figure 49B is a schematic plan view of a part of a modification example of the imaging device of Embodiment 8.

[0081] Figure 50 is a schematic plan view of the first electrode and the charge accumulation electrode section in the solid-state imaging device of Embodiment 9.

[0082] Figure 51 is a schematic plan view of the first electrode and the charge accumulation electrode section in a first modification example of the solid-state imaging device of Embodiment 9.

[0083] Figure 52is a schematic plan view of a first electrode and a charge accumulation electrode section in a second modification example of the solid-state imaging device of Embodiment 9.

[0084] Figure 53 is a schematic plan view of a first electrode and a charge accumulation electrode section in a third modification example of the solid-state imaging device of Embodiment 9.

[0085] Figure 54 is a schematic plan view of a first electrode and a charge accumulation electrode section in a fourth modification example of the solid-state imaging device of Embodiment 9.

[0086] Figure 55 is a schematic plan view of a first electrode and a charge accumulation electrode section in a fifth modification example of the solid-state imaging device of Embodiment 9.

[0087] Figure 56 is a schematic plan view of a first electrode and a charge accumulation electrode section in a sixth modification example of the solid-state imaging device of Embodiment 9.

[0088] Figure 57 is a schematic plan view of a first electrode and a charge accumulation electrode section in a seventh modification example of the solid-state imaging device of Embodiment 9.

[0089] Figure 58A 、 Figure 58B and Figure 58C are graphs each showing a read drive example in the imaging element block of Embodiment 9.

[0090] Figure 59 is a schematic plan view of a first electrode and a charge accumulation electrode section in the solid-state imaging device of Embodiment 10.

[0091] Figure 60 is a schematic plan view of a first electrode and a charge accumulation electrode section in one modification example of the solid-state imaging device of Embodiment 10.

[0092] Figure 61 is a schematic plan view of a first electrode and a charge accumulation electrode section in one modification example of the solid-state imaging device of Embodiment 10.

[0093] Figure 62 is a schematic plan view of a first electrode and a charge accumulation electrode section in one modification example of the solid-state imaging device of Embodiment 10.

[0094] Figure 63 is a schematic partial cross-sectional view of the imaging element, yet another modification example of the layered imaging element, in Embodiment 1.

[0095] Figure 64is a schematic partial cross-sectional view of still another modification example of the solid-state imaging device of Embodiment 1.

[0096] Figure 65 is a schematic partial cross-sectional view of yet another modification example of the solid-state imaging device of Embodiment 1.

[0097] Figure 66 is a schematic partial cross-sectional view of another modification example of the solid-state imaging device of Embodiment 1.

[0098] Figure 67 is a schematic partial cross-sectional view of yet another modification example of the solid-state imaging device of Embodiment 4.

[0099] Figure 68 is a conceptual view of the solid-state imaging device of Embodiment 1.

[0100] Figure 69 is a conceptual view of an example in which the solid-state imaging device including the imaging element or the stacked-type imaging element of any one of the first to third aspects of the present application is applied to an electronic device (camera).

[0101] Figure 70 is a conceptual view of a conventional stacked-type imaging element (stacked-type solid-state imaging device).

[0102] Figure 71A and Figure 71B are graphs showing the results of calculation of the relationship between the input power used when forming the inorganic oxide semiconductor material layer based on the sputtering method and the average film density, and the relationship between the average film density and the average oxygen vacancy generation energy, respectively.

[0103] Figure 72A , Figure 72B , Figure 72C and Figure 72D are graphs showing the results of evaluation of the characteristics of the TFTs in which the channel formation regions were formed of the inorganic oxide semiconductor material layer in Embodiment 1A, Comparative Example 1A, Comparative Example 1B, and Comparative Example 1C.

[0104] Figure 73 is a graph showing the results of evaluation of the characteristics of the TFTs in which the channel formation regions were formed of the inorganic oxide semiconductor material layer in Embodiment 1B and Comparative Example 1D.

[0105] Figure 74 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0106] Figure 75 is an explanatory view showing an example of the mounting positions of the vehicle exterior information detecting unit and the imaging section.

[0107] Figure 76 Fig. 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0108] Figure 77 Fig. 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU (camera control unit). DETAILED DESCRIPTION

[0109] Hereinafter, the present application will be described based on embodiments with reference to the accompanying drawings. However, the present application is not limited to these embodiments, and each numerical value and material in each embodiment is illustrative. Note that the description will be made in the following order.

[0110] 1. General description of the imaging element of the first to third aspects of the present application, the stacked imaging element of the present application, and the solid-state imaging apparatus of the first to second aspects of the present application

[0111] 2. Embodiment 1 (imaging element of the first to third aspects of the present application, stacked imaging element of the present application, and solid-state imaging apparatus of the second aspect of the present application)

[0112] 3. Embodiment 2 (modification example of Embodiment 1)

[0113] 4. Embodiment 3 (modification example of Embodiments 1 to 2, and solid-state imaging apparatus of the first aspect of the present application)

[0114] 5. Embodiment 4 (modification example of Embodiments 1 to 3, imaging element having a transfer control electrode)

[0115] 6. Embodiment 5 (modification example of Embodiments 1 to 4, imaging element having a charge discharge electrode)

[0116] 7. Embodiment 6 (modification example of Embodiments 1 to 5, imaging element having a plurality of charge accumulation electrode sections)

[0117] 8. Embodiment 7 (modification example of Embodiments 1 to 6, imaging element having a charge movement control electrode)

[0118] 9. Embodiment 8 (modification example of Embodiment 7)

[0119] 10. Embodiment 9 (solid-state imaging apparatus of the first to second configurations)

[0120] 11. Embodiment 10 (modification example of Embodiment 9)

[0121] 12. Others

[0122] <General Description of the Imaging Element of the First Aspect to the Third Aspect of the Present Invention, the Laminated Imaging Element of the Present Invention, the Solid-state Imaging Apparatus of the First Aspect to the Second Aspect of the Present Invention>

[0123] Hereinafter, the imaging element of the first aspect of the present invention, the imaging element of the first aspect of the present invention constituting the laminated imaging element of the present invention, the imaging element of the first aspect of the present invention constituting the solid-state imaging apparatus of the first aspect to the second aspect of the present invention, and the imaging element of the first aspect of the present invention obtained by the imaging element manufacturing method are sometimes collectively referred to as "the imaging element of the first aspect of the present invention or the like". Furthermore, hereinafter, the imaging element of the second aspect of the present invention, the imaging element of the second aspect of the present invention constituting the laminated imaging element of the present invention, the imaging element of the second aspect of the present invention constituting the solid-state imaging apparatus of the first aspect to the second aspect of the present invention, and the imaging element of the second aspect of the present invention obtained by the imaging element manufacturing method are sometimes collectively referred to as "the imaging element of the second aspect of the present invention or the like". Moreover, hereinafter, the imaging element of the third aspect of the present invention, the imaging element of the third aspect of the present invention constituting the laminated imaging element of the present invention, the imaging element of the third aspect of the present invention constituting the solid-state imaging apparatus of the first aspect to the second aspect of the present invention, and the imaging element of the third aspect of the present invention obtained by the imaging element manufacturing method are sometimes collectively referred to as "the imaging element of the third aspect of the present invention or the like". Furthermore, hereinafter, the imaging element of the first aspect of the present invention or the like, the imaging element of the second aspect of the present invention, and the imaging element of the third aspect of the present invention or the like are sometimes collectively referred to as "the imaging element of the present invention or the like".

[0124] In the imaging element of the first aspect of the present invention or the like and the imaging element of the third aspect of the present invention or the like, a configuration in which the component of the first layer is the same as the component of the second layer can be provided.

[0125] In the imaging element of the first aspect of the present invention or the like and the imaging element of the second aspect of the present invention or the like including the above-described preferable configuration, when the average oxygen vacancy generation energy of the first layer is set to E OD-1 , and the average oxygen vacancy generation energy of the second layer is set to E OD-2 , a configuration in which E OD-1 ≥ 2.8 eV and E OD1 – E OD-2 ≥ 0.2 eV is satisfied, preferably a configuration in which E OD-1 ≥ 2.9 eV and E OD-1 – E OD-2 ≥ 0.3 eV is satisfied can be provided.

[0126] The oxygen vacancy generation energy E OD-2Preferably, it is 3 eV or more, and more desirably, it is 4 eV or more. Furthermore, in the case where the inorganic oxide semiconductor material layer is composed of a plurality of kinds of metal atoms, the "oxygen vacancy formation energy of a metal atom" is the average of the oxygen vacancy formation energies of the plurality of kinds of metal atoms. The oxygen vacancy formation energy is the energy required to form an oxygen vacancy. The higher the value of the oxygen vacancy formation energy, the more difficult it is to form an oxygen vacancy, and the more difficult it is to trap an oxygen atom or an oxygen molecule, or other atoms or molecules. This can be said to have a high stability. The oxygen vacancy formation energy can be calculated, for example, by first principles.

[0127] In the imaging device or the like of the present application including the above-described preferred aspect, if the energy level of vacuum is taken as a reference, and it is defined that the greater the absolute value of the energy (the sign of the value is negative) from the energy level of vacuum, then when the average value of the energy at the maximum energy value of the conduction band of the inorganic oxide semiconductor material layer is set to E1, and the average value of the energy at the LUMO (Lower Unoccupied Molecular Orbital) value of the photoelectric conversion layer is set to E0, preferably, E0≥ E1 is satisfied, more desirably, E0– E1≥ 0.1 (eV) is satisfied, and even more desirably, E0– E1> 0.1 (eV) is satisfied. Furthermore, the "minimum energy" means the absolute value of the energy is the smallest, and the "maximum energy" means the absolute value of the energy is the largest. The same applies hereinafter. The average value E1 of the energy at the maximum energy value of the conduction band of the inorganic oxide semiconductor material layer is set to the average in the inorganic oxide semiconductor material layer. In addition, the average value E0 of the energy at the LUMO value of the photoelectric conversion layer is set to the average in the portion of the photoelectric conversion layer that is located in the vicinity of the inorganic oxide semiconductor material layer. Here, the "portion of the photoelectric conversion layer that is located in the vicinity of the inorganic oxide semiconductor material layer" refers to the portion of the photoelectric conversion layer that is located in a region that is within 10% of the thickness of the photoelectric conversion layer (i.e., a region that extends from 0% to 10% of the thickness of the photoelectric conversion layer) from the interface between the inorganic oxide semiconductor material layer and the photoelectric conversion layer.

[0128] The valence band energy and the HOMO (Highest Occupied Molecular Orbital) value can be calculated, for example, based on ultraviolet photoelectron spectroscopy (UPS (ultraviolet photoelectron spectroscopy) method). In addition, the conduction band energy and the LUMO value can be calculated from {(valence band energy, HOMO value) + E b}. Furthermore, the band gap energy E b The band gap energy E b = h v = h (c / l) = 1239.8 / l [eV] can be calculated from the wavelength l (optical absorption end wavelength, unit: nm) of optical absorption based on the following formula.

[0129] The composition of the inorganic oxide semiconductor material layer can be determined based on, for example, ICP emission spectrochemical analysis (ICP-AES: high-frequency inductively coupled plasma atomic emission spectroscopy) or X-ray photoelectron spectroscopy (XPS). Note that in some cases, hydrogen, other metal, or other impurities such as metal compounds can be mixed in during the formation of the inorganic oxide semiconductor material layer, but if the amount of the impurities is small (e.g., 3 % or less in mole fraction), the mixing of the impurities is not problematic.

[0130] The film density can be determined based on an XRR (X-Ray Reflectivity) method. Here, the XRR method is a method in which X-rays are made to be incident on a sample surface at a very shallow angle, the intensity distribution of X-rays reflected in the direction opposite to the mirror surface with respect to the incident angle is measured, the obtained intensity distribution of X-rays is compared with a simulation result, and a simulation parameter is optimized, whereby the film thickness and the film density of the sample are determined.

[0131] Further, in the imaging device and the like of the present application including the above-described preferred embodiments, the following embodiment can be employed: the photoelectric conversion portion can further include an insulating layer and a charge accumulation electrode which is provided separately from the first electrode and is provided opposite to the inorganic oxide semiconductor material layer with the insulating layer interposed therebetween.

[0132] Further, in the imaging device and the like of the present application including the above-described preferred embodiments, the following embodiment can be employed: the charge generated in the photoelectric conversion layer moves to the first electrode through the inorganic oxide semiconductor material layer. In this case, the following embodiment can be employed: the charge is an electron.

[0133] Further, in the imaging device and the like of the present application including the above-described preferred embodiments, the carrier mobility of the material constituting the inorganic oxide semiconductor material layer is preferably 10 cm 2 / V·s or higher. With this, the charge accumulated in the inorganic oxide semiconductor material layer can be moved to the first electrode at high speed. Further, the carrier concentration of the inorganic oxide semiconductor material layer is preferably 1 x 10 16 / cm 3 With this, an increase in the amount of charge accumulation in the inorganic oxide semiconductor material layer can be achieved.

[0134] Further, in the imaging device or the like of the present application including the above-described various preferred modes, preferably, the surface roughness Ra of the surface of the inorganic oxide semiconductor material layer at the interface between the photoelectric conversion layer and the inorganic oxide semiconductor material layer is 1.5 nm or less, and the value of the root mean square roughness Rq of the surface of the inorganic oxide semiconductor material layer is 2.5 nm or less. The values of the surface roughness Ra and Rq are determined based on the provisions of JIS B0601:2013. Such smoothness of the surface of the inorganic oxide semiconductor material layer at the interface between the photoelectric conversion layer and the inorganic oxide semiconductor material layer makes it possible to suppress the diffuse reflection at the surface of the inorganic oxide semiconductor material layer, and makes it possible to improve the bright current characteristics in photoelectric conversion. Preferably, it can be provided in a mode in which the surface roughness Ra of the surface of the charge accumulation electrode is 1.5 nm or less, and the value of the root mean square roughness Rq of the surface of the charge accumulation electrode is 2.5 nm or less.

[0135] Further, the imaging device or the like of the present application including the above-described various preferred modes can adopt a mode in which the inorganic oxide semiconductor material layer is amorphous (for example, amorphous not having a local crystalline structure). Whether the inorganic oxide semiconductor material layer is amorphous or not can be determined according to X-ray diffraction analysis.

[0136] Further, the imaging device or the like of the present application including the above-described various preferred modes can adopt a mode in which the thickness of the inorganic oxide semiconductor material layer is preferably 1 x 10 -8 m to 1.5 x 10 -7 m, preferably 2 x 10 -8 m to 1.0 x 10 -7 m, more preferably 3 x 10 -8 m to 1.0 x 10 -7 m.

[0137] The inorganic oxide semiconductor material layer can be configured in a form in which the inorganic oxide semiconductor material layer is composed of at least two kinds of elements selected from the group consisting of indium (In), tungsten (W), tin (Sn), and zinc (Zn). Here, the inorganic oxide semiconductor material layer does not contain gallium atoms, and specifically, can be configured in a form in which the inorganic oxide semiconductor material layer contains indium-tungsten oxide (IWO) as a material in which tungsten (W) is added to indium oxide, indium-tungsten-zinc oxide (IWZO) as a material in which tungsten (W) and zinc (Zn) are added to indium oxide, indium-tin-zinc oxide (ITZO) as a material in which tin (Sn) and zinc (Zn) are added to indium oxide, or zinc-tin oxide (ZTO). More specifically, the inorganic oxide semiconductor material layer contains In-W oxide, or contains In-Sn oxide, or contains In-Zn oxide, or contains W-Sn oxide, or contains W-Zn oxide, or contains Sn-Zn oxide, or contains In-W-Sn oxide, or contains In-W-Zn oxide, or contains In-Sn-Zn oxide, or contains In-W-Sn-Zn oxide. With respect to IWO, when the total mass of indium oxide and tungsten oxide is set to 100 mass%, the mass ratio of tungsten oxide is preferably 10 mass% to 30 mass%. Also, with respect to IWZO, when the total mass of indium oxide, tungsten oxide, and Zn oxide is set to 100 mass%, the mass ratio of tungsten oxide is preferably 2 mass% to 15 mass%, and the mass ratio of Zn oxide is preferably 1 mass% to 3 mass%. Further, with respect to ITZO, when the total mass of indium oxide, Zn oxide, and Sn oxide is set to 100 mass%, the mass ratio of tungsten oxide is preferably 3 mass% to 10 mass%, and the mass ratio of tin oxide is preferably 10 mass% to 17 mass%. However, the present application is not limited to these values.

[0138] Alternatively, the inorganic oxide semiconductor material layer can be configured in a form in which the inorganic oxide semiconductor material layer contains indium (In) atoms, gallium (Ga) atoms, tin (Sn) atoms, and zinc (Zn) atoms, and specifically, in a form in which the inorganic oxide semiconductor material layer contains In-Sn-Zn oxide in which the total content of In, Sn, and Zn is 100 atomic% and the atomic ratio of In to Sn and Zn is In:(Sn+Zn) = 1:1 to 1:4. a Ga b Sn c Zn d O e When the inorganic oxide semiconductor material layer is represented by InGaO3(Zn), it can be configured in a form in which 1.8 < (b + c) / a < 2.3 and 2.3 < d / a < 2.6 are satisfied, and further, b > 0 is satisfied.

[0139] Alternatively, the metal element constituting the inorganic oxide semiconductor material can be configured to have a closed-shell d orbital, and specifically, the metal atom can be configured to be a metal atom selected from the group consisting of copper, silver, gold, zinc, gallium, germanium, indium, tin, and thallium. That is, as the metal atom having a closed-shell d orbital, specifically, the metal atom can be configured to be selected from the group consisting of copper (Cu), silver (Ag), gold (Au), zinc (Zn), gallium (Ga), germanium (Ge), indium (In), tin (Sn), thallium (Tl), cadmium (Cd), mercury (Hg), and lead (Pb). Preferably, the metal atom can be configured to be selected from the group consisting of copper (Cu), silver (Ag), gold (Au), zinc (Zn), gallium (Ga), germanium (Ge), indium (In), tin (Sn), and thallium (Tl). More preferably, the metal atom can be configured to be free of indium (In). Still more preferably, the metal atom can be selected from the group consisting of copper (Cu), silver (Ag), zinc (Zn), gallium (Ga), germanium (Ge), and tin (Sn). Here, more preferably, as the combination of the metal atom, (In, Ga), (In, Zn), (In, Sn), (Ga, Sn), (Ga, Zn), (Zn, Sn), (Cu, Zn), (Cu, Ga), (Cu, Sn), (Ag, Zn), (Ag, Ga), or (Ag, Sn) can be exemplified.

[0140] Alternatively, the inorganic oxide semiconductor material layer can be configured to contain indium (In) atoms, gallium (Ga) atoms, and tin (Sn) atoms. Here, in the case where the inorganic oxide semiconductor material layer contains In a Ga b Sn c O d When the inorganic oxide semiconductor material layer is represented by InaGbgScOd, preferably, a > b and a > c are satisfied, more preferably, a > b > c or a > c > b is further satisfied, and still more preferably, a > b > c is satisfied. Also, in the imaging device and the like of the present application including these preferable modes, preferably, a > b and a > c are satisfied, more preferably, a > b > c is further satisfied, and still more preferably, a > b > c is satisfied.

[0141] a + b + c + d = 1.00

[0142] 0.4 < a / (a + b + c) < 0.5

[0143] 0.3 < b / (a + b + c) < 0.4, and

[0144] 0.2 < c / (a + b + c) < 0.3.

[0145] Alternatively, preferably, the following is satisfied:

[0146] a + b + c + d = 1.00

[0147] 0.30 < a / (a + b + c) < 0.55

[0148] 0.20 < b / (a+b+c) < 0.35 and

[0149] 0.25 < c / (a+b+c) < 0.45.

[0150] Alternatively, it can be configured as follows: the inorganic oxide semiconductor material layer contains gallium (Ga) atoms and tin (Sn) atoms. Here, when the inorganic oxide semiconductor material layer is represented by Ga a Sn b O c when represented by Ga

[0151] a+b+c = 1.00 and

[0152] 0.20 < b / (a+b) < 0.35.

[0153] Alternatively, it can be configured as follows: the inorganic oxide semiconductor material layer contains gallium (Ga) atoms and indium (In) atoms. Here, when the inorganic oxide semiconductor material layer is represented by Ga d In e O f when represented by Ga

[0154] d+e+f = 1.00 and

[0155] 0.20 < e / (d+e) < 0.40.

[0156] Alternatively, it can be configured as follows: the inorganic oxide semiconductor material layer contains zinc (Zn) atoms and tin (Sn) atoms, and here, when the inorganic oxide semiconductor material layer is represented by Zn a Sn b O c when represented by Zn a Sn b M d O c when represented by Zn

[0157] a+b+c+d = 1.00 and

[0158] 0.0005 < d < 0.065.

[0159] Alternatively, the inorganic oxide semiconductor material layer preferably further contains tantalum atoms or hafnium atoms. When the inorganic oxide semiconductor material layer is composed of Zn a Sn b M d O c (where M means tantalum atoms or hafnium atoms) is represented, it is preferable that:

[0160] a + b + c + d = 1.00 and

[0161] 0.0005 < d < 0.065.

[0162] Alternatively, a configuration in which the inorganic oxide semiconductor material layer contains In a Ga b Sn c O d , 0.30 < b / (a+b+c) < 0.50 and b > c can be provided. Alternatively, a configuration in which 0.40 < b / (a+b+c) < 0.50 can be provided. Alternatively, a configuration in which b > 1.2c can be provided.

[0163] Alternatively, a configuration in which the inorganic oxide semiconductor material layer contains indium (In) atoms, tin (Sn) atoms, titanium (Ti) atoms, and zinc (Zn) atoms can be provided. In the case of In a Sn b Ti c Zn d O e represents components of the inorganic oxide semiconductor material layer, and when a + b + c + d = 1.00 is set, it is preferable that b > d > c > 0.09. Alternatively, when a + b + c + d = 1.00 is set, it is preferable that a < (b + c + d) < 0.6.

[0164] Alternatively, in the case of In a Sn b M f Zn d O e represents components of the inorganic oxide semiconductor material layer, and when a + b + f + d = 1.00 is set, it is preferable that b > d > f > 0.09. Here, M is any one of aluminum, hafnium, or zirconium.

[0165] Alternatively, in the case of In a Sn b Ti c Zn d O erepresents a component of the inorganic oxide semiconductor material layer, and preferably satisfies a < (b + c + d) ≤ 0.6 when a + b + c + d = 1.00. Further, preferably, 0.4 ≤ a < (b + d) ≤ 0.5 is satisfied.

[0166] Alternatively, in the case where In a Sn b M f Zn d O e represents a component of the inorganic oxide semiconductor material layer, and preferably satisfies a < (b + f + d) ≤ 0.6 when a + b + f + d = 1.00. Further, preferably, 0.4 ≤ a < (b + d) ≤ 0.5 is satisfied. M is any one of aluminum, hafnium, or zirconium as described above.

[0167] Alternatively, as a material example of the inorganic oxide semiconductor material layer, for example, indium oxide, gallium oxide, zinc oxide, tin oxide, or a material containing at least one of these oxides, or a material to which a dopant is added among these materials, specifically, for example, IGZO (indium-gallium-zinc oxide, or indium and gallium are added to zinc oxide as dopants), ITZO, IWZO, IWO, ZTO, ITO-SiO X GZO (gallium-zinc oxide, or gallium is added to zinc oxide as a dopant), IGO (indium-gallium oxide, or indium is added to gallium oxide as a dopant), ZnSnO3, AlZnO, GaZnO, InZnO. Further, material examples can also include materials containing CuI, InSbO4, ZnMgO, CuInO2, MgIn2O4, CdO, and the like. Alternatively, as a material example constituting the inorganic oxide semiconductor material layer, in the case where the charge to be accumulated is an electron, a material having a larger ionization potential than that of the material constituting the photoelectric conversion layer can be exemplified, and in the case where the charge to be accumulated is a hole, a material having a smaller electron affinity than that of the material constituting the photoelectric conversion layer can be exemplified. Alternatively, the impurity concentration of the material constituting the inorganic oxide semiconductor material layer is preferably 1 x 10 18 cm -3 The following.

[0168] Alternatively, the inorganic oxide semiconductor material layer includes a composite oxide composed of titanium oxide and zinc oxide. However, the present application is not limited to this, and titanium oxide can be replaced with aluminum oxide, hafnium oxide, or zirconium oxide. That is, the inorganic oxide semiconductor material layer can be configured to include indium (In) atoms, tin (Sn) atoms, aluminum (Al), and zinc (Zn) atoms, or can be configured to include indium (In) atoms, tin (Sn) atoms, hafnium (Hf), and zinc (Zn) atoms, or can be configured to include indium (In) atoms, tin (Sn) atoms, zirconium (Zr) atoms, and zinc (Zn) atoms. Alternatively, the inorganic oxide semiconductor material layer can be configured to include indium (In) atoms, tin (Sn) atoms, metal atoms, and zinc (Zn) atoms, and the metal atoms can be at least one atom selected from the group consisting of titanium, aluminum, hafnium, and zirconium.

[0169] The first electrode, the second electrode, the charge accumulation electrode, and the photoelectric conversion layer will be described in detail below.

[0170] In Figure 70 In the conventional imaging device shown in FIG. 10, the charges generated by photoelectric conversion in the second photoelectric conversion section 341A and the third photoelectric conversion section 343A are temporarily accumulated in the second photoelectric conversion section 341A and the third photoelectric conversion section 343A, and then the charges are transferred to the second floating diffusion layer FD2 and the third floating diffusion layer FD3, respectively. Thus, the second photoelectric conversion section 341A and the third photoelectric conversion section 343A can be completely depleted. However, the charges generated by photoelectric conversion in the first photoelectric conversion section 310A are directly accumulated in the first floating diffusion layer FD1. Thus, it is difficult to completely deplete the first photoelectric conversion section 310A. As a result, kTC noise increases, random noise deteriorates, and this leads to a decrease in the quality of the captured image.

[0171] As described above, the imaging device of the present application and the like includes a charge accumulation electrode that is provided separately from the first electrode and faces the inorganic oxide semiconductor material layer with the insulating layer interposed therebetween. Thus, when light is irradiated to the photoelectric conversion section and the light is photoelectrically converted in the photoelectric conversion section, charges can be accumulated in the inorganic oxide semiconductor material layer (or in some cases, in the inorganic oxide semiconductor material layer and the photoelectric conversion layer). Thus, at the start of exposure, the charge accumulation section can be completely depleted, and the charges can be eliminated. As a result, it is possible to suppress the occurrence of kTC noise increase, random noise deterioration, and the resulting decrease in the quality of the captured image. Note that in the following description, the inorganic oxide semiconductor material layer, or the inorganic oxide semiconductor material layer and the photoelectric conversion layer can be collectively referred to as "the inorganic oxide semiconductor material layer or the like" in some cases.

[0172] The inorganic oxide semiconductor material layer can have a single-layer structure or a multi-layer structure. Furthermore, the material that constitutes the inorganic oxide semiconductor material layer positioned above the charge accumulation electrode can be different from the material that constitutes the inorganic oxide semiconductor material layer positioned above the first electrode.

[0173] The inorganic oxide semiconductor material layer can be formed on the basis of a physical vapor deposition (PVD) method, particularly a sputtering method. More specifically, for example, the following sputtering method can be given: one method is to use a parallel plate sputtering device, a DC (direct current) magnetron sputtering device, or an RF (radio frequency) sputtering device as a sputtering device, use argon (Ar) gas as a process gas, and use a desired sintered body (e.g., an In a Sn b Ti c Zn d Oe sintered body or In a Sn b M f Zn d O e sintered body) as a target.

[0174] Note that the energy level of the inorganic oxide semiconductor material layer can be controlled by controlling the amount of oxygen (oxygen partial pressure) to be introduced when the inorganic oxide semiconductor material layer is formed on the basis of a sputtering method. Specifically, when the inorganic oxide semiconductor material layer is formed on the basis of a sputtering method, the oxygen partial pressure = (O2 gas pressure) / (total pressure of Ar gas and O2 gas) is preferably set to 0.005 to 0.10. Furthermore, the imaging device and the like of the present application can adopt a form in which the oxygen content in the inorganic oxide semiconductor material layer is less than that of the stoichiometric composition. Here, the energy level of the inorganic oxide semiconductor material layer can be controlled on the basis of the oxygen content. The deeper the energy level is, the lower the oxygen content is than that of the stoichiometric composition, i.e., the more oxygen vacancies there are.

[0175] Examples of the imaging device and the like of the present application include a CCD element, a CMOS image sensor, a contact image sensor (CIS), and a charge modulation device (CMD) type signal amplification type image sensor. For example, the solid-state imaging apparatus of the first aspect and the second aspect of the present application and the solid-state imaging apparatus of the first configuration and the second configuration described later can be used to constitute, for example, a digital camera, a video recorder, a camcorder, a monitoring camera, a car-mounted camera, a camera for a smartphone, a camera for a game user interface, and a camera for biological authentication.

[0176] [Example 1]

[0177] Example 1 relates to the imaging element of the first aspect to the third aspect of the present application, the stacked imaging element of the present application, and the solid-state imaging apparatus of the second aspect of the present application. Figure 1 A schematic partial cross-sectional view of the imaging element and the stacked imaging element (hereinafter, simply referred to as "imaging element") of Example 1 is shown. Figure 2 and Figure 3 A circuit diagram of the imaging element of Example 1 is shown.

[0178] Figure 4 A schematic layout view of the first electrode and the charge accumulation electrode that constitute the photoelectric conversion section of the imaging element of Example 1 and the transistor that constitutes the control section is shown. Figure 5 The potential state of each part during the operation of the imaging element of Example 1 is schematically shown. Figure 6A A circuit diagram for explaining each part of the imaging element of Example 1 is shown. Further, Figure 7 A schematic layout view of the first electrode and the charge accumulation electrode that constitute the photoelectric conversion section of the imaging element of Example 1 is shown. Figure 8 A schematic perspective view of the first electrode, the charge accumulation electrode, the second electrode, and the contact hole section is shown. Further, Figure 68 A conceptual view of the solid-state imaging apparatus of Example 1 is shown.

[0179] Note that, in Figure 2 , Figure 3 , Figure 6A , Figure 6B , Figure 6C , Figure 9 , Figure 16 , Figure 17 , Figure 18 , Figure 25 , Figure 28 , Figure 29 , Figure 30 , Figure 63 , Figure 64 , Figure 65 , Figure 66 and Figure 67 , the illustration of the first layer 23C and the second layer 23D that constitute the inorganic oxide semiconductor material layer 23B is omitted, and the first layer 23C and the second layer 23D are collectively represented as the inorganic oxide semiconductor material layer 23B. Further, in Figure 37 , Figure 43 , Figure 46A , Figure 46B , Figure 47A and Figure 47BIn the present embodiment, the illustration of the photoelectric conversion layer 23A, and the first layer 23C and the second layer 23D that constitute the inorganic oxide semiconductor material layer 23B is omitted, and the photoelectric conversion layer 23A and the inorganic oxide semiconductor material layer 23B (the first layer 23C and the second layer 23D) are collectively referred to as a photoelectric conversion layer stack 23.

[0180] The imaging device of Embodiment 1 includes a photoelectric conversion section formed by laminating the first electrode 21, the photoelectric conversion layer 23A formed of an organic material, and the second electrode 22. Between the first electrode 21 and the photoelectric conversion layer 23A, the inorganic oxide semiconductor material layer 23B is formed. The semiconductor material layer 23B includes the first layer 23C and the second layer 23D from the first electrode side. Here, the first layer 23C is in contact with the first electrode 21, and the second layer 23D is in contact with the photoelectric conversion layer 23A.

[0181] Furthermore, the imaging device of Embodiment 1, when described based on the imaging device of the first aspect of the present application, satisfies ρ1≥ 5.9 g / cm3and ρ1– ρ2≥ 0.1 g / cm3when the average film density of the first layer 23C within 3 nm, preferably 5 nm, more preferably 10 nm from the interface between the first electrode 21 and the inorganic oxide semiconductor material layer 23B is set as ρ1, and the average film density of the second layer 23D is set as ρ2. 3 and ρ1– ρ2≥ 0.1 g / cm3 3 . Preferably, ρ1≥ 6.1 g / cm3and ρ1– ρ2≥ 0.2 g / cm3 3 are satisfied. 3

[0182] Further, when described based on the imaging device of the second aspect of the present application, the composition of the first layer is the same as that of the second layer, and ρ1– ρ2≥ 0.1 g / cm3 3 is satisfied. Preferably, ρ1– ρ2≥ 0.2 g / cm3 3 is satisfied.

[0183] In addition, when described based on the imaging device of the third aspect of the present application, E OD-1 is set as E OD-2 for the first layer 23C, and E OD-1 ≥ 2.8 eV and E OD-1 – E OD-2 ≥ 0.2 eV are satisfied. Preferably, E OD-1 ≥ 2.9 eV and E OD-1 – E OD-2 ≥ 0.3 eV are satisfied. Alternatively, the composition of the first layer is the same as that of the second layer, and E OD-1 – E OD-2 ​≥ 0.2 eV. Preferably, E0- E1≥ 0.1 (eV) is satisfied. OD-1 - E0- E1≥ 0.1 (eV) is satisfied. OD-2 ≥ 0.3 eV. In the imaging element of Embodiment 1, the oxygen vacancy formation energy of the metal atoms constituting the inorganic oxide semiconductor material layer 23B is 2.8 eV or more.

[0184] The stacked type imaging element of Embodiment 1 includes at least one imaging element as in Embodiment 1. Further, the solid-state imaging device of Embodiment 1 includes a plurality of stacked type imaging elements as in Embodiment 1. In addition, for example, a digital camera, a video recorder, a camcorder, a monitoring camera, a car-mounted camera, a camera for a smartphone, a camera for a game user interface, and a camera for biological authentication, and the like can be configured with the solid-state imaging device of Embodiment 1.

[0185] Here, as described above, the composition of the first layer 23C is the same as that of the second layer 23D. Specifically, the composition of the first layer 23C and the second layer 23D is IGZO.

[0186] Further, when the energy average at the maximum energy value of the conduction band of the inorganic oxide semiconductor material layer 23B is set as E1, and the energy average at the LUMO value of the photoelectric conversion layer 23A is set as E0, then E0≥ E1 is satisfied, and it is more desirable that E0- E1≥ 0.1 (eV), and even more desirable that E0- E1> 0.1 (eV).

[0187] The charge generated in the photoelectric conversion layer 23A moves to the first electrode 21 via the inorganic oxide semiconductor material layer 23B. At this time, the charge is an electron. Further, the thickness of the inorganic oxide semiconductor material layer 23B is 1 x 10 -8 m to 1.5 x 10 -7 m. Further, the carrier mobility of the material constituting the inorganic oxide semiconductor material layer 23B is 10 cm 2 / V·s or more, and the carrier concentration of the inorganic oxide semiconductor material layer 23B is 1 x 10 16 / cm 3 Hereinafter, the inorganic oxide semiconductor material layer 23B is amorphous. Specific examples of these values are shown in Table 1 below. Further, the photoelectric conversion layer 23A contains quinacridone having a thickness of 0.1 μm. Also, the values of the thickness, the average film density ρ1 and ρ2, the average oxygen vacancy formation energy E OD-1 , and E OD-2 of the first layer 23C and the second layer 23D in the inorganic oxide semiconductor material layer 23B are shown in Table 1. Also, the results obtained by investigating the energy level (E1) and the carrier concentration of the inorganic oxide semiconductor material layer 23B, and the energy level (E0) of the photoelectric conversion layer 23A are shown in Table 1.

[0188] [Table 1]

[0189]

[0190] In Figure 71A and Figure 71B are shown results obtained by finding the relationship between the input power used when forming the inorganic-oxide-semiconductor-material layer 23B by sputtering and the average film density, and the relationship between the average film density and the average oxygen vacancy generation energy. According to Figure 71A It can be seen that the average film density linearly increases as the input power used when forming the inorganic-oxide-semiconductor-material layer 23B increases, and according to Figure 71B It can be seen that the average oxygen vacancy generation energy linearly increases as the average film density increases.

[0191] Figure 72A , Figure 72B , Figure 72C and Figure 72D are shown results obtained by forming a channel formation region of a thin film transistor (TFT) from the inorganic-oxide-semiconductor-material layer, and evaluating the characteristics of the TFT. That is, Figure 72A , Figure 72B , Figure 72C and Figure 72D are shown graphs of results obtained by finding the relationship between V gs and I d in a TFT having a channel formation region composed of IGZO with a thickness of 60 nm. Here, Figure 72A , Figure 72B , Figure 72C and Figure 72D The composition of the inorganic-oxide-semiconductor-material layer in each of 3 was set to 300 W, and the input power when forming an IGZO layer with an average film density of 5.8 g / cm 3 was set to 160 W. In the case of a higher input power, the orientation of the material constituting the inorganic-oxide-semiconductor-material layer becomes uniform, and the inorganic-oxide-semiconductor-material layer becomes dense. On the other hand, it is considered that in the case of a lower input power, the orientation of the material constituting the inorganic-oxide-semiconductor-material layer is difficult to become uniform, and the inorganic-oxide-semiconductor-material layer becomes coarse.

[0192] Further, as an evaluation sample, a back gate type TFT was produced in which an n-Si substrate was used as a gate electrode, an insulating film made of SiO2 and having a thickness of 150 nm was formed on the substrate as a gate insulating film, an inorganic oxide semiconductor material layer having a stacked structure including a first layer and a second layer from the insulating film side was formed on the insulating film, and a source electrode and a drain electrode were formed on the inorganic oxide semiconductor material layer (specifically, on the second layer). After the evaluation sample was produced, the inorganic oxide semiconductor material layer was subjected to an annealing treatment at 350°C for 2 hours.

[0193] [Table 2]

[0194]

[0195] The results of calculating the carrier mobility (unit: / V·s), V on ( unit: volt), and subthreshold value (unit: volt / amperes) of the carrier mobility of Example 1A, Comparative Example 1A, Comparative Example 1B, and Comparative Example 1C are shown in Table 3 below. Further, the subthreshold value (SS value) is calculated by [d(V gs ) / {d (log 10 (I d ))}], and it is considered that the smaller this value is, the more excellent the switching characteristics are.

[0196] [Table 3]

[0197] Carrier mobility V on ]]> SS value Example 1A 12 -2 0.15 Comparative Example 1A 10 0 0.15 to 0.20 Comparative Example 1B 11 -4 0.35 Comparative Example 1C 12 -3.5 0.30

[0198] According to the results of Table 3, all of the characteristics including the carrier mobility, V on , and SS value are most excellent in Example 1A. The carrier mobility of Comparative Example 1A is lower than that of Example 1A. The carrier mobility, V on , and SS value of Comparative Example 1B are all lower than those of Example 1A. The V on and SS value of Comparative Example 1C are lower than those of Example 1A. Note that, in Example 1A, when the thickness of the first layer was set to 5 nm and 3 nm, respectively, 0.12 and 0.08 were obtained as the SS value, respectively.

[0199] According to the above results, by forming the first layer having a higher average film density and the second layer having a lower average film density, a camera element having excellent balance of characteristics of the carrier mobility, V on , and SS value can be obtained. According to Comparative Examples 1B and 1C, if the layer having a higher average film density is too thick, the characteristics deteriorate. It is considered that this is a result of damage to the lower layer due to too high input power when the inorganic oxide semiconductor material layer is formed by the sputtering method.

[0200] Thus, it is determined that the first layer 23C and the second layer 23D of the inorganic-oxide semiconductor material layer 23B are optimal by the method for manufacturing an imaging device including the step of forming the second layer based on the sputtering method with less input power than that used when forming the first layer after forming the first layer based on the sputtering method. That is, for example, using one sputtering device, using the same target, forming the first layer and the second layer based on the sputtering method, it is only necessary to set the input power used when forming the second layer to be less than the input power used when forming the first layer. As for conditions other than the input power in the sputtering method, it is only necessary to seek optimization when forming the first layer and when forming the second layer.

[0201] The photoelectric conversion section also has an insulating layer 82 and a charge accumulation electrode 24 that is arranged separately from the first electrode 21 and that is arranged opposite the inorganic-oxide semiconductor material layer 23B with the insulating layer 82 interposed therebetween. Specifically, the inorganic-oxide semiconductor material layer 23B includes a region in contact with the first electrode 21, a region in contact with the insulating layer 82 and in which no charge accumulation electrode 24 is present below, and a region in contact with the insulating layer 82 and in which a charge accumulation electrode 24 is present below. Also, light is incident from the second electrode 22. The surface roughness Ra of the surface of the inorganic-oxide semiconductor material layer 23B at the interface of the photoelectric conversion layer 23A and the inorganic-oxide semiconductor material layer 23B is 1.5 nm or less, specifically, can be 0.65 nm, and the value of the root-mean-square roughness Rq of the surface of the inorganic-oxide semiconductor material layer 23B is 2.5 nm or less, specifically, can be 1.3 nm. The surface roughness Ra of the surface of the charge accumulation electrode 24 is 1.5 nm or less, specifically, can be 0.45 nm, and the value of the root-mean-square roughness Rq of the surface of the charge accumulation electrode 24 is 2.5 nm or less, specifically, can be 1.5 nm. Furthermore, according to the results of X-ray diffractometry of the inorganic-oxide semiconductor material layer 23B, it is determined that the inorganic-oxide semiconductor material layer 23B is amorphous (for example, amorphous that does not have a local crystalline structure).

[0202] As Embodiment 1B, an evaluation sample (TFT) was produced in which, instead of IGZO, the inorganic-oxide semiconductor material layer 23B was set to In a Sn b Ti c Zn d O e(where a = 0.40, b = 0.30, c = 0.10, d = 0.20, and e = 1.00). Note that the evaluation sample (TFT) had the same configuration as that of Example 1A. The thicknesses of the first layer 23C and the second layer 23D in the inorganic-oxide semiconductor material layer 23B, the average film densities p1 and p2, and the average oxygen vacancy formation energy E OD-1 and E OD-2 are shown in Table 4. Further, the investigation results of the energy level (E1) and the carrier concentration of the inorganic-oxide semiconductor material layer 23B, and the energy level (E0) of the photoelectric conversion layer 23A are shown in Table 4. Furthermore, as Comparative Example 1D, an evaluation sample (TFT) was produced in which the inorganic-oxide semiconductor material layer was formed of the same material as that of Example 1B, but here, the average film density of the inorganic-oxide semiconductor material layer was set to 5.8 g / cm 3 .

[0203] [Table 4]

[0204]

[0205] Figure 73 The results obtained by evaluating the TFT characteristics of Example 1B and Comparative Example 1D are shown. Also, in Table 5 below, "A" shows the evaluation results of Example 1B, and "B" shows the evaluation results of Comparative Example 1D. Also, the results of calculating the carrier mobility (unit: / V s) and the subthreshold value (unit: volt / amperes) of Example 1B and Comparative Example 1D are shown, and it is seen that the carrier mobility and the SS value of Example 1B are superior to those of Comparative Example 1D. Figure 73

[0206] [Table 5]

[0207] Carrier mobility SS value Example 1B 12 0.10 Comparative Example 1D 10 0.40

[0208] In the imaging device of Example 1, since the inorganic-oxide semiconductor material layer containing the first layer and the second layer from the first electrode side is formed between the first electrode and the photoelectric conversion layer, and the thickness of the first layer and the thickness of the second layer, the relationship between the average film density p1 of the first layer and the average film density p2 of the second layer, the relationship between the average oxygen vacancy formation energy E OD-1 of the first layer and the average oxygen vacancy formation energy E OD-2 of the second layer are specified, the carrier mobility, the V on ​and the SS value. Therefore, it is possible to provide an imaging element, a stacked imaging element, and a solid-state imaging device in which the transport characteristics of the charge accumulated in the photoelectric conversion layer are excellent, despite a simple structure or configuration. Furthermore, the energy level E1 of the conduction band of the inorganic oxide semiconductor material layer is formed deeper than the LUMO value E0 of the photoelectric conversion layer, and as a result, it is possible to reduce the energy barrier between the inorganic oxide semiconductor material layer and the photoelectric conversion layer adjacent thereto, to reliably achieve transport of the charge from the photoelectric conversion layer to the inorganic oxide semiconductor material layer, and to suppress escape of the hole. In addition, since the photoelectric conversion portion is provided in a double-layer configuration of the inorganic oxide semiconductor material layer and the photoelectric conversion layer, it is possible to prevent recombination of the charge at the time of accumulation, and to further improve the charge transport efficiency of the charge accumulated in the photoelectric conversion layer to the first electrode. Furthermore, it is possible to temporarily hold the charge generated in the photoelectric conversion layer to control the timing of transport and the like, and to suppress formation of dark current.

[0209] Hereinafter, the imaging element of the present application, the stacked imaging element of the present application, and the solid-state imaging device of the second aspect of the present application will be generally described, and then the imaging element and the solid-state imaging device of Embodiment 1 will be described in detail. In the following description, the symbols indicating the applied potential to the various electrodes are shown in Table 6 below.

[0210] [Table 6]

[0211] During charge accumulation During charge transport First electrode V 11 ]]> V 12 ]]> Second electrode V 21 ]]> V 22 ]]> Charge accumulation electrode V 31 ]]> V 32 ]]> Charge movement control electrode V 41 ]]> V 42 ]]> Transport control electrode V 51 ]]> V 52 ]]> Charge discharge electrode V 61 ]]> V 62 ]]>

[0212] Hereinafter, for the sake of convenience, the imaging element and the like of the present application including the above-described preferred modes, and the imaging element and the like including the charge accumulation electrode can be referred to as "the imaging element and the like of the present application including the charge accumulation electrode".

[0213] In the imaging element and the like of the present application including the charge accumulation electrode, the light transmittance of the inorganic oxide semiconductor material layer to light having a wavelength of 400 nm to 660 nm is preferably 65% or more. In addition, the light transmittance of the charge accumulation electrode to light having a wavelength of 400 nm to 660 nm is also preferably 65% or more. The sheet resistance value of the charge accumulation electrode is preferably 3 x 10 Ω / D to 1 x 10 3 Ω / D.

[0214] The imaging element and the like of the present application including the charge accumulation electrode can be provided in a mode in which the imaging element and the like further include a semiconductor substrate, and the photoelectric conversion portion is provided above the semiconductor substrate. Note that the first electrode, the charge accumulation electrode, the second electrode, and the various electrodes and the like are connected to the drive circuit described later.

[0215] The second electrode on the light-incident side can be shared by a plurality of imaging elements. That is, the second electrode can be configured as a so-called solid electrode, except for the imaging element of the present application provided with the upper charge movement control electrode and the like described later. The photoelectric conversion layer can be shared by a plurality of imaging elements. That is, one photoelectric conversion layer can be formed in a plurality of imaging elements, or alternatively, a photoelectric conversion layer can be provided for each imaging element. The inorganic oxide semiconductor material layer is preferably provided for each imaging element, but can sometimes be shared by a plurality of imaging elements. In other words, for example, as described later, a single inorganic oxide semiconductor material layer shared by a plurality of imaging elements can be formed by providing a charge movement control electrode between the imaging elements. In the case where a single inorganic oxide semiconductor material layer shared by a plurality of imaging elements is formed, it is preferable that the end portion of the inorganic oxide semiconductor material layer be covered with at least the photoelectric conversion layer from the viewpoint of protecting the end portion of the inorganic oxide semiconductor material layer.

[0216] Further, the imaging element of the present application and the like including the above-described various preferred modes can adopt a mode in which the first electrode extends within the opening portion formed in the insulating layer to be connected to the inorganic oxide semiconductor material layer. Alternatively, a mode in which the inorganic oxide semiconductor material layer extends within the opening portion formed in the insulating layer to be connected to the first electrode can be adopted.

[0217] In this case, a mode in which:

[0218] the edge of the top surface of the first electrode is covered with the insulating layer,

[0219] the first electrode is exposed at the bottom surface of the opening portion, and

[0220] when a surface of the insulating layer that is in contact with the top surface of the first electrode is referred to as a first surface, and a surface of the insulating layer that is in contact with a portion of the inorganic oxide semiconductor material layer facing the charge accumulation electrode is referred to as a second surface, the side surface of the opening portion has a slope that widens from the first surface toward the second surface. Further, a mode in which the side surface of the opening portion having a slope that widens from the first surface toward the second surface is located on the charge accumulation electrode side can be adopted.

[0221] Further, the imaging element of the present application and the like including the above-described various preferred modes can adopt a mode in which:

[0222] the imaging element and the like further includes a control portion provided on the semiconductor substrate and having a drive circuit,

[0223] the first electrode and the charge accumulation electrode are connected to the drive circuit,

[0224] During the charge accumulation period, the potential V 11 is applied to the first electrode, and the potential V 31 is applied to the charge accumulation electrode, and charges are accumulated in the inorganic oxide semiconductor material layer or the like, and

[0225] During the charge transfer period, the potential V 12 is applied to the first electrode, and the potential V 32 is applied to the charge accumulation electrode, and the charges accumulated in the inorganic oxide semiconductor material layer or the like are read out to the control section via the first electrode. Note that the potential of the first electrode is higher than that of the second electrode, and the following is satisfied:

[0226] V 31 ≥ V 11 and V 32 < V 12 .

[0227] Further, the imaging device or the like of the present application including the above-described various preferred modes can also adopt a mode in which a charge movement control electrode is formed in a region that opposes a region of the photoelectric conversion layer between adjacent imaging devices via an insulating layer. For convenience, such a mode is sometimes referred to as "imaging device or the like of the present application having a lower charge movement control electrode". Alternatively, the imaging device or the like of the present application including the above-described various preferred modes can also adopt a mode in which a charge movement control electrode is formed instead of a second electrode on a region of the photoelectric conversion layer between adjacent imaging devices. For convenience, such a mode is sometimes referred to as "imaging device or the like of the present application having an upper charge movement control electrode".

[0228] In the following description, for convenience, a "region of the photoelectric conversion layer between adjacent imaging devices" is referred to as "region-A of the photoelectric conversion layer", and for convenience, a "region of the insulating layer between adjacent imaging devices" is referred to as "region-A of the insulating layer". The region-A of the photoelectric conversion layer corresponds to the region-A of the insulating layer. Further, for convenience, a "region between adjacent imaging devices" is referred to as "region-a".

[0229] In the imaging element of the present invention, which has a lower charge movement control electrode (lower charge movement control electrode, a charge movement control electrode located on the side opposite to the light incident side with reference to the photoelectric conversion layer), the lower charge movement control electrode is formed in a region opposite to the region A of the photoelectric conversion layer, separated by an insulating layer. In other words, the lower charge movement control electrode is formed below a portion of the insulating layer located in a region (region A) between the charge accumulation electrodes constituting adjacent imaging elements. The lower charge movement control electrode is disposed separately from the charge accumulation electrode. Alternatively, in other words, the lower charge movement control electrode surrounds the charge accumulation electrode and is disposed separately from it, and is arranged opposite to the region A of the photoelectric conversion layer, separated by an insulating layer.

[0230] Furthermore, the imaging element having a lower charge movement control electrode of the present invention can be configured in the following form:

[0231] The imaging element also includes a control unit, which is disposed on a semiconductor substrate and has a driving circuit.

[0232] The first electrode, the second electrode, the charge accumulation electrode, and the lower charge movement control electrode are connected to the drive circuit.

[0233] During charge accumulation, a potential V is applied from the driving circuit to the first electrode. 11 Apply a potential V to the charge accumulation electrode 31 Apply potential V to the lower charge-moving control electrode 41 And it accumulates charge in inorganic oxide semiconductor material layers, etc.

[0234] During charge transfer, a potential V is applied from the driving circuit to the first electrode. 12 Apply a potential V to the charge accumulation electrode 32 Apply potential V to the lower charge-moving control electrode 42 Furthermore, the charge accumulated in the inorganic oxide semiconductor material layer, etc., is read out to the control unit via the first electrode. Here, V 31 ≥V 11 V 31 >V 41 And V 12 >V 32 >V 42 The lower charge movement control electrode may be formed on the same horizontal plane as the first electrode or the charge accumulation electrode, or it may not be formed on the same horizontal plane.

[0235] In the imaging element of the present invention, which has an upper charge movement control electrode (upper charge movement control electrode, a charge movement control electrode located on the light incident side based on the photoelectric conversion layer), the upper charge movement control electrode is formed on the region of the photoelectric conversion layer located between adjacent imaging elements, instead of forming a second electrode. The upper charge movement control electrode and the second electrode are provided separately. In other words, it can be configured as follows:

[0236] [A] A second electrode is provided for each imaging element, and an upper charge movement control electrode is provided on region A of the photoelectric conversion layer in a manner that surrounds at least a portion of the second electrode and is separate from the second electrode; or, it can be configured as follows:

[0237] [B] A second electrode is provided for each imaging element, and an upper charge movement control electrode is provided in such a way that it surrounds at least a portion of the second electrode and is separate from the second electrode. Below the upper charge movement control electrode, there is a portion of a charge accumulation electrode; or, it can be configured as follows:

[0238] [C] A second electrode is provided for each imaging element, and an upper charge movement control electrode is provided such that it surrounds at least a portion of the second electrode and is separate from the second electrode. Below the upper charge movement control electrode, a portion of a charge accumulation electrode is present, and below the upper charge movement control electrode, a lower charge movement control electrode is formed. In some cases, a potential generated by the coupling between the upper charge movement control electrode and the second electrode can be applied to a region of the photoelectric conversion layer located below the region between the upper charge movement control electrode and the second electrode.

[0239] Furthermore, the imaging element having an upper charge movement control electrode of the present invention can be configured in the following form:

[0240] The imaging element also includes a control unit, which is disposed on a semiconductor substrate and has a driving circuit.

[0241] The first electrode, the second electrode, the charge accumulation electrode, and the upper charge movement control electrode are connected to the drive circuit.

[0242] During charge accumulation, a potential V is applied from the drive circuit to the second electrode. 21 Apply potential V to the upper charge movement control electrode 41 This causes charge to accumulate in inorganic oxide semiconductor material layers, and...

[0243] During charge transfer, a potential V is applied from the driving circuit to the second electrode. 22 Apply potential V to the upper charge movement control electrode 42The charge accumulated in the inorganic oxide semiconductor material layer or the like is read out to the control section via the first electrode. Here, V 21 ≥ V 41 and V 22 ≥ V 42 The upper charge movement control electrode and the second electrode are formed on the same plane.

[0244] Further, the imaging device or the like of the present application including the above-described various preferred modes can also adopt a mode in which the imaging device or the like further includes a transfer control electrode (charge transfer electrode) provided between the first electrode and the charge accumulation electrode, the transfer control electrode is arranged separately from the first electrode and the charge accumulation electrode, and the transfer control electrode faces the inorganic oxide semiconductor material layer through an insulating layer. For convenience, the imaging device or the like of the present application having this mode is referred to as an "imaging device or the like of the present application including a transfer control electrode".

[0245] In addition, the imaging device or the like of the present application including a transfer control electrode can adopt a mode in which:

[0246] wherein the imaging device or the like further includes a control section provided on the semiconductor substrate and having a drive circuit,

[0247] the first electrode, the charge accumulation electrode, and the transfer control electrode are connected to the drive circuit,

[0248] during the charge accumulation period, a potential V 11 is applied to the first electrode, a potential V 31 is applied to the charge accumulation electrode, and a potential V 51 is applied to the transfer control electrode, and charge is accumulated in the inorganic oxide semiconductor material layer or the like, and

[0249] during the charge transfer period, a potential V 12 is applied to the first electrode, a potential V 32 is applied to the charge accumulation electrode, and a potential V 52 is applied to the transfer control electrode, and the charge accumulated in the inorganic oxide semiconductor material layer or the like is read out to the control section via the first electrode. Further, the potential of the first electrode is higher than the potential of the second electrode, and V 31 >V 51 and V 32 ≤ V 52 ≤ V 12 .

[0250] Further, the imaging device and the like of the present application including the above-described various preferred modes can also be configured as follows: the imaging device and the like includes a charge drain electrode connected to the inorganic oxide semiconductor material layer and provided separately from the first electrode and the charge accumulation electrode. For convenience, the imaging device and the like of the present application of this mode is referred to as "imaging device and the like of the present application including a charge drain electrode". In addition, the imaging device and the like of the present application including a charge drain electrode can adopt a mode in which the charge drain electrode is provided so as to surround the first electrode and the charge accumulation electrode (i.e., in a frame shape). The charge drain electrode can be shared (commonized) by a plurality of imaging devices. In this case, a mode in which:

[0251] wherein the inorganic oxide semiconductor material layer extends within the second opening portion formed in the insulating layer so as to be connected to the charge drain electrode,

[0252] an edge of a top surface of the charge drain electrode is covered with the insulating layer,

[0253] the charge drain electrode is exposed at a bottom surface of the second opening portion, and

[0254] when a surface of the insulating layer that is in contact with a top surface of the charge drain electrode is referred to as a third surface, and a surface of the insulating layer that is in contact with a portion of the inorganic oxide semiconductor material layer facing the charge accumulation electrode is referred to as a second surface, a side surface of the second opening portion has a slope that widens from the third surface toward the second surface.

[0255] Further, the imaging device and the like of the present application including a charge drain electrode can adopt a mode in which:

[0256] wherein the imaging device and the like further includes a control portion provided on the semiconductor substrate and having a drive circuit,

[0257] the first electrode, the charge accumulation electrode, and the charge drain electrode are connected to the drive circuit,

[0258] in a charge accumulation period, a potential V 11 is applied to the first electrode, a potential V 31 is applied to the charge accumulation electrode, and a potential V 61 is applied to the charge drain electrode, and charges are accumulated in the inorganic oxide semiconductor material layer and the like, and

[0259] in a charge transfer period, a potential V 12 is applied to the first electrode, a potential V 32 is applied to the charge accumulation electrode, and a potential V 62The electric charge applied to the electric charge discharging electrode and accumulated in the inorganic oxide semiconductor material layer or the like is read out to the control section via the first electrode. Further, the potential of the first electrode is higher than the potential of the second electrode, and V 61 >V 11 and V 62 <V 12 .

[0260] Further, in the above-described various preferred forms of the imaging device or the like of the present application, a form in which the electric charge accumulation electrode includes a plurality of electric charge accumulation electrode sections can be provided. For convenience, the imaging device or the like of the present application of such a form is referred to as "imaging device or the like of the present application including a plurality of electric charge accumulation electrode sections". The number of the electric charge accumulation electrode sections only needs to be two or more. In addition, in the imaging device or the like of the present application including a plurality of electric charge accumulation electrode sections, in a case where different potentials are applied to the N electric charge accumulation electrode sections respectively, the following form can be adopted:

[0261] where, in a case where the potential of the first electrode is higher than the potential of the second electrode, during the electric charge transfer period, the potential applied to the electric charge accumulation electrode section closest to the first electrode (the first photoelectric conversion section) is higher than the potential applied to the electric charge accumulation electrode section farthest from the first electrode (the Nth photoelectric conversion section), and

[0262] where, in a case where the potential of the first electrode is lower than the potential of the second electrode, during the electric charge transfer period, the potential applied to the electric charge accumulation electrode section closest to the first electrode (the first photoelectric conversion section) is lower than the potential applied to the electric charge accumulation electrode section farthest from the first electrode (the Nth photoelectric conversion section).

[0263] The imaging device or the like of the present application including the above-described various preferred forms can adopt the following configuration:

[0264] where, on the semiconductor substrate, at least the floating diffusion layer and the amplification transistor constituting the control section are provided, and

[0265] the first electrode is connected to the gate section of the floating diffusion layer and the amplification transistor. In this case, further, the following configuration can be adopted:

[0266] where, on the semiconductor substrate, further, the reset transistor and the selection transistor constituting the control section are provided,

[0267] the floating diffusion layer is connected to one source / drain region of the reset transistor, and

[0268] one source / drain region of the amplification transistor is connected to one source / drain region of the selection transistor, and the other source / drain region of the selection transistor is connected to the signal line.

[0269] Further, the imaging device and the like of the present application including the above-described various preferred aspects can adopt an aspect in which the size of the charge accumulation electrode is larger than the first electrode. When the area of the charge accumulation electrode is represented by S1' and the area of the first electrode is represented by S1, although there is no limitation, it is preferable to satisfy 4 ≤ S1' / S1.

[0270] Alternatively, as a modification of the imaging device and the like of the present application including the above-described various preferred aspects, the imaging device can include the first to sixth configurations described below. Specifically, in each of the imaging devices of the first to sixth configurations in the imaging device and the like of the present application including the above-described various preferred aspects,

[0271] The photoelectric conversion section includes N (where N ≥ 2) photoelectric conversion section segments,

[0272] The inorganic oxide semiconductor material layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0273] The insulating layer includes N insulating layer segments,

[0274] In the imaging devices of the first to third configurations, the charge accumulation electrode includes N charge accumulation electrode segments, while in the imaging devices of the fourth and fifth configurations, the charge accumulation electrode includes N charge accumulation electrode segments arranged separately from each other,

[0275] The nth (where n = 1, 2, 3,..., N) photoelectric conversion section segment includes an nth charge accumulation electrode segment, an nth insulating layer segment, and an nth photoelectric conversion layer segment, and

[0276] The photoelectric conversion section segment having a larger n value is farther from the first electrode. Here, the "photoelectric conversion layer segment" refers to a segment formed by laminating the photoelectric conversion layer and the inorganic oxide semiconductor material layer.

[0277] Further, in the imaging device of the first configuration, the thickness of the insulating layer section gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section. Further, in the imaging device of the second configuration, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section. Note that, in the photoelectric conversion layer section, the thickness of the photoelectric conversion layer section can be changed by changing the thickness of the photoelectric conversion layer and keeping the thickness of the inorganic oxide semiconductor material layer constant. Further, the thickness of the photoelectric conversion layer section can be changed by keeping the thickness of the photoelectric conversion layer constant and changing the thickness of the inorganic oxide semiconductor material layer. Further, the thickness of the photoelectric conversion layer section can be changed by changing the thickness of the photoelectric conversion layer and changing the thickness of the inorganic oxide semiconductor material layer. Further, in the imaging device of the third configuration, the material constituting the insulating layer section is different for the photoelectric conversion sections that are adjacent to each other. Further, in the imaging device of the fourth configuration, the material constituting the charge accumulation electrode section is different for the photoelectric conversion sections that are adjacent to each other. Further, in the imaging device of the fifth configuration, the area of the charge accumulation electrode section gradually decreases from the first photoelectric conversion section to the Nth photoelectric conversion section. The area can continuously decrease or decrease in steps.

[0278] Alternatively, in the imaging device of a sixth configuration in the imaging device and the like of the present application including the above-described various preferred modes, if the stacking direction of the charge accumulation electrode, the insulating layer, the inorganic oxide semiconductor material layer, and the photoelectric conversion layer is defined as the Z direction, and the direction away from the first electrode is defined as the X direction, when the stacked portion in which the charge accumulation electrode, the insulating layer, the inorganic oxide semiconductor material layer, and the photoelectric conversion layer are stacked is cut along a YZ imaginary plane, the cross-sectional area of the stacked portion changes depending on the distance from the first electrode. The change in the cross-sectional area can be a continuous change or a change in steps.

[0279] In the image pickup element of the first configuration and the second configuration, the N photoelectric conversion layer segments are continuously provided, the N insulating layer segments are continuously provided, and the N charge accumulation electrode segments are continuously provided. In the image pickup element of the third configuration to the fifth configuration, the N photoelectric conversion layer segments are continuously provided. Further, in the image pickup element of the fourth configuration and the fifth configuration, the N insulating layer segments are continuously provided. In the image pickup element of the third configuration, the N insulating layer segments are provided so as to correspond to the respective photoelectric conversion portion segments, respectively. Further, in the image pickup element of the fourth configuration and the fifth configuration, and sometimes in the image pickup element of the third configuration, the N charge accumulation electrode segments are provided so as to correspond to the respective photoelectric conversion portion segments, respectively. Further, in each of the image pickup elements of the first configuration to the sixth configuration, the same potential is applied to all of the charge accumulation electrode segments. Alternatively, in the image pickup element of the fourth configuration and the fifth configuration, and sometimes in the image pickup element of the third configuration, different potentials can be applied to the N charge accumulation electrode segments.

[0280] In the image pickup element of the present application including the image pickup element of the first configuration to the sixth configuration, the thickness of the insulating layer segment is specified. Alternatively, the thickness of the photoelectric conversion layer segment is specified. Alternatively, the material constituting the insulating layer segment is different. Alternatively, the material constituting the charge accumulation electrode segment is different. Alternatively, the area of the charge accumulation electrode segment is specified. Alternatively, the cross-sectional area of the laminated portion is specified. Thus, a charge transport gradient is formed, and the charge generated by photoelectric conversion can be more easily and reliably transported to the first electrode. In addition, as a result, it is possible to prevent the generation of residual images or to prevent the generation of charge transport residues.

[0281] In the image pickup element of the first configuration to the fifth configuration, the greater the value of n, the further the photoelectric conversion portion segment is from the first electrode. Whether the photoelectric conversion portion segment is far from the first electrode is judged with the X direction as a reference. In addition, in the image pickup element of the sixth configuration, the direction away from the first electrode is specified as the X direction, and the definition of the "X direction" is as follows. That is, the pixel region in which a plurality of image pickup elements or laminated image pickup elements are arranged includes a plurality of pixels arranged in a two-dimensional array (i.e., regularly arranged in the X direction and the Y direction). In the case where the planar shape of the pixel is rectangular, the direction of extension of the edge closest to the first electrode is defined as the Y direction, and the direction orthogonal to the Y direction is defined as the X direction. Alternatively, in the case where the planar shape of the pixel is an arbitrary shape, the general direction including the line segment or the curve closest to the first electrode is defined as the Y direction, and the direction orthogonal to the Y direction is defined as the X direction.

[0282] Hereinafter, with respect to the image pickup element of the first configuration to the sixth configuration, a case where the potential of the first electrode is higher than the potential of the second electrode will be described.

[0283] In the imaging device of the first configuration, the thickness of the insulating layer section gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section. However, preferably, the thickness of the insulating layer section gradually increases, thereby forming a charge transport gradient. Further, when a state of V 31 ≥ V 11 is reached during the charge accumulation period, the nth photoelectric conversion section is able to accumulate more charges than the (n+1)th photoelectric conversion section, and a stronger electric field is applied to the nth photoelectric conversion section than to the (n+1)th photoelectric conversion section. This makes it possible to reliably prevent the flow of charges from the first photoelectric conversion section to the first electrode. In addition, when a state of V 32 < V 12 is reached during the charge transport period, the flow of charges from the first photoelectric conversion section to the first electrode and the flow of charges from the (n+1)th photoelectric conversion section to the nth photoelectric conversion section are reliably ensured.

[0284] In the imaging device of the second configuration, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section. However, preferably, the thickness of the photoelectric conversion layer section gradually increases, thereby forming a charge transport gradient. Further, when a state of V 31 ≥ V 11 is reached during the charge accumulation period, a stronger electric field is applied to the nth photoelectric conversion section than to the (n+1)th photoelectric conversion section. This makes it possible to reliably prevent the flow of charges from the first photoelectric conversion section to the first electrode. In addition, when a state of V 32 < V 12 is reached during the charge transport period, the flow of charges from the first photoelectric conversion section to the first electrode and the flow of charges from the (n+1)th photoelectric conversion section to the nth photoelectric conversion section are reliably ensured.

[0285] In the imaging device of the third configuration, the material used to constitute the insulating layer section is different for the photoelectric conversion sections that are adjacent to each other, thereby forming a charge transport gradient. Preferably, the value of the dielectric constant of the material constituting the insulating layer section gradually decreases from the first photoelectric conversion section to the Nth photoelectric conversion section. At this time, by adopting this configuration, when a state of V 31 ≥ V 11 is reached during the charge accumulation period, the nth photoelectric conversion section is able to accumulate more charges than the (n+1)th photoelectric conversion section. Further, when a state of V 32 < V 12the flow of the electric charge from the first photoelectric conversion section to the first electrode and the flow of the electric charge from the (n+l)th photoelectric conversion section to the nth photoelectric conversion section can be reliably ensured.

[0286] In the fourth configuration of the image pickup element, the material for constituting the charge accumulation electrode section is different for the photoelectric conversion section sections adjacent to each other, which forms a charge transport gradient. Preferably, the value of the work function of the material constituting the charge accumulation electrode section gradually increases from the first photoelectric conversion section to the Nth photoelectric conversion section. In addition, by adopting this configuration, a potential gradient that is favorable for the transport of the signal charge can be formed regardless of whether the voltage (potential) is positive or negative.

[0287] In the fifth configuration of the image pickup element, the area of the charge accumulation electrode section gradually decreases from the first photoelectric conversion section to the Nth photoelectric conversion section, thereby forming a charge transport gradient. Thus, when a state where V 31 ≥ V 11 is reached in the charge accumulation period, the nth photoelectric conversion section can accumulate more electric charge than the (n+l)th photoelectric conversion section. Furthermore, when a state where V 32 < V 12 is reached in the charge transport period, the flow of the electric charge from the first photoelectric conversion section to the first electrode and the flow of the electric charge from the (n+l)th photoelectric conversion section to the nth photoelectric conversion section can be reliably ensured.

[0288] In the sixth configuration of the image pickup element, the cross-sectional area of the laminated portion varies depending on the distance from the first electrode, which forms a charge transport gradient. Specifically, if a configuration is adopted in which the thickness of the cross-section of the laminated portion is constant and the width of the cross-section of the laminated portion narrows as it gets farther from the first electrode, as explained in the fifth configuration of the image pickup element, when a state where V 31 ≥ V 11 is reached in the charge accumulation period, the region closer to the first electrode can accumulate more electric charge than the region farther from the first electrode. Thus, when a state where V 32 < V 12 is reached in the charge transport period, the flow of the electric charge from the region closer to the first electrode to the first electrode and the flow of the electric charge from the region farther from the first electrode to the region closer to the first electrode can be reliably ensured. On the other hand, if a configuration is adopted in which the width of the cross-section of the laminated portion is constant and the thickness of the cross-section of the laminated portion gradually increases (specifically, the thickness of the insulating layer section gradually increases), as explained in the first configuration of the image pickup element, when a state where V31 ≥ V 11 When the state where V 32 < V 12 When the state where V 31 ≥ V 11 When the state where V 32 < V 12 When the state where V

[0289] Two or more of the image pickup elements including the first to sixth configurations described above can be appropriately combined as needed.

[0290] The solid-state imaging device of the first aspect and the second aspect of the present application can be a solid-state imaging device having a configuration in which the solid-state imaging device includes a plurality of the first to sixth configurations of imaging elements, the plurality of imaging elements constitute an imaging element block, and the first electrode is shared by the plurality of imaging elements constituting the imaging element block. For convenience, the solid-state imaging device having this configuration is referred to as a "first configuration of solid-state imaging device". Alternatively, the solid-state imaging device of the first aspect and the second aspect of the present application can be a solid-state imaging device having a configuration in which the solid-state imaging device includes a plurality of the first to sixth configurations of imaging elements or a plurality of stacked imaging elements including at least one of the first to sixth configurations of imaging elements, the plurality of imaging elements or the plurality of stacked imaging elements constitute an imaging element block, and the first electrode is shared by the plurality of imaging elements or the plurality of stacked imaging elements constituting the imaging element block. For convenience, the solid-state imaging device having this configuration is referred to as a "second configuration of solid-state imaging device". In addition, if the first electrode is shared by the plurality of imaging elements constituting the imaging element block as described above, it is possible to simplify and miniaturize the configuration and structure of a pixel region in which the plurality of imaging elements are arranged.

[0291] In the solid-state imaging device of the first configuration and the second configuration, one floating diffusion layer is provided for a plurality of imaging elements (one imaging element block). Here, the plurality of imaging elements provided corresponding to one floating diffusion layer can include a plurality of first-type imaging elements as described later, or can include at least one first-type imaging element and one or more second-type imaging elements as described later. In addition, by appropriately controlling the timing during charge transfer, it is possible to allow the plurality of imaging elements to share one floating diffusion layer. The plurality of imaging elements operate in association and are connected to a drive circuit described later in the form of an imaging element block. That is, the plurality of imaging elements constituting an imaging element block are connected to one drive circuit. However, the control of the charge accumulation electrode is performed separately for each imaging element. Furthermore, the plurality of imaging elements can share one contact hole portion. As for the arrangement relationship between the first electrode shared by the plurality of imaging elements and the charge accumulation electrodes of the respective imaging elements, there is also a case where the first electrode is arranged to be contiguous to the charge accumulation electrodes of the respective imaging elements. Alternatively, there is also a case where the first electrode is arranged to be contiguous to the charge accumulation electrodes of some of the plurality of imaging elements, but not contiguous to the charge accumulation electrodes of the remaining imaging elements of the plurality of imaging elements. In this case, the movement of the charge from the above-mentioned remaining imaging elements of the plurality of imaging elements to the first electrode is movement via the above-mentioned some of the plurality of imaging elements. Preferably, the distance (for convenience, referred to as "distance A") between the charge accumulation electrodes constituting the imaging elements is larger than the distance (for convenience, referred to as "distance B") between the first electrode and the charge accumulation electrode in the imaging element contiguous to the first electrode, in order to secure the movement of the charge from the respective imaging elements to the first electrode. Furthermore, preferably, the value of the distance A is larger as the distance of the imaging element from the first electrode is farther. Note that the above description can be applied not only to the solid-state imaging device of the first configuration and the second configuration, but also to the solid-state imaging device of the first aspect and the second aspect of the present application.

[0292] Further, the imaging device and the like of the present application including the above-described various preferred modes can adopt a mode in which light is incident from the second electrode side, and a light shielding layer is formed on the light incident side of the second electrode. Alternatively, a mode in which light is incident from the second electrode side, and light is not incident on the first electrode (in some cases, the first electrode and the transfer control electrode) can be adopted. In this case, a configuration in which a light shielding layer is formed on the light incident side of the second electrode and above the first electrode (in some cases, the first electrode and the transfer control electrode) can be adopted. Alternatively, a configuration in which a chip-on-micro-lens is provided above the charge accumulation electrode and the second electrode, and light incident on the chip-on-micro-lens is condensed on the charge accumulation electrode can be adopted. Here, the light shielding layer can be disposed above the light incident side surface of the second electrode, or can be disposed on the light incident side surface of the second electrode. In some cases, a light shielding layer can be formed in the second electrode. Examples of a material constituting the light shielding layer include chromium (Cr), copper (Cu), aluminum (Al), tungsten (W), and a light impermeable resin (for example, a polyimide resin).

[0293] Specific examples of the imaging element and the like of the present application include an imaging element (for convenience, referred to as "a first type blue light imaging element") having a photoelectric conversion layer or a photoelectric conversion portion (for convenience, referred to as "a first type blue light photoelectric conversion layer" or "a first type blue light photoelectric conversion portion") that absorbs blue light (light of 425 nm to 495 nm) and that is sensitive to blue light, an imaging element (for convenience, referred to as "a first type green light imaging element") having a photoelectric conversion layer or a photoelectric conversion portion (for convenience, referred to as "a first type green light photoelectric conversion layer" or "a first type green light photoelectric conversion portion") that absorbs green light (light of 495 nm to 570 nm) and that is sensitive to green light, and an imaging element (for convenience, referred to as "a first type red light imaging element") having a photoelectric conversion layer or a photoelectric conversion portion (for convenience, referred to as "a first type red light photoelectric conversion layer" or "a first type red light photoelectric conversion portion") that absorbs red light (light of 620 nm to 750 nm) and that is sensitive to red light. In addition, for convenience, a conventional imaging element that does not have a charge accumulation electrode and that is sensitive to blue light is referred to as "a second type blue light imaging element". For convenience, a conventional imaging element that does not have a charge accumulation electrode and that is sensitive to green light is referred to as "a second type green light imaging element". For convenience, a conventional imaging element that does not have a charge accumulation electrode and that is sensitive to red light is referred to as "a second type red light imaging element". For convenience, a photoelectric conversion layer or a photoelectric conversion portion that constitutes the second type blue light imaging element is referred to as "a second type blue light photoelectric conversion layer" or "a second type blue light photoelectric conversion portion". For convenience, a photoelectric conversion layer or a photoelectric conversion portion that constitutes the second type green light imaging element is referred to as "a second type green light photoelectric conversion layer" or "a second type green light photoelectric conversion portion". For convenience, a photoelectric conversion layer or a photoelectric conversion portion that constitutes the second type red light imaging element is referred to as "a second type red light photoelectric conversion layer" or "a second type red light photoelectric conversion portion".

[0294] The stacked type imaging element of the present application includes at least one imaging element and the like (photoelectric conversion element) of the present application, and a specific example of the configuration and structure of the stacked type imaging element can be a configuration and structure as follows:

[0295] [A] In the configuration and structure, the first type blue light photoelectric conversion portion, the first type green light photoelectric conversion portion, and the first type red light photoelectric conversion portion are stacked in the vertical direction, and the control portion of the first type blue light imaging element, the control portion of the first type green light imaging element, and the control portion of the first type red light imaging element are all provided on the semiconductor substrate;

[0296] [B] In this configuration and structure, the first-type blue light photoelectric conversion section and the first-type green light photoelectric conversion section are stacked in the vertical direction, the second-type red light photoelectric conversion section is arranged below the two layers of the first-type photoelectric conversion sections, and the control sections of the first-type blue light image pickup element, the first-type green light image pickup element, and the second-type red light image pickup element are all provided on the semiconductor substrate.

[0297] [C] In this configuration and structure, the second-type blue light photoelectric conversion section and the second-type red light photoelectric conversion section are arranged below the first-type green light photoelectric conversion section, and the control sections of the first-type green light image pickup element, the second-type blue light image pickup element, and the second-type red light image pickup element are all provided on the semiconductor substrate.

[0298] [D] In this configuration and structure, the second-type green light photoelectric conversion section and the second-type red light photoelectric conversion section are arranged below the first-type blue light photoelectric conversion section, and the control sections of the first-type blue light image pickup element, the second-type green light image pickup element, and the second-type red light image pickup element are all provided on the semiconductor substrate.

[0299] Preferably, the arrangement order of the photoelectric conversion sections of the image pickup elements in the vertical direction is, in order from the light incident direction, a blue light photoelectric conversion section, a green light photoelectric conversion section, and a red light photoelectric conversion section, or, in order from the light incident direction, a green light photoelectric conversion section, a blue light photoelectric conversion section, and a red light photoelectric conversion section. This is because shorter-wavelength light is more effectively absorbed on the light incident surface side. Since red has the longest wavelength among the three colors, it is preferable to position the red light photoelectric conversion section at the lowermost layer from the light incident surface. The stacked structure of the image pickup elements constitutes one pixel. In addition, a first-type near-infrared light photoelectric conversion section (alternatively, an infrared light photoelectric conversion section) can be included. Here, preferably, the photoelectric conversion layer of the first-type infrared light photoelectric conversion section includes, for example, an organic material, and is arranged at the lowermost layer of the stacked structure of the first-type image pickup elements and above the second-type image pickup elements. Alternatively, a second-type near-infrared light photoelectric conversion section (alternatively, an infrared light photoelectric conversion section) can be provided below the first-type photoelectric conversion section.

[0300] In the first-type image pickup element, for example, a first electrode is formed on an interlayer insulating layer provided on the semiconductor substrate. The image pickup element formed on the semiconductor substrate can be back-illuminated or front-illuminated.

[0301] In the case where the photoelectric conversion layer includes an organic material, the photoelectric conversion layer can adopt any one of the following four forms: (1) The photoelectric conversion layer is composed of a p-type organic semiconductor. (2) The photoelectric conversion layer is composed of an n-type organic semiconductor. (3) The photoelectric conversion layer is composed of a stacked structure of a p-type organic semiconductor layer / n-type organic semiconductor layer. The photoelectric conversion layer is composed of a stacked structure of a p-type organic semiconductor layer / [mixed layer (bulk heterostructure) of a p-type organic semiconductor and an n-type organic semiconductor] / n-type organic semiconductor layer. The photoelectric conversion layer is composed of a stacked structure of a p-type organic semiconductor layer / [mixed layer (bulk heterostructure) of a p-type organic semiconductor and an n-type organic semiconductor]. The photoelectric conversion layer is composed of a stacked structure of an n-type organic semiconductor layer / [mixed layer (bulk heterostructure) of a p-type organic semiconductor and an n-type organic semiconductor]. (4) The photoelectric conversion layer is composed of a mixed layer (bulk heterostructure) of a p-type organic semiconductor and an n-type organic semiconductor. However, the order of the stacking can be arbitrarily changed.

[0302] Examples of the p-type organic semiconductor include naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, tetracene derivatives, pentacene derivatives, quinacridone derivatives, thiophene derivatives, thienothiophene derivatives, benzothiophene derivatives, benzothienobenzothiophene derivatives, triallylamine derivatives, carbazole derivatives, perylene derivatives, coronene derivatives, Derivatives, fluoranthene derivatives, phthalocyanine derivatives, subphthalocyanine derivatives, subporphyrin derivatives, metal complexes with heterocyclic compounds as coordination bases, polythiophene derivatives, polybenzothiadiazole derivatives, and polyfluorene derivatives, and the like. Examples of n-type organic semiconductors include: fullerenes and fullerene derivatives (for example, fullerenes (higher fullerenes) such as C60, C70, or C74, or intercalated fullerenes, or fullerene derivatives (for example, fullerene fluorides, PCBM fullerene compounds, or fullerene polymers, and the like)); organic semiconductors with a larger (deeper) HOMO and LUMO than p-type organic semiconductors; and transparent inorganic metal oxides. Specific examples of n-type organic semiconductors include: organic molecules with heterocyclic compounds containing nitrogen atoms, oxygen atoms, or sulfur atoms in a portion of the molecular skeleton; or organometallic complexes; or subphthalocyanine derivatives. Examples of the above-mentioned heterocyclic compounds include, for example: pyridine derivatives, pyrazine derivatives, pyrimidine derivatives, triazine derivatives, quinoline derivatives, quinoxaline derivatives, isoquinoline derivatives, acridine derivatives, phenoxazine derivatives, phenanthroline derivatives, tetrazole derivatives, pyrazole derivatives, imidazole derivatives, thiazole derivatives, oxazole derivatives, imidazole derivatives, benzimidazole derivatives, benzotriazole derivatives, benzoxazole derivatives, benzoxazole derivatives, carbazole derivatives, benzofuran derivatives, dibenzofuran derivatives, subporphyrin derivatives, poly-p-phenylenevinylene derivatives, polybenzothiadiazole derivatives, and polyfluorene derivatives, and the like. Examples of groups and the like included in fullerene derivatives include: halogen atoms; straight-chain, branched, or cyclic alkyl groups or phenyl groups; groups with straight-chain or condensed aromatic compounds; groups including halides; partially fluorinated alkyl groups; perfluorinated alkyl groups; silylalkyl groups; silylalkoxy groups; arylsilyl groups; arylsulfanyl groups; alkylsulfanyl groups; arylsulfonyl groups; alkylsulfonyl groups; arylsulfide groups; alkylsulfide groups; amino groups; alkylamino groups; arylamino groups; hydroxyl groups; alkoxy groups; acylamino groups; acyloxy groups; carbonyl groups; carboxyl groups; carboxamide groups; carboalkoxy groups; acyl groups; sulfonyl groups; cyano groups; nitro groups; groups with chalcogen compounds; phosphine groups; phosphonic groups; and derivatives thereof. Although the thickness of the photoelectric conversion layer including an organic material (sometimes also referred to as an "organic photoelectric conversion layer") is not limited, the above-mentioned thickness may, for example, be 1 x 10 -8 m to 5 x 10 -7 m, preferably 2.5 x 10 -8 m to 3 x 10 -7 m, more preferably 2.5 x 10 -8 m to 2 x 10 -7 m, and most preferably 1 x 10 -7m to 1.8 x 10 -7 m. Note that an organic semiconductor is generally classified into a p-type and an n-type. The p-type indicates easy transport of holes, and the n-type indicates easy transport of electrons. The organic semiconductor is not limited to the explanation that it has holes or electrons as majority carriers of thermal excitation as in the case of an inorganic semiconductor.

[0303] Alternatively, examples of a material constituting an organic photoelectric conversion layer that photoelectrically converts green light include rhodamine-based dyes, merocyanine-based dyes, quinacridone derivatives, and subphthalocyanine dyes (subphthalocyanine derivatives), and the like. Examples of a material constituting an organic photoelectric conversion layer that photoelectrically converts blue light include coumalin dyes, tris-8-hydroxyquinoline aluminum (Alq3), and merocyanine-based dyes, and the like. Examples of a material constituting an organic photoelectric conversion layer that photoelectrically converts red light include phthalocyanine-based dyes and subphthalocyanine-based dyes (subphthalocyanine derivatives).

[0304] Alternatively, examples of an inorganic material constituting a photoelectric conversion layer can include crystalline silicon, amorphous silicon, microcrystalline silicon, crystalline selenium, amorphous selenium, a chalcopyrite compound (e.g., CIGS (CuInGaSe), CIS (CuInSe2), CuInS2, CuAlS2, CuAlSe2, CuGaS2, CuGaSe2, AgAlS2, AgAlSe2, AgInS2, or AgInSe2), or a III-V compound (e.g., GaAs, InP, AlGaAs, InGaP, AlGaInP, or InGaAsP), and the example can further include a compound semiconductor such as CdSe, CdS, In2Se3, In2S3, Bi2Se3, Bi2S3, ZnSe, ZnS, PbSe, or PbS. In addition, a quantum dot including these materials can also be used for the photoelectric conversion layer.

[0305] The solid-state imaging device of the first aspect to the second aspect of the present application, and the solid-state imaging device of the first configuration to the second configuration can be used to constitute a single-board type color solid-state imaging device.

[0306] In the solid-state imaging device of the second aspect of the present application including the stacked imaging element, unlike the solid-state imaging device including the imaging element in a Bayer array (i.e., without using a color filter layer to split light into blue, green, and red), one pixel is configured by stacking imaging elements having sensitivity to light of a plurality of wavelengths in the light incident direction within the same pixel. Therefore, it is possible to improve sensitivity and increase the pixel density per unit volume. Furthermore, since organic materials have a high absorption coefficient, it is possible to make the film thickness of the organic photoelectric conversion layer thinner than the film thickness of a conventional Si-based photoelectric conversion layer. This alleviates light leakage from an adjacent pixel and relaxes the restriction on the incident angle of light. Furthermore, in a conventional Si-based imaging element, since three-color pixels are subjected to interpolation processing to generate color signals, false colors are generated. However, in the solid-state imaging device of the second aspect of the present application including the stacked imaging element, it is possible to suppress the generation of false colors. The organic photoelectric conversion layer itself also functions as a color filter layer. Therefore, even without providing a color filter layer, it is possible to perform color separation.

[0307] Furthermore, in the solid-state imaging device of the first aspect of the present application, by using a color filter layer, it is possible to alleviate the requirement for the light splitting characteristics of blue, green, and red, and to have higher mass productivity. Examples of the array of imaging elements in the solid-state imaging device of the first aspect of the present application can be cited in addition to the Bayer array: an interline arrangement, a G stripe RB checkerboard array, a G stripe RB full checkerboard array, a checkerboard complementary color array, a stripe array, a diagonal stripe array, a primary color color difference array, a field color difference sequence array, a frame color difference sequence array, a MOS type array, a modified MOS type array, a frame interlaced array, and a field interlaced array. Here, one imaging element constitutes one pixel (or sub-pixel).

[0308] As examples of the color filter layer (wavelength selection mechanism), not only a filter layer capable of transmitting red light, green light, and blue light can be cited, but a filter layer capable of transmitting light having a specific wavelength such as cyan, magenta, or yellow can also be cited as appropriate. The color filter layer can be constituted not only by an organic material type color filter layer using an organic compound (such as a pigment and a dye, etc.), but also by a thin film containing an inorganic material such as amorphous silicon, or a wavelength selection element (color filter layer having a conductor grid structure having a grid-shaped hole structure provided in a conductor thin film, for example, see Japanese Patent Application Publication No. 2008-177191) to which a plasmon is applied.

[0309] The pixel region of the imaging element or the like of the present application or the stacked imaging element of the present application in which a plurality of pixels are arranged includes a plurality of pixels regularly arranged in a two-dimensional manner. The pixel region generally includes an effective pixel region for actually receiving light, amplifying signal charges generated by photoelectric conversion, and reading out to a driving circuit, and a black reference pixel region (also referred to as an optical black pixel region (OPB)) for outputting optical black as a reference of a black level. The black reference pixel region is generally arranged at the periphery of the effective pixel region.

[0310] The imaging element or the like of the present application including the above-described various preferred modes is irradiated with light, photoelectric conversion occurs in the photoelectric conversion layer, and carrier separation of holes and electrons is performed. In addition, an electrode that extracts holes is referred to as a positive electrode, and an electrode that extracts electrons is referred to as a negative electrode. The first electrode constitutes the negative electrode, and the second electrode constitutes the positive electrode.

[0311] The first electrode, the charge accumulation electrode, the transfer control electrode, the charge movement control electrode, the charge discharge electrode, and the second electrode each can include a transparent conductive material. The first electrode, the charge accumulation electrode, the transfer control electrode, and the charge discharge electrode can be collectively referred to as "first electrode or the like". Alternatively, in the case where the imaging device or the like of the present application is arranged in a plane, for example, in a manner like a Bayer array, the second electrode can include a transparent conductive material, and the first electrode or the like can include a metal material. In this case, specifically, the second electrode on the light incident side can include a transparent conductive material, and the first electrode or the like can include, for example, Al-Nd (an alloy of aluminum and neodymium) or ASC (an alloy of aluminum, samarium, and copper). The electrode including a transparent conductive material can sometimes be referred to as a "transparent electrode". Here, preferably, the band gap of the transparent conductive material is 2.5 eV or more, and more preferably, 3.1 eV or more. Examples of the transparent conductive material constituting the transparent electrode include conductive metal oxides. Specific examples thereof include: indium oxide, indium tin oxide (ITO, i.e., In2O3doped with Sn, including crystalline ITO and amorphous ITO), indium zinc oxide (IZO) obtained by adding indium as a dopant to zinc oxide, indium-gallium oxide (IGO) obtained by adding indium as a dopant to gallium oxide, indium-gallium-zinc oxide (IGZO, In-GaZnO4) obtained by adding indium and gallium as dopants to zinc oxide, indium-tin-zinc oxide (ITZO) obtained by adding indium and tin as dopants to zinc oxide, IFO (In2O3doped with F), tin oxide (SnO2), ATO (SnO2doped with Sb), FTO (SnO2doped with F), zinc oxide (including: ZnO doped with other elements), aluminum zinc oxide (AZO) obtained by adding aluminum as a dopant to zinc oxide, gallium zinc oxide (GZO) obtained by adding gallium as a dopant to zinc oxide, titanium oxide (TiO2), niobium titanium oxide (TNO) obtained by adding niobium as a dopant to titanium oxide, antimony oxide, CuI, InSbO4, ZnMgO, CuInO2, MgIn2O4, CdO, ZnSnO3, spinel-type oxides, and oxides having a YbFe2O4structure. Alternatively, examples of the transparent electrode include a transparent electrode containing gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like as a parent layer. The thickness of the transparent electrode can be 2 x 10 -8 m to 2 x 10 -7 m, and preferably, 3 x 10 -8 m to 1 x 10 -7 m. In the case where the first electrode is required to be transparent, the charge discharge electrode is also preferably composed of a transparent conductive material from the viewpoint of simplifying the manufacturing process.

[0312] Alternatively, in the case where transparency is not required, as the conductive material constituting the negative electrode serving as an electrode for extracting electrons, the negative electrode is preferably constituted by a conductive material having a low work function (for example, φ = 3.5 eV to 4.5 eV). Specific examples thereof include: alkali metals (for example, Li, Na, or K, etc.), fluorides of alkali metals, oxides of alkali metals, alkaline earth metals (for example, Mg or Ca, etc.), fluorides of alkaline earth metals, oxides of alkaline earth metals, aluminum (Al), zinc (Zn), tin (Sn), thallium (Tl), sodium-potassium alloys, aluminum-lithium alloys, magnesium-silver alloys, rare earth metals such as indium or ytterbium, and alloys of the above. Alternatively, examples of the material constituting the negative electrode include: metals such as platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), cobalt (Co), or molybdenum (Mo); alloys containing the above metal elements; conductive particles containing the above metals; conductive particles of alloys containing the above metals; polycrystalline silicon containing impurities; carbon-based materials; oxide semiconductor materials; and conductive materials such as carbon nanotubes or graphene. A laminated structure containing several layers of the above elements can also be used. Furthermore, examples of the material constituting the negative electrode include organic materials (conductive polymers) such as poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) [PEDOT / PSS]. Furthermore, these conductive materials can be mixed with a binder (a polymer) to form a paste or an ink, and the paste or the ink can be hardened and used as an electrode.

[0313] A dry method or a wet method can be used as a film formation method for the first electrode or the like or the second electrode (negative electrode or positive electrode). Examples of the dry method include a physical vapor deposition method (PVD method) and a chemical vapor deposition method (CVD method). Examples of the film formation method using the principle of the PVD method include a vacuum vapor deposition method using resistance heating or high-frequency heating, an EB (electron beam) vapor deposition method, various sputtering methods (magnetron sputtering method, RF-DC (radio frequency-direct current) combined bias sputtering method, ECR (electron cyclotron resonance) sputtering method, facing target sputtering method, or high-frequency sputtering method), ion plating method, laser ablation method, molecular beam epitaxy method, and laser transfer method. In addition, examples of the CVD method include a plasma CVD method, thermal CVD method, metal organic (MO) CVD method, and optical CVD method. Meanwhile, examples of the wet method include an electroplating method, an electroless plating method, a spin coating method, an inkjet method, a spray coating method, an imprint method, a microcontact printing method, a flexographic printing method, a gravure printing method, a gravure printing method, a gravure printing method, and an immersion method. Examples of the patterning method include chemical etching such as a shadow mask, laser transfer, or photolithography; and physical etching using ultraviolet light, laser light, or the like. Examples of the technique for planarizing the first electrode or the like or the second electrode include a laser planarization method, a reflow method, and a chemical mechanical polishing (CMP) method.

[0314] Examples of the material constituting the insulating layer include not only inorganic insulating materials but also organic insulating materials (organic polymers), and combinations thereof can be used. Examples of the inorganic insulating material include metal oxide high-dielectric insulating materials such as a silicon oxide material, a silicon nitride (SiN Y ), or an aluminum oxide (AI2O3). Examples of the organic insulating material (organic polymer) include polymethyl methacrylate (PMMA); polyvinyl phenol (PVP); polyvinyl alcohol (PVA); polyimide; polycarbonate (PC); polyethylene terephthalate (PET); polystyrene; silanol derivatives (silane coupling agents) such as N-(2-aminoethyl)-3-aminopropyltrimethoxysilane (AEAPTMS), 3-mercaptopropyltrimethoxysilane (MPTMS), or octadecyltrichlorosilane (OTS); novolac phenolic resin; fluorine-based resin; and straight-chain hydrocarbons having a functional group capable of bonding to the control electrode at one end such as octadecyl mercaptan or dodecyl isocyanate. Examples of the silicon oxide material include silicon oxide (SiO X), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin on glass), and low dielectric insulating materials (e.g., polyarylether, cycloperfluorocarbon polymers and benzocyclobutene, cyclic fluorocarbon resins, polytetrafluoroethylene, fluorinated arylether, fluorinated polyimide, amorphous carbon, and organic SOG). The insulating layer can have a single layer configuration, or can have a configuration in which a plurality of layers (e.g., two layers) are stacked. In the latter case, by forming an insulating layer-underlayer at least on the charge accumulation electrode and in the region between the charge accumulation electrode and the first electrode, and performing a planarization process on the insulating layer-underlayer, it is only necessary to leave the insulating layer-underlayer at least in the region between the charge accumulation electrode and the first electrode, and to form an insulating layer-overlayer on the remaining insulating layer-underlayer and the charge accumulation electrode. Thus, planarization of the insulating layer can be reliably achieved. The materials constituting the protective material layer, the various interlayer insulating layers, and the insulating material film are appropriately selected from among the above materials.

[0315] The configuration and structure of the floating diffusion layer, the amplification transistor, the reset transistor, and the selection transistor constituting the control section can be the same as those of a conventional floating diffusion layer, amplification transistor, reset transistor, and selection transistor, respectively. The drive circuit can also have a well-known configuration and structure.

[0316] The first electrode is connected to the gate portion of the floating diffusion layer and the amplification transistor, and to connect the first electrode to the gate portion of the floating diffusion layer and the amplification transistor, it is only necessary to form a contact hole portion. Examples of the material constituting the contact hole portion include: polysilicon doped with impurities; high-melting-point metals or metal silicides, such as tungsten, Ti, Pt, Pd, Cu, TiW, TiN, TiNW, WSi2, or MoSi2, etc.; and a stacked structure (e.g., Ti / TiN / W) including several layers of the above materials.

[0317] A first carrier blocking layer can be provided between the inorganic oxide semiconductor material layer and the first electrode, and a second carrier blocking layer can be provided between the organic photoelectric conversion layer and the second electrode. Furthermore, a first charge injection layer can be provided between the first carrier blocking layer and the first electrode, and a second charge injection layer can be provided between the second carrier blocking layer and the second electrode. Examples of the material constituting the electron injection layer include: alkali metals such as lithium (Li), sodium (Na), and potassium (K); fluorides of alkali metals; oxides of alkali metals; alkaline earth metals such as magnesium (Mg) or calcium (Ca); fluorides of alkaline earth metals; and oxides of alkaline earth metals.

[0318] Examples of the film formation method of the various organic layers include dry film formation methods and wet film formation methods. Examples of the dry film formation methods include vacuum vapor deposition methods using resistance heating, high-frequency heating, or electron beam heating; flash deposition methods; plasma vapor deposition methods; EB vapor deposition methods; various sputtering methods (bipolar sputtering methods, direct current sputtering methods, direct current magnetron sputtering methods, high-frequency sputtering methods, magnetron sputtering methods, RF-DC combined bias sputtering methods, ECR sputtering methods, facing target sputtering methods, high-frequency sputtering methods, and ion beam sputtering methods); DC (Direct Current) methods; RF methods; multi-cathode methods; activation reaction methods; electric field vapor deposition methods; various ion plating methods (e.g., high-frequency ion plating methods and reactive ion plating methods); laser ablation methods; molecular beam epitaxy methods; laser transfer methods; and molecular beam epitaxy (MBE) methods. Furthermore, examples of the CVD methods include plasma CVD methods, thermal CVD methods, MOCVD methods, and optical CVD methods. Meanwhile, specific examples of the wet film formation methods include spin coating methods; dipping methods; flow casting methods; micro-contact printing methods; drop casting methods; various printing methods such as screen printing methods, inkjet printing methods, offset printing methods, gravure printing methods, and flexographic printing methods; stamping methods; spray coating methods; and various coating methods such as air knife coating methods, blade coating methods, bar coating methods, knife coater methods, extrusion coating methods, reverse roll coating methods, transfer roll coating methods, gravure coating methods, contact coating methods, flow coating methods, spray coating methods, slit-die coating methods, and calendar coater methods. In the coating methods, examples of the solvent include organic solvents having no polarity or low polarity such as toluene, chloroform, hexane, or ethanol. Examples of the patterning method include chemical etching such as a shadow mask, laser transfer, or photolithography; and physical etching using ultraviolet rays, laser light, or the like. Examples of the technology for planarizing the various organic layers include laser planarization methods, reflow methods, and the like.

[0319] As described above, the image pickup element or the solid-state image pickup device can include an on-chip microlens or a light-blocking layer, and if necessary, can further include a drive circuit or a wiring for driving the image pickup element. If necessary, a shutter for controlling the incidence of light onto the image pickup element can be provided, or an optical cut filter can be provided depending on the purpose of the solid-state image pickup device.

[0320] Furthermore, the solid-state image pickup device of the first configuration and the second configuration can each have a configuration in which one on-chip microlens is provided above one image pickup element of the present application or a configuration in which an image pickup element block is composed of two image pickup elements of the present application and one on-chip microlens is provided above the image pickup element block.

[0321] For example, in the case of stacking a solid-state imaging device and a readout integrated circuit (ROIC), by stacking a drive substrate in which a readout integrated circuit and a connection portion including copper (Cu) are formed and an imaging element in which a connection portion is formed so that the connection portions thereof contact each other, the connection portions can be joined to each other, and the connection portions can be joined to each other using solder bumps or the like.

[0322] Further, the driving method for driving the solid-state imaging device of the first and second aspects of the present application can be a solid-state imaging device driving method that repeats the steps of simultaneously, in all the imaging elements, accumulating electric charges in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer) while discharging electric charges in the first electrode to the outside of the system, then, simultaneously, in all the imaging elements, transferring electric charges accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer) to the first electrode, and after the transfer is completed, sequentially reading out electric charges transferred to the first electrode in each of the imaging elements.

[0323] In such a solid-state imaging device driving method, each of the imaging elements has a structure in which light incident from the second electrode side does not incident on the first electrode, and simultaneously, in all the imaging elements, electric charges are accumulated in the inorganic oxide semiconductor material layer or the like while electric charges in the first electrode are discharged to the outside of the system. Thus, the first electrode can be reliably reset in all the imaging elements at the same time. Further, subsequently, electric charges accumulated in the inorganic oxide semiconductor material layer or the like are simultaneously transferred to the first electrode in all the imaging elements, and after the transfer is completed, electric charges transferred to the first electrode are sequentially read out in each of the imaging elements. Thus, a so-called global shutter function can be easily implemented.

[0324] Hereinafter, the imaging element and the solid-state imaging device of Embodiment 1 will be described in detail.

[0325] The imaging element 10 of Embodiment 1 or the like further includes a semiconductor substrate (more specifically, a silicon semiconductor layer) 70, and a photoelectric conversion portion is provided above the semiconductor substrate 70. Further, the imaging element 10 of Embodiment 1 or the like further includes a control portion provided on the semiconductor substrate 70 and having a drive circuit connected to the first electrode 21 and the second electrode 22. Here, the light incident surface of the semiconductor substrate 70 is defined as the upper side, and the opposite side of the semiconductor substrate 70 is defined as the lower side. A wiring layer 62 including a plurality of wirings is provided below the semiconductor substrate 70.

[0326] The semiconductor substrate 70 includes at least a floating diffusion layer FD1 and an amplification transistor TR1 ampand the first electrode 21 is connected to a floating diffusion layer FD1 and an amplification transistor TR1 amp The semiconductor substrate 70 further includes a reset transistor TR1 rst and a selection transistor TR1 SEL for constituting a control section. The floating diffusion layer FD1 is connected to one source / drain region of the reset transistor TR1 rst The other source / drain region of the amplification transistor TR1 amp is connected to one source / drain region of the selection transistor TR1 sel The other source / drain region of the selection transistor TR1 sel is connected to a signal line VSL1. These amplification transistor TR1 amp , reset transistor TR1 rst and selection transistor TR1 sel constitute a drive circuit.

[0327] Specifically, the imaging device of Embodiment 1, the stacked type imaging device, is a back-illuminated imaging device, the stacked type imaging device, and has a structure formed by stacking three imaging devices, which are: a green light imaging device of Embodiment 1 of the first type (hereinafter referred to as "first imaging device") including a first type green light photoelectric conversion layer that absorbs green light and is sensitive to green light; a blue light imaging device of the second type (hereinafter referred to as "second imaging device") that is a conventional one including a second type blue light photoelectric conversion layer that absorbs blue light and is sensitive to blue light; and a red light imaging device of the second type (hereinafter referred to as "third imaging device") that is a conventional one including a second type red light photoelectric conversion layer that absorbs red light and is sensitive to red light. Here, the red light imaging device (third imaging device) 12 and the blue light imaging device (second imaging device) 11 are disposed in the semiconductor substrate 70, and the second imaging device 11 is closer to the light incident side than the third imaging device 12. Further, the green light imaging device (first imaging device 10) is disposed above the blue light imaging device (second imaging device 11). One pixel is constituted by the stacked structure of the first imaging device 10, the second imaging device 11, and the third imaging device 12. A color filter layer is not disposed.

[0328] In the first imaging device 10, the first electrode 21 and the charge accumulation electrode 24 are formed on the interlayer insulating layer 81 separately from each other. The interlayer insulating layer 81 and the charge accumulation electrode 24 are covered with the insulating layer 82. The inorganic oxide semiconductor material layer 23B and the photoelectric conversion layer 23A are formed on the insulating layer 82, and the second electrode 22 is formed on the photoelectric conversion layer 23A. The protective material layer 83 is formed on the entire surface including the second electrode 22, and the on-chip microlens 14 is provided on the protective material layer 83. The color filter layer is not provided. The first electrode 21, the charge accumulation electrode 24, and the second electrode 22 are each composed of a transparent electrode containing, for example, ITO (work function: about 4.4 eV). The inorganic oxide semiconductor material layer 23B is composed of In a Sn b Ti c Zn d O e . The photoelectric conversion layer 23A is composed of a layer containing a known organic photoelectric conversion material (for example, an organic material such as a rhodamine dye, a merocyanine dye, and a quinacridone) that is sensitive to at least green light. The interlayer insulating layer 81, the insulating layer 82, and the protective material layer 83 each contain a known insulating material (for example, SiO2or SiN). The inorganic oxide semiconductor material layer 23B and the first electrode 21 are connected by a connection portion 67 provided in the insulating layer 82. The inorganic oxide semiconductor material layer 23B extends into the connection portion 67. That is, the inorganic oxide semiconductor material layer 23B extends within an opening portion 85 provided in the insulating layer 82 and is connected to the first electrode 21.

[0329] The charge accumulation electrode 24 is connected to the drive circuit. Specifically, the charge accumulation electrode 24 is connected to the vertical drive circuit 112 that constitutes the drive circuit via a connection hole 66 formed in the interlayer insulating layer 81, a pad portion 64, and a wiring V OA that constitutes the drive circuit.

[0330] The size of the charge accumulation electrode 24 is larger than that of the first electrode 21. When the area of the charge accumulation electrode 24 is represented by S1' and the area of the first electrode 21 is represented by S1, although not limited thereto, it is preferable that 4 ≤ S1' / S1 be satisfied. In Embodiment 1, for example, although not limited thereto, it can be set that S1' / S1 = 8.

[0331] The element separation region 71 is formed on the first surface (front surface) 70A side of the semiconductor substrate 70. Further, the oxide film 72 is formed on the first surface 70A of the semiconductor substrate 70. Further, on the first surface side of the semiconductor substrate 70, the reset transistor TR1 rst , the amplification transistor TR1 amp , and the selection transistor TR1 seland also provided with a first floating diffusion layer FD1.

[0332] Reset transistor TR1 rst includes a gate portion 51, a channel formation region 51A, and source / drain regions 51B and 51C. The reset transistor TR1 rst The gate portion 51 of the reset transistor TR1 rst One of the source / drain regions 51C of the reset transistor TR1 rst The other source / drain region 51B of the reset transistor TR1 DD .

[0333] The first electrode 21 is connected to one of the source / drain regions 51C (the first floating diffusion layer FD1) of the reset transistor TR1 rst via a connection hole 65 and a pad portion 63 formed in an interlayer insulating layer 81, via a contact hole portion 61 formed in a semiconductor substrate 70 and an interlayer insulating layer 76, and via a wiring layer 62 formed in the interlayer insulating layer 76.

[0334] Amplification transistor TR1 amp includes a gate portion 52, a channel formation region 52A, and source / drain regions 52B and 52C. The gate portion 52 is connected to the first electrode 21 and one of the source / drain regions 51C (the first floating diffusion layer FD1) of the reset transistor TR1 rst via the wiring layer 62. Further, one of the source / drain regions 52B of the amplification transistor TR1 amp is connected to a power supply V DD .

[0335] Selection transistor TR1 sel includes a gate portion 53, a channel formation region 53A, and source / drain regions 53B and 53C. The gate portion 53 is connected to a selection line SEL1. Further, one of the source / drain regions 53B of the selection transistor TR1 sel shares an area with the other source / drain region 52C of the amplification transistor TR1 amp , and the other source / drain region 53C of the selection transistor TR1 sel is connected to a signal line (data output line) VSL1 (117).

[0336] The second imaging device 11 includes an n-type semiconductor region 41 provided in the semiconductor substrate 70 as a photoelectric conversion layer. A gate portion 45 of a transfer transistor TR2 trs constituted of a vertical transistor extends up to the n-type semiconductor region 41 and is connected to a transfer gate line TG2. Further, a second floating diffusion layer FD2 is provided in the semiconductor substrate 70 at the transfer transistor TR2trs The charge accumulated in the n-type semiconductor region 41 is read out to the second floating diffusion layer FD2 via a transfer channel formed along the gate portion 45.

[0337] In the second imaging device 11, on the first surface side of the semiconductor substrate 70, a reset transistor TR2 rst , an amplification transistor TR2 amp , and a selection transistor TR2 sel are also arranged, which constitute a control portion of the second imaging device 11.

[0338] The reset transistor TR2 rst includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the reset transistor TR2 rst is connected to a reset line RST2. One of the source / drain regions of the reset transistor TR2 rst is connected to a power supply VDD, and the other source / drain region also serves as a second floating diffusion layer FD2.

[0339] The amplification transistor TR2 amp includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the amplification transistor TR2 amp is connected to the other source / drain region (the second floating diffusion layer FD2) of the reset transistor TR2 rst . Further, one of the source / drain regions of the amplification transistor TR2 amp is connected to a power supply V DD .

[0340] The selection transistor TR2 sel includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the selection transistor TR2 sel is connected to a selection line SEL2. Further, one of the source / drain regions of the selection transistor TR2 sel shares an area with the other source / drain region constituting the amplification transistor TR2 amp , and the other source / drain region of the selection transistor TR2 sel is connected to a signal line (a data output line) VSL2.

[0341] The third imaging device 12 includes an n-type semiconductor region 43 as a photoelectric conversion layer provided in a semiconductor substrate 70. A gate portion 46 of a transfer transistor TR3 trs is connected to a transfer gate line TG3. Further, a third floating diffusion layer FD3 is provided in the semiconductor substrate 70 at the other source / drain region of the transfer transistor TR3 trsThe charge accumulated in the n-type semiconductor region 43 is read out to the third floating diffusion layer FD3 through a transfer channel 46A formed along the gate portion 46.

[0342] In the third imaging device 12, on the first surface side of the semiconductor substrate 70, a reset transistor TR3 rst , an amplification transistor TR3 amp , and a selection transistor TR3 sel that constitute a control portion of the third imaging device 12 are further provided.

[0343] The reset transistor TR3 rst includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the reset transistor TR3 rst is connected to a reset line RST3. One of the source / drain regions of the reset transistor TR3 rst is connected to a power supply V DD , and the other source / drain region of the reset transistor TR3 rst also functions as the third floating diffusion layer FD3.

[0344] The amplification transistor TR3 amp includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the amplification transistor TR3 amp is connected to the other source / drain region (the third floating diffusion layer FD3) of the reset transistor TR3 rst . Further, one of the source / drain regions of the amplification transistor TR3 amp is connected to a power supply V DD .

[0345] The selection transistor TR3 sel includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the selection transistor TR3 sel is connected to a selection line SEL3. Further, one of the source / drain regions of the selection transistor TR3 sel shares a region with the other source / drain region that constitutes the amplification transistor TR3 amp , and the other source / drain region of the selection transistor TR3 sel is connected to a signal line (a data output line) VSL3.

[0346] The reset lines RST1, RST2, and RST3, the selection lines SEL1, SEL2, and SEL3, and the transfer gate lines TG2 and TG3 are connected to a vertical drive circuit 112 that constitutes a drive circuit, and the signal lines (data output lines) VSL1, VSL2, and VSL3 are connected to a column signal processing circuit 113 that constitutes the drive circuit.

[0347] p +The layer 44 is provided between the n-type semiconductor region 43 and the front surface 70A of the semiconductor substrate 70, so as to suppress generation of dark current. + The layer 42 is formed between the n-type semiconductor region 41 and the n-type semiconductor region 43, and in addition, a part of the side surface of the n-type semiconductor region 43 is surrounded by the layer 42. + The layer 42 is formed between the n-type semiconductor region 41 and the n-type semiconductor region 43, and in addition, a part of the side surface of the n-type semiconductor region 43 is surrounded by the layer 42. + The layer 73 is formed on the back surface 70B side of the semiconductor substrate 70. The HfO2 film 74 and the insulating material film 75 are formed so as to extend from the layer 73 to a portion inside the semiconductor substrate 70 where the contact hole portion 61 is to be formed. In the interlayer insulating layer 76, a wiring is formed in a plurality of layers, but is not illustrated. + The layer 73 is formed on the back surface 70B side of the semiconductor substrate 70. The HfO2 film 74 and the insulating material film 75 are formed so as to extend from the layer 73 to a portion inside the semiconductor substrate 70 where the contact hole portion 61 is to be formed. In the interlayer insulating layer 76, a wiring is formed in a plurality of layers, but is not illustrated.

[0348] The HfO2 film 74 is a film having a negative fixed charge. By forming such a film, it is possible to suppress generation of dark current. Instead of the HfO2 film, it is also possible to use a film of an aluminum oxide (Al2O3) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, a titanium oxide (TiO2) film, a lanthanum oxide (La2O3) film, a praseodymium oxide (Pr2O3) film, a cerium oxide (CeO2) film, a neodymium oxide (Nd2O3) film, a promethium oxide (Pm2O3) film, a samarium oxide (Sm2O3) film, an europium oxide (Eu2O3) film, a gadolinium oxide (Gd2O3) film, a terbium oxide (Tb2O3) film, a dysprosium oxide (Dy2O3) film, a holmium oxide (Ho2O3) film, a thulium oxide (Tm2O3) film, a ytterbium oxide (Yb2O3) film, a lutetium oxide (Lu2O3) film, a yttrium oxide (Y2O3) film, a hafnium nitride film, an aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film. Examples of the film formation method of these films include a CVD method, a PVD method, and an ALD method.

[0349] Hereinafter, the operation of the stacked type imaging device (first imaging device 10) including the charge accumulation electrode of Embodiment 1 will be described with reference to Figure 5 and Figure 6A The imaging device of Embodiment 1 further includes a control section provided on the semiconductor substrate 70 and having a drive circuit. The first electrode 21, the second electrode 22, and the charge accumulation electrode 24 are connected to the drive circuit. Here, the potential of the first electrode 21 is set to be higher than the potential of the second electrode 22. That is, for example, the first electrode 21 is set to a positive potential, and the second electrode 22 is set to a negative potential. Electrons generated by photoelectric conversion in the photoelectric conversion layer 23A are read out to the floating diffusion layer. This similarly applies to the other embodiments.

[0350] In Figure 5 , the Figure 20 and Figure 21 in Embodiment 4 described later, and the Figure 32 and Figure 33The reference numerals used in the drawings are as follows.

[0351] P A : potential at point P of region of inorganic oxide semiconductor material layer 23B facing region between charge accumulation electrode 24 and first electrode 21 or between transfer control electrode (charge transport electrode) 25 and first electrode 21 A : potential at point P of region of inorganic oxide semiconductor material layer 23B facing region between charge accumulation electrode 24 and first electrode 21 or between transfer control electrode (charge transport electrode) 25 and first electrode 21

[0352] P B : potential at point P of region of inorganic oxide semiconductor material layer 23B facing charge accumulation electrode 24 B : potential at point P of region of inorganic oxide semiconductor material layer 23B facing charge accumulation electrode 24

[0353] P C1 : potential at point P of region of inorganic oxide semiconductor material layer 23B facing charge accumulation electrode section 24A C1 : potential at point P of region of inorganic oxide semiconductor material layer 23B facing charge accumulation electrode section 24A

[0354] P C2 : potential at point P of region of inorganic oxide semiconductor material layer 23B facing charge accumulation electrode section 24B C2 : potential at point P of region of inorganic oxide semiconductor material layer 23B facing charge accumulation electrode section 24B

[0355] P C3 : potential at point P of region of inorganic oxide semiconductor material layer 23B facing charge accumulation electrode section 24C C3 : potential at point P of region of inorganic oxide semiconductor material layer 23B facing charge accumulation electrode section 24C

[0356] P D : potential at point P of region of inorganic oxide semiconductor material layer 23B facing transfer control electrode (charge transport electrode) 25 D : potential at point P of region of inorganic oxide semiconductor material layer 23B facing transfer control electrode (charge transport electrode) 25

[0357] FD: potential at first floating diffusion layer FD1

[0358] V OA : potential at charge accumulation electrode 24

[0359] V OA-A : potential at charge accumulation electrode section 24A

[0360] V OA-B : potential at charge accumulation electrode section 24B

[0361] V OA-C : potential at charge accumulation electrode section 24C

[0362] V OT : potential at transfer control electrode (charge transport electrode) 25

[0363] RST: reset transistor TR1 rstthe potential at the gate portion 51 of the transistor 50

[0364] V DD : the potential of the power supply

[0365] VSL1: signal line (data output line) VSL1

[0366] TR1 rst : reset transistor TR1 rst

[0367] TR1 amp : amplification transistor TR1 amp

[0368] TR1 sel : selection transistor TR1 sel

[0369] In the charge accumulation period, the potential V 11 is applied from the drive circuit to the first electrode 21, and the potential V 31 is applied to the charge accumulation electrode 24. By light incident on the photoelectric conversion layer 23A, photoelectric conversion occurs in the photoelectric conversion layer 23A. Holes generated by the photoelectric conversion are transferred from the second electrode 22 to the drive circuit through the wiring V OU . On the other hand, since the potential of the first electrode 21 is set to be higher than the potential of the second electrode 22, i.e., for example, since a positive potential is applied to the first electrode 21 and a negative potential is applied to the second electrode 22, V 31 ≥ V 11 is satisfied, and preferably V 31 > V 11 is satisfied. As a result, electrons generated by the photoelectric conversion are attracted to the charge accumulation electrode 24, and the electrons stay in the region of the inorganic oxide semiconductor material layer 23B (or the inorganic oxide semiconductor material layer 23B and the photoelectric conversion layer 23A) (hereinafter, they will be collectively referred to as "inorganic oxide semiconductor material layer 23B and the like") facing the charge accumulation electrode 24. That is, charges are accumulated in the inorganic oxide semiconductor material layer 23B and the like. Since V 31 > V 11 is satisfied, the electrons generated inside the photoelectric conversion layer 23A do not move to the first electrode 21. With the progress of the photoelectric conversion, the potential in the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode 24 becomes a more negative value.

[0370] In the later stage of the charge accumulation period, a reset operation is performed. As a result, the potential of the first floating diffusion layer FD1 is reset, and the potential of the first floating diffusion layer FD1 becomes the potential V DD of the power supply.

[0371] After the reset operation is completed, the charge is read out. That is, during the charge transfer period, the potential V 12 is applied to the first electrode 21, and the potential V 32 is applied to the charge accumulation electrode 24. Here, V 32 < V 12 . As a result, the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B or the like facing the charge accumulation electrode 24 are read out to the first electrode 21, and further read out to the first floating diffusion layer FD1. That is, the charge accumulated in the inorganic oxide semiconductor material layer 23B or the like is read out to the control section.

[0372] In this way, a series of operations including charge accumulation, a reset operation, and charge transfer is completed.

[0373] After the electrons are read out to the first floating diffusion layer FD1, the amplification transistor TR1 amp and the selection transistor TR1 sel operate in the same manner as the conventional transistors. Furthermore, a series of operations including charge accumulation, a reset operation, and charge transfer of the second imaging device 11 and the third imaging device 12 is the same as the conventional series of operations including charge accumulation, a reset operation, and charge transfer. Furthermore, the reset noise of the first floating diffusion layer FD1 can be removed by a correlated double sampling (CDS) process as in the related art.

[0374] As described above, in Embodiment 1, since the charge accumulation electrode is arranged separately from the first electrode and faces the photoelectric conversion layer with the insulating layer interposed therebetween, when the photoelectric conversion layer is irradiated with light and the light is photoelectrically converted in the photoelectric conversion layer, the inorganic oxide semiconductor material layer or the like forms a kind of capacitor with the insulating layer and the charge accumulation electrode, and the charge can be accumulated in the inorganic oxide semiconductor material layer or the like. Therefore, at the start of exposure, the charge storage section can be completely depleted and the charge can be eliminated. As a result, it is possible to suppress the occurrence of phenomena such as an increase in kTC noise, random noise deterioration, and a decrease in the quality of the captured image. Furthermore, since it is possible to reset all the pixels at the same time, it is possible to realize a so-called global shutter function.

[0375] Figure 68A conceptual diagram of the solid-state imaging device of Embodiment 1 is shown. The solid-state imaging device 100 of Embodiment 1 includes an imaging region 111 in which the stacked imaging elements 101 are arranged in a two-dimensional array, a vertical drive circuit 112 that is a drive circuit (peripheral circuit) of the stacked imaging elements 101, a column signal processing circuit 113, a horizontal drive circuit 114, an output circuit 115, a drive control circuit 116, and the like. Needless to say, the above-described circuits can be configured by well-known circuits, and of course, the above-described circuits can be configured using other circuit configurations (for example, various circuits used in a conventional CCD imaging device or CMOS imaging device). In Figure 68 In the drawing, only the reference numeral "101" of the stacked imaging element 101 is shown in one row.

[0376] The drive control circuit 116 generates a clock signal or a control signal as a reference for the operation of the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114, based on a vertical synchronization signal, a horizontal synchronization signal, and a main clock. Further, the generated clock signal or control signal is input to the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114.

[0377] For example, the vertical drive circuit 112 includes a shift register, and the vertical drive circuit 112 sequentially selects and scans the stacked imaging elements 101 in the imaging region 111 in units of rows in the vertical direction. Further, a pixel signal (image signal) based on a current (signal) generated in correspondence with the amount of light received by each stacked imaging element 101 is transferred to the column signal processing circuit 113 through a signal line (data output line) 117 (VSL).

[0378] For example, the column signal processing circuit 113 is arranged corresponding to each column of the stacked imaging elements 101. Using a signal from a black reference pixel (although not shown, it is formed around the effective pixel region), the image signal output from one row of the stacked imaging elements 101 is subjected to signal processing such as noise removal or signal amplification for each imaging element. In the output stage of the column signal processing circuit 113, a horizontal selection switch (not shown) is connected and provided between the column signal processing circuit 113 and a horizontal signal line 118.

[0379] For example, the horizontal drive circuit 114 includes a shift register. By sequentially outputting a horizontal scanning pulse, the horizontal drive circuit 114 sequentially selects each column signal processing circuit 113 and outputs a signal from each column signal processing circuit 113 to the horizontal signal line 118.

[0380] The output circuit 115 performs signal processing on a signal sequentially supplied from each column signal processing circuit 113 via the horizontal signal line 118, and then outputs the signal.

[0381] Figure 9 An equivalent circuit diagram of a variation of the stacked image pickup element of Embodiment 1 is shown, Figure 10 A schematic layout of the first electrode, the charge accumulation electrode, and a transistor for constituting the control section is shown. As shown in the figure, the reset transistor TR1 rst The other source / drain region 51B can be grounded instead of connecting the other source / drain region 51B to the power supply V DD .

[0382] For example, the image pickup element, the stacked image pickup element of Embodiment 1 can be manufactured by the following method. That is, first, an SOI substrate is prepared. Then, a first silicon layer is formed on the surface of the SOI substrate based on an epitaxial growth method, and a p + layer 73 and an n-type semiconductor region 41 are formed on the first silicon layer. Subsequently, a second silicon layer is formed on the first silicon layer based on an epitaxial growth method, and an element separation region 71, an oxide film 72, a p + layer 42, an n-type semiconductor region 43, and a p + layer 44 are formed on the second silicon layer. Further, various transistors and the like constituting the control section of the image pickup element are formed on the second silicon layer, and further, a wiring layer 62, an interlayer insulating layer 76, and various wirings are formed thereon. Then, the interlayer insulating layer 76 and a support substrate (not shown) are attached together. Subsequently, the SOI substrate is removed to expose the first silicon layer. The surface of the second silicon layer corresponds to the front surface 70A of the semiconductor substrate 70, and the surface of the first silicon layer corresponds to the back surface 70B of the semiconductor substrate 70. Further, the first silicon layer and the second silicon layer are collectively denoted as the semiconductor substrate 70. Subsequently, an opening portion for forming the contact hole portion 61 is formed on the back surface 70B side of the semiconductor substrate 70, and an HfO2 film 74, an insulating material film 75, and the contact hole portion 61 are formed. Further, a pad portion 63 and 64, an interlayer insulating layer 81, connection holes 65 and 66, the first electrode 21, the charge accumulation electrode 24, and an insulating layer 82 are also formed. Next, a connection portion 67 is opened, and further, an inorganic oxide semiconductor material layer 23B, a photoelectric conversion layer 23A, a second electrode 22, a protective material layer 83, and an on-chip microlens 14 are formed. As a result, the image pickup element, the stacked image pickup element of Embodiment 1 can be obtained.

[0383] Further, although not illustrated, the insulating layer 82 can have a two-layered structure including an insulating layer_lower layer and an insulating layer_upper layer. That is, it is only necessary to form the insulating layer_lower layer at least on the charge accumulation electrode 24 and in a region between the charge accumulation electrode 24 and the first electrode 21 (more specifically, it is only necessary to form the insulating layer_lower layer on the interlayer insulating layer 81 including the charge accumulation electrode 24), then perform a planarization process on the insulating layer_lower layer, and then form the insulating layer_upper layer on the insulating layer_lower layer and the charge accumulation electrode 24. As a result, it is possible to reliably planarize the insulating layer 82. Then, it is only necessary to form the opening portion of the connection portion 67 in the insulating layer 82 thus obtained.

[0384] [Embodiment 2]

[0385] Embodiment 2 is a modification of Embodiment 1. Figure 11 The imaging device, the stacked-type imaging device of Embodiment 2 shown in the schematic partial cross-sectional view is a front-illuminated imaging device, a stacked-type imaging device, and has a structure formed by stacking three imaging devices, which are: a green light imaging device (first imaging device 10) of the first type of Embodiment 1 including a first-type green light photoelectric conversion layer for absorbing green light and being sensitive to green light; a second-type conventional blue light imaging device (second imaging device 11) including a second-type blue light photoelectric conversion layer for absorbing blue light and being sensitive to blue light; and a second-type conventional red light imaging device (third imaging device 12) including a second-type red light photoelectric conversion layer for absorbing red light and being sensitive to red light. Here, the red light imaging device (third imaging device 12) and the blue light imaging device (second imaging device 11) are provided in the semiconductor substrate 70, and the second imaging device 11 is closer to the light incident side than the third imaging device 12. Further, the green light imaging device (first imaging device 10) is provided above the blue light imaging device (second imaging device 11).

[0386] As in Embodiment 1, various transistors for constituting a control portion are provided on the front surface 70A side of the semiconductor substrate 70. These transistors can adopt substantially the same configuration and structure as the transistors described in Embodiment 1. Further, the semiconductor substrate 70 includes the second imaging device 11 and the third imaging device 12, and these imaging devices can adopt substantially the same configuration and structure as the second imaging device 11 and the third imaging device 12 described in Embodiment 1.

[0387] The interlayer insulating layer 81 is formed above the front surface 70A of the semiconductor substrate 70. Above the interlayer insulating layer 81, the first electrode 21, the inorganic oxide semiconductor material layer 23B, the photoelectric conversion layer 23A, the second electrode 22, the charge accumulation electrode 24, and the like are provided as in the imaging device of Embodiment 1.

[0388] In this way, the configuration and structure of the imaging element, the stacked-type imaging element of Embodiment 2 can be made the same as those of the imaging element, the stacked-type imaging element of Embodiment 1 except that the imaging element, the stacked-type imaging element of Embodiment 2 is front-illuminative. Therefore, detailed description thereof is omitted.

[0389] [Embodiment 3]

[0390] Embodiment 3 is a modification of Embodiments 1 and 2.

[0391] Figure 12 The imaging element, the stacked-type imaging element of Embodiment 3 shown in the schematic partial cross-sectional view is a back-illuminative imaging element, a stacked-type imaging element, and has a structure formed by stacking the two imaging elements of the first imaging element 10 of the first type of Embodiment 1 and the third imaging element 12 of the second type. Further, Figure 13 A modification of the imaging element, the stacked-type imaging element of Embodiment 3 shown in the schematic partial cross-sectional view is a front-illuminative imaging element, a stacked-type imaging element, and has a structure formed by stacking the two imaging elements of the first imaging element 10 of the first type of Embodiment 1 and the third imaging element 12 of the second type. Here, the first imaging element 10 absorbs primary color light, and the third imaging element 12 absorbs complementary color light. Alternatively, the first imaging element 10 absorbs white light, and the third imaging element 12 absorbs infrared light.

[0392] Figure 14 A modification of the imaging element of Embodiment 3 shown in the schematic partial cross-sectional view is a back-illuminative imaging element, and is composed of the first imaging element 10 of the first type of Embodiment 1. Further, Figure 15 A modification of the imaging element of Embodiment 3 shown in the schematic partial cross-sectional view is a front-illuminative imaging element, and is composed of the first imaging element 10 of the first type of Embodiment 1. Here, the first imaging element 10 is composed of three kinds of imaging elements for absorbing red light, imaging elements for absorbing green light, and imaging elements for absorbing blue light. Further, the solid-state imaging device of the first aspect of the present application is composed of a plurality of the above-described imaging elements. As the arrangement of the plurality of imaging elements, a Bayer array can be cited. On the light-incident side of each imaging element, a color filter layer for performing spectral separation of blue, green, and red colors can be provided as needed.

[0393] Instead of providing one imaging element of the first type of Embodiment 1, a configuration in which two imaging elements are provided in a stacked manner (i.e., a configuration in which two photoelectric conversion sections are stacked, and control sections of the two photoelectric conversion sections are provided in a semiconductor substrate) can be employed, or a configuration in which three imaging elements are provided in a stacked manner (i.e., a configuration in which three photoelectric conversion sections are stacked, and control sections of the three photoelectric conversion sections are provided in a semiconductor substrate) can be employed. In the following table, examples of the stacked configuration of the first type of imaging element and the second type of imaging element are shown.

[0394]

[0395] [Embodiment 4]

[0396] Embodiment 4 is a modification of Embodiments 1 to 3, and relates to an imaging element including a transfer control electrode (charge transfer electrode) and the like according to the present application. Figure 16 A schematic partial cross-sectional view of a part of the imaging element, the stacked type imaging element of Embodiment 4 is shown. Figure 17 and Figure 18 An equivalent circuit diagram of the imaging element, the stacked type imaging element of Embodiment 4 is shown. Figure 19 A schematic layout view of the first electrode, the transfer control electrode, and the charge accumulation electrode that constitute the imaging element of Embodiment 4, and a transistor that constitutes the control section is shown. Figure 20 and Figure 21 A potential state of each section during the operation of the imaging element of Embodiment 4 is schematically shown. Figure 6B An equivalent circuit diagram for explaining each section of the imaging element of Embodiment 4 is shown. Further, Figure 22 A schematic layout view of the first electrode, the transfer control electrode, and the charge accumulation electrode that constitute the photoelectric conversion section of the imaging element of Embodiment 4 is shown. Figure 23 A schematic perspective view of the first electrode, the transfer control electrode, the charge accumulation electrode, the second electrode, and the contact hole section is shown.

[0397] The imaging element, the stacked type imaging element of Embodiment 4 further includes a transfer control electrode (charge transfer electrode) 25 that is disposed between the first electrode 21 and the charge accumulation electrode 24, is arranged separately from the first electrode 21 and the charge accumulation electrode 24, and faces the inorganic oxide semiconductor material layer 23B through the insulating layer 82. The transfer control electrode 25 is connected to the first electrode 21 and the charge accumulation electrode 24 through the connection hole 68B, the pad section 68A, and the wiring V OT to a pixel drive circuit that constitutes a drive circuit. Note that, in Figure 16 , Figure 25 ,Figure 28 , Figure 37 , Figure 43 , Figure 46A , Figure 46B , Figure 47A , Figure 47B , Figure 66 and Figure 67 In

[0398] Hereinafter, the operation of the imaging device (first imaging device 10) of Embodiment 4 will be described with reference to Figure 20 and Figure 21 Note that, for Figure 20 and Figure 21 , in particular, the potential value applied to the charge accumulation electrode 24 and the potential value at the point P D are different.

[0399] In the charge accumulation period, the potential V 11 is applied to the first electrode 21, the potential V 31 is applied to the charge accumulation electrode 24, and the potential V 51 is applied to the transfer control electrode 25 from the drive circuit. Photoelectric conversion occurs in the photoelectric conversion layer 23A by light incident on the photoelectric conversion layer 23A. Holes generated by the photoelectric conversion are transferred from the second electrode 22 to the drive circuit through the wiring V OU In addition, the potential of the first electrode 21 is set to be higher than the potential of the second electrode 22, that is, for example, a positive potential is applied to the first electrode 21, and a negative potential is applied to the second electrode 22. Thus, V 31 > V 51 (for example, V 31 > V 11 > V 51 or V 11 > V 31 > V 51 ) is satisfied. As a result, the electrons generated by the photoelectric conversion are attracted to the charge accumulation electrode 24, and the electrons stay in the region of the inorganic oxide semiconductor material layer 23B or the like facing the charge accumulation electrode 24. That is, the charge is accumulated in the inorganic oxide semiconductor material layer 23B or the like. Since V 31 > V 51 is satisfied, the electrons generated inside the photoelectric conversion layer 23A can be reliably prevented from moving to the first electrode 21. The potential in the region of the inorganic oxide semiconductor material layer 23B or the like facing the charge accumulation electrode 24 becomes a more negative value as the photoelectric conversion is performed.

[0400] During the later stage of charge accumulation, a reset operation is performed. As a result, the potential of the first floating diffusion layer FD1 is reset, and the potential of the first floating diffusion layer FD1 becomes the potential V of the power supply. DD .

[0401] After the reset operation is completed, the charge is read out. That is, during the charge transfer period, the potential V is transferred from the drive circuit. 12 Applying a potential V to the first electrode 21 32 Apply to charge accumulation electrode 24 and set potential V 52 It is applied to the transmission control electrode 25. Here, V is satisfied. 32 ≤V 52 ≤V 12 (Preferably, V) 32 <V 52 <V 12 As a result, electrons remaining in the region of the inorganic oxide semiconductor material layer 23B, etc., facing the charge accumulation electrode 24, are reliably read out to the first electrode 21, and further read out to the first floating diffusion layer FD1. That is, the charge accumulated in the inorganic oxide semiconductor material layer 23B, etc., is read out to the control unit.

[0402] In this way, a series of operations, including charge accumulation, reset operation and charge transfer, are completed.

[0403] After electrons are read out into the first floating diffusion layer FD1, the amplifying transistor TR1 amp and select transistor TR1 sel The operation is the same as that of conventional transistors. Furthermore, for example, the series of operations including charge accumulation, reset operation, and charge transfer of the second imaging element 11 and the third imaging element 12 are the same as those of conventional transistors including charge accumulation, reset operation, and charge transfer.

[0404] Figure 24 A schematic layout diagram of the first electrode and charge accumulation electrode constituting a modified example of the imaging element of Embodiment 4, and the transistor constituting the control unit is shown. As shown, the reset transistor TR1 rst The other source / drain region 51B can be grounded, instead of connecting the other source / drain region 51B to the power supply V. DD .

[0405] [Example 5]

[0406] Example 5 is a variation of Examples 1 to 4, and Example 5 relates to the imaging element including a charge discharge electrode of the present invention. Figure 25 A schematic partial cross-sectional view of a portion of the imaging element of Embodiment 5 is shown. Figure 26A schematic layout view of the first electrode, the charge accumulation electrode, and the charge discharge electrode of the photoelectric conversion section including the charge accumulation electrode that constitutes the imaging device of Embodiment 5 is shown. Figure 27 A schematic perspective view of the first electrode, the charge accumulation electrode, the charge discharge electrode, the second electrode, and the contact hole section is shown.

[0407] The imaging device of Embodiment 5 further includes the charge discharge electrode 26 that is connected to the inorganic oxide semiconductor material layer 23B through the connection section 69, and that is disposed separately from the first electrode 21 and the charge accumulation electrode 24. Here, the charge discharge electrode 26 is disposed so as to surround the first electrode 21 and the charge accumulation electrode 24 (i.e., in a frame shape). The charge discharge electrode 26 is connected to the pixel drive circuit that constitutes the drive circuit. The inorganic oxide semiconductor material layer 23B extends into the connection section 69. That is, the inorganic oxide semiconductor material layer 23B extends within the second opening section 86 formed in the insulating layer 82, thereby being connected to the charge discharge electrode 26. The charge discharge electrode 26 is shared by a plurality of imaging devices. The side surface of the second opening section 86 can be inclined in a manner that widens the second opening section 86 upward. The charge discharge electrode 26 can function as, for example, a floating diffusion or an overflow drain of the photoelectric conversion section.

[0408] In Embodiment 5, during the charge accumulation period, a potential V 11 is applied to the first electrode 21, a potential V 31 is applied to the charge accumulation electrode 24, and a potential V 61 is applied to the charge discharge electrode 26, and charges are accumulated in the inorganic oxide semiconductor material layer 23B or the like. Photoelectric conversion occurs in the photoelectric conversion layer 23A by light incident on the photoelectric conversion layer 23A. Holes generated by the photoelectric conversion are transferred from the second electrode 22 to the drive circuit through the wiring V OU . At the same time, the potential of the first electrode 21 is set to be higher than the potential of the second electrode 22, i.e., for example, a positive potential is applied to the first electrode 21, and a negative potential is applied to the second electrode 22. Thus, V 61 > V 11 is satisfied (for example, V 31 > V 61 > V 11). As a result, the electrons generated by the photoelectric conversion are attracted to the charge accumulation electrode 24, and the electrons stay in the region of the inorganic oxide semiconductor material layer 23B or the like facing the charge accumulation electrode 24. This can reliably prevent the electrons from moving toward the first electrode 21. However, the electrons that are not sufficiently attracted to the charge accumulation electrode 24 or the electrons that do not completely accumulate in the inorganic oxide semiconductor material layer 23B or the like (so-called overflow electrons) are transferred to the drive circuit via the charge discharge electrode 26.

[0409] In the latter part of the charge accumulation period, a reset operation is performed. As a result, the potential of the first floating diffusion layer FD1 is reset, and the potential of the first floating diffusion layer FD1 becomes the potential VDD of the power supply DD .

[0410] After the reset operation is completed, the charge is read out. That is, in the charge transfer period, the potential VDD is applied to the first electrode 21 from the drive circuit, the potential V 12 is applied to the charge accumulation electrode 24, and the potential V 32 is applied to the charge discharge electrode 26. Here, V 62 < V 62 < V 12 (For example, V 62 < V 32 < V 12 ). As a result, the electrons staying in the region of the inorganic oxide semiconductor material layer 23B or the like facing the charge accumulation electrode 24 are reliably read out to the first electrode 21, and further read out to the first floating diffusion layer FD1. That is, the charge accumulated in the inorganic oxide semiconductor material layer 23B or the like is read out to the control section.

[0411] In this way, a series of operations including charge accumulation, a reset operation, and charge transfer is completed.

[0412] After the electrons are read out to the first floating diffusion layer FD1, the amplification transistor TR1 amp and the selection transistor TR1 sel operate in the same way as the conventional operation of these transistors. Furthermore, for example, a series of operations including charge accumulation, a reset operation, and charge transfer of the second and third imaging devices are the same as the conventional series of operations including charge accumulation, a reset operation, and charge transfer.

[0413] In Embodiment 5, the so-called overflow electrons are transferred to the drive circuit via the charge discharge electrode 26. Therefore, it is possible to suppress the leakage to the charge accumulation section of the adjacent pixel, and it is possible to suppress the occurrence of blooming. In addition, this also makes it possible to improve the imaging performance of the imaging device.

[0414] [Embodiment 6]

[0415] Embodiment 6 is a modification of Embodiments 1 to 5, and relates to an imaging device or the like including a plurality of charge accumulation electrode sections according to the present application.

[0416] Figure 28 A schematic partial cross-sectional view of a portion of the imaging device of Embodiment 6 is shown. Figure 29 and Figure 30 A circuit diagram of the imaging device of Embodiment 6 is shown. Figure 31 A schematic layout view of the first electrode and the charge accumulation electrode of the photoelectric conversion section including the charge accumulation electrode that constitutes the imaging device of Embodiment 6, and a transistor that constitutes the control section are shown. Figure 32 and Figure 33 A potential state of each section during operation of the imaging device of Embodiment 6 is schematically shown. Figure 6C A circuit diagram for explaining each section of the imaging device of Embodiment 6 is shown. Further, Figure 34 A schematic layout view of the first electrode and the charge accumulation electrode of the photoelectric conversion section including the charge accumulation electrode that constitutes the imaging device of Embodiment 6 is shown. Figure 35 A schematic perspective view of the first electrode, the charge accumulation electrode, the second electrode, and the contact hole section is shown.

[0417] In Embodiment 6, the charge accumulation electrode 24 includes a plurality of charge accumulation electrode sections 24A, 24B, and 24C. The number of charge accumulation electrode sections only needs to be two or more, and in Embodiment 6, the number is set to “3”. In addition, in the imaging device of Embodiment 6, the potential of the first electrode 21 is higher than the potential of the second electrode 22. Thus, for example, a positive potential is applied to the first electrode 21, and a negative potential is applied to the second electrode 22. In addition, during the charge transfer period, the potential applied to the charge accumulation electrode section 24A located closest to the first electrode 21 is higher than the potential applied to the charge accumulation electrode section 24C located farthest from the first electrode 21. In this way, by imparting a potential gradient to the charge accumulation electrode 24, the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B or the like facing the charge accumulation electrode 24 are more reliably read out to the first electrode 21 and further read out to the first floating diffusion layer FD1. That is, the charge accumulated in the inorganic oxide semiconductor material layer 23B or the like is read out to the control section.

[0418] In Figure 32In the example shown, during the charge transfer period, since the potential of the charge accumulation electrode section 24C < the potential of the charge accumulation electrode section 24B < the potential of the charge accumulation electrode section 24A is satisfied, the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B and the like are simultaneously read out to the first floating diffusion layer FD1. At the same time, in the example shown, during the charge transfer period, by making the potential of the charge accumulation electrode section 24C, the potential of the charge accumulation electrode section 24B, and the potential of the charge accumulation electrode section 24A change step by step (i.e., by making the potential of the charge accumulation electrode section 24C, the potential of the charge accumulation electrode section 24B, and the potential of the charge accumulation electrode section 24A change in a stepped or ramped manner), the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24C are moved to the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24B. Subsequently, the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24B are moved to the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24A. Subsequently, the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24A are reliably read out to the first floating diffusion layer FD1. Figure 33 In the example shown, during the charge transfer period, by making the potential of the charge accumulation electrode section 24C, the potential of the charge accumulation electrode section 24B, and the potential of the charge accumulation electrode section 24A change step by step (i.e., by making the potential of the charge accumulation electrode section 24C, the potential of the charge accumulation electrode section 24B, and the potential of the charge accumulation electrode section 24A change in a stepped or ramped manner), the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24C are moved to the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24B. Subsequently, the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24B are moved to the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24A. Subsequently, the electrons that have stayed in the region of the inorganic oxide semiconductor material layer 23B and the like facing the charge accumulation electrode section 24A are reliably read out to the first floating diffusion layer FD1.

[0419] Figure 36 A schematic layout view of the first electrode and the charge accumulation electrode and the transistors constituting the control section of the imaging device of the modification example of Embodiment 6 is shown. As shown, the reset transistor TR1 rst The other source / drain region 51B can be grounded instead of being connected to the power source V DD .

[0420] [Embodiment 7]

[0421] Embodiment 7 is a modification example of Embodiments 1 to 6, and relates to an imaging device and the like having a charge moving control electrode of the present application, and specifically, to an imaging device and the like having a lower charge moving control electrode (lower side charge moving control electrode) of the present application. Figure 37 A schematic partial cross-sectional view of a portion of the imaging device of Embodiment 7 is shown, Figure 38 A schematic layout view of the first electrode and the charge accumulation electrode and the like and the transistors constituting the control section of the imaging device of Embodiment 7 is shown, Figure 39 and Figure 40 A schematic layout view of the first electrode, the charge accumulation electrode, and the lower charge moving control electrode of the photoelectric conversion section having the charge accumulation electrode of the imaging device of Embodiment 7 is shown.

[0422] In the imaging device of Embodiment 7, the lower charge movement control electrode 27 is formed in a region (a region-A of the photoelectric conversion layer) of the photoelectric conversion layered body 23 that is positioned between the imaging devices adjacent to each other A The lower charge movement control electrode 27 is formed in a region (a region-A of the photoelectric conversion layer) of the photoelectric conversion layered body 23 that is positioned between the imaging devices adjacent to each other A The lower charge movement control electrode 27 is formed in a region (a region-A of the photoelectric conversion layer) of the photoelectric conversion layered body 23 that is positioned between the imaging devices adjacent to each other A The lower charge movement control electrode 27 is formed in a region (a region-A of the photoelectric conversion layer) of the photoelectric conversion layered body 23 that is positioned between the imaging devices adjacent to each other OB The lower charge movement control electrode 27 is formed in a region (a region-A of the photoelectric conversion layer) of the photoelectric conversion layered body 23 that is positioned between the imaging devices adjacent to each other

[0423] In the imaging device of Embodiment 7, when light is incident on the photoelectric conversion layer 23A and photoelectric conversion is performed in the photoelectric conversion layer 23A, the charges generated by the photoelectric conversion are more strongly directed to the portion of the inorganic oxide semiconductor material layer 23B facing the charge accumulation electrode 24, because the absolute value of the potential applied to the portion of the photoelectric conversion layer 23A facing the charge accumulation electrode 24 is larger than the absolute value of the potential applied to the region-A of the photoelectric conversion layer 23A. As a result, the flow of the charges generated by the photoelectric conversion to the adjacent imaging device can be suppressed, and thus the quality of the captured image (picture) does not deteriorate. Alternatively, because the lower charge movement control electrode 27 is formed in the region of the insulating layer opposite to the region-A of the photoelectric conversion layer 23A, the electric field or the potential of the region-A of the photoelectric conversion layer 23A above the lower charge movement control electrode 27 can be controlled. As a result, the flow of the charges generated by the photoelectric conversion to the adjacent imaging device can be suppressed by the lower charge movement control electrode 27, and thus the quality of the captured image (picture) does not deteriorate.

[0424] In Figure 39 and Figure 40 the example shown, the lower charge movement control electrode 27 is formed below the portion 82 A of the insulating layer 82 in the region (region-a) sandwiched by the charge accumulation electrodes 24. On the other hand, in Figure 41 , Figure 42A , Figure 42B the example shown, the lower charge movement control electrode 27 is formed below the portion of the insulating layer 82 in the region surrounded by the four charge accumulation electrodes 24. Also, Figure 41 , Figure 42A , Figure 42B the example shown is the solid-state imaging device of the first configuration and the second configuration. Also, in the four imaging devices, one common first electrode 21 is provided corresponding to the four charge accumulation electrodes 24.

[0425] In Figure 42B the example shown, in the four imaging devices, one common first electrode 21 is provided corresponding to the four charge accumulation electrodes 24, the lower charge movement control electrode 27 is formed below the portion of the insulating layer 82 in the region surrounded by the four charge accumulation electrodes 24, and further, the charge discharge electrode 26 is formed below the portion of the insulating layer 82 in the region surrounded by the four charge accumulation electrodes 24. As described above, the charge discharge electrode 26 can function as, for example, a floating diffusion or an overflow drain of the photoelectric conversion section.

[0426] [Embodiment 8]

[0427] Example 8 is a variation of Example 7, relating to an imaging element of the present invention having an upper charge movement control electrode (upper side - charge movement control electrode). Figure 43 A schematic cross-sectional view of a portion of the imaging elements (two imaging elements arranged side by side) of Embodiment 8 is shown. Figure 44 and Figure 45 A schematic plan view of the imaging element (2×2 imaging elements arranged side by side) of Embodiment 8 and a portion thereof is shown. In the imaging element of Embodiment 8, in region 23 of the photoelectric conversion laminate 23 located between adjacent imaging elements... A An upper charge movement control electrode 28 is formed instead of a second electrode 22. The upper charge movement control electrode 28 is disposed separately from the second electrode 22. In other words, a second electrode 22 is provided for each imaging element, and an upper charge movement control electrode 28 is disposed on region A of the photoelectric conversion stack 23 in a manner that surrounds at least a portion of the second electrode 22 and is separate from the second electrode 22. The upper charge movement control electrode 28 and the second electrode 22 are formed on the same horizontal plane.

[0428] Moreover, in Figure 44 In the example shown, in one imaging element, a charge accumulation electrode 24 is provided corresponding to a first electrode 21. On the other hand, in Figure 45 In the variant shown, a common first electrode 21 is provided in both imaging elements, corresponding to the two charge accumulation electrodes 24. Figure 43 A schematic cross-sectional view of a portion of the imaging element (two imaging elements arranged side by side) in Embodiment 8 shown corresponds to Figure 45 .

[0429] and, Figure 46A A schematic cross-sectional view of a portion of a modified example of the imaging element (two imaging elements arranged side by side) of Embodiment 8 is shown. As shown, the second electrode 22 can be divided into multiple parts, and different potentials can be applied to each of the divided second electrodes 22. Furthermore, as... Figure 46B As shown, an upper charge movement control electrode 28 can be provided between the divided second electrode 22 and the second electrode 22.

[0430] In embodiment 8, the second electrode 22 located on the light incident side is along... Figure 44 The imaging elements arranged horizontally on the paper share common features, and along the... Figure 44 The image is shared by a pair of imaging elements arranged vertically on the paper. Furthermore, the upper charge movement control electrode 28 is also along... Figure 44 The imaging elements arranged horizontally on the paper share common features, and along the... Figure 44In the pair of imaging elements arranged in the up-and-down direction on the paper, the second electrode 22 and the upper charge movement control electrode 28 are shared. The second electrode 22 and the upper charge movement control electrode 28 can be obtained by forming a material layer for constituting the second electrode 22 and the upper charge movement control electrode 28 on the photoelectric conversion layer stack 23, and then patterning the material layer. The second electrode 22 and the upper charge movement control electrode 28 are respectively connected to wirings (not shown) connected to a drive circuit. The wiring connected to the second electrode 22 is shared among a plurality of solid-state imaging elements. The wiring connected to the upper charge movement control electrode 28 is also shared among a plurality of imaging elements.

[0431] In the imaging element of Embodiment 8, during the charge accumulation period, a potential V 21 is applied to the second electrode 22 from the drive circuit, and a potential V 41 is applied to the upper charge movement control electrode 28, and the charge is accumulated in the photoelectric conversion layer stack 23, during the charge transfer period, a potential V 22 is applied to the second electrode 22 from the drive circuit, and a potential V 42 is applied to the upper charge movement control electrode 28, and the charge accumulated in the photoelectric conversion layer stack 23 is read out to the control section via the first electrode 21. Here, since the potential of the first electrode 21 is set to be higher than the potential of the second electrode 22, V 21 ≥ V 41 and V 22 ≥ V 42 .

[0432] As described above, in the imaging element of Embodiment 8, since the charge movement control electrode is formed instead of the second electrode on the region of the photoelectric conversion layer between the adjacent imaging elements, the inflow of the charge generated by the photoelectric conversion to the adjacent imaging element is suppressed by the charge movement control electrode, and thus the quality degradation of the captured image (picture) does not occur.

[0433] Figure 47A A schematic cross-sectional view of a part of a modification example of the imaging element (2 imaging elements arranged side by side) of Embodiment 8 is shown, Figure 48A and Figure 48B A schematic plan view of a part is shown. In this modification example, the second electrode 22 is provided for each imaging element, the upper charge movement control electrode 28 is provided in a manner of surrounding at least a part of the second electrode 22 and being separated from the second electrode 22, and a part of the charge accumulation electrode 24 exists below the upper charge movement control electrode 28. The second electrode 22 is provided above the charge accumulation electrode 24, and the size of the second electrode 22 is smaller than that of the charge accumulation electrode 24.

[0434] Figure 47BA schematic cross-sectional view of a part of a modification example of the image pickup element (two image pickup elements arranged side by side) of Embodiment 8 is shown, Figure 49A and Figure 49B A schematic plan view of a part is shown. In this modification example, the second electrode 22 is provided for each image pickup element, the upper charge movement control electrode 28 is provided in a manner of surrounding at least a part of the second electrode 22 and being separated from the second electrode 22, there is a part of the charge accumulation electrode 24 below the upper charge movement control electrode 28, and the lower charge movement control electrode (lower_charge_movement_control_electrode) 27 is provided below the upper charge movement control electrode (upper_charge_movement_control_electrode) 28. The size of the second electrode 22 is smaller than that of the modification example shown in Figure 47A . That is, the region of the second electrode 22 facing the upper charge movement control electrode 28 is located at a position closer to the first electrode 21 side than the region of the second electrode 22 facing the upper charge movement control electrode 28 in the modification example shown in Figure 47A . The charge accumulation electrode 24 is surrounded by the lower charge movement control electrode 27.

[0435] [Embodiment 9]

[0436] Embodiment 9 relates to a solid-state imaging device of the first configuration and the second configuration.

[0437] The solid-state imaging device of Embodiment 9 includes a plurality of image pickup elements each including a photoelectric conversion section formed by laminating a first electrode 21, an inorganic oxide semiconductor material layer 23B, a photoelectric conversion layer 23A, and a second electrode 22. The photoelectric conversion section further includes a charge accumulation electrode 24 arranged separately from the first electrode 21 and arranged opposite to the inorganic oxide semiconductor material layer 23B with an insulating layer 82 interposed. The plurality of image pickup elements constitute an image pickup element block. The first electrode 21 is shared by the plurality of image pickup elements constituting the image pickup element block.

[0438] Alternatively, the solid-state imaging device of Embodiment 9 includes a plurality of image pickup elements as described in Embodiments 1 to 8.

[0439] In Embodiment 9, one floating diffusion layer is provided for the plurality of image pickup elements. In addition, by appropriately controlling the timing during charge transfer, the plurality of image pickup elements can share one floating diffusion layer. In addition, in this case, the plurality of image pickup elements can share one contact hole section.

[0440] Note that the solid-state imaging device of Embodiment 9 has substantially the same configuration and structure as the solid-state imaging device described in Embodiments 1 to 8 except for the point that the first electrode 21 is shared by the plurality of image pickup elements constituting the image pickup element block.

[0441] Figure 50 (Example 9), Figure 51 (First modification of Example 9), Figure 52 (Second modification of Example 9), Figure 53 (Third modification of Example 9), Figure 54 (Fourth modification of Example 9), and Figure 55 (Fifth modification of Example 9) schematically show the arrangement state of the first electrode 21 and the charge accumulation electrode 24 in the solid-state imaging device of Example 9. Figure 50 , Figure 51 , Figure 54 and Figure 55 show 16 imaging elements, and Figure 52 and Figure 53 respectively show 12 imaging elements. In addition, an imaging element block is constituted by two imaging elements. The region surrounded by the broken line indicates the imaging element block. The subscripted numbers attached to the first electrode 21 and the charge accumulation electrode 24 are shown for distinguishing the first electrode 21 and the charge accumulation electrode 24, respectively. This is equally applied to the following description. Furthermore, one on-chip microlens (not shown in Figure 50 to 57 ) is arranged above one imaging element. In addition, in one imaging element block, two charge accumulation electrodes 24 are arranged so that the first electrode 21 is interposed between the two charge accumulation electrodes 24 (see Figure 50 and Figure 51 ). Alternatively, one first electrode 21 is arranged so as to face two charge accumulation electrodes 24 arranged side by side (see Figure 54 and Figure 55 ). That is, the first electrode is arranged so as to abut on the charge accumulation electrodes of each of the imaging elements. Alternatively, the first electrode is arranged so as to abut on the charge accumulation electrodes of some of the plurality of imaging elements and not to abut on the charge accumulation electrodes of the remaining imaging elements among the plurality of imaging elements (see Figure 52 and Figure 53 ). In this case, the transfer of the charge from the above-mentioned remaining imaging elements among the plurality of imaging elements to the first electrode is transferred via the above-mentioned some of the plurality of imaging elements. In order to ensure the transfer of the charge from each of the imaging elements to the first electrode, preferably, the distance A between the charge accumulation electrode constituting the imaging element and the charge accumulation electrode constituting the imaging element is longer than the distance B between the first electrode and the charge accumulation electrode in the imaging element abutting on the first electrode. Furthermore, preferably, the farther the position of the imaging element from the first electrode, the larger the value of the distance A is set to be. Furthermore, in Figure 51 , Figure 53 and Figure 55In the illustrated example, the charge movement control electrode 27 is provided between a plurality of imaging elements constituting an imaging element block. By providing the charge movement control electrode 27, it is possible to reliably suppress the transfer of charges in the imaging element block at a position sandwiching the charge movement control electrode 27. Note that when the potential applied to the charge movement control electrode 27 is referred to as V 17 , it is only necessary to satisfy V 31 > V 17 .

[0442] The charge movement control electrode 27 can be formed on the same level as the first electrode 21 or the charge accumulation electrode 24, or can be formed on a different level (specifically, on a level below the first electrode 21 or the charge accumulation electrode 24) from the first electrode 21 or the charge accumulation electrode 24. In the former case, since it is possible to shorten the distance between the charge movement control electrode 27 and the photoelectric conversion layer, it is easy to control the potential. On the other hand, in the latter case, since it is possible to shorten the distance between the charge movement control electrode 27 and the charge accumulation electrode 24, it is advantageous for miniaturization.

[0443] Hereinafter, the operation of an imaging element block constituted by the first electrode 212 and two charge accumulation electrodes 24 21 and 24 22 will be described.

[0444] During the charge accumulation period, a potential V 11 is applied to the first electrode 212 from the drive circuit, and potentials V 31 are applied to the charge accumulation electrodes 24 21 and 24 22 . By light incident on the photoelectric conversion layer 23A, photoelectric conversion occurs in the photoelectric conversion layer 23A. Holes generated by the photoelectric conversion are transported from the second electrode 22 to the drive circuit through the wiring V OU . On the other hand, the potential V 11 of the first electrode 212 is set to be higher than the potential V 21 of the second electrode 22, i.e., for example, a positive potential is applied to the first electrode 212, and a negative potential is applied to the second electrode 22. Therefore, V 31 ≥ V 11 is satisfied, and preferably V 31 > V 11 . As a result, electrons generated by the photoelectric conversion are attracted to the charge accumulation electrodes 24 21 and 24 22 , and the electrons stay at the inorganic oxide semiconductor material layer 23B or the like facing the charge accumulation electrodes 24 21 and 24 22In the region, that is, charge accumulates in the inorganic oxide semiconductor material layer 23B, etc. Because V satisfies... 31 ≥V 11 Therefore, electrons generated inside the photoelectric conversion layer 23A do not move toward the first electrode 212. As photoelectric conversion proceeds, the inorganic oxide semiconductor material layer 23B, etc., faces the charge accumulation electrode 24. 21 and 24 22 The potential in the region becomes more negative.

[0445] During the later stage of charge accumulation, a reset operation is performed. As a result, the potential of the first floating diffusion layer is reset, and the potential of the first floating diffusion layer becomes the potential V of the power supply. DD .

[0446] After the reset operation is completed, the charge is read out. That is, during the charge transfer period, the potential V is transferred from the drive circuit. 21 Applying a potential V to the first electrode 212 32-A Applied to charge accumulation electrode 24 21 and the potential V 32-B Applied to charge accumulation electrode 24 22 Here, V is satisfied. 32-A <V 21 <V 32-B As a result, the inorganic oxide semiconductor material layer 23B, etc., faces the charge accumulation electrode 24. 21 Electrons in the region are read out to the first electrode 212, and further read out to the first floating diffusion layer. That is, electrons accumulated on the inorganic oxide semiconductor material layer 23B, etc., facing the charge accumulation electrode 24. 21 The charge in the region is read out to the control unit. When the reading is complete, it is set to satisfy V. 32-B ≤V 32-A <V 21 Note that in Figure 54 and Figure 55 In the example shown, it can also be set to satisfy V 32-B <V 21 <V 32-A As a result, the inorganic oxide semiconductor material layer 23B, etc., faces the charge accumulation electrode 24. 22 Electrons in the region are read out to the first electrode 212, and further read out to the first floating diffusion layer. Furthermore, in Figure 52 and Figure 53 In the example shown, the surface of the inorganic oxide semiconductor material layer 23B, etc., faces the charge accumulation electrode 24. 22 Electrons in the region can pass through the charge accumulation electrode 24 22The first electrode 213 adjacent to the first floating diffusion layer is read out. In this way, the charge accumulated in the region of the inorganic-oxide semiconductor material layer 23B or the like facing the charge accumulation electrode 24 22 is read out to the control section. Note that when the charge accumulated in the region of the inorganic-oxide semiconductor material layer 23B or the like facing the charge accumulation electrode 24 21 is read to the control section, the potential of the first floating diffusion layer can be reset.

[0447] Figure 58A An example of readout driving in the imaging element block of Embodiment 9 is shown.

[0448] [Step-A] Input of automatic zeroing signal to comparator

[0449] [Step-B] Reset operation of one common floating diffusion layer

[0450] [Step-C] P-phase readout in the imaging element corresponding to the charge accumulation electrode 24 21 and charge transfer to the first electrode 212

[0451] [Step-D] D-phase readout in the imaging element corresponding to the charge accumulation electrode 24 21 and charge transfer to the first electrode 212

[0452] [Step-E] Reset operation of one common floating diffusion layer

[0453] [Step-F] Input of automatic zeroing signal to comparator

[0454] [Step-G] P-phase readout in the imaging element corresponding to the charge accumulation electrode 24 22 and charge transfer to the first electrode 212

[0455] [Step-H] D-phase readout in the imaging element corresponding to the charge accumulation electrode 24 22 and charge transfer to the first electrode 212

[0456] Through the above procedure, signals from two imaging elements corresponding to the charge accumulation electrode 24 21 and the charge accumulation electrode 24 22 are read out. Based on correlated double sampling (CDS) processing, the difference between the P-phase readout in [Step-C] and the D-phase readout in [Step-D] is the signal from the imaging element corresponding to the charge accumulation electrode 24 21 , and the difference between the P-phase readout in [Step-G] and the D-phase readout in [Step-H] is the signal from the imaging element corresponding to the charge accumulation electrode 24 22 .

[0457] Note that the operation of [Step-E] can be omitted (see Figure 58B ). Furthermore, the operation of [Step-F] can be omitted. In this case, the operation of [Step-G] can be further omitted (see Figure 58C ). The difference between the P-phase readout in [Step-C] and the D-phase readout in [Step-D] is a signal from the charge accumulation electrode 24 21 corresponding to the imaging device, and the difference between the D-phase readout in [Step-D] and the D-phase readout in [Step-H] is a signal from the charge accumulation electrode 24 22 corresponding to the imaging device.

[0458] In the modified examples of the arrangement state of the first electrode 21 and the charge accumulation electrode 24 shown in Figure 56 (6th modified example of Embodiment 9) and Figure 57 (7th modified example of Embodiment 9), the imaging device block includes four imaging devices. The operations of these solid-state imaging apparatuses can be substantially similar to the operation of the solid-state imaging apparatus shown in Figure 50 to 55 .

[0459] In the solid-state imaging apparatus of Embodiment 9, since the first electrode is shared by the plurality of imaging devices constituting the imaging device block, it is possible to simplify and miniaturize the configuration and structure in the pixel region in which the plurality of imaging devices are arranged. Note that the plurality of imaging devices provided for one floating diffusion layer can be constituted by a plurality of first-type imaging devices, or can be constituted by at least one first-type imaging device and one or more than two second-type imaging devices.

[0460] [Embodiment 10]

[0461] Embodiment 10 is a modified example of Embodiment 9. In the solid-state imaging apparatus of Embodiment 10 shown in Figure 59 , Figure 60 , Figure 61 and Figure 62 , the imaging device block includes two imaging devices. In addition, one on-chip microlens 14 is provided above the imaging device block. Note that in the examples shown in Figure 60 and Figure 62 , the charge movement control electrode 27 is provided between the plurality of imaging devices constituting the imaging device block.

[0462] For example, the charge accumulation electrodes 24 11 , 24 21 , 24 31 and 24 41The corresponding photoelectric conversion layer is highly sensitive to light incident from the upper right of the image. Furthermore, it is related to the charge accumulation electrode 24 that constitutes the imaging element block. 12 ,twenty four 22 ,twenty four 32 and 24 42 The corresponding photoelectric conversion layer is highly sensitive to light incident from the upper left of the figure. Therefore, for example, by including charge accumulation electrode 24 11 The camera element and including charge accumulation electrodes 24 12 The camera element combination can acquire the image plane phase difference signal. Furthermore, if the signal from the charge accumulation electrode 24 is... 11 Signals from the camera element and from sources including charge accumulation electrodes 24 12 The signals from the various camera elements are added together, and a combination of these camera elements can be used to form a single camera element. Figure 59 In the example shown, the first electrode 211 is disposed on the charge accumulation electrode 24. 11 With charge accumulation electrode 24 12 Between. However, as Figure 61 As shown in the example, a first electrode 211 is positioned facing two charge accumulation electrodes 24 arranged side by side. 11 and 24 12 This can further enhance sensitivity.

[0463] The present invention has now been described based on preferred embodiments. However, the present invention is not limited to these embodiments. The structures or configurations, manufacturing conditions, manufacturing methods, and materials used for the imaging elements, stacked imaging elements, and solid-state imaging devices described in the embodiments are illustrative and can be appropriately modified. The imaging elements of the various embodiments can be appropriately combined. The construction and structure of the imaging elements of the present invention can be applied to light-emitting elements (e.g., organic EL elements) or to the channel formation region of thin-film transistors.

[0464] In some cases, it is also possible to share floating diffusion layers FD1, FD2, FD3, 51C, 45C and 46C.

[0465] In addition, for example, Figure 63 A modified example of the imaging element and the stacked imaging element described in Embodiment 1 is shown. As shown in the figure, it can be constructed in a manner in which light is incident from the second electrode 22 side, and a light-shielding layer 15 is formed on the light-incident side of the second electrode 22. Note that the various wirings disposed on the light-incident side of the photoelectric conversion layer can function as a light-shielding layer.

[0466] Note that in Figure 63In the example shown, the light-shielding layer 15 is formed above the second electrode 22, i.e., the light-shielding layer 15 is formed on the light incident side of the second electrode 22 and above the first electrode 21. However, as Figure 64 shown, the light-shielding layer 15 can also be provided on the light incident side surface of the second electrode 22. Further, as Figure 65 shown, in some cases, the light-shielding layer 15 can be formed in the second electrode 22.

[0467] Alternatively, a structure can be employed in which light is incident from the second electrode 22 side, and light does not incident on the first electrode 21. Specifically, as Figure 63 shown, the light-shielding layer 15 is formed on the light incident side of the second electrode 22 and above the first electrode 21. Alternatively, as Figure 67 shown, a structure can be employed in which the on-chip microlens 14 is provided above the charge accumulation electrode 24 and the second electrode 22, and light incident on the on-chip microlens 14 is gathered to the charge accumulation electrode 24 and does not reach the first electrode 21. Note that, as explained in Embodiment 4, in the case where the transfer control electrode 25 is provided, a structure can be employed in which light does not incident on the first electrode 21 and the transfer control electrode 25. Specifically, as Figure 66 shown, a structure can be employed in which the light-shielding layer 15 is formed above the first electrode 21 and the transfer control electrode 25. Alternatively, a structure can be employed in which light incident on the on-chip microlens 14 does not reach the first electrode 21, or does not reach the first electrode 21 and the transfer control electrode 25.

[0468] By employing those configurations and structures described above, or alternatively, by providing the light-shielding layer 15 so that light is incident only on the portion of the photoelectric conversion section located above the charge accumulation electrode 24, or alternatively, by designing the on-chip microlens 14 so that the portion of the photoelectric conversion layer located above the first electrode 21 (or above the first electrode 21 and the transfer control electrode 25) does not contribute to photoelectric conversion, thereby, it is possible to more reliably reset all the pixels at the same time, and it is possible to more easily realize a global shutter function. That is, in a driving method of a solid-state imaging device including a plurality of imaging elements having the above configurations and structures, the following steps are repeated: in all the imaging elements, simultaneously, while accumulating electric charges in the inorganic oxide semiconductor material layer 23B or the like, discharging the electric charges in the first electrode 21 to the outside of the system; then, in all the imaging elements, simultaneously, transferring the electric charges accumulated in the inorganic oxide semiconductor material layer 23B or the like to the first electrode 21, and after the transfer is completed, sequentially reading out the electric charges transferred to the first electrode 21 in each imaging element.

[0469] In the driving method of the aforementioned solid-state imaging device, each imaging element has the following structure: light incident from the second electrode side does not incident on the first electrode, and in all imaging elements, charge is simultaneously accumulated in the inorganic oxide semiconductor material layer, while the charge in the first electrode is discharged to the outside of the system. Therefore, the first electrode can be reliably reset simultaneously in all imaging elements. Furthermore, subsequently, the charge accumulated in the inorganic oxide semiconductor material layer, etc., in all imaging elements is simultaneously transferred to the first electrode, and after the transfer is completed, the charge transferred to the first electrode is sequentially read out in each imaging element. Therefore, a so-called global shutter function can be easily implemented.

[0470] In the case where a single inorganic oxide semiconductor material layer 23B is formed in multiple imaging elements, from the viewpoint of protecting the ends of the inorganic oxide semiconductor material layer 23B, it is preferable that the ends of the inorganic oxide semiconductor material layer 23B are covered by at least the photoelectric conversion layer 23A. In this case, the structure of the imaging element only needs to be such that its schematic cross-sectional view is formed by... Figure 1 The structure shown is located at the right end of the inorganic oxide semiconductor material layer 23B.

[0471] Furthermore, in a variation of Example 4, such as Figure 67 As shown, multiple transmission control electrodes can be arranged from the position closest to the first electrode 21 toward the charge accumulation electrode 24. Note that... Figure 67 An example with two transmission control electrodes 25A and 25B is shown. Alternatively, a structure can be adopted in which an on-chip microlens 14 is positioned above the charge accumulation electrode 24 and the second electrode 22, and light incident on the on-chip microlens 14 is focused onto the charge accumulation electrode 24 and does not reach the first electrode 21 or the transmission control electrodes 25A and 25B.

[0472] Alternatively, it can be configured as follows: wherein the first electrode 21 extends within the opening 85 disposed in the insulating layer 82 and is connected to the inorganic oxide semiconductor material layer 23B.

[0473] In the embodiments, the application has been described as an example of application to a CMOS type solid-state imaging device in which unit pixels that detect signal charges corresponding to the amount of incident light as physical quantities are arranged in a matrix. However, the application is not limited to application to a CMOS type solid-state imaging device, and the application can also be applied to a CCD type solid-state imaging device. In the latter case, a vertical transfer register having a CCD type structure transfers signal charges in the vertical direction, a horizontal transfer register transfers signal charges in the horizontal direction, and the signal charges are amplified, whereby a pixel signal (image signal) is output. Further, the application is not limited to a general column type solid-state imaging device in which pixels are formed in a two-dimensional matrix and a column signal processing circuit is provided for each pixel column. Further, in some cases, a selection transistor can be omitted.

[0474] Further, the imaging element and the stacked imaging element of the application are not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and images the distribution as an image, but the imaging element and the stacked imaging element of the application can also be applied to a solid-state imaging device for imaging the distribution of the amount of incident light of infrared light, X-rays, or particles, etc. as an image. Further, the imaging element and the stacked imaging element of the application can be applied to, in a broad sense, a solid-state imaging device (physical quantity distribution detecting device) such as a fingerprint detection sensor, etc. that detects the distribution of other physical quantities (for example, pressure or electrostatic capacitance, etc.) and images the distribution as an image.

[0475] Further, the application is not limited to a solid-state imaging device that sequentially scans each unit pixel in an imaging region in units of rows and reads a pixel signal from each unit pixel. The application can also be applied to an X-Y address type solid-state imaging device that selects an arbitrary pixel in units of pixels and reads a pixel signal in units of pixels from the selected pixel. The solid-state imaging device can be formed as one chip, or can be in the form of a module having an imaging function in which an imaging region is packaged together with a drive circuit or an optical system.

[0476] Further, the application is not limited to application to a solid-state imaging device, but can also be applied to an imaging device. Here, the imaging device refers to a camera system (for example, a digital camera or a video camera), or an electronic device (for example, a mobile phone) having an imaging function. Sometimes, a module form (i.e., a camera module) mounted on an electronic device is used as an imaging device.

[0477] Figure 69The illustration shows an example in which a solid-state imaging device 201, including the imaging element of the present invention and a stacked imaging element, is used in an electronic device (camera) 200. The electronic device 200 includes a solid-state imaging device 201, an optical lens 210, a shutter device 211, a drive circuit 212, and a signal processing circuit 213. The optical lens 210 allows image light (incident light) from the subject to be imaged on the imaging surface of the solid-state imaging device 201. As a result, signal charge accumulates in the solid-state imaging device 201 over a period of time. The shutter device 211 controls the illumination and shading periods of the solid-state imaging device 201. The drive circuit 212 provides a drive signal for controlling the transmission operation of the solid-state imaging device 201 and the shutter operation of the shutter device 211. The solid-state imaging device 201 transmits signals via the drive signal (timing signal) provided from the drive circuit 212. The signal processing circuit 213 performs various signal processing operations. The processed video signal is stored in a storage medium such as a memory or output to a monitor. In such an electronic device 200, the pixel size of the solid-state camera device 201 can be miniaturized, and charge transfer efficiency can be improved; therefore, an electronic device 200 with improved pixel characteristics can be obtained. The electronic device 200 that can apply the solid-state camera device 201 is not limited to cameras, and the solid-state camera device 201 can be applied to camera devices such as digital cameras or camera modules suitable for mobile devices (e.g., mobile phones).

[0478] The technology of this invention (the technology) can be applied to a variety of products. For example, the technology of this invention can be implemented as a device mounted on any type of mobile body, such as: automobiles, electric vehicles, hybrid vehicles, electric motorcycles, bicycles, personal mobility vehicles, airplanes, drones, ships, or robots.

[0479] Figure 74 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology of the present invention can be applied.

[0480] The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. Figure 74 In the example shown, the vehicle control system 12000 includes: a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as part of the functional structure of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0481] The drive system control unit 12010 controls the operations of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device of the drive power generation device such as an internal combustion engine or a drive motor that generates the drive power of the vehicle, the drive power transmission mechanism that transmits the drive power to the wheels, the steering mechanism that adjusts the steering angle of the vehicle, and the brake device that generates the braking force of the vehicle.

[0482] The body system control unit 12020 controls the operations of various devices mounted on the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device of the keyless entry system, the smart key system, the power window device, or various lamps such as the headlamp, the backup lamp, the brake lamp, the turn signal lamp, or the fog lamp. In this case, the radio waves transmitted from the portable device that substitutes for the key or the signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, the power window device, the lamps, and the like of the vehicle.

[0483] The outside information detecting unit 12030 detects the outside information of the vehicle on which the vehicle control system 12000 is mounted. For example, the imaging section 12031 is connected to the outside information detecting unit 12030. The outside information detecting unit 12030 causes the imaging section 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside information detecting unit 12030 can perform an object detection process or a distance detection process on a pedestrian, a vehicle, an obstacle, a traffic sign, or a character on the road surface.

[0484] The imaging section 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of received light. The imaging section 12031 can output the electric signal as an image or can output the electric signal as distance measurement information. Furthermore, the light received by the imaging section 12031 can be visible light or can be non-visible light such as infrared light.

[0485] The inside information detecting unit 12040 detects the information of the inside of the vehicle. For example, the driver state detecting section 12041 that detects the state of the driver is connected to the inside information detecting unit 12040. For example, the driver state detecting section 12041 includes a camera that captures the driver. The inside information detecting unit 12040 can calculate the degree of fatigue or the degree of concentration of the driver or can determine whether the driver is dozing based on the detection information input from the driver state detecting section 12041.

[0486] The microcomputer 12051 is able to calculate a control target value of a driving force generation device, a steering mechanism, or a braking device on the basis of information on the outside and inside of the vehicle acquired by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and is able to output a control command to the drive system control unit 12010. For example, the microcomputer 12051 is able to perform cooperative control aimed at realizing an advanced driver assistance system (ADAS: advanced driver assistance system) function including collision avoidance or impact mitigation of the vehicle, follow-up running based on an inter-vehicle distance, vehicle speed maintenance running, collision warning of the vehicle, and lane departure warning of the vehicle, and the like.

[0487] Further, the microcomputer 12051 is able to control a driving force generation device, a steering mechanism, or a braking device, and the like on the basis of information on the surroundings of the vehicle acquired by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, thereby performing cooperative control aimed at realizing, for example, autonomous driving that is independent of the operation of the driver.

[0488] Further, on the basis of vehicle exterior information acquired by the outside-vehicle information detecting unit 12030, the microcomputer 12051 is able to output a control command to the body system control unit 12020. For example, the microcomputer 12051 is able to control a headlamp in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030, thereby performing coordinated control for the purpose of realizing glare prevention, such as switching a high beam to a low beam, and the like.

[0489] The sound / image output section 12052 transmits at least one of a sound output signal or an image output signal to an output device that is able to visually or aurally notify a passenger on the vehicle or outside the vehicle of information. In Figure 74 Examples of the output device are shown as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 can include at least one of an on-board display and / or a head-up display, for example.

[0490] Figure 75 FIG. 12 is a diagram showing an example of a mounting position of the imaging section 12031.

[0491] In Figure 75 The vehicle 12100 includes imaging sections 12101, 12102, 12103, 12104, and 12105 as the imaging section 12031.

[0492] For example, the imaging sections 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, the side mirrors, the rear bumper or the tailgate, and the upper portion of the front windshield in the vehicle cabin of the vehicle 12100. The imaging section 12101 provided at the front nose and the imaging section 12105 provided at the upper portion of the front windshield in the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging section 12104 provided at the rear bumper or the tailgate mainly acquires images of the rear of the vehicle 12100. The front images acquired by the imaging sections 12101 and 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a signal lamp, a traffic sign, or a lane.

[0493] Note that, Figure 75 Examples of the imaging ranges of the imaging sections 12101 to 12104 are shown. The imaging range 12111 indicates the imaging range of the imaging section 12101 provided at the front nose. The imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging sections 12102 and 12103 provided at the side mirrors, respectively. The imaging range 12114 indicates the imaging range of the imaging section 12104 provided at the rear bumper or the tailgate. For example, by superimposing the image data taken by the imaging sections 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0494] At least one of the imaging sections 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera including a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0495] For example, the microcomputer 12051 calculates the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in the distance over time (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby can extract, as a preceding vehicle, a three-dimensional object that is closest to the vehicle 12100, in particular, on the travel road of the vehicle 12100, and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, greater than or equal to 0 km / h). Further, the microcomputer 12051 can set the inter-vehicle distance to the preceding vehicle to be ensured in advance in the front, and can perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control), and the like. In this way, cooperative control aimed at realizing, for example, autonomous travel independent of the operation of the driver can be performed.

[0496] For example, based on distance information obtained from the imaging sections 12101 to 12104, the microcomputer 12051 classifies three-dimensional object data on a three-dimensional object into a two-wheeled vehicle, a general vehicle, a large vehicle, a pedestrian, and other three-dimensional objects such as a utility pole, and extracts data, and can use the extracted data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can see and obstacles that are difficult to see. Then, the microcomputer 12051 judges a collision risk that indicates a degree of danger of collision with each obstacle. When the collision risk is higher than a set value and there is a possibility of collision, the microcomputer 12051 can output an alarm to the driver through the audio speaker 12061 or the display unit 12062, or perform forced deceleration or avoidance steering by driving the system control unit 12010, to perform a driving assist for avoiding collision.

[0497] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize a pedestrian by judging whether a pedestrian is present in an image captured by the imaging sections 12101 to 12104. For example, such recognition of a pedestrian is performed by extracting feature points in an image captured by the imaging sections 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points representing the outline of an object, and judging whether a pedestrian is present. If the microcomputer 12051 judges that a pedestrian is present in an image captured by the imaging sections 12101 to 12104 and recognizes the pedestrian, the sound image output section 12052 controls the display unit 12062 so that the display unit 12062 displays a rectangular outline line for emphasis superimposed on the recognized pedestrian. In addition, the sound image output section 12052 can control the display unit 12062 so that the display unit 12062 displays an icon or the like indicating a pedestrian at a desired position.

[0498] In addition, for example, the technology of the present application can be applied to an endoscopic surgery system.

[0499] Figure 76 is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technology of the present application (the present technology) can be applied.

[0500] Figure 76A case in which a surgeon (doctor) 11131 performs surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000 is shown. As shown in the figure, the endoscopic surgery system 11000 includes: an endoscope 11100; other surgical tools 11110 such as a pneumoperitoneum tube 11111 or an energy treatment tool 11112; a support arm device 11120 that supports the endoscope 11100; and a cart 11200 on which various devices used for endoscopic surgery are installed.

[0501] The endoscope 11100 includes: a lens barrel 11101 of which a region having a predetermined length from a front end of the lens barrel 11101 is inserted into a body cavity of the patient 11132; and a camera head 11102 connected to a base end of the lens barrel 11101. In the example shown, a so-called rigid scope in which the endoscope 11100 is configured to include a rigid lens barrel 11101 is shown, but the endoscope 11100 can also be configured as a so-called flexible scope including a flexible lens barrel.

[0502] At the front end of the lens barrel 11101, an opening portion on which an objective lens is mounted is provided. A light source device 11203 is connected to the endoscope 11100. Light generated by the light source device 11203 is guided to the front end of the lens barrel 11101 by a light guide extending within the lens barrel 11101, and the light is irradiated to an observation object in the body cavity of the patient 11132 by the objective lens described above. Note that the endoscope 11100 can be a forward-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0503] An optical system and an imaging element are provided inside the camera head 11102. Reflected light (observation light) from the observation object is converged on the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element, and an electric signal corresponding to the observation light, that is, an image signal corresponding to an observation image is generated. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW (raw) data.

[0504] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), and the like, and comprehensively controls the operation of the endoscope 11100 and the display apparatus 11202. Further, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing such as development processing (demosaicing processing) for displaying an image based on the image signal, for example, on the image signal.

[0505] The display apparatus 11202 displays an image based on an image signal on which image processing has been performed by the CCU 11201, under the control of the CCU 11201.

[0506] The light source apparatus 11203 includes a light source such as a light emitting diode (LED), for example, and supplies irradiation light for imaging a surgical site or the like to the endoscope 11100.

[0507] The input apparatus 11204 is an input interface of the endoscope surgery system 11000. The user is able to input various information and instructions to the endoscope surgery system 11000 through the input apparatus 11204. For example, the user inputs an instruction for changing an imaging condition (a type of irradiation light, a magnification, a focal distance, and the like) of the endoscope 11100, or the like.

[0508] The treatment tool control apparatus 11205 controls the driving of the energy treatment tool 11112 for cauterizing or incising tissue, or sealing a blood vessel, or the like. In order to secure a field of view of the endoscope 11100 and a work space of the surgeon, the insufflation apparatus 11206 sends a gas into a body cavity of the patient 11132 through the insufflation tube 11111 to inflate the body cavity of the patient 11132. The recorder 11207 is an apparatus capable of recording various information relating to surgery. The printer 11208 is an apparatus capable of printing various information relating to surgery in various forms such as text, graphics, and charts.

[0509] Note that, for example, the light source device 11203 for supplying irradiation light for imaging a surgical site to the endoscope 11100 can include an LED, a laser light source, or a white light source constituted by a combination of an LED and a laser light source. In the case where a white light source is constituted by a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, and thus adjustment of white balance of an imaged image can be performed by the light source device 11203. Further, in this case, by irradiating an observation object with laser light from each of the R, G, and B laser light sources in a time division manner and controlling the driving of the imaging element of the camera head 11102 in synchronization with the irradiation timing, images corresponding to each of the R, G, and B colors can also be imaged in a time division manner. According to this method, even in the case where no color filter is provided in the imaging element, a color image can be obtained.

[0510] Further, the driving of the light source device 11203 can be controlled so as to change the output light intensity at predetermined time intervals. By controlling the driving of the imaging element of the camera head 11102 in synchronization with the timing of the change in the light intensity and acquiring images in a time division manner, and by synthesizing these images, a high dynamic range image in which so-called blocked up shadows or blown out highlights do not exist can be generated.

[0511] Further, the light source device 11203 can be configured to be able to supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow band light observation is performed in which, by utilizing the wavelength dependency of light absorption in human tissue, a predetermined tissue such as a blood vessel of a mucosal surface layer is imaged with high contrast by irradiation with light of a narrower band than the irradiation light (in other words, white light) at the time of normal observation. Alternatively, in special light observation, fluorescence observation can be performed in which an image is obtained by fluorescence generated by irradiation with excitation light. In fluorescence observation, for example, fluorescence from human tissue (autofluorescence observation) can be observed by irradiating the human tissue with excitation light, or a fluorescent image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into human tissue and irradiating the human tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to be able to supply narrow band light and / or excitation light corresponding to such special light observation.

[0512] Figure 77 is shown Figure 76A block diagram of an example of the functional configuration of the camera head 11102 and the CCU 11201 is shown.

[0513] The camera head 11102 includes a lens unit 11401, an imaging section 11402, a driving section 11403, a communication section 11404, and a camera head control section 11405. The CCU 11201 includes a communication section 11411, an image processing section 11412, and a control section 11413. The camera head 11102 and the CCU 11201 are communicably connected to each other through a transmission cable 11400.

[0514] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. The observation light picked up from the front end of the lens barrel 11101 is guided to the camera head 11102 and is incident on the lens unit 11401. The lens unit 11401 can be a combination of a plurality of lenses including a zoom lens and a focus lens.

[0515] The imaging section 11402 includes an imaging element. The imaging section 11402 can include one imaging element (so-called single board type) or a plurality of imaging elements (so-called multi board type). In the case where the imaging section 11402 includes multi board type imaging elements, for example, an image signal corresponding to each of R, G, and B can be generated by each imaging element, and a color image can be obtained by synthesizing these image signals. Alternatively, the imaging section 11402 can include a pair of imaging elements for respectively acquiring a right eye image signal and a left eye image signal corresponding to three-dimensional (3D) display. By performing 3D display, the surgeon 11131 is able to more accurately grasp the depth of biological tissue at the surgical site. Note that in the case where the imaging section 11402 includes multi board type imaging elements, a plurality of system lens units 11401 can be provided in correspondence with each imaging element.

[0516] Further, the imaging section 11402 is not necessarily provided in the camera head 11102. For example, the imaging section 11402 can be provided inside the lens barrel 11101 immediately behind the objective lens.

[0517] The driving section 11403 includes an actuator, and under the control of the camera head control section 11405, the driving section 11403 moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis. Thus, the magnification and the focus of the image taken by the imaging section 11402 can be appropriately adjusted.

[0518] The communication section 11404 includes a communication device for transmitting and receiving various information to and from the CCU 11201. The communication section 11404 transmits an image signal obtained from the imaging section 11402 to the CCU 11201 as raw (RAW) data through the transmission cable 11400.

[0519] Further, the communication section 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control section 11405. The above-described control signal includes, for example, information on imaging conditions such as information for specifying a frame rate of an image to be captured, information for specifying an exposure value at the time of imaging, and / or information for specifying a magnification and a focus of an image to be captured.

[0520] Note that the imaging conditions such as the above-described frame rate, exposure value, magnification, and focus can be appropriately designated by a user, or can be automatically set by the control section 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 has a so-called auto exposure (AE) function, an auto focus (AF) function, and an auto white balance (AWB) function.

[0521] The camera head control section 11405 controls driving of the camera head 11102 based on the control signal from the CCU 11201 received through the communication section 11404.

[0522] The communication section 11411 includes a communication device for transmitting and receiving various information to and from the camera head 11102. The communication section 11411 receives an image signal transmitted from the camera head 11102 through the transmission cable 11400.

[0523] Further, the communication section 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The above-described image signal and the above-described control signal can be transmitted through electrical communication or optical communication, or the like.

[0524] The image processing section 11412 performs various image processing on the image signal transmitted from the camera head 11102 as raw data.

[0525] The control section 11413 performs various controls related to imaging of a surgical site or the like by the endoscope 11100 and display of a captured image obtained by imaging of the surgical site or the like. For example, the control section 11413 generates a control signal for controlling driving of the camera head 11102.

[0526] Further, based on the image signal on which image processing has been performed by the image processing section 11412, the control section 11413 causes the display device 11202 to display the captured image reflecting the surgical site or the like. In this case, the control section 11413 can recognize various objects in the captured image using various image recognition techniques. For example, the control section 11413 can recognize a surgical tool such as forceps, a specific living body site, bleeding, and mist when the energy treatment tool 11112 is used, by detecting the edge shape or color of the object included in the captured image or the like. When the display device 11202 displays the captured image, the control section 11413 can cause the display device 11202 to display various pieces of surgery assistance information on the image of the surgical site superimposed using the recognition result. In this way, the surgery assistance information is displayed superimposed and presented to the surgeon 11131. This can reduce the burden on the surgeon 11131 and enable the surgeon 11131 to reliably perform surgery.

[0527] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electric signal cable corresponding to communication of electric signals, an optical fiber corresponding to optical communication, or a composite cable thereof.

[0528] Here, in the illustrated example, communication is performed in a wired manner using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 can also be performed in a wireless manner.

[0529] Note that the endoscope surgery system is described as an example here. However, the technology of the present application can also be applied to, for example, a microscope surgery system or the like.

[0530] Note that the present application can have the following configuration.

[0531] [A01] <Image pickup element: first aspect>

[0532] An image pickup element including: a photoelectric conversion section formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode,

[0533] An inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, the inorganic oxide semiconductor material layer including a first layer and a second layer from the first electrode side,

[0534] When an average film density of the first layer within 3 nm, preferably 5 nm, more preferably 10 nm from an interface between the first electrode and the inorganic oxide semiconductor material layer is set as ρ1, and an average film density of the second layer is set as ρ2, ρ1 ≥ 5.9 g / cm 3 and ρ1 – ρ2 ≥ 0.1 g / cm3 .

[0535] [A02] The imaging device according to any one of [A01], wherein a composition of the first layer is the same as a composition of the second layer.

[0536] [A03] <Imaging device: second aspect>

[0537] An imaging device including a photoelectric conversion section formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode,

[0538] wherein an inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, the inorganic oxide semiconductor material layer includes a first layer and a second layer from the first electrode side,

[0539] a composition of the first layer is the same as a composition of the second layer,

[0540] when an average film density of the first layer within 3 nm, preferably 5 nm, more preferably 10 nm from an interface between the first electrode and the inorganic oxide semiconductor material layer is set as p1, and an average film density of the second layer is set as p2, p1 - p2 ≥ 0.1 g / cm 3 .

[0541] [A04] The imaging device according to any one of [A01] to [A03], wherein when an average oxygen vacancy generation energy of the first layer is set as E OD-1 , and an average oxygen vacancy generation energy of the second layer is set as E OD-2 , E OD-1 ≥ 2.8 eV and E OD-1 – E OD-2 ≥ 0.2 eV.

[0542] [A05] <Imaging device: third aspect>

[0543] An imaging device including a photoelectric conversion section formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode,

[0544] an inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, the inorganic oxide semiconductor material layer includes a first layer and a second layer from the first electrode side,

[0545] when an average oxygen vacancy generation energy of the first layer within 3 nm, preferably 5 nm, more preferably 10 nm from an interface between the first electrode and the inorganic oxide semiconductor material layer is set as E OD-1 , and an average oxygen vacancy generation energy of the second layer is set as EOD-2 E0 - E1 > 0.2 (eV) is satisfied. OD-1 E0 - E1 > 0.2 (eV) is satisfied. OD-1 E0 - E1 > 0.2 (eV) is satisfied. OD-2 E0 - E1 > 0.2 (eV) is satisfied.

[0546] [A06] The image pickup element according to any one of [A01] to [A05], wherein a composition of the first layer is the same as a composition of the second layer.

[0547] [A07] <IMAGE PICKUP ELEMENT: FOURTH ASPECT>

[0548] An image pickup element including a photoelectric conversion section formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode,

[0549] An inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, the inorganic oxide semiconductor material layer including a first layer and a second layer from the first electrode side,

[0550] A composition of the first layer is the same as a composition of the second layer,

[0551] When an average oxygen vacancy generation energy of the first layer within 3 nm, preferably 5 nm, more preferably 10 nm from an interface between the first electrode and the inorganic oxide semiconductor material layer is set as E0, and an average oxygen vacancy generation energy of the second layer is set as E1, E0 - E1 > 0.2 (eV) is satisfied. OD-1 OD-2 OD-1 OD-2 E0 - E1 > 0.2 (eV) is satisfied.

[0552] [A08] The image pickup element according to any one of [A01] to [A07], wherein when an average energy value at a maximum energy value of a conduction band of the inorganic oxide semiconductor material layer is set as E1, and an average energy value at a LUMO value of the photoelectric conversion layer is set as E0, E0 - E1 > 0.1 (eV) is satisfied. 12 E0 - E1 > 0.1 (eV).

[0553] [A09] The image pickup element according to [A08], wherein E0 - E1 > 0.1 (eV) is satisfied.

[0554] [A10] The image pickup element according to any one of [A01] to [A09], wherein the photoelectric conversion section further has an insulating layer and a charge accumulation electrode, the charge accumulation electrode being arranged separately from the first electrode, and the charge accumulation electrode being arranged opposite to the inorganic oxide semiconductor material layer with the insulating layer interposed therebetween.

[0555] ​​​[A11] The imaging device according to any one of [A01] to [A10], wherein the electric charge generated in the photoelectric conversion layer moves to the first electrode via the inorganic oxide semiconductor material layer.

[0556] [A12] The imaging device according to [A11], wherein the electric charge is an electron.

[0557] [A13] The imaging device according to any one of [A01] to [A12], wherein a carrier mobility of a material constituting the inorganic oxide semiconductor material layer is 10 cm 2 / V·s or more.

[0558] [A14] The imaging device according to any one of [A01] to [A13], wherein a carrier concentration of the inorganic oxide semiconductor material layer is 1 x 10 16 / cm 3 or less.

[0559] [A15] The imaging device according to any one of [A01] to [A14], wherein a thickness of the inorganic oxide semiconductor material layer is 1 x 10 -8 m to 1.5 x 10 -7 m.

[0560] [A16] The imaging device according to any one of [A01] to [A15], wherein the inorganic oxide semiconductor material layer is amorphous.

[0561] [B01] The imaging device according to any one of [A01] to [A16], further comprising a semiconductor substrate, the photoelectric conversion section being disposed above the semiconductor substrate.

[0562] [B02] The imaging device according to any one of [A01] to [B01], wherein the first electrode extends within an opening portion provided in the insulating layer to be connected to the inorganic oxide semiconductor material layer.

[0563] [B03] The imaging device according to any one of [A01] to [B01], wherein the inorganic oxide semiconductor material layer extends within an opening portion provided in the insulating layer to be connected to the first electrode.

[0564] [B04] The imaging device according to [B03], wherein an edge of a top surface of the first electrode is covered with the insulating layer,

[0565] the first electrode is exposed at a bottom surface of the opening portion,

[0566] When a surface of the insulating layer that is in contact with a top surface of the first electrode is provided as a first surface, and a surface of the insulating layer that is in contact with a portion of the inorganic oxide semiconductor material layer that faces the charge accumulation electrode is provided as a second surface, a side surface of the opening portion has a gradient that widens from the first surface toward the second surface.

[0567] [B05] The imaging device according to [B04], wherein the side surface of the opening portion having the gradient that widens from the first surface toward the second surface is on the charge accumulation electrode side.

[0568] [B06] <Control of potentials of first electrode and charge accumulation electrode>

[0569] The imaging device according to any one of [A01] to [B05], further comprising a control portion provided on the semiconductor substrate and having a drive circuit,

[0570] The first electrode and the charge accumulation electrode are connected to the drive circuit,

[0571] During a charge accumulation period, a potential V 11 is applied from the drive circuit to the first electrode, and a potential V 31 is applied to the charge accumulation electrode, and a charge is accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer),

[0572] During a charge transfer period, a potential V 12 is applied from the drive circuit to the first electrode, and a potential V 32 is applied to the charge accumulation electrode, and a charge accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer) is read out to the control portion via the first electrode,

[0573] wherein the potential of the first electrode is higher than the potential of the second electrode, and

[0574] V 31 ≥ V 11 and V 32 < V 12 .

[0575] [B07] <Lower charge movement control electrode>

[0576] The imaging device according to any one of [A01] to [B06], wherein a lower charge movement control electrode is formed in a region of the semiconductor substrate that opposes a region of the photoelectric conversion layer between adjacent imaging devices via the insulating layer.

[0577] [B08] Control of potentials of first electrode, charge accumulation electrode, and lower charge movement control electrode

[0578] The imaging device described in [B07], further comprising a control section provided on the semiconductor substrate and having a drive circuit,

[0579] The first electrode, the second electrode, the charge accumulation electrode, and the lower charge movement control electrode are connected to the drive circuit;

[0580] During the charge accumulation period, a potential V 11 is applied from the drive circuit to the first electrode, a potential V 31 is applied to the charge accumulation electrode, and a potential V 41 is applied to the lower charge movement control electrode, and charges are accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer);

[0581] During the charge transfer period, a potential V 12 is applied from the drive circuit to the first electrode, a potential V 32 is applied to the charge accumulation electrode, and a potential V 42 is applied to the lower charge movement control electrode, and the charges accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer) are read out to the control section via the first electrode,

[0582] wherein V 31 ≥ V 11 , V 31 > V 41 , V 12 > V 32 > V 42 .

[0583] [B09] Upper charge movement control electrode

[0584] The imaging device described in any one of [A01] to [B06], wherein an upper charge movement control electrode is formed instead of the second electrode on a region of the photoelectric conversion layer between adjacent imaging devices.

[0585] [B10] The imaging device described in [B09], wherein the second electrode is provided for each imaging device, and the upper charge movement control electrode is provided on the region-A of the photoelectric conversion layer in a manner that surrounds at least a part of the second electrode and is separated from the second electrode.

[0586] [B11] The imaging device according to any one of [B09], wherein the second electrode is provided for each of the imaging devices, and the upper charge movement control electrode is provided so as to surround at least a part of the second electrode and be separate from the second electrode, and a part of the charge accumulation electrode is present below the upper charge movement control electrode.

[0587] [B12] The imaging device according to any one of [B09] to [B11], wherein the second electrode is provided for each of the imaging devices, and the upper charge movement control electrode is provided so as to surround at least a part of the second electrode and be separate from the second electrode, a part of the charge accumulation electrode is present below the upper charge movement control electrode, and the lower charge movement control electrode is formed below the upper charge movement control electrode.

[0588] [B13] <Control of potentials of first electrode, charge accumulation electrode, and charge movement control electrode>

[0589] The imaging device according to any one of [B09] to [B12], further comprising a control section provided on the semiconductor substrate and having a drive circuit,

[0590] the first electrode, the second electrode, the charge accumulation electrode, and the charge movement control electrode are connected to the drive circuit,

[0591] during the charge accumulation, a potential V 21 is applied from the drive circuit to the second electrode, and a potential V 41 is applied to the charge movement control electrode, and charges are accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer),

[0592] during the charge transfer, a potential V 22 is applied from the drive circuit to the second electrode, and a potential V 42 is applied to the charge movement control electrode, and the charges accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer) are read out to the control section via the first electrode,

[0593] wherein V 21 ≥ V 41 and V 22 ≥ V 42 .

[0594] [B14] <Transfer control electrode>

[0595] The imaging device according to any one of [A01] to [B13], wherein a transfer control electrode is further provided between the first electrode and the charge accumulation electrode, the transfer control electrode being arranged separately from the first electrode and the charge accumulation electrode, and the transfer control electrode being arranged so as to face the inorganic oxide semiconductor material layer with the insulating layer interposed therebetween.

[0596] [B15] <Control of potentials of first electrode, charge accumulation electrode, and transfer control electrode>

[0597] The imaging device according to [B14], further comprising a control section provided on the semiconductor substrate and having a drive circuit,

[0598] the first electrode, the charge accumulation electrode, and the transfer control electrode being connected to the drive circuit,

[0599] during a charge accumulation period, a potential V 11 is applied from the drive circuit to the first electrode, a potential V 31 is applied from the drive circuit to the charge accumulation electrode, and a potential V 51 is applied from the drive circuit to the transfer control electrode, and

[0600] during a charge transfer period, a potential V 12 is applied from the drive circuit to the first electrode, a potential V 32 is applied from the drive circuit to the charge accumulation electrode, and a potential V 52 is applied from the drive circuit to the transfer control electrode, and

[0601] wherein the potential of the first electrode is higher than the potential of the second electrode, and

[0602] V 31 > V 51 and V 32 ≤ V 52 ≤ V 12 .

[0603] [B16] <Charge discharge electrode>

[0604] The imaging device according to any one of [A01] to [B15], further comprising a charge discharge electrode connected to the inorganic oxide semiconductor material layer and arranged separately from the first electrode and the charge accumulation electrode.

[0605] [B17] The imaging device according to any one of [B16], wherein the charge drain electrode is disposed so as to surround the first electrode and the charge accumulation electrode.

[0606] [B18] The imaging device according to [B16] or [B17], wherein the inorganic oxide semiconductor material layer extends in a second opening portion provided in the insulating layer to be connected to the charge drain electrode,

[0607] an edge of a top surface of the charge drain electrode is covered by the insulating layer,

[0608] the charge drain electrode is exposed at a bottom surface of the second opening portion,

[0609] when a surface of the insulating layer that is in contact with a top surface of the charge drain electrode is set as a third surface, and a surface of the insulating layer that is in contact with a portion of the inorganic oxide semiconductor material layer that faces the charge accumulation electrode is set as a second surface, a side surface of the second opening portion has a slope that widens from the third surface toward the second surface.

[0610] [B19] Control of potentials of the first electrode, the charge accumulation electrode, and the charge drain electrode

[0611] The imaging device according to any one of [B16] to [B18], further comprising a control section provided on the semiconductor substrate and having a drive circuit,

[0612] the first electrode, the charge accumulation electrode, and the charge drain electrode are connected to the drive circuit,

[0613] during a charge accumulation period, a potential V 11 is applied from the drive circuit to the first electrode, a potential V 31 is applied from the drive circuit to the charge accumulation electrode, and a potential V 61 is applied from the drive circuit to the charge drain electrode, and a charge is accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer),

[0614] during a charge transfer period, a potential V 12 is applied from the drive circuit to the first electrode, a potential V 32 is applied from the drive circuit to the charge accumulation electrode, and a potential V 62 is applied from the drive circuit to the charge drain electrode, and a charge accumulated in the inorganic oxide semiconductor material layer (or the inorganic oxide semiconductor material layer and the photoelectric conversion layer) is read out to the control section via the first electrode,

[0615] wherein the potential of the first electrode is higher than the potential of the second electrode, and the following condition is satisfied

[0616] V 61 >V 11 and V 62 <V 12 .

[0617] [B20] Charge accumulation electrode section

[0618] The imaging device according to any one of [A01] to [B19], wherein the charge accumulation electrode includes a plurality of charge accumulation electrode sections.

[0619] [B21] The imaging device according to [B20], wherein,

[0620] in a case where the potential of the first electrode is higher than the potential of the second electrode, during the charge transfer, the potential applied to the charge accumulation electrode section closest to the first electrode is higher than the potential applied to the charge accumulation electrode section farthest from the first electrode, and

[0621] in a case where the potential of the first electrode is lower than the potential of the second electrode, during the charge transfer, the potential applied to the charge accumulation electrode section closest to the first electrode is lower than the potential applied to the charge accumulation electrode section farthest from the first electrode.

[0622] [B22] The imaging device according to any one of [A01] to [B21], wherein, on the semiconductor substrate, at least a floating diffusion layer and an amplification transistor for constituting the control section are provided, and

[0623] the first electrode is connected to the floating diffusion layer and a gate section of the amplification transistor.

[0624] [B23] The imaging device according to [B22], wherein, on the semiconductor substrate, a reset transistor and a selection transistor for constituting the control section are further provided,

[0625] the floating diffusion layer is connected to one source / drain region of the reset transistor, and

[0626] one source / drain region of the amplification transistor is connected to one source / drain region of the selection transistor, and the other source / drain region of the selection transistor is connected to a signal line.

[0627] [B24] The imaging device according to any one of [A01] to [B23], wherein a size of the charge accumulation electrode is larger than the first electrode.

[0628] [B25] The image pickup element according to any one of [A01] to [B24], wherein light is incident from the second electrode side, and a light-shielding layer is formed on the light incident side of the second electrode.

[0629] [B26] The image pickup element according to any one of [A01] to [B24], wherein light is incident from the second electrode side, and light is not incident to the first electrode.

[0630] [B27] The image pickup element according to [B26], wherein a light-shielding layer is formed on the light incident side of the second electrode and above the first electrode.

[0631] [B28] The image pickup element according to [B26], wherein an on-chip microlens is provided above the charge accumulation electrode and the second electrode, and

[0632] light incident to the on-chip microlens is condensed to the charge accumulation electrode.

[0633] [B29] <Image pickup element: first configuration>

[0634] The image pickup element according to any one of [A01] to [B28], wherein the photoelectric conversion section includes N (wherein N ≥ 2) photoelectric conversion section segments,

[0635] the inorganic oxide semiconductor material layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0636] the insulating layer includes N insulating layer segments,

[0637] the charge accumulation electrode includes N charge accumulation electrode segments,

[0638] the nth (wherein n = 1, 2, 3,..., N) photoelectric conversion section segment includes an nth charge accumulation electrode segment, an nth insulating layer segment, and an nth photoelectric conversion layer segment,

[0639] the photoelectric conversion section segment having a larger n value is farther from the first electrode, and

[0640] the thickness of the insulating layer segment gradually changes from the first photoelectric conversion section segment to the Nth photoelectric conversion section segment.

[0641] [B30] <Image pickup element: second configuration>

[0642] The image pickup element according to any one of [A01] to [B28], wherein the photoelectric conversion section includes N (wherein N ≥ 2) photoelectric conversion section segments,

[0643] The inorganic oxide semiconductor material layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0644] The insulating layer includes N insulating layer segments,

[0645] The charge accumulation electrode includes N charge accumulation electrode segments,

[0646] The nth (where n = 1, 2, 3,..., N) photoelectric conversion section includes an nth charge accumulation electrode segment, an nth insulating layer segment, and an nth photoelectric conversion layer segment,

[0647] The photoelectric conversion section having a larger n value is farther from the first electrode, and

[0648] The thickness of the photoelectric conversion layer segments gradually changes from the first photoelectric conversion section to the Nth photoelectric conversion section.

[0649] [B31] <Image pickup element: third configuration>

[0650] The image pickup element according to any one of [A01] to [B28], wherein the photoelectric conversion section includes N (where N ≥ 2) photoelectric conversion section segments,

[0651] The inorganic oxide semiconductor material layer and the photoelectric conversion layer include N photoelectric conversion layer segments,

[0652] The insulating layer includes N insulating layer segments,

[0653] The charge accumulation electrode includes N charge accumulation electrode segments,

[0654] The nth (where n = 1, 2, 3,..., N) photoelectric conversion section includes an nth charge accumulation electrode segment, an nth insulating layer segment, and an nth photoelectric conversion layer segment, ...

Claims

1. An image pickup element comprising: A photoelectric conversion section is formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode, An inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, the inorganic oxide semiconductor material layer includes a first layer and a second layer from the first electrode side, the thickness of the second layer is greater than the thickness of the first layer, When an average film density of the first layer within 3 nm from an interface between the first electrode and the inorganic oxide semiconductor material layer is set as p1, and an average film density of the second layer is set as p2, p1 < p2 is satisfied, pl > 5.9 g / cm 3 and pl - p2 > 0.1 g / cm 3 , wherein, when the average oxygen vacancy generation energy of the first layer is set as E OD-1 , and the average oxygen vacancy generation energy of the second layer is set as E OD-2 , the following is satisfied E OD-1 ≥ 2.8 eV and E OD-1 - E OD-2 ≥ 0.2 eV.

2. The image pickup element according to claim 1, wherein The first layer and the second layer are composed of the same component.

3. The image pickup element according to claim 1, wherein When an average energy value at a maximum energy value of a conduction band of the inorganic oxide semiconductor material layer is set as E1, and an average energy value at a LUMO value of the photoelectric conversion layer is set as E0, E0 - E1 ≥ 0.1 (eV) is satisfied. E0 - E1 > 0.1 (eV) is satisfied.

4. The image pickup element according to claim 3, wherein The photoelectric conversion section further has an insulating layer and a charge accumulation electrode, the charge accumulation electrode is arranged separately from the first electrode, and the charge accumulation electrode is arranged opposite to the inorganic oxide semiconductor material layer with the insulating layer interposed therebetween. Charge generated in the photoelectric conversion layer moves to the first electrode via the inorganic oxide semiconductor material layer.

5. The image pickup element according to claim 1, wherein The charge is an electron.

6. The image pickup element according to claim 1, wherein A photoelectric conversion section is formed by stacking a first electrode, a photoelectric conversion layer formed of an organic material, and a second electrode, 7. The image pickup element according to claim 6, wherein wherein an inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, the inorganic oxide semiconductor material layer includes a first layer and a second layer from the first electrode side, the thickness of the second layer is greater than the thickness of the first layer, 8. The image pickup element according to any one of claims 1 to 7, wherein The carrier mobility of the material constituting the inorganic oxide semiconductor material layer is 10 cm2 / V-s or more. 2 / V·s or more.

9. The image pickup element according to any one of claims 1 to 7, wherein The carrier concentration of the inorganic oxide semiconductor material layer is 1 x 10 16 / cm 3 The following.

10. The image pickup element according to any one of claims 1 to 7, wherein The thickness of the inorganic oxide semiconductor material layer is 1 x 10 -8 m to 1.5 x 10 -7 m.

11. An image pickup element comprising: the first layer and the second layer are composed of the same component, When an average film density of the first layer within 3 nm from an interface between the first electrode and the inorganic oxide semiconductor material layer is set as p1, and an average film density of the second layer is set as p2, p1 < p2 is satisfied.

12. A stacked type image pickup element including at least one image pickup element according to any one of claims 1 to 11.

13. A solid-state imaging device including a plurality of image pickup elements according to any one of claims 1 to 11. p1 - p2 > 0.1 g / cm 3 , wherein, when the average oxygen vacancy generation energy of the first layer is set as E OD-1 , and the average oxygen vacancy generation energy of the second layer is set as E OD-2 , the following is satisfied E OD-1 ≥ 2.8 eV and E OD-1 - E OD-2 ≥ 0.2 eV.

14. A solid-state imaging device including a plurality of stacked type image pickup elements according to claim 12.

15. An image pickup element manufacturing method which is a manufacturing method of the image pickup element according to any one of claims 1 to 11, the image pickup element manufacturing method includes a step of forming the second layer with input power smaller than that used for forming the first layer based on a sputtering method after forming the first layer based on a sputtering method. ​ ​

Images