Wafer-level packaging structure and packaging method

Abstract

The present invention provides a wafer-level packaging structure and packaging method, including: a chip body, the chip body including a chip unit, and a plurality of packaging pins located on the surface of the chip unit; a shielding metal layer located on the side of the chip unit away from the packaging pins; a plurality of metallized half holes located on the side wall of the chip unit, and the metallized half holes are in contact with and connected to the shielding metal layer, wherein the metallized half holes and the shielding metal layer are used to access ground signals. The metallized half holes and the shielding metal layer are connected to the ground signal and are connected to form a Faraday cage that isolates electromagnetic energy, thereby realizing an electromagnetic shielding structure in a wafer-level packaging structure. In addition, the metallized half holes provided by the present invention are arranged on the side walls of the chip unit, so as to avoid the metallized half holes occupying the wiring area of ​​the chip unit, thereby ensuring that the volume of the wafer-level packaging structure is small while ensuring the maximization of the effective wiring area of ​​the chip body.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and more specifically, to a wafer-level packaging structure and a packaging method. Background Art

[0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology that packages and tests the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is consistent with the bare die. Wafer Level Chip Size Packaging technology completely subverts traditional packaging such as Ceramic Leadless Chip Carrier, Organic Leadless Chip Carrier and digital camera module mode, and conforms to the market's requirements for microelectronic products to be increasingly light, small, short, thin and low-priced. The chip size packaged by wafer level chip size packaging technology has reached a high degree of miniaturization, and the chip cost is significantly reduced as the chip size decreases and the wafer size increases. Wafer Level Chip Size Packaging technology is a technology that can integrate IC design, wafer manufacturing, packaging testing, and substrate manufacturing. It is a hot spot in the current packaging field and a trend of future development. Although wafer level chip size packaging has become the mainstream packaging product type, it currently lacks an economical and efficient electromagnetic shielding structure. Summary of the invention

[0003] In view of this, the present invention provides a wafer-level packaging structure and a packaging method, which effectively solve the technical problems existing in the prior art, realize the electromagnetic shielding structure in the wafer-level packaging structure, ensure the small volume of the wafer-level packaging structure, and maximize the effective wiring area of ​​the chip body.

[0004] To achieve the above purpose, the technical solution provided by the present invention is as follows:

[0005] A wafer-level packaging structure, comprising:

[0006] A chip body, the chip body comprising a chip unit and a plurality of package pins located on a surface of the chip unit;

[0007] A shielding metal layer located on a side of the chip unit away from the package pins;

[0008] A plurality of metallized half holes are located on the side wall of the chip unit, and the metallized half holes are in contact with and connected to the shielding metal layer, wherein the metallized half holes and the shielding metal layer are used to access ground signals.

[0009] Optionally, the package pin includes at least one ground package pin, and the metallized half hole is electrically connected to the ground package pin.

[0010] Optionally, the chip unit includes a rewiring layer, the rewiring layer includes a connecting line connected to the ground package pin, and the metallized half hole is connected to the ground package pin through the connecting line.

[0011] Optionally, the connection line located on the side wall of the chip unit includes an external connection line, and the metallized half hole is in contact with and connected to the external connection line.

[0012] Optionally, the chip unit includes a rewiring layer, the rewiring layer includes a first ground grid line for accessing the ground signal, and the metallized half hole is electrically connected to the first ground grid line.

[0013] Optionally, the first ground grid line is located on a side wall of the chip unit and includes a first external wiring line, and the metallized half hole is in contact with and connected to the first external wiring line.

[0014] Optionally, the chip unit includes a line interconnection layer, the line interconnection layer includes a second ground grid line for accessing the ground signal, and the metallized half hole is electrically connected to the second ground grid line.

[0015] Optionally, the second ground grid line is located on a side wall of the chip unit and includes a second external wiring line, and the metallized half hole is in contact with and connected to the second external wiring line.

[0016] Accordingly, the present invention also provides a wafer-level packaging method, comprising:

[0017] Providing a wafer structure, the wafer structure comprising a plurality of chip bodies, and comprising a dicing path between adjacent chip bodies, wherein the chip body comprises a chip unit, and a plurality of package pins located on a surface of the chip unit;

[0018] A plurality of grooves are formed at the cutting path and from a side of the chip unit away from the package pins;

[0019] Forming a first metal layer on a side of the chip unit away from the package pins, and forming a second metal layer on an inner wall of the groove;

[0020] The wafer structure is cut along the cutting path and the groove is cut into two parts to obtain a plurality of wafer-level packaging structures, wherein in the wafer-level packaging structure, the chip unit includes a shielding metal layer on the side away from the packaging pin, and the side wall of the chip unit includes a plurality of metallized half holes, and the metallized half holes are in contact and connected with the shielding metal layer, wherein the metallized half holes and the shielding metal layer are used to access the ground signal.

[0021] Optionally, the first metal layer and the second metal layer are the same metal layer.

[0022] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0023] The present invention provides a wafer-level packaging structure and a packaging method, comprising: a chip body, the chip body comprising a chip unit, and a plurality of packaging pins located on the surface of the chip unit; a shielding metal layer located on the side of the chip unit away from the packaging pins; a plurality of metallized half holes located on the side wall of the chip unit, and the metallized half holes are in contact with and connected to the shielding metal layer, wherein the metallized half holes and the shielding metal layer are used to access ground signals.

[0024] From the above content, it can be seen that the technical solution provided by the present invention is that the metallized half hole and the shielding metal layer are connected to the ground signal and connected, thereby forming a Faraday cage that isolates electromagnetic energy, and realizing the electromagnetic shielding structure in the wafer-level packaging structure. In addition, the metallized half hole provided by the present invention is arranged on the side wall of the chip unit, which avoids the metallized half hole occupying the wiring area of ​​the chip unit, thereby ensuring that the volume of the wafer-level packaging structure is small while ensuring the maximization of the effective wiring area of ​​the chip body. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0026] Figure 1 A schematic structural diagram of a wafer-level packaging structure provided by an embodiment of the present invention;

[0027] Figure 2 for Figure 1 Section view along AA' direction;

[0028] Figure 3 A schematic structural diagram of another wafer-level packaging structure provided by an embodiment of the present invention;

[0029] Figure 4 A schematic structural diagram of another wafer-level packaging structure provided by an embodiment of the present invention;

[0030] Figure 5 A schematic structural diagram of another wafer-level packaging structure provided by an embodiment of the present invention;

[0031] Figure 6A schematic structural diagram of another wafer-level packaging structure provided by an embodiment of the present invention;

[0032] Figure 7 A schematic structural diagram of another wafer-level packaging structure provided by an embodiment of the present invention;

[0033] Figure 8 A flowchart of a wafer-level packaging method provided by an embodiment of the present invention;

[0034] Figures 9 to 12 for Figure 8 Schematic diagram of the corresponding structure of each step. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] As described in the background technology, the chip size after packaging by wafer-level chip-size packaging technology has reached a high degree of miniaturization, and the chip cost is significantly reduced as the chip size decreases and the wafer size increases. Wafer-level chip-size packaging technology is a technology that can integrate IC design, wafer manufacturing, packaging testing, and substrate manufacturing. It is a hot spot in the current packaging field and a trend of future development. Although wafer-level chip-size packaging has become a mainstream packaging product type, it currently lacks an economical and efficient electromagnetic shielding structure.

[0037] Based on this, the embodiments of the present invention provide a wafer-level packaging structure and a packaging method, which effectively solve the technical problems existing in the prior art, realize the electromagnetic shielding structure in the wafer-level packaging structure, ensure the small volume of the wafer-level packaging structure, and maximize the effective wiring area of ​​the chip body.

[0038] To achieve the above purpose, the technical solution provided by the embodiment of the present invention is as follows, specifically combined with Figures 1 to 12 The technical solution provided by the embodiment of the present invention is described in detail.

[0039] Combination Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of a wafer-level packaging structure provided by an embodiment of the present invention is provided. Figure 2 for Figure 1 The wafer-level packaging structure includes:

[0040] The chip body includes a chip unit 110 and a plurality of package pins 120 located on a surface of the chip unit 110 .

[0041] The shielding metal layer 200 is located at a side of the chip unit 110 away from the package pins 120 .

[0042] A plurality of metallized half holes 300 are located on the side wall of the chip unit 110 , and the metallized half holes 300 are in contact with and connected to the shielding metal layer 200 , wherein the metallized half holes 300 and the shielding metal layer 200 are used to access ground signals.

[0043] It can be understood that the technical solution provided by the embodiment of the present invention is that the metallized half hole and the shielding metal layer are connected to the ground signal and connected, thereby forming a Faraday cage that isolates electromagnetic energy, and realizing the electromagnetic shielding structure in the wafer-level packaging structure. In addition, the metallized half hole provided by the embodiment of the present invention is arranged on the side wall of the chip unit, which avoids the metallized half hole occupying the wiring area of ​​the chip unit, thereby ensuring that the volume of the wafer-level packaging structure is small while ensuring the maximization of the effective wiring area of ​​the chip body.

[0044] In one embodiment of the present invention, among all the packaging pins of the wafer-level packaging structure provided by the present invention, at least one grounding packaging pin for externally connecting to a ground line may be provided, and by connecting the metallized half hole to the grounding packaging pin, the metallized half hole and the shielding metal layer are connected to the ground signal. Figure 3 As shown, it is a structural schematic diagram of another wafer-level packaging structure provided in an embodiment of the present invention, wherein the packaging pin 120 includes at least one grounding packaging pin 121, and the metallized half hole 300 is electrically connected to the grounding packaging pin 121.

[0045] It should be noted that the number of grounding package pins and metallized half-holes provided in the embodiment of the present invention can be the same, and then each metallized half-hole is respectively connected to a corresponding grounding package pin; or, the number of grounding package pins can be less than the number of metallized half-holes, and multiple metallized half-holes can be set to connect to the same grounding package pin, and the present invention does not make specific restrictions on this.

[0046] The metallized half hole provided in the embodiment of the present invention can be directly connected to the ground package pin, that is, the ground package pin is set at the edge of the chip unit, and then directly connected to the metallized half hole set on the side wall of the chip unit. Alternatively, the metallized half hole provided in the embodiment of the present invention can also be connected to the ground package pin through the line of the re-distribution layer (RDL); specifically, Figure 4As shown, it is a structural schematic diagram of another wafer-level packaging structure provided by an embodiment of the present invention, wherein the chip unit 110 includes a rewiring layer 111, the rewiring layer 111 includes a connecting line 1111 connected to the grounding packaging pin 121, and the metallized half hole 300 is connected to the grounding packaging pin 121 through the connecting line 1111.

[0047] like Figure 4 As shown, the connection line 1111 provided in the embodiment of the present invention is located on the side wall of the chip unit 110 and includes an external connection line (not shown), and the metallized half hole 300 is in contact with and connected to the external connection line. The external connection line provided in the embodiment of the present invention is the connection line 1111 located on the side wall of the chip unit 110. By contacting and connecting the metallized half hole 300 with the connection port of the side wall, the metallized half hole 300 is electrically connected to the connection line 1111, and finally the metallized half hole 300 is electrically connected to the ground package pin 121.

[0048] In one embodiment of the present invention, the technical solution provided by the present invention can also achieve the purpose of connecting the metallized half hole to the shielding metal layer through the metallized half hole and the ground grid line connected to the ground signal in the rewiring layer. Figure 5 As shown, it is a schematic diagram of another wafer-level packaging structure provided in an embodiment of the present invention, wherein the chip unit 110 provided in the embodiment of the present invention includes a rewiring layer 111, the rewiring layer 111 includes a first ground grid line 1112 for accessing the ground signal GND, and the metallized half hole 300 is electrically connected to the first ground grid line 1112.

[0049] like Figure 5 As shown, the first ground grid line 1112 provided in the embodiment of the present invention is located on the side wall of the chip unit 110 and includes a first external wiring (not shown), and the metallized half hole 300 is in contact with and connected to the first external wiring. The first external wiring provided in the embodiment of the present invention is the wiring port of the first ground grid line 1112 located on the side wall of the chip unit 110. By contacting and connecting the metallized half hole 300 with the wiring port of the side wall, the electrical connection between the metallized half hole 300 and the first ground grid line 1112 is achieved, and finally the purpose of connecting the metallized half hole 300 and the shielding metal layer 200 to the ground signal GND is achieved.

[0050] It can be understood that the technical solution provided by the embodiment of the present invention, while ensuring that the metallized half-hole and the shielding metal layer are connected to the ground signal, further improves the shielding effect of the electromagnetic shielding structure in the wafer-level packaging structure by electrically connecting the metallized half-hole to the first ground grid line.

[0051] In one embodiment of the present invention, the technical solution provided by the present invention can also achieve the purpose of connecting the metallized half hole to the shielding metal layer through the metallized half hole and the ground grid line connected to the ground signal in the line interconnection layer (BEOL, Back End of Line). Figure 6 As shown, it is a structural schematic diagram of another wafer-level packaging structure provided by an embodiment of the present invention, wherein the chip unit 110 provided by the embodiment of the present invention includes a circuit interconnection layer 112, the circuit interconnection layer 112 includes a second ground grid line 1121 for accessing the ground signal GND, and the metallized half hole 300 is electrically connected to the second ground grid line 1121.

[0052] like Figure 6 As shown, the second ground grid line 1121 provided in the embodiment of the present invention is located on the side wall of the chip unit 110 and includes a second external wiring (not shown), and the metallized half hole 300 is in contact with and connected to the second external wiring. The second external wiring provided in the embodiment of the present invention is the wiring port of the second ground grid line 1121 located on the side wall of the chip unit 110. By contacting and connecting the metallized half hole 300 with the wiring port of the side wall, the electrical connection between the metallized half hole 300 and the second ground grid line 1121 is achieved, and finally the purpose of connecting the metallized half hole 300 and the shielding metal layer 200 to the ground signal GND is achieved.

[0053] It can be understood that the technical solution provided by the embodiment of the present invention further improves the shielding effect of the electromagnetic shielding structure in the wafer-level packaging structure by electrically connecting the metallized half-hole to the second ground grid line while ensuring that the metallized half-hole and the shielding metal layer are connected to the ground signal. Among them, the line interconnection layer provided by the embodiment of the present invention can be a copper interconnection layer.

[0054] In one embodiment of the present invention, the technical solution provided by the present invention can also achieve the purpose of connecting the metallized half hole to the shielding metal layer through the metallized half hole and the ground grid line connected to the ground signal in the rewiring layer and the line interconnection layer. Figure 7 As shown, it is a structural schematic diagram of another wafer-level packaging structure provided in an embodiment of the present invention, wherein the chip unit 110 provided in an embodiment of the present invention includes a rewiring layer 111, the rewiring layer 111 includes a first ground grid line 1112 for accessing the ground signal GND, and the metallized half hole 300 is electrically connected to the first ground grid line 1112.

[0055] Furthermore, the chip unit 110 provided in the embodiment of the present invention includes a circuit interconnection layer 112, and the circuit interconnection layer 112 may be located on the side of the rewiring layer 111 away from the package pin 120. The circuit interconnection layer 112 includes a second ground grid line 1121 for accessing the ground signal GND, and the metallized half hole 300 is electrically connected to the second ground grid line 1121.

[0056] It can be understood that the technical solution provided by the embodiment of the present invention, while ensuring that the metallized half-hole and the shielding metal layer are connected to the ground signal, further improves the shielding effect of the electromagnetic shielding structure in the wafer-level packaging structure by electrically connecting the metallized half-hole to the first ground grid line and the second ground grid line.

[0057] Accordingly, an embodiment of the present invention further provides a wafer-level packaging method for preparing the wafer-level packaging structure provided by any of the above embodiments. Figures 8 to 12 As shown, Figure 8 A flowchart of a wafer-level packaging method provided by an embodiment of the present invention; Figures 9 to 12 for Figure 8 The wafer-level packaging method includes:

[0058] S1. Provide a wafer structure, wherein the wafer structure includes a plurality of chip bodies and a cutting path between adjacent chip bodies, wherein the chip body includes a chip unit and a plurality of packaging pins located on a surface of the chip unit.

[0059] like Fig. 9 As shown, corresponding to step S1 , the wafer structure includes a plurality of chip bodies, and a cutting path 400 is included between adjacent chip bodies, wherein the chip body includes a chip unit 110 and a plurality of package pins 120 located on the surface of the chip unit 110 .

[0060] S2. Form a plurality of grooves at the cutting path and from a side of the chip unit away from the package pins.

[0061] like Fig.10 As shown, corresponding to step S2, a plurality of grooves 410 are formed at the cutting path and on the side of the chip unit 110 away from the package pin 120. The embodiment of the present invention does not specifically limit the depth of the provided grooves 410, and the depth can be shallow or can also be in the form of through holes, which needs to be specifically designed according to the actual application.

[0062] S3, forming a first metal layer on a side of the chip unit away from the package pin, and forming a second metal layer on an inner wall of the groove.

[0063] like Fig.11As shown, corresponding to step S3 , a first metal layer 510 is formed on the side of the chip unit 110 away from the package pin 120 , and a second metal layer 520 is formed on the inner wall of the groove 410 .

[0064] Preferably, the first metal layer 510 and the second metal layer 520 provided in the embodiment of the present invention can be the same metal layer, thereby simplifying the preparation process and reducing the preparation cost. In one embodiment of the present invention, the present invention can form the metal layer by wet plating, dry sputtering, etc.

[0065] S4. Cut the wafer structure along the cutting path and cut the groove into two parts to obtain a plurality of wafer-level packaging structures, wherein, in the wafer-level packaging structure, the chip unit includes a shielding metal layer on the side away from the packaging pin, and the side wall of the chip unit includes a plurality of metallized half holes, and the metallized half holes are in contact and connected with the shielding metal layer, wherein the metallized half holes and the shielding metal layer are used to access ground signals.

[0066] like Fig.12 As shown, corresponding to step S4, the wafer structure is cut to obtain a plurality of wafer-level packaging structures. In the wafer-level packaging structure, the chip unit 110 includes a shielding metal layer 200 (wherein the shielding metal layer is formed by the first metal layer) on the side away from the package pin 120, and the side wall of the chip unit 110 includes a plurality of metallized half holes 300 (wherein the metallized half holes are formed by the second metal layer), and the metallized half holes 300 are in contact with and connected to the shielding metal layer 200, wherein the metallized half holes 300 and the shielding metal layer 200 are used to access the ground signal.

[0067] An embodiment of the present invention provides a wafer-level packaging structure and a packaging method, including: a chip body, the chip body including a chip unit, and a plurality of packaging pins located on the surface of the chip unit; a shielding metal layer located on the side of the chip unit away from the packaging pins; a plurality of metallized half holes located on the side wall of the chip unit, and the metallized half holes are in contact with and connected to the shielding metal layer, wherein the metallized half holes and the shielding metal layer are used to access ground signals.

[0068] From the above content, it can be seen that the technical solution provided by the embodiment of the present invention is that the metallized half hole and the shielding metal layer are connected to the ground signal and connected, thereby forming a Faraday cage that isolates electromagnetic energy, and realizing the electromagnetic shielding structure in the wafer-level packaging structure. In addition, the metallized half hole provided by the embodiment of the present invention is arranged on the side wall of the chip unit, which avoids the metallized half hole occupying the wiring area of ​​the chip unit, thereby ensuring that the volume of the wafer-level packaging structure is small while ensuring the maximization of the effective wiring area of ​​the chip body.

[0069] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer-level packaging structure, characterized in that: include: A chip body, the chip body comprising a chip unit and a plurality of package pins located on a surface of the chip unit; A shielding metal layer located on a side of the chip unit away from the package pins; A plurality of metallized half holes are located on the side wall of the chip unit, and the metallized half holes are in contact with and connected to the shielding metal layer, wherein the metallized half holes and the shielding metal layer are used to access ground signals; The chip unit includes a rewiring layer, the rewiring layer includes a first ground grid line for accessing the ground signal, the metallized half hole is electrically connected to the first ground grid line, so as to be electrically connected to the ground grid lines accessing the ground signal in the rewiring layer and the line interconnection layer through the metallized half hole, so as to realize the access of the metallized half hole and the shielding metal layer to the ground signal; The chip unit includes a circuit interconnection layer, the circuit interconnection layer includes a second ground grid line for accessing the ground signal, and the metallized half hole is electrically connected to the second ground grid line to ensure that the metallized half hole and the shielding metal layer are accessed to the ground signal while the metallized half hole is electrically connected to both the first ground grid line and the second ground grid line.

2. The wafer-level packaging structure according to claim 1, characterized in that: The package pins include at least one ground package pin, and the metallized half hole is electrically connected to the ground package pin.

3. The wafer-level packaging structure according to claim 2, characterized in that: The chip unit comprises a rewiring layer, the rewiring layer comprises a connecting line connected to the grounding package pin, and the metallized half hole is connected to the grounding package pin through the connecting line.

4. The wafer-level packaging structure according to claim 3, characterized in that: The connecting wires are located on the side walls of the chip unit and include external connecting wires, and the metallized half holes are in contact with and connected to the external connecting wires.

5. The wafer-level packaging structure according to claim 1, characterized in that: The first ground grid line is located on the side wall of the chip unit and includes a first external wiring line, and the metallized half hole is in contact with and connected to the first external wiring line.

6. The wafer-level packaging structure according to claim 1, characterized in that: The second ground grid line is located on the side wall of the chip unit and includes a second external wiring line, and the metallized half hole is in contact with and connected to the second external wiring line.

7. A wafer-level packaging method, characterized in that: include: Providing a wafer structure, the wafer structure comprising a plurality of chip bodies, and comprising a dicing path between adjacent chip bodies, wherein the chip body comprises a chip unit, and a plurality of package pins located on a surface of the chip unit; A plurality of grooves are formed at the cutting path and from a side of the chip unit away from the package pins; Forming a first metal layer on a side of the chip unit away from the package pins, and forming a second metal layer on an inner wall of the groove; The wafer structure is cut along the cutting path and the groove is cut into two parts to obtain a plurality of wafer-level packaging structures, wherein in the wafer-level packaging structure, the chip unit includes a shielding metal layer on the side away from the packaging pin, and the side wall of the chip unit includes a plurality of metallized half holes, and the metallized half holes are in contact and connected with the shielding metal layer, wherein the metallized half holes and the shielding metal layer are used to access the ground signal.

8. The wafer-level packaging method according to claim 7, characterized in that: The first metal layer and the second metal layer are the same metal layer.

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