Self-tuning regulator and self-tuning adjustment method for interleaved power factor correction circuit

Abstract

A regulator of an interleaved power factor correction circuit for enhancing current sharing performance includes: a regulator circuit that determines a duty cycle adjustment; a judgment circuit that determines whether to activate the regulator circuit; a distributor circuit that determines a tuned duty cycle based on an input duty cycle and the duty cycle adjustment; and a tuner circuit that determines a tuned average inductor current in a first stage and a second stage of the interleaved power factor correction circuit based on the tuned duty cycle.

Description

Technical Field

[0001] The present invention relates to a self-tuning regulator for interleaved power factor correction (PFC) circuits and devices. More particularly, the present invention relates to a self-tuning regulator that counteracts inaccuracies and characteristic drifts of a sampling circuit to enhance current sharing performance in a PFC circuit. Background Art

[0002] For interleaved PFC, current sharing is achieved by controlling each average inductor current to follow a common reference current. Under light load conditions where discontinuous and boundary conduction modes occur, the average inductor current is calculated by multiplying the sampled current and the duty cycle with an appropriate coefficient. When the sampling circuit is inaccurate, the current sharing controller will incorrectly or inaccurately adjust the duty cycle so that the calculated average inductor current follows its reference current, but the actual inductor current remains unbalanced. This situation can cause large input current ripple and severe noise at certain operating points, especially when the input voltage is direct current (DC).

[0003] Due to the different characteristic variations, drifts and resolution issues of the sampling circuits in different PFC circuits, these adverse effects on the current sharing performance cannot be eliminated by fixed hardware or firmware compensation solutions.

[0004] Bing et al. (US9,923,455) proposed a current sensing and gain switching circuit to improve the current sampling resolution and accuracy of the PFC circuit under light load conditions by changing the sampling gain amplifier to improve the resolution when the load condition changes from heavy to light. However, when the load condition changes, this technique requires changing the sampling resistor in hardware and changing the control gain in firmware.

[0005] Yan (CN 101594049B) proposed another solution to periodically and alternately change the driving signal to the interleaved PFC circuit to achieve current balance. However, this method can only balance the current passively. If the parameters of the sampling circuit, power circuit or driving circuit are asymmetric, this method cannot actively balance the current well.

[0006] Gabriel et al. (US9,077,243) achieved current sharing of all stages through a common parameter, which demultiplexed the common signal into two separate inductor currents through a stage selection signal and multiple digital signals. However, the accuracy of the separate inductor currents obtained indirectly through demultiplexing cannot be guaranteed, especially when the duty cycle is greater than 0.5 in discontinuous conduction mode, which means that the current may be unbalanced in this case.

[0007] The current sharing method of the interleaved PFC circuit of Qiongyou et al. (US7,116,087) is to directly control the two sampling inductor currents to the same reference current through two integrated circuit chips (UC3845), but this technology does not solve the sampling inaccuracy or characteristic drift of the sampling circuit and does not solve the discontinuous conduction mode. Therefore, even if two separate current controllers are used, the current may still be unbalanced under light load conditions.

[0008] Neidorff et al. (US2007 / 0253223) current sharing is achieved by adjusting the level difference of the interleaved PFC circuit, which attempts to offset the difference between the interleaved levels. However, this technique fails to solve the accuracy problem of the sampling circuit and is only applicable to the switching mode of the PFC circuit for low power applications. Summary of the invention

[0009] To overcome the above problems, the preferred embodiment of the present invention provides improved current sharing between the various stages of the interleaved PFC circuit by self-tuning to offset the degradation of the accuracy, resolution and characteristic drift of the current sampling circuit (especially under light load conditions).

[0010] Through self-tuning regulation, the preferred embodiment of the present invention makes the current balance control immune to the characteristic variation, drift and resolution problem of the sampling circuit of the interleaved PFC circuit without any hardware change or control gain change.

[0011] Typically, the sampling circuit mainly includes a current transformer or a shunt resistor, a signal amplifier, and an analog-to-digital converter (ADC). The components of the sampling circuit affect the sampling accuracy and resolution, which deteriorates when the current is small. When an inaccurate sampled current is input to the current controller, an incorrect control output is obtained, resulting in current imbalance. A preferred embodiment of the present invention may include an interleaved PFC circuit with a self-tuning regulator that improves current sharing performance by offsetting inaccurate sampling under light load conditions.

[0012] According to a preferred embodiment of the present invention, a regulator for a power factor correction circuit includes: a regulator circuit that determines a duty cycle adjustment; a judgment circuit that determines whether to activate the regulator circuit; a distributor circuit that determines a tuned duty cycle based on an input duty cycle and a duty cycle adjustment; and a tuner circuit that tunes a sampling instant of an average inductor current in a first stage and a second stage of the power factor correction circuit based on the tuned duty cycle.

[0013] Preferably, the regulator circuit determines a duty cycle adjustment by inputting a duty cycle difference between a first duty cycle of a first transistor in the first subcircuit and a second duty cycle of a second transistor in the second subcircuit into a proportional integrator (PI). Preferably, the frequency divider circuit subtracts the duty cycle adjustment from one half of the first duty cycle and the second duty cycle to obtain a first tuned duty cycle; adds the duty cycle adjustment to one half of the other of the first duty cycle and the second duty cycle to obtain a second tuned duty cycle; and sends the first tuned duty cycle and the second tuned duty cycle to the tuner circuit. Preferably, the tuner circuit determines a sampling instant by multiplying both the first tuned duty cycle and the second tuned duty cycle by a switching period; and samples the current in the first subcircuit and the second subcircuit at the determined sampling instant.

[0014] According to a preferred embodiment of the present invention, a power factor correction circuit includes: a regulator according to various other preferred embodiments of the present invention; an input voltage; a rectifier for rectifying the input voltage; a first sub-circuit including a first inductor, a first transistor, a first current sensor and a first diode; a second sub-circuit including a second inductor, a second transistor, a second current sensor and a second diode; and a capacitor connecting the first sub-circuit and the second sub-circuit and connected to the positive terminal and the negative terminal of the DC voltage output.

[0015] Each of the first current sensor and the second current sensor is preferably a mutual inductor. The judgment circuit preferably activates the regulator circuit: if the average current of the first inductor and the second inductor is less than or equal to a threshold value; and if the first current in the first inductor is less than or equal to the difference between the second current in the second inductor and a predetermined inductor current value, and the first duty cycle of the first transistor is greater than or equal to the sum of the second duty cycle of the second transistor and a predetermined duty cycle value; or if the first current in the first inductor is greater than or equal to the sum of the second current in the second inductor and the predetermined inductor current value, and the first duty cycle of the first transistor is less than or equal to the difference between the second duty cycle of the second transistor and the predetermined duty cycle value.

[0016] According to a preferred embodiment of the present invention, a method for adjusting a power factor correction circuit includes adjusting a difference between input duty cycles to determine a duty cycle adjustment, and then determining a tuned duty cycle for sampling an average inductor current of a first subcircuit and a second subcircuit; determining whether to activate the duty cycle adjustment; and tuning to determine a tuned average inductor current of a first inductor and a second inductor in the power factor correction circuit based on the tuned duty cycle.

[0017] According to a preferred embodiment of the present invention, the power factor correction circuit includes: an input voltage; a diode rectifier connected to the input voltage; a first boost stage connected to the rectifier and including a first transistor, a first diode and a first inductor; a second boost stage connected to the rectifier and including a second transistor, a second diode and a second inductor; an output capacitor connected to the first boost stage and the second boost stage; a current controller, which adjusts the first duty cycle d sp1 output to the first transistor and the second duty cycle d sp2 Output to the second transistor; pulse width modulator, based on the duty cycle d sp1 and d sp2 generating gate control signals G1 and G2 with a 180° phase shift for the first transistor and the second transistor; and a self-tuning regulator, when the self-tuning regulator detects that the two average inductor currents are unbalanced, adjusting the duty cycle d pt1 and the second tuning duty cycle d pt2 Iteratively tune the sampling time to tune the average inductor current I of the current controller L1 and I L2 .

[0018] Preferably, the current controller determines the first duty cycle d by adjusting the difference between the average inductor current tuned in the first boost stage and the reference current by the first PI sp1 The second duty cycle d is determined by adjusting the difference between the tuned average inductor current of the second boost stage and the reference current through the second PI sp2。

[0019] Preferably, the self-tuning regulator adjusts the sampling time d pt1 T s and d pt2 T s to respectively determine the tuned average inductor current in the first boost stage and the tuned average inductor current in the second boost stage, the sampling time d pt1 T s and d pt2 T s is the tuning duty cycle d pt1 ,d pt2 and the switching period T s The product of; and the self-tuning regulator iteratively adjusts the first tuning duty cycle d by the following steps pt1 and the second tuning duty cycle d pt2 : Calculate the first duty cycle d sp1 With the second duty cycle d sp2 The difference between the two is sent to the PI to obtain the duty cycle adjustment Δd st; Determine the tuning duty cycle d of the first boost stage based on the following formula pt1 and the second boost stage’s tuned duty cycle d pt2 :

[0020]

[0021]

[0022] or

[0023]

[0024]

[0025] At t1 = d pt1 T s The current in the first boost stage is sampled at time t2=d pt2 T s The current in the second boost stage is sampled at time T s is a sampling period; and the first duty cycle d is updated by adjusting the difference between the current sampled in the first boost stage and the reference current at time t1 by the PI of the current controller. sp1 , and the second duty cycle d is updated by adjusting the difference between the current sampled in the first boost stage at time t2 and the same reference current through another PI regulation of the current controller. sp2 .

[0026] Preferably, the self-tuning regulator iteratively adjusts the duty cycle d of the first tuning only when pt1 and the second tuning duty cycle d pt2 : The first average inductor current I in the first boost stage L1 and the second average inductor current I L2 Both are less than or equal to the threshold current I th ; and either

[0027] I L1 ≤I L2 -ΔI L And d sp1 ≥d sp2 +Δd (3)

[0028] or

[0029] I L1 ≥I L2 +ΔI L And d sp1 ≤d sp2 -Δd (4)

[0030] Where ΔI L and Δd is a predetermined value; and otherwise, the current controller does not iteratively adjust the first tuned duty cycle d pt1 and the second tuned duty cycle d pt2 .

[0031] The above and other features, elements, characteristics, steps and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 An interleaved PFC circuit according to a preferred embodiment of the present invention is shown.

[0033] Figure 2 A self-tuning regulator circuit, a current controller and a pulse width modulator according to a preferred embodiment of the present invention are shown.

[0034] Figure 3 The preferred embodiment of the present invention is shown Figure 2 An example implementation diagram of a judgment circuit.

[0035] Figure 4 The preferred embodiment of the present invention is shown Figure 2 Figure 2 is a diagram of an example implementation of a tuner circuit.

[0036] Figure 5 The inductor current of the interleaved PFC circuit is shown before the self-tuning regulation is implemented.

[0037] Figure 6 FIG. 4 shows the inductor current of the interleaved PFC circuit after implementing self-tuning adjustment according to the preferred embodiment of the present invention.

[0038] Figure 7 The total input current of the interleaved PFC circuit before implementing self-tuning regulation is shown.

[0039] Figure 8 FIG. 4 shows the total input current of the interleaved PFC circuit after implementing self-tuning regulation according to the preferred embodiment of the present invention. DETAILED DESCRIPTION

[0040] like Figure 1 As shown, the interleaved PFC circuit may include two parallel interleaved stages or subcircuits with a shared output capacitor C. Each stage or subcircuit may include an inductor Lx, a diode Dx, and a transistor Sx, where x=1 or 2 to indicate the stage or subcircuit number. The input voltage V in(can be alternating current (AC) or direct current (DC)) is connected to an interleaved PFC circuit through a diode bridge DB, which converts the input voltage v in The interleaved PFC circuit then boosts the unregulated DC voltage to the desired regulated DC voltage V dc .although Figure 1 An interleaved PFC circuit with two parallel interleaved stages or sub-circuits with a shared output capacitor C is shown, but interleaved PFC circuits with more than two parallel interleaved stages are also possible.

[0041] exist Figure 1 In the self-tuning regulator, the current transformer V CT1 and V CT2 The output of the current controller (i.e., the duty cycle d sp1 and d sp2 ) to determine the tuned average inductor current I L1 and I L2 The tuned current I generated by the PFC output voltage controller L1 and I L2 And the current reference I Lref is sent to the current controller 110. Afterwards, the duty cycles dsp1 and dsp2 are obtained and sent to the pulse width modulator (PWM) circuit 120 to generate the gate control signals G1 and G2 that control the on and off switching of the transistors S1 and S2. The self-tuning regulator 130, the current controller 110 and the PWM circuit 120 are implemented together in a single microcontroller, although other configurations are possible. For example, each can be implemented in a separate microcontroller or IC. Any suitable microcontroller can be used.

[0042] like Figure 1 As shown, transistors S1 and S2 may be metal oxide semiconductor field effect transistors (MOSFETs). That is, the currents flowing through transistors S1 and S2 may be sensed by respective current transformers CT1 and CT2 connected to source terminals, each current transformer having a function of converting the current into a voltage V CT1 and V CT2 Alternatively, the current transformers CT1 and CT2 may be connected to the drains of the transistors S1 and S2, or to the branches of the inductors L1 and L2, and the current transformers CT1 and CT2 may be replaced with shunt resistors or current transducers using the Hall effect to measure the current.

[0043] Figure 2 Shows that it can be Figure 1The interleaved PFC circuit is used together with the self-tuning regulator 230, the current controller 210 and the PWM circuit 220. sp1 and d sp2 and the average inductor current I L1 and I L2 Afterwards, the decision circuit 231 will determine whether to activate or enable the subsequent regulator circuit 232 to determine the duty cycle adjustment Δd st In the divider circuit 233 following the adjuster circuit 232, the duty cycle adjustment is added to half of the duty cycle d sp1 / 2 and d sp2 / 2 or half the duty cycle d sp1 / 2 and d sp2 / 2 minus the duty cycle adjustment to determine the duty cycle d for following the tuning of tuner 1 234 and tuner 2 235, respectively. pt1 and d pt2 Based on the tuned duty cycle, tuner 1 234 and tuner 2 235 can determine the current transformer V CT1 and V CT2 The output is sampled at the moment, and then the tuned average inductor current I can be obtained L1 and I L2 . Figure 2 The determination circuit 231, the regulator circuit 232, the tuner 1 234 and the tuner 2 235 of the self-tuning regulator 230 shown may all be implemented together in a single microcontroller. However, other configurations are possible.

[0044] like Figure 2 As shown, the self-tuning regulator 230 includes a judgment circuit 231, a regulator circuit 232, a distributor circuit 233, a tuner 1 circuit 234, and a tuner 2 circuit 235. The judgment circuit 231 receives the average inductor current I L1 and I L2 And the duty cycle d sp1 and d sp2 Following this as input, it is determined whether the subsequent regulator circuit 232 needs to be activated or enabled.

[0045] Figure 3 Shows Figure 2 In the top block, upon receiving the average inductor current I L1 and I L2 And the duty cycle d ps1 and d ps2 As input, the decision circuit 231 determines the average inductor current I L1 and I L2 Is it less than the current threshold I th, the current threshold I th When Figure 1 The average inductor current value when the PFC circuit operates under boundary conditions. Under boundary conditions, the PFC inductor current starts from zero at the beginning of each switching cycle and ends at zero at the end of each switching cycle. Therefore, when the average inductor current is greater than the threshold, the PFC will operate in continuous mode. Otherwise, when the average inductor current is less than the threshold, the PFC will operate in discontinuous mode. If the inductor current I L1 and I L2 are less than or equal to the current threshold I th , the judgment circuit 231 determines whether the following conditions (1) or (2) are met, where ΔI L and Δd is a predetermined value for hysteresis to avoid frequent activation and deactivation (or enabling and disabling) of the regulator circuit 232 around boundary points:

[0046] I L1 ≤I L2 -ΔI L And d sp1 ≥d sp2 +Δd (1)

[0047] I L1 ≥I L2 +ΔI L And d sp1 ≤d sp2 -Δd (2)

[0048] ΔI L The specific values ​​of and Δd depend on the accuracy requirements of the current sharing control and the resolution of the sampling circuit.

[0049] If at least one of the conditions (1) and (2) is satisfied, the determination circuit 231 activates or enables the regulator circuit 232. L1 and I L2 Both are greater than the current threshold I th Or if neither of the conditions (1) and (2) is satisfied, the determination circuit 231 disables the regulator circuit 232 .

[0050] Once activated or enabled, the regulator circuit 232 uses the PI (eg Figure 2 As shown) to control the duty cycle d sp1 and d sp2 to obtain the duty cycle adjustment Δd st , and then passed to the distributor circuit 233, where they are respectively divided from d sp1 and d sp2 half of the duty cycle adjustment and d sp1 and d sp2Half of the duty cycle is added to the duty cycle adjustment (as shown in equations (3) and (4) below) to determine the tuned duty cycle d pt1 and d pt2 .

[0051]

[0052]

[0053] Alternatively, the tuning duty cycle d can be calculated using the following equations (3') and (4'): pt1 and d pt2 .

[0054]

[0055]

[0056] Once determined, the two tuned duty cycles d pt1 and d pt2 Together with the voltage output V of transformers CT1 and CT2 CT1 、V CT2 The signals are sent to tuner 1 234 and tuner 2 235 of the tuner circuit of the self-tuning regulator 230 to tune the sampling time d pt1 T s and d pt2 T s (Wherein, T s is a switching cycle) to correct the sampling inaccuracy of the sampling circuit, thereby improving the current sharing performance of each stage of the PFC circuit.

[0057] like Figure 1 As shown, the sampling circuit may include a current transformer, a sampling resistor, and an analog-to-digital converter (ADC), which are not shown in the self-regulating regulator 130 .

[0058] like Figure 2 As shown, the average inductor current I of the tuner 1 234 circuit and the tuner 2 235 circuit is tuned L1 and I L2 The current reference I output from the PFC output voltage controller Lref Compare them and calculate the difference between them (I Lref -I L1 , I Lref -I L2 ) is sent to the next two PIs to update the duty cycle d sp1 and d sp2 Then the updated duty cycle d sp1 and d sp2Sent to the PWM circuit to generate gate signals for switches S1 and S2 of the interleaved PFC to make I L1 and I L2 The difference between becomes smaller, thereby improving current sharing. This self-tuning process is iterative until neither (1) nor (2) is satisfied and the decision circuit 231 disables the regulator circuit 232.

[0059] If the regulator circuit 232 is disabled, the duty cycle adjustment Δd st The same duty cycle adjustment is maintained as was obtained the last time the regulator circuit 232 was still activated or enabled, and no self-tuning adjustment is performed.

[0060] exist Figure 4 In the implementation diagram of tuner circuits 1 and 2, by changing the tuning duty cycle d pt1 d pt2 Multiply by the switching period Ts (ie, d pt1 T s and d pt2 T s ) to determine the sampling instants SI1 and SI2. 180° phase shift sawtooth carrier C r1 and C r2 Generated by a circuit or a dedicated microchip. When using formulas (3) and (4) to adjust the duty cycle d pt1 and d pt2 When the sampling time SI1 and SI2 are adjusted within the range of half the duty cycle, Δd st , which is different from the conventional method where the sampling instant is fixed at half of the duty cycle.

[0061] The performance of the self-tuning regulator of the interleaved PFC circuit has been verified by experiments, in which the input voltage is selected as DC. Figure 5 As shown in Figure 1, the inductor currents of the two inductors in the interleaved PFC circuit are unbalanced before the self-tuning adjustment is implemented. Figure 6 As shown, after implementing the self-tuning adjustment, the inductor current becomes well balanced. Figure 7 and Figure 8 The total input current of the interleaved PFC circuit before and after the implementation of self-tuning regulation is shown respectively. Figure 7 and Figure 8 When the total input current is adjusted, it is shown that through self-tuning adjustment, the peak-to-peak ripple of the total input current of the interleaved PFC circuit can be greatly reduced from about 45% of the average value to about 3.2% of the average value.

[0062] It should be understood that the above description is only for illustrating the present invention. Without departing from the present invention, those skilled in the art can design various substitutions and modifications. Therefore, the present invention is intended to include all these substitutions, modifications and variations that fall within the scope of the appended claims.

Claims

1. A regulator for a power factor correction circuit, the power factor correction circuit being an interleaved PFC circuit having two parallel interleaved subcircuits, the regulator comprising: a regulator circuit, determining the duty cycle adjustment; A judgment circuit, determining whether to activate the regulator circuit; a divider circuit that determines a tuned duty cycle based on an input duty cycle and the duty cycle adjustment; as well as a tuner circuit for tuning a sampling instant of an average inductor current in a first subcircuit and a second subcircuit of the power factor correction circuit based on a first tuning duty cycle and a second tuning duty cycle, wherein the regulator circuit determines the duty cycle adjustment by inputting a duty cycle difference between a first duty cycle of a first transistor in a first subcircuit and a second duty cycle of a second transistor in a second subcircuit into a proportional integrator, Wherein, the distributor circuit: subtracting the duty cycle adjustment from one-half of the first duty cycle and the second duty cycle to obtain a first tuned duty cycle; adding half of the other of the first duty cycle and the second duty cycle to the duty cycle adjustment to obtain a second tuned duty cycle; and The first tuning duty cycle and the second tuning duty cycle are sent to the tuner circuit.

2. The regulator according to claim 1, wherein: The tuner circuit: determining a sampling instant of the inductor current by multiplying both the first tuned duty cycle and the second tuned duty cycle by the switching period; as well as The inductor currents in the first subcircuit and the second subcircuit are sampled at the determined sampling instants.

3. A power factor correction circuit, comprising: The regulator according to claim 1; Input voltage; A rectifier, for rectifying the input voltage; a first subcircuit comprising a first inductor, a first transistor, a first current sensor, and a first diode; a second subcircuit including a second inductor, a second transistor, a second current sensor, and a second diode; as well as A capacitor is connected to the first sub-circuit and the second sub-circuit and is connected to the positive terminal and the negative terminal of the DC voltage output.

4. The power factor correction circuit according to claim 3, wherein: Each of the first current sensor and the second current sensor is a transformer.

5. The power factor correction circuit according to claim 3, wherein: The judgment circuit activates the regulator circuit in the following cases: if an average current of the first inductor and the second inductor is less than or equal to a threshold; as well as if a first current in the first inductor is less than or equal to a difference between a second current in the second inductor and a predetermined inductor current value, and a first duty cycle of the first transistor is greater than or equal to a sum of a second duty cycle of the second transistor and a predetermined duty cycle value; or If the first current in the first inductor is greater than or equal to the sum of the second current in the second inductor and the predetermined inductor current value, and the first duty cycle of the first transistor is less than or equal to the difference between the second duty cycle of the second transistor and the predetermined duty cycle value.

6. A method for adjusting a power factor correction circuit, the method comprising: adjusting a difference between the input duty cycles to determine a duty cycle adjustment, wherein the duty cycle adjustment is determined by inputting a duty cycle difference between a first duty cycle of a first transistor in a first subcircuit of the power factor correction circuit and a second duty cycle of a second transistor in a second subcircuit of the power factor correction circuit into a proportional integrator; then determining a tuned duty cycle for sampling the average inductor current of the first subcircuit and the second subcircuit, wherein the duty cycle adjustment is subtracted from half of one of the first duty cycle and the second duty cycle to obtain a first tuned duty cycle; and the duty cycle adjustment is added to half of the other of the first duty cycle and the second duty cycle to obtain a second tuned duty cycle; determining whether to activate the duty cycle adjustment; and Tuning is performed based on the first tuning duty cycle and the second tuning duty cycle to determine a tuned average inductor current of a first inductor and a second inductor in the power factor correction circuit.

7. A power factor correction circuit comprising: Input voltage terminal; a diode rectifier connected to the input voltage terminal; a first boost stage connected to the diode rectifier and comprising a first transistor, a first diode and a first inductor; a second boost stage connected to the diode rectifier and comprising a second transistor, a second diode and a second inductor; an output capacitor connected to the first boost stage and the second boost stage; A current controller generates a first duty cycle d for the first transistor sp1 , and generates a second duty cycle d for the second transistor sp2 ; Pulse width modulator, based on the tuned average inductor current signal I L1 and I L2 Based on the duty cycle d sp1 and d sp2 generating gate control signals G1 and G2 with a 180° phase shift for the first transistor and the second transistor; as well as A self-tuning regulator is provided, wherein the self-tuning regulator is based on the first duty cycle d sp1 and the second duty cycle d sp2 Determine the first tuning duty cycle d pt1 and the second tuning duty cycle d pt2 , wherein a duty cycle adjustment is determined by inputting a duty cycle difference between a first duty cycle of a first transistor in the first boost stage and a second duty cycle of a second transistor in the second boost stage into a proportional integrator, wherein the duty cycle adjustment is subtracted from one half of the first duty cycle and the second duty cycle to obtain a first tuned duty cycle; and the duty cycle adjustment is added to one half of the other of the first duty cycle and the second duty cycle to obtain a second tuned duty cycle; And when the self-tuning regulator detects the average inductor current I L1 and I L2 When unbalanced, the first tuning duty cycle d pt1 and the second tuning duty cycle d pt2 The sampling instants are iteratively tuned to obtain the average inductor current I for tuning of the current controller L1 and I L2 .

8. The power factor correction circuit according to claim 7, wherein: The current controller: The first duty cycle d is determined by adjusting the difference between the tuned average inductor current in the first boost stage and a reference current via a first proportional integrator. sp1 ; as well as The second duty cycle d is determined by adjusting the difference between the tuned average inductor current in the second boost stage and a reference current via a second proportional integrator. sp2 .

9. The power factor correction circuit according to claim 7, wherein: The self-tuning regulator adjusts the sampling time d pt1 T s and d pt2 T s To determine the tuned average inductor current in the first boost stage and the tuned average inductor current in the second boost stage, the sampling time d pt1 T s and d pt2 T s are the tuning duty cycle d pt1 d pt2 and the switching period T s The product of as well as The self-tuning regulator iteratively adjusts the first tuning duty cycle d by the following steps: pt1 and the second tuning duty cycle d pt2 : Calculate the first duty cycle d sp1 With the second duty cycle d sp2 The difference between the two is sent to the proportional integrator to obtain the duty cycle adjustment Δd st ; The tuning duty cycle d of the first boost stage is determined based on the following formula: pt1 and the tuning duty cycle of the second boost stage d pt2 : （1） （2）； or （1 ’ ） （2 ’ ）； At t1=d pt1 T s The current in the first boost stage is sampled at time t2=d pt2 T s The current in the second boost stage is sampled at time T s is the sampling period; as well as The first duty cycle d is updated by adjusting the difference between the current sampled in the first boost stage at time t1 and the reference current via the proportional integrator of the current controller. sp1 , and the second duty cycle d is updated by adjusting the difference between the current sampled in the second boost stage at time t2 and the same reference current through another proportional integrator of the current controller. sp2 .

10. The power factor correction circuit according to claim 7, wherein The self-tuning regulator iteratively adjusts the first tuning duty cycle d only when pt1 and the second tuning duty cycle d pt2 : The first average inductor current I in the first boost stage L1 and the second average inductor current I L2 Both are less than or equal to the threshold current I th ; as well as Or: I L1 ≤I L2 -ΔI L and d sp1 ≥d sp2 +Δd (3) or I L1 ≥ I L2 + ΔI L and d sp1 ≤ d sp2 - Δd (4) Where ΔI L and Δd are predetermined values; as well as Otherwise, the self-tuning regulator does not iteratively adjust the first tuning duty cycle d pt1 and the second tuning duty cycle d pt2 .

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