Memory device and method of operating the memory device

Abstract

A memory device and a method for operating the memory device. A memory device and a method for operating the memory device are provided herein. The memory device includes: a reference voltage generating circuit configured to generate a standby mode reference voltage in a standby mode, and to generate and output an active mode reference voltage in an active mode; and an internal voltage generating circuit configured to receive the standby mode reference voltage or the active mode reference voltage from the reference voltage generating circuit, and to generate an internal voltage. When an error is detected from the internal voltage generated in the standby mode, the reference voltage generating circuit may generate and output the active mode reference voltage.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to an electronic device, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0002] As the use of mobile information devices (particularly smart phones, tablet computers, etc.) using memory systems as storage media increases, the interest and importance of memory devices are growing.

[0003] Not only due to parallelization using high-speed processors or multi-cores but also due to the development of various applications, the required level of semiconductor memory systems is increasing in terms of reliability as well as performance.

[0004] A memory system is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Memory systems are classified into volatile memory devices and non-volatile memory devices. A volatile memory device is a memory device in which the data stored therein is lost when power is off. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A non-volatile memory device is a memory device that retains the data stored therein even when power is off. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is classified into NOR type memory and NAND type memory.

[0005] The advantages provided by a data storage device using a memory system are that, since there is no mechanical drive part, stability and durability are excellent, information access speed is improved, and power consumption is reduced. Examples of data storage devices proposed as memory systems having such advantages may include a universal serial bus (USB) memory device, a memory card having various interfaces, and a solid state drive (SSD). Summary of the invention

[0006] Embodiments of the present disclosure may provide a memory device, comprising: a reference voltage generating circuit configured to generate a standby mode reference voltage in a standby mode, and to generate and output an active mode reference voltage in an active mode; and an internal voltage generating circuit configured to receive the standby mode reference voltage or the active mode reference voltage from the reference voltage generating circuit, and to generate an internal voltage. When an error is detected from the internal voltage generated in the standby mode, the reference voltage generating circuit may generate and output the active mode reference voltage.

[0007] Embodiments of the present disclosure may provide a memory device, comprising: a reference voltage generating circuit configured to generate a standby mode reference voltage in a standby mode, and to generate and output an active mode reference voltage in an active mode; an internal voltage generating circuit configured to receive a standby mode reference voltage or an active mode reference voltage from the reference voltage generating circuit, and to generate an internal voltage; and an internal circuit configured to be driven using the internal voltage and to perform a programming operation, a reading operation, an erasing operation, and a testing operation. When an error is detected from the internal voltage generated in the standby mode, the reference voltage generating circuit may automatically generate an active mode reference voltage in the standby mode.

[0008] Embodiments of the present disclosure may provide a method for operating a memory device, comprising: generating a standby mode reference voltage when in a standby mode; generating an internal voltage using the standby mode reference voltage; detecting whether there is an error in the internal voltage by comparing the internal voltage with a comparison voltage; when an error is detected from the internal voltage, disabling the operation of generating the standby mode reference voltage and generating an active mode reference voltage; and generating the internal voltage using the active mode reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0010] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0011] Figure 3 It is an example Figure 2 Block diagram of a reference voltage generating circuit.

[0012] Figure 4 Is used to describe Figure 3 A circuit diagram of an embodiment of a comparison voltage generating circuit.

[0013] Figure 5 Is used to describe Figure 3 A circuit diagram of an embodiment of a comparison voltage generating circuit.

[0014] Figure 6 Is used to describe Figure 3 Circuit diagram of an enable signal generating circuit.

[0015] Figure 7 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0016] Figure 8 is a waveform diagram of signals for describing a method of operating a memory device according to an embodiment of the present disclosure.

[0017] Fig. 9 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0018] Fig.10 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0019] Fig.11 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0020] Fig.12 is a diagram illustrating a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are only used to describe the embodiments of the present disclosure. The descriptions should not be interpreted as limiting the embodiments described in the specification or application.

[0022] In the description of the following embodiments, when a parameter is referred to as "predetermined", it may be intended to mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or the value of the parameter may be set during the period of execution of the process or algorithm.

[0023] Various embodiments of the present disclosure may be directed to a memory device in which an internal voltage is generated in a standby mode and an active mode so that operations of the memory device can be reliably performed, and a method of operating the memory device.

[0024] Figure 1 is a block diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.

[0025] Reference Figure 1 , the memory system 1000 may include a memory device 1100 configured to store data and a memory controller 1200 configured to control the memory device 1100 under the control of a host 2000 .

[0026] The host 2000 may communicate with the memory system 1000 using an interface protocol such as PCI-E (Peripheral Component Interconnect Express), ATA (Advanced Technology Attachment), SATA (Serial ATA), PATA (Parallel ATA), or SAS (Serial Attached SCSI). In addition, the interface protocol provided for the purpose of data communication between the host 2000 and the memory system 1000 is not limited to the above examples, and may be any one of interface protocols such as a Universal Serial Bus (USB) protocol, a MultiMediaCard (MMC) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol.

[0027] The memory device 1100 may operate under the control of the memory controller 1200. In an implementation, the memory device 1100 may be a flash memory device.

[0028] The memory device 1100 may receive a command CMD and an address ADD from the memory controller 1200 through a channel, and access an area of ​​the memory cell array selected by the address ADD. In other words, the memory device 1100 may perform an internal operation corresponding to the command CMD on the area selected by the address ADD. For example, the memory device 1100 may perform a programming operation on a selected memory block in response to a command CMD, an address ADD, and data DATA corresponding to a programming operation. In addition, the memory device 1100 may perform a read operation on a selected memory block in response to a command CMD and an address ADD corresponding to a read operation. The read data DATA may be output to the memory controller 1200. The memory device 1100 may perform a test operation of the memory device 1100 in response to a command CMD and an address ADD corresponding to a test operation.

[0029] The memory controller 1200 may control the overall operation of the memory system 1000 and data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 may control the memory device 1100 to program or read data or erase programmed data in response to a request of the host 2000. For example, the memory controller 1200 may output a command CMD, an address ADD, and data DATA corresponding to each overall operation to the memory device 1100 in response to a request from the host 2000, and may receive data DATA from the memory device 1100 and output the data DATA to the host 2000.

[0030] The memory device 1100 and the memory controller 1200 may be provided with an external power supply voltage VCCE and may operate using the external power supply voltage VCCE. For example, the memory device 1100 may receive the external power supply voltage VCCE and generate at least one or more internal voltages and may perform overall operations using at least one or more internal voltages.

[0031] Although in the embodiments of the present disclosure, the memory system 1000 is illustrated and described as including one memory device 1100, the memory system 1000 may include a plurality of memory devices 1100. The memory device 1100 may operate in a standby mode to reduce power consumption in a power-on period. For example, the memory device 1100 may generate a standby mode reference voltage during a power-on period, and may use the standby mode reference voltage to generate an internal voltage. In addition, during the overall operation after the power-on period, the memory device 1100 may operate in an active mode. For example, the memory device 1100 may generate an active mode reference voltage, and use the active mode reference voltage to generate an internal voltage.

[0032] If an error occurs during the operation of generating the standby mode reference voltage in the power-up period of the memory device 1100, the internal voltage may not be generated normally. Therefore, the operation of receiving the command CMD for controlling the memory device 1100 and the overall operation of the memory device 1100 may not be performed normally.

[0033] In an embodiment of the present disclosure, the memory device 1100 may operate in a standby mode during a power-on period and generate a standby mode reference voltage, and may use the standby mode reference voltage to generate an internal voltage. If the generated internal voltage does not reach a target level, the memory device 1100 may generate an active mode reference voltage in place of the standby mode reference voltage in the standby mode, and use the active mode reference voltage to generate an internal voltage.

[0034] Figure 2 is a block diagram illustrating a memory device 1100 according to an embodiment of the present disclosure.

[0035] Reference Figure 2 , the memory device 1100 may include a power-on reset circuit 100 , a reference voltage generating circuit 200 , an internal voltage generating circuit 300 , and an internal circuit 400 .

[0036] The power-on reset circuit 100 can detect the potential level of the external power supply voltage VCCE, and then generate and output a power-on reset signal POR and an inverted power-on reset signal POR_B. For example, the power-on reset circuit 100 can generate and output a power-on reset signal POR that toggles when the potential level of the external power supply voltage VCCE increases above a set level during a power-on operation of the memory system.

[0037] The reference voltage generating circuit 200 may receive an external power supply voltage VCCE and generate a reference voltage VCCI_REF. For example, the reference voltage generating circuit 200 may operate in a standby mode in response to an inverted power-on reset signal PRO_B during a power-on period, and may generate a standby mode reference voltage when in the standby mode and output the standby mode reference voltage as the reference voltage VCCI_REF. The reference voltage generating circuit 200 may operate in an active mode in response to an activation signal ACT_EN, and may generate an active reference mode voltage when in the active mode, and output the active mode reference voltage as the reference voltage VCCI_REF.

[0038] The reference voltage generating circuit 200 may compare the internal voltage VCCI generated from the internal voltage generating circuit 300 with a comparison voltage having a target level when in the standby mode. When the internal voltage VCCI is lower than the comparison voltage, the reference voltage generating circuit 200 may operate in an active mode to generate an active mode reference voltage and output the active mode reference voltage as the reference voltage VCCI_REF.

[0039] The internal voltage generating circuit 300 may receive the external power voltage VCCE and the reference voltage VCCI_REF and generate the internal voltage VCCI, and then output the internal voltage VCCI to the reference voltage generating circuit 200 and the internal circuit 400 .

[0040] The internal circuit 400 may be initialized in response to a power-on reset signal POR output from the power-on reset circuit 100. In addition, the internal circuit 400 may operate using the internal voltage VCCI generated from the internal voltage generating circuit 300 as a power supply and in response to the power-on reset signal POR output from the power-on reset circuit 100. Figure 1 The memory controller 1200 receives commands, addresses, and multiple data to perform overall operations such as a program operation to store data, a read operation to read the stored data, an erase operation to erase the stored data, and a test operation of the memory device.

[0041] Figure 3 It is an example Figure 2 1 is a block diagram of a reference voltage generating circuit 200 .

[0042] Reference Figure 3, the reference voltage generating circuit 200 may include a comparison voltage generating circuit 210 , an enable signal generating circuit 220 , a standby mode reference voltage generating circuit 230 , an active mode reference voltage generating circuit 240 , and a selection circuit 250 .

[0043] The comparison voltage generating circuit 210 may be enabled in response to a reset latch signal RESET_LAT, and receive an external power supply voltage VCCE and generate a comparison voltage VCCE_REF. The reset latch signal RESET_LAT may be a signal that is enabled in a power-on period of the memory device and disabled in response to a reset signal received from an external device of the memory device after the power-on period to perform a reset operation of the memory device.

[0044] The enable signal generating circuit 220 may generate and output a standby mode enable signal EN_S in response to the inverted power-on reset signal POR_B when in standby mode. In addition, the enable signal generating circuit 220 may generate and output an active mode enable signal EN_A in response to the active signal ACT_EN when in active mode. The enable signal generating circuit 220 may compare the comparison voltage VCCE_REF with the internal voltage VCCI in response to the first reset signal RESET_1st when in standby mode, and based on the comparison result, continuously generate and output the standby mode enable signal EN_S, or disable the standby mode enable signal EN_S and generate and output the active mode enable signal EN_A. For example, when the internal voltage VCCI generated in standby mode is equal to or higher than the comparison voltage VCCE_REF, the enable signal generating circuit 220 may continuously enable and output the standby mode enable signal EN_S. When the internal voltage VCCI generated in the standby mode is lower than the comparison voltage VCCE_REF, the enable signal generating circuit 220 may disable the standby mode enable signal EN_S, and enable and output the active mode enable signal EN_A.

[0045] The standby mode reference voltage generating circuit 230 may generate and output a standby mode reference voltage VCCI_REF_S in response to a standby mode enable signal EN_S.

[0046] The active mode reference voltage generating circuit 240 may generate and output the active mode reference voltage VCCI_REF_A in response to the active mode enable signal EN_A.

[0047] The selection circuit 250 may output the standby mode reference voltage VCCI_REF_S generated from the standby mode reference voltage generating circuit 230 as the reference voltage VCCI_REF in response to the standby mode enable signal EN_S, or output the active mode reference voltage VCCI_REF_A generated from the active mode reference voltage generating circuit 240 as the reference voltage VCCI_REF. For example, the selection circuit 250 may output the standby mode reference voltage VCCI_REF_S as the reference voltage VCCI_REF when the standby mode enable signal EN_S is enabled, and output the active mode reference voltage VCCI_REF_A as the reference voltage VCCI_REF when the standby mode enable signal EN_S is disabled.

[0048] Figure 4 Is used to describe Figure 3 2 is a circuit diagram of an embodiment of a comparison voltage generating circuit 210 .

[0049] Reference Figure 4 , the comparison voltage generating circuit 210 may include a PMOS transistor P1 , a first resistance stage 211 , and a second resistance stage 212 .

[0050] The PMOS transistor P1 may be coupled between a terminal to which the external power supply voltage VCCE is applied and one end of the first resistance stage 211 , and provide the external power supply voltage VCCE to the first resistance stage 211 in response to a reset latch signal RESET_LAT.

[0051] The first resistance stage 211 may be coupled between the PMOS transistor P1 and the output node NA, and include at least one or more resistors R1 and R2 .

[0052] The second resistance stage 212 may be coupled between the output node NA and the ground power terminal VSS and include at least one or more resistors R11 to R13 .

[0053] When the reset latch signal RESET_LAT is enabled to a logic low level, the comparison voltage generating circuit 210 may be provided with the external power supply voltage VCCE and thus enabled. The comparison voltage generating circuit 210 may output the comparison voltage VCCE_REF by voltage-dividing the received external power supply voltage VCCE based on the ratio of the resistance value of the first resistance stage 211 to the resistance value of the second resistance stage 212.

[0054] In the comparison voltage generating circuit 210 , the potential level of the comparison voltage VCCE_REF may be changed according to the potential level of the external power supply voltage VCCE.

[0055] Figure 5 Is used to describe Figure 32 is a circuit diagram of an embodiment of a comparison voltage generating circuit 210 .

[0056] Reference Figure 5 , the comparison voltage generating circuit 210 may include a PMOS transistor P2 , a first resistance stage 213 , and a second resistance stage 214 .

[0057] The PMOS transistor P2 may be coupled between a terminal to which the external power voltage VCCE is applied and one end of the first resistance stage 213 , and provide the external power voltage VCCE to the first resistance stage 213 in response to a reset latch signal RESET_LAT.

[0058] The first resistance stage 213 may be coupled between the PMOS transistor P2 and the output node NB and include at least one or more resistors R21 and R22 .

[0059] The second resistance stage 214 may be coupled between the output node NB and the ground power terminal VSS and include at least one or more diode-connected transistors D1 and D2 .

[0060] When the reset latch signal RESET_LAT is enabled as a logic low level, the comparison voltage generating circuit 210 may be provided with an external power supply voltage VCCE and thus enabled. The comparison voltage generating circuit 210 may output a comparison voltage VCCE_REF by voltage distribution of the received external power supply voltage VCCE based on the ratio of the resistance value of the first resistance level 214 and the resistance value of the second resistance level 214. The resistance value of the second resistance level 214 may be changed according to the potential level of the output node NB. For example, when the potential level of the output node NB is relatively increased, the resistance value of the second resistance level 214 is relatively reduced. When the potential level of the output node NB is relatively reduced, the resistance value of the second resistance level 214 is relatively increased. Therefore, even when the potential level of the external power supply voltage VCCE changes, the comparison voltage generating circuit 210 may maintain a constant potential level of the output node NB, and thus output a comparison voltage VCCE_REF having a constant potential level.

[0061] Figure 6 Is used to describe Figure 3 1 is a circuit diagram of an enable signal generating circuit 220 .

[0062] Reference Figure 6 , the enable signal generating circuit 220 may include a mode changer 221 and an enable signal generator 222 .

[0063] The mode changer 221 may include a comparator 221_A, a latch 221_B, and a plurality of PMOS transistors P11 and P12 .

[0064] The comparator 221_A may be enabled in response to a first reset signal RESET_1st, and includes a first input terminal (-) configured to receive a comparison voltage VCCE_REF and a second input terminal (+) configured to receive an internal voltage VCCI. The comparator 221_A may compare the comparison voltage VCCE_REF with the internal voltage VCCI and output a comparison signal CS1 (i.e., an output signal) to a first internal node NC. For example, when the potential level of the internal voltage VCCI is higher than the potential level of the comparison voltage VCCE_REF, the comparator 221_A may generate and output a comparison signal CS1 having a logic high level. When the potential level of the internal voltage VCCI is lower than the potential level of the comparison voltage VCCE_REF, the comparator 221_A may generate and output a comparison signal CS1 having a logic low level.

[0065] The latch 221_B may be enabled in response to the first reset signal RESET_1st, and receive and temporarily store the comparison signal CS1 and then output the comparison signal CS2 to the second internal node ND.

[0066] The PMOS transistor P11 is coupled between a terminal of an external power voltage VCCE and a first internal node NC, and may initialize the first internal node NC by supplying the external power voltage VCCE to the first internal node NC in response to an inverted power-on reset signal POR_B.

[0067] The PMOS transistor P12 is coupled between a terminal of an external power voltage VCCE and a second internal node ND, and may initialize the second internal node ND by supplying the external power voltage VCCE to the second internal node ND in response to an inverted power-on reset signal POR_B.

[0068] The mode changer 221 may initialize the first and second internal nodes NC and ND to a logic high level in response to the inverted power on reset signal POR_B in the standby mode and thus output the comparison signal CS2 having a logic high level.

[0069] In addition, the mode changer 221 may compare the comparison voltage VCCE_REF with the internal voltage VCCI during a period of the standby mode in which the first reset signal RESET_1st is enabled as a logic high level, and generate and output a comparison signal CS2 based on the comparison result. For example, when the potential level of the internal voltage VCCI is higher than the potential level of the comparison voltage VCCE_REF during a period of the standby mode in which the first reset signal RESET_1st is enabled as a logic high level and is received, the mode changer 221 may generate and output a comparison signal CS2 having a logic high level. When the potential level of the internal voltage VCCI is lower than the potential level of the comparison voltage VCCE_REF, the mode changer 221 may generate and output a comparison signal CS2 having a logic low level.

[0070] The enable signal generator 222 may include at least two inverters IV1 and IV2 and a logic gate OR.

[0071] At least two inverters IV1 and IV2 are connected in series to the second internal node ND, and can buffer the comparison signal CS2 and output the standby mode enable signal EN_S. For example, in the case of receiving the comparison signal CS2 with a logic high level, at least two inverters IV1 and IV2 can buffer the comparison signal CS2 with a logic high level and output the standby mode enable signal EN_S enabled as a logic high level. In addition, in the case of receiving the comparison signal CS2 with a logic low level, at least two inverters IV1 and IV2 can buffer the comparison signal CS2 with a logic low level and output the standby mode enable signal EN_S disabled as a logic low level.

[0072] The logic gate OR can generate and output the active mode enable signal EN_A in response to the output signal EN_S_b of the inverter IV1 or the activation signal ACT_EN. For example, when receiving the output signal EN_S_b having a logic high level (i.e., the inverted signal of the standby mode enable signal) or the activation signal ACT_EN having a logic high level, the logic gate OR can generate and output the active mode enable signal EN_A enabled to a logic high level.

[0073] The enable signal generating circuit 220 may output a standby mode enable signal EN_S enabled as a logic high level in response to the inverted power-on reset signal POR_B in standby mode. Thereafter, in a period in which the first reset signal RESET_1st is enabled as a logic high level and received, the internal voltage VCCI may be compared with the comparison voltage VCCE_REF. As a result of the comparison, if the potential level of the internal voltage VCCI is higher than the potential level of the comparison voltage VCCE_REF, the standby mode enable signal EN_S enabled as a logic high level may be continuously output. As a result of the comparison of the internal voltage VCCI with the comparison voltage VCCE_REF, if the internal voltage VCCI is lower than the comparison voltage VCCE_REF, the standby mode enable signal EN_S may be disabled as a logic low level, and the active mode enable signal EN_A may be enabled as a logic high level and output.

[0074] Furthermore, when in the active mode, the enable signal generating circuit 220 may enable the active mode enable signal EN_A to a logic high level in response to the active signal ACT_EN and then output the enabled active mode enable signal EN_A.

[0075] Figure 7 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0076] Figure 8 is a waveform diagram of signals for describing a method of operating a memory device according to an embodiment of the present disclosure.

[0077] Will refer to Figures 1 to 8 A method of operating a memory system according to an embodiment of the present disclosure is described.

[0078] In an embodiment of the present disclosure, an example will be described in which an internal voltage is generated in a standby mode during a power-up period, and a test operation is performed by driving an internal circuit of a memory device using the generated internal voltage.

[0079] At step S710, an external power voltage VCCE may be provided to the memory system 1000. The memory device 1100 may receive the external power voltage VCCE and perform a power-on operation.

[0080] The power-on reset circuit 100 may generate and output a power-on reset signal POR, which flips when the external power supply voltage VCCE increases to above a set level during a power-on operation. In other words, the power-on reset signal POR may increase as the external power supply voltage VCCE increases, and transition to a low level when the external power supply voltage VCCE increases to above a set level. In addition, the power-on reset circuit 100 may generate and output an inverted power-on reset signal POR_B having a logic signal inverted from the power-on reset signal POR.

[0081] At step S720 , the reference voltage generating circuit 200 may generate a standby mode reference voltage VCCI_REF_S in response to the inverted power on reset signal POR_B.

[0082] For example, the mode changer 221 of the enable signal generating circuit 220 may output the comparison signal CS2 having a logic high level in response to the inverted power-on reset signal POR_B. The enable signal generator 222 may generate and output the standby mode enable signal EN_S in response to the comparison signal CS2 having a logic high level. The standby mode reference voltage generating circuit 230 may generate and output the standby mode reference voltage VCCI_REF_S in response to the standby mode enable signal EN_S.

[0083] At step S730, the internal voltage generating circuit 300 may generate the internal voltage VCCI using the generated reference voltage VCCI_REF in the standby mode. The internal circuit 400 may operate in the standby mode using the internal voltage VCCI. For example, the standby mode may be a waiting mode for receiving a command CMD from the memory controller 1200.

[0084] For example, the selection circuit 250 of the reference voltage generating circuit 200 may output the standby mode reference voltage VCCI_REF_S as the reference voltage VCCI_REF. The internal voltage generating circuit 300 may receive the standby mode reference voltage VCCI_REF_S as the reference voltage VCCI_REF and generate the internal voltage VCCI.

[0085] In step S740 , the reference voltage generating circuit 200 may detect whether there is an error in the internal voltage VCCI generated from the internal voltage generating circuit 300 .

[0086] For example, the comparison voltage generating circuit 210 may be enabled in response to the reset latch signal RESET_LAT, and receive the external power supply voltage VCCE and generate the comparison voltage VCCE_REF. The reset latch signal RESET_LAT may be a signal that is enabled in the power-on period of the memory device 1100 and disabled after the power-on period in response to the first reset signal RESET_1st to perform a reset operation of the memory device 1100, the first reset signal RESET_1st being the first received signal among the reset signals RESET received from an external device (e.g., the memory controller 1200) of the memory device 1100.

[0087] The enable signal generating circuit 220 may be enabled in response to the first reset signal RESET_1st, and compare the comparison voltage VCCE_REF with the internal voltage VCCI. As a result of the comparison, if the internal voltage VCCI is higher than the comparison voltage VCCE_REF, the enable signal generating circuit 220 may determine that the internal voltage VCC is normal. If the internal voltage VCCI is lower than the comparison voltage VCCE_REF, the enable signal generating circuit 220 may determine that there is an error in the internal voltage VCCI, and detect the error.

[0088] As a result of the detection at step S740 , if the internal voltage VCCI is lower than the comparison voltage VCCE_REF and it is determined that an error has occurred in the internal voltage VCCI (see “Yes”), an active mode reference voltage VCCI_REF_A is generated at step S750 .

[0089] For example, if the internal voltage VCCI is lower than the comparison voltage VCCE_REF, the enable signal generation circuit 220 may disable the standby mode enable signal EN_S and enable and output the active mode enable signal EN_A.

[0090] The active mode reference voltage generating circuit 240 may generate and output the active mode reference voltage VCCI_REF_A in response to the active mode enable signal EN_A.

[0091] At step S760, the internal voltage generating circuit 300 may generate the internal voltage VCCI using the generated reference voltage VCCI_REF in the active mode. The internal circuit 400 may operate in the standby mode using the internal voltage VCCI.

[0092] For example, the selection circuit 250 of the reference voltage generation circuit 200 may output the active mode reference voltage VCCI_REF_A as the reference voltage VCCI_REF. The internal voltage generation circuit 300 may receive the active mode reference voltage VCCI_REF_A as the reference voltage VCCI_REF and generate the internal voltage VCCI. Therefore, the internal circuit 400 may operate in the standby mode using the internal voltage VCCI generated using the active mode reference voltage VCCI_REF_A.

[0093] Thereafter, when a command CMD corresponding to a test operation is received from the memory controller 1200, the mode of the memory device 1100 may be changed from the standby mode to the active mode in response to the command CMD. The reference voltage generating circuit 200 may operate in the active mode in response to the activation signal ACT_EN. The internal voltage generating circuit 300 may receive the active mode reference voltage VCCI_REF_A as the reference voltage VCCI_REF, and generate and output the internal voltage VCCI. The internal circuit 400 may perform an overall operation, for example, a test operation, using the internal voltage VCCI.

[0094] As a result of the detection at step S740 , if the internal voltage VCCI is higher than the comparison voltage VCCE_REF and it is determined that there is no error in the internal voltage VCCI (see “No”), it is determined at step S770 whether the active mode has been enabled.

[0095] For example, in the case where a command CMD is received from the memory controller 1200 while the memory device 1100 is in the standby mode, the active mode may be enabled in response to the received command CMD. If the active mode is enabled, the active signal ACT_EN is enabled and generated.

[0096] If it is determined in step S770 that the active mode has been enabled (see “Yes”), the above operation of step S750 is performed.

[0097] If it is determined that the active mode is not enabled in step S770 (see "No"), the internal voltage generating circuit 300 may receive the standby mode reference voltage VCCI_REF_S as the reference voltage VCCI_REF and generate the internal voltage VCCI in step S780. Therefore, the internal circuit 400 may operate in the standby mode using the internal voltage VCCI.

[0098] As described above, according to an embodiment of the present disclosure, if there is an error in the internal voltage generated in the standby mode, the reference voltage generating circuit can automatically change the mode to the active mode and generate the reference voltage, and generate the internal voltage using the generated reference voltage in the active mode. Therefore, the standby mode of the memory device can be reliably operated.

[0099] Fig. 9 is a diagram illustrating a memory system 30000 according to an embodiment of the present disclosure.

[0100] Reference Fig. 9 , the memory system 30000 may be embodied in a cellular phone, a smart phone, a tablet computer, a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 configured to control the operation of the memory device 1100. The memory controller 1200 may control data access operations of the memory device 1100, such as a program operation, an erase operation, or a read operation, under the control of the processor 3100.

[0101] Data programmed in the memory device 1100 may be output through the display 3200 under the control of the memory controller 1200 .

[0102] The radio transceiver 3300 can send and receive radio signals through the antenna ANT. For example, the radio transceiver 3300 can change the radio signal received through the antenna ANT into a signal that can be processed in the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and send the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 can program the signal processed by the processor 3100 to the memory device 1100. In addition, the radio transceiver 3300 can change the signal output from the processor 3100 into a radio signal and output the changed radio signal to an external device through the antenna ANT. The input device 3400 can be used to input a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be embodied in a pointing device, a keypad or a keyboard such as a touch pad and a computer mouse. The processor 3100 may control the operation of the display 3200 so that data output from the memory controller 1200 , data output from the radio transceiver 3300 , or data output from the input device 3400 is output through the display 3200 .

[0103] In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be embodied as a part of the processor 3100 or as a chip provided separately from the processor 3100. In addition, the memory controller 1200 may be implemented as Figure 1 An example of a memory controller is shown in FIG. Memory device 1100 may be implemented as Figure 1 An example of a memory device is shown.

[0104] Fig.10 is a diagram illustrating a memory system 40000 according to an embodiment of the present disclosure.

[0105] Reference Fig.10 , the memory system 40000 may be embodied in a personal computer (PC), a tablet computer, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0106] The memory system 40000 may include a memory device 1100 and a memory controller 1200 configured to control a data processing operation of the memory device 1100 .

[0107] The processor 4100 may output data stored in the memory device 1100 through the display 4300 according to data input from the input device 4200. For example, the input device 4200 may be embodied in a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0108] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the memory controller 1200. In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be embodied as a part of the processor or a chip provided separately from the processor 4100. In addition, the memory controller 1200 may be implemented as Figure 1 Memory device 1100 may be implemented as Figure 1 An example of a memory device is shown.

[0109] Fig.11 is a diagram illustrating a memory system 50000 according to an embodiment of the present disclosure.

[0110] Reference Fig.11 , the memory system 50000 may be embodied in an image processing apparatus, for example, a digital camera, a portable phone equipped with a digital camera, a smart phone equipped with a digital camera, or a tablet computer equipped with a digital camera.

[0111] The memory system 50000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation, such as a program operation, an erase operation, or a read operation, of the memory device 1100 .

[0112] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal. The converted digital signal may be sent to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signal may be output through the display 5300 or stored in the memory device 1100 through the memory controller 1200. The data stored in the memory device 1100 may be output through the display 5300 under the control of the processor 5100 or the memory controller 1200.

[0113] In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be embodied as a part of the processor 5100 or as a chip provided separately from the processor 5100. In addition, the memory controller 1200 may be implemented as Figure 1 An example of a memory controller is shown in FIG. Memory device 1100 may be implemented as Figure 1 An example of a memory device is shown.

[0114] Fig.12 is a diagram illustrating a memory system 70000 according to an embodiment of the present disclosure.

[0115] Reference Fig.12 The memory system 70000 may be embodied in a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0116] The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In an implementation, the card interface 7100 may be a secure digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto.

[0117] The card interface 7100 may perform interface data exchange between the host 60000 and the memory controller 1200 according to the protocol of the host 60000. In an embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. Here, the card interface may refer to hardware that can support the protocol used by the host 60000, software installed in the hardware, or a signal transmission scheme.

[0118] When the memory system 70000 is connected to the host interface 6200 of the host 60000 such as a PC, a tablet computer, a digital camera, a digital audio player, a cellular phone, a console video game hardware, or a digital set-top box, the host interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100. In addition, the memory controller 1200 may be implemented as Figure 1 An example of a memory controller is shown in FIG. Memory device 1100 may be implemented as Figure 1 An example of a memory device is shown in .

[0119] In various embodiments of the present disclosure, when in standby mode, the memory device can generate an internal voltage using a standby reference voltage. When an error is detected from the internal voltage, the internal voltage is generated using an active mode reference voltage, so that the internal operation of the memory device can be reliably performed.

[0120] Although examples of embodiments of the present disclosure have been disclosed for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions and substitutions are possible. Therefore, the scope of the present disclosure must be defined by the appended claims and the equivalents of the claims, rather than by the above description.

[0121] CROSS-REFERENCE TO RELATED APPLICATIONS

[0122] This application claims the priority benefit of Korean Patent Application No. 10-2020-0057338 filed on May 13, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, the memory device comprising: a reference voltage generating circuit configured to generate a standby mode reference voltage in the standby mode and to generate and output an active mode reference voltage in the active mode; as well as an internal voltage generating circuit configured to receive one of the standby mode reference voltage and the active mode reference voltage from the reference voltage generating circuit and generate an internal voltage, When an error is detected from the internal voltage generated in the standby mode, the reference voltage generating circuit generates and outputs the active mode reference voltage, and the memory device is driven in the standby mode using the internal voltage generated using the active mode reference voltage.

2. The memory device according to claim 1, wherein: When the internal voltage generated in the standby mode is lower than the comparison voltage, the reference voltage generating circuit generates the active mode reference voltage in the standby mode and outputs the active mode reference voltage to the internal voltage generating circuit.

3. The memory device according to claim 2, wherein: The reference voltage generating circuit comprises: A comparison voltage generating circuit, the comparison voltage generating circuit being configured to generate the comparison voltage; an enable signal generating circuit configured to generate a standby mode enable signal in response to an inverted power-on reset signal when in the standby mode, and to generate an active mode enable signal in response to an activation signal when in the active mode; a standby mode reference voltage generating circuit configured to generate the standby mode reference voltage in response to the standby mode enable signal; and An active mode reference voltage generating circuit is configured to generate the active mode reference voltage in response to the active mode enable signal.

4. The memory device according to claim 3, wherein: The enable signal generating circuit receives and compares the comparison voltage and the internal voltage when in the standby mode, and based on the result of the comparison between the comparison voltage and the internal voltage, continuously enables and outputs the standby mode enable signal, or disables the standby mode enable signal and enables and outputs the active mode enable signal.

5. The memory device according to claim 4, wherein: in, When the internal voltage is greater than the comparison voltage, the enable signal generating circuit is continuously enabled and outputs the standby mode enable signal, and Wherein, when the internal voltage is less than the comparison voltage, the enable signal generating circuit disables the standby mode enable signal and enables and outputs the active mode enable signal.

6. The memory device according to claim 3, wherein: The reference voltage generating circuit further includes a selection circuit configured to output one of the standby mode reference voltage and the active mode reference voltage to the internal voltage generating circuit in response to the standby mode enable signal.

7. The memory device according to claim 3, wherein: The enable signal generating circuit comprises: a mode changer configured to generate a comparison signal having a first logic level in response to the inverted power-on reset signal when in the standby mode; and An enable signal generator is configured to enable and output the standby mode enable signal in response to the comparison signal, or to enable and output the active mode enable signal in response to the activation signal.

8. The memory device according to claim 7, wherein: The mode changer compares the comparison voltage with the internal voltage when in the standby mode, and maintains a logic level of the comparison signal at the first logic level or changes the logic level to a second logic level according to a result of the comparison.

9. The memory device according to claim 7, wherein: The mode changer comprises: a comparator configured to compare the comparison voltage and the internal voltage and output an output signal to a first internal node based on a result of the comparison; a latch coupled between the first internal node and a second internal node and configured to latch the output signal and output a comparison signal to the second internal node; and A transistor is coupled between an external power supply voltage terminal and the second internal node and is configured to set a logic level of the comparison signal to the first logic level in response to the inverted power-on reset signal.

10. The memory device according to claim 9, wherein: The comparator and the latch are enabled in response to a reset signal enabled for a predetermined time when in the standby mode.

11. The memory device according to claim 7, wherein: The enable signal generator comprises: a plurality of inverters configured to buffer the comparison signal and output the standby mode enable signal; and A logic gate is configured to generate and output the active mode enable signal in response to an inverted signal of the standby mode enable signal and the activation signal.

12. A memory device, the memory device comprising: a reference voltage generating circuit configured to generate a standby mode reference voltage in the standby mode and to generate and output an active mode reference voltage in the active mode; an internal voltage generating circuit configured to receive one of the standby mode reference voltage and the active mode reference voltage from the reference voltage generating circuit and generate an internal voltage; as well as an internal circuit configured to be driven using the internal voltage and to perform a programming operation, a reading operation, an erasing operation, and a testing operation, When an error is detected from the internal voltage generated in the standby mode, the reference voltage generating circuit automatically generates the active mode reference voltage in the standby mode, and the memory device is driven in the standby mode using the internal voltage generated using the active mode reference voltage.

13. The memory device according to claim 12, wherein: The reference voltage generating circuit comprises: a comparison voltage generating circuit configured to generate a comparison voltage; an enable signal generating circuit configured to generate a standby mode enable signal in response to an inverted power-on reset signal when in the standby mode, and to generate an active mode enable signal in response to an active signal when in the active mode, and to continuously enable and output the standby mode enable signal, or to disable the standby mode enable signal and enable and output the active mode enable signal based on a result of a comparison between the comparison voltage and the internal voltage; a standby mode reference voltage generating circuit configured to generate the standby mode reference voltage in response to the standby mode enable signal; and An active mode reference voltage generating circuit is configured to generate the active mode reference voltage in response to the active mode enable signal.

14. The memory device according to claim 13, in, When the internal voltage is greater than the comparison voltage, the enable signal generating circuit is continuously enabled and outputs the standby mode enable signal, and Wherein, when the internal voltage is less than the comparison voltage, the enable signal generating circuit disables the standby mode enable signal and enables and outputs the active mode enable signal.

15. The memory device of claim 13, wherein: The enable signal generating circuit comprises: a mode changer configured to generate a comparison signal having a first logic level in response to the inverted power-on reset signal when in the standby mode, or to generate a comparison signal having a second logic level based on a result of comparison of the internal voltage and the comparison voltage; and An enable signal generator is configured to enable and output the standby mode enable signal in response to the comparison signal, or to enable and output the active mode enable signal in response to the activation signal.

16. The memory device of claim 15, wherein: The mode changer comprises: a comparator configured to compare the comparison voltage and the internal voltage and output an output signal to a first internal node based on a result of the comparison; a latch coupled between the first internal node and a second internal node and configured to latch the output signal and output a comparison signal to the second internal node; and A transistor is coupled between an external power supply voltage terminal and the second internal node and is configured to set the logic level of the comparison signal to the first logic level in response to the inverted power-on reset signal.

17. The memory device of claim 15, wherein: The enable signal generator comprises: a plurality of inverters configured to buffer the comparison signal and output the standby mode enable signal; and A logic gate is configured to generate and output the active mode enable signal in response to an inverted signal of the standby mode enable signal and the activation signal.

18. A method of operating a memory device, the method comprising the steps of: generating a standby mode reference voltage when in standby mode; generating an internal voltage using the standby mode reference voltage; detecting whether there is an error in the internal voltage by comparing the internal voltage with a comparison voltage; disabling the operation of generating the standby mode reference voltage and generating an active mode reference voltage when an error is detected from the internal voltage; as well as The internal voltage is generated using the active mode reference voltage, and the memory device is driven in the standby mode with the internal voltage generated using the active mode reference voltage.

19. The method according to claim 18, further comprising the steps of: When no error is detected in the step of detecting an error from the internal voltage, determining whether an active mode is enabled; as well as When the active mode is enabled, the internal voltage is generated using the active mode reference voltage.

20. The method according to claim 18, wherein: The memory device is driven in a waiting mode for receiving a command input from an external device using the internal voltage generated when in the standby mode.

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