Chip packaging component, electronic device and manufacturing method of chip packaging component

Abstract

The present application discloses a chip packaging component, an electronic device and a method for manufacturing a chip packaging component. The chip packaging component includes a packaging substrate, a chip and a heat dissipation part. The packaging substrate includes an upper conductive layer, a lower conductive layer and a conductive part connected between the upper conductive layer and the lower conductive layer. The chip includes a front electrode and a back electrode arranged opposite to each other. The chip is embedded in the packaging substrate. The conductive part surrounds the chip. The front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer. The heat dissipation part is connected to the surface of the upper conductive layer away from the chip. The upper conductive layer, the lower conductive layer and the conductive part all have thermal conductivity. The present application sets the chip to be connected to the upper conductive layer and the lower conductive layer of the packaging substrate, so that the heat generated by the chip can be dissipated by bidirectional conduction, and the heat dissipation part is set on the upper conductive layer, so that the chip packaging component can achieve a better heat dissipation effect.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a chip packaging component, an electronic device, and a method for manufacturing a chip packaging component. Background Art

[0002] As electronic devices continue to develop in the direction of being lighter, thinner and smaller, the integration of chip packaging components in electronic devices is getting higher and higher. The industry has gradually spawned high-density integrated embedded packages that bury chips in substrates or packages. However, the above-mentioned chip packaging components usually have more serious heat dissipation problems. The heat generated by the chip cannot be effectively dissipated, which causes certain safety hazards. Summary of the invention

[0003] The purpose of the present application is to provide a chip packaging component, an electronic device and a method for manufacturing a chip packaging component, wherein the chip in the chip packaging component can effectively dissipate heat to effectively reduce safety hazards.

[0004] In order to achieve the purpose of this application, the following technical solutions are provided:

[0005] In the first aspect, the present application provides a chip packaging component, which includes a packaging substrate, a chip and a heat dissipation part, wherein the packaging substrate includes an upper conductive layer, a lower conductive layer and a conductive part connected between the upper conductive layer and the lower conductive layer; the chip includes a front electrode and a back electrode arranged in opposite directions, the chip is embedded in the packaging substrate, the conductive part surrounds the chip, the front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer; the heat dissipation part is connected to the surface of the upper conductive layer away from the chip; the upper conductive layer, the lower conductive layer and the conductive part all have thermal conductivity. It can be understood that the conductive part, the lower conductive layer and the upper conductive layer all have thermal conductivity to effectively conduct the heat generated by the chip, thereby realizing the heat dissipation function. In addition, the conductive part, the lower conductive layer and the upper conductive layer jointly surround the chip, thereby realizing the corresponding chip packaging function. In other words, the conductive part, the upper conductive layer and the lower conductive layer are connected to each other and enclosed to form a receiving cavity, and the receiving cavity is used to accommodate the chip. The chip includes a front electrode and a back electrode arranged in opposite directions, the chip is embedded in the packaging substrate, and the front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer. It is understandable that the chip will generate a large amount of heat when working. The generated heat can not only be conducted to the lower conductive layer through the front electrode for heat dissipation, but also be conducted to the upper conductive layer through the back electrode for heat dissipation, thereby realizing a two-way heat dissipation function, so that the chip packaging assembly can achieve a better heat dissipation effect. The heat dissipation part is connected to the surface of the upper conductive layer away from the chip. It is understandable that compared with the upper conductive layer, the heat dissipation part has a larger heat exchange surface area, so it has a stronger heat dissipation function. The heat generated by the chip can be conducted to the heat dissipation part through the upper conductive layer to achieve a better heat dissipation effect. It can also be understood that since the conductive part is respectively connected to the upper conductive layer and the lower conductive layer, part of the heat conducted to the lower conductive layer can also be conducted to the heat dissipation part through the conductive part and the upper conductive layer to further improve the heat dissipation effect.

[0006] The chip packaging assembly provided in the present application is configured to connect the chip to the upper conductive layer and the lower conductive layer of the packaging substrate, so that the heat generated by the chip can be dissipated by bidirectional conduction, and a heat dissipation part is provided on the upper conductive layer, so that the chip packaging assembly can achieve a better heat dissipation effect.

[0007] In one embodiment, the front electrode is in contact with the upper conductive layer. When the front electrode of the chip is in direct contact with the upper conductive layer, the corresponding circuit transmission function can be effectively satisfied, and the heat generated by the chip can be effectively transferred to the upper conductive layer via the front electrode for heat dissipation. Similarly, the back electrode of the chip can also be in contact with the lower conductive layer, so that the heat generated by the chip can be effectively transferred to the lower conductive layer via the back electrode for bidirectional heat dissipation.

[0008] In one embodiment, the heat dissipation part includes a plurality of heat dissipation monomers, and the plurality of heat dissipation monomers are all connected to the upper conductive layer, and the plurality of heat dissipation monomers are arranged at intervals. It is understandable that the heat dissipation part can be a fin-type structure, and by arranging a plurality of heat dissipation monomers spaced apart from each other, the heat exchange surface area can be effectively increased, so that the heat dissipation part has a better heat dissipation effect, thereby avoiding safety hazards caused by poor heat dissipation of the chip packaging assembly. It should be noted that the structure of the heat dissipation part includes but is not limited to a fin-type structure, and can also be any other structure with better heat dissipation function, and the structure of the heat dissipation part is not specifically limited here.

[0009] In one embodiment, the extension direction of each heat dissipation unit is arranged at an angle with the extension direction of the upper conductive layer. It can be understood that under the above structure, there is enough heat dissipation space between the heat dissipation unit and the upper conductive layer, thereby achieving a better heat dissipation effect.

[0010] In one embodiment, all the heat dissipation units extend in the same direction. It is understandable that, under the above structure, the overall structure of the heat dissipation unit is relatively neat and simple, thereby effectively simplifying the processing technology and improving the process production efficiency while ensuring the corresponding heat dissipation effect.

[0011] In one embodiment, the extension direction of some of the heat dissipation monomers is the first direction, and the extension direction of some of the heat dissipation monomers is the second direction, and the first direction and the second direction are different. It is understandable that in some cases, a refrigeration component may also be provided on the periphery of the chip packaging assembly. For example, corresponding water cooling components or air cooling components are provided in the first direction and the second direction of the heat dissipation portion, respectively. In this case, some of the heat dissipation monomers can be arranged to extend in the first direction, and some of the heat dissipation monomers can be arranged to extend in the second direction, so that the heat dissipation monomers are close to the refrigeration component to achieve a better heat dissipation effect.

[0012] In one embodiment, the heat dissipation unit is in a flat plate or column shape. It is understandable that the heat dissipation unit can be designed to be in a flat plate or column shape according to actual production requirements. The production process of the heat dissipation unit in the above shape is relatively simple and can effectively meet the corresponding heat dissipation function.

[0013] In one embodiment, the heat dissipation portion and the upper conductive layer are an integrated structure. It is understandable that when the heat dissipation portion and the upper conductive layer are split structures, the heat dissipation portion needs to be fixedly connected to the upper conductive layer by corresponding fasteners. Therefore, installing the heat dissipation portion on the upper conductive layer will bring additional thermal resistance, thereby affecting the heat dissipation performance of the chip packaging assembly. By designing the heat dissipation portion and the upper conductive layer as an integrated structure, the additional thermal resistance can be effectively removed, thereby achieving a better heat dissipation effect, and the board loading steps can also be reduced, effectively improving the production efficiency of the chip packaging assembly. It should be noted that the heat dissipation portion and the upper conductive layer can also be formed into an integrated structure by electroplating or other methods, and the method of forming the integrated structure is not specifically limited here.

[0014] In one embodiment, the conductive part, the upper conductive layer and the lower conductive layer are all made of metal materials. It is understandable that since the conductive part, the upper conductive layer and the lower conductive layer surround the chip, when the three are made of metal materials, the packaging substrate composed of the three can be regarded as a metal shielding cover, which can effectively block the electromagnetic field between the chip and the external environment, thereby effectively improving the anti-interference ability of the chip packaging component to achieve a better electromagnetic shielding effect. It is also understandable that in the embodiment of the present application, the packaging substrate is made of metal material, has better moisture-proof performance, can effectively prevent moisture intrusion, thereby improving the service life of the chip packaging component in a humid environment. In addition, the packaging substrate has a high structural strength, so that the chip packaging component is not easy to deform during use, thereby effectively avoiding structural damage to the chip due to stress.

[0015] In one embodiment, the conductive part, the upper conductive layer, the lower conductive layer and the heat dissipation part are all made of metal copper. It is understandable that copper has good electrical and thermal conductivity. When the conductive part, the upper conductive layer, the lower conductive layer and the heat dissipation part are made of copper material, the chip packaging assembly composed of the above components can meet the corresponding circuit transmission function and heat conduction function at the same time, so that it can have a better heat dissipation effect while working normally.

[0016] In one embodiment, the chip packaging assembly further includes an insulating member, which is disposed between the chip and the conductive portion to isolate the chip from the conductive portion. It is understandable that the conductive portion generally also has conductive properties. When the chip is in direct contact with the conductive portion, short circuits or other circuit problems are likely to occur, resulting in abnormal functions of the chip packaging assembly. Therefore, by providing an insulating member between the chip and the conductive portion, the chip and the conductive portion can be effectively isolated, thereby effectively ensuring the normal functions of the chip packaging assembly. It is also understandable that, usually, the volume of the accommodating cavity is greater than the volume of the chip, and the insulating member is filled in the gap between the chip and the conductive portion to effectively fix the chip, thereby improving the structural stability of the chip packaging assembly. The insulating member includes but is not limited to being made of resin materials, and can also be made of any other material with insulating properties, as long as it can meet the corresponding insulating function, and is not specifically limited here.

[0017] In one embodiment, the packaging substrate further includes at least one partition, the partition is connected to the conductive part and surrounded by the conductive part, and the partition and the conductive part together surround the plurality of chips, and each adjacent two chips are isolated by the partition. In other words, the partition is housed in the accommodating cavity and connected to the conductive part to divide the accommodating cavity into a plurality of sub-accommodating cavities; the number of chips is multiple, and each sub-accommodating cavity accommodates a chip. By providing at least one partition to form a plurality of sub-accommodating cavities, the packaging substrate can encapsulate a plurality of chips at the same time, so that the chip packaging assembly can effectively meet the multi-chip working requirements. It should be noted that the chips in each sub-accommodating cavity are connected to the upper conductive layer and the lower conductive layer, so that each chip can perform bidirectional conduction heat dissipation to achieve a better heat dissipation effect. In addition, the conductive part, the partition, the upper conductive layer and the lower conductive layer encapsulate the plurality of chips separately, so that each chip can be subjected to moisture-proof treatment and electromagnetic shielding treatment.

[0018] In one embodiment, the insulating member is disposed between the chip and the conductive portion and between the chip and the partition portion to isolate the chip from the conductive portion and the chip from the partition portion. In other words, the insulating member is disposed in each of the sub-accommodating cavities, and the insulating member is disposed between the chip and the conductive portion and between the chip and the partition portion to isolate the chip from the conductive portion and the chip from the partition portion. By providing insulating members in each sub-accommodating cavity, each chip is isolated from the conductive portion and the partition portion, thereby effectively avoiding short circuits or other circuit problems, thereby ensuring the normal functioning of the chip packaging assembly. In addition, the presence of multiple insulating members can limit and fix multiple chips, thereby effectively preventing the chips from shifting in the packaging substrate.

[0019] In one embodiment, at least one of the partitions includes a first partition and a second partition, the first partition extends along a third direction, and the second partition extends along a fourth direction; the third direction and the fourth direction are both perpendicular to the thickness direction of the chip package component, and the third direction and the fourth direction are arranged at an angle. It should be noted that the number of partitions and the relative positional relationship between the multiple partitions can be multiple, which are determined according to actual production requirements and are not specifically limited here.

[0020] In one embodiment, the first partition includes a first sub-partition and a second sub-partition spaced apart from each other, and the first sub-partition and the second sub-partition both extend along the third direction; the second partition includes a third sub-partition and a fourth sub-partition spaced apart from each other, and the third sub-partition and the fourth sub-partition both extend along the fourth direction. By arranging a plurality of sub-partitions side by side to form a partition, the structural strength of the partition is greatly improved, thereby effectively improving the overall structural stability of the chip packaging assembly.

[0021] In one embodiment, the conductive part, the upper conductive layer and the lower conductive layer together form an integrated structure. The conductive part, the upper conductive layer and the lower conductive layer can form an integrated structure by electroplating, and the three together constitute a packaging substrate. When the packaging substrate is an integrated structure, the structure of the packaging substrate is relatively stable, thereby effectively improving the overall structural stability of the chip packaging assembly. It should be noted that the conductive part, the upper conductive layer and the lower conductive layer can also be formed into an integrated structure by other methods, and the method of forming the integrated structure is not specifically limited here.

[0022] In a second aspect, the present application provides an electronic device, comprising a mainboard and a chip packaging assembly as described in any embodiment of the first aspect, wherein the mainboard comprises a board body and a circuit structure arranged on the surface of the board body, the chip packaging assembly is arranged on a side of the circuit structure away from the board body, and a connecting member is further provided between the mainboard and the chip packaging assembly, the connecting member connecting the lower conductive layer and the circuit structure so as to electrically connect the chip packaging assembly to the mainboard.

[0023] The electronic device provided in the present application electrically connects the chip packaging component to the mainboard to meet the corresponding circuit transmission function. Moreover, since the electronic device provided in the present application adopts the chip packaging component provided in the present application, the electronic device also has better heat dissipation performance, moisture-proof performance and electromagnetic shielding performance, and its structural stability is strong, which can effectively prevent the chip from being damaged due to stress.

[0024] In one embodiment, the packaging substrate, the main board and the connector in the chip packaging assembly together surround the chip to isolate the chip from the outside world. Under the above structure, the packaging substrate, the main board and the connector together form a complete moisture-proof barrier to effectively block the intrusion of moisture, thereby achieving a better moisture-proof effect. It should be noted that there can be many types of connectors, as long as they can meet the corresponding conductive and moisture-proof functions. Exemplarily, the connector can be solder paste, that is, the lower conductive layer and the circuit structure are connected by soldering to achieve electrical connection between the main board and the chip packaging assembly.

[0025] In a third aspect, the present application provides a method for manufacturing a chip packaging component, which is used to manufacture the chip packaging component described in the first aspect, and the manufacturing method includes: providing a carrier; forming a conductive part and a limiting part on the carrier, the conductive part surrounding the limiting part and being spaced from the limiting part, the conductive part enclosing to form a accommodating cavity, forming a first space between the conductive part and the limiting part, and the limiting part enclosing to form a second space; arranging an insulating structure in the first space and the second space; removing the carrier, the limiting part and the insulating structure located in the second space, retaining the insulating structure located in the first space to form an insulating member, and retaining the conductive part; placing a chip in the space surrounded by the insulating member; forming an upper conductive layer on one side of the chip and the conductive part, and forming a lower conductive layer on the opposite side; forming a heat dissipation part on the surface of the upper conductive layer away from the chip, and processing the lower conductive layer to form a corresponding circuit layer.

[0026] The chip packaging assembly provided in the present application can be manufactured through the manufacturing method of the chip packaging assembly provided in the present application, and the chip packaging assembly has better heat dissipation performance, moisture resistance and electromagnetic shielding performance, and has strong structural stability, which can effectively prevent the chip from being damaged by stress.

[0027] In one embodiment, "forming a conductive part and a stopper on the carrier" includes: covering a portion of the surface of the carrier with a first dry film; forming the conductive part and the stopper by electroplating at a position not covered with the first dry film; and removing the first dry film. It can be understood that by dividing the area on the surface of the carrier, the first dry film is covered at a position where the conductive part and the stopper are not needed, and the first dry film can prevent the electroplated metal from contacting the carrier; the first dry film is not covered at a position where the conductive part and the stopper are needed to be formed, so as to expose the carrier at this position, thereby forming the conductive part and the stopper by electroplating on the surface of the carrier at this position.

[0028] In one embodiment, "arranging an insulating structure in the first space and the second space" includes: filling the first space and the second space with insulating material and performing a pressing process to form the insulating structure; grinding the conductive portion and the limiting portion to make the insulating structure, the conductive portion and the limiting portion flush in height along the thickness direction of the carrier. Insulating materials include, but are not limited to, resin materials, and can also be any other material with insulating properties, which is not specifically limited here. It is understandable that by grinding, the height dimensions of the insulating structure, the conductive portion and the limiting portion are made the same, so that when the upper conductive layer is subsequently formed, the surface to which the upper conductive layer is attached is smoother, which is conducive to the processing and forming of the upper conductive layer.

[0029] In one embodiment, "removing the carrier, the limiting portion and the insulating structure located in the second space" includes: etching the carrier to remove the carrier; covering the surface of the conductive portion with a second dry film; etching the limiting portion not covered by the second dry film to remove the limiting portion and the insulating structure located in the second space; removing the second dry film. It is understandable that the carrier does not exist in the finished product and is an intermediate structure in the manufacturing process, so the carrier can be removed by etching first. It is also understandable that the limiting portion does not exist in the finished product either, and its function is to form a first space between the conductive portion and the conductive portion for forming an insulating member, so the limiting portion also needs to be removed. Among them, the second dry film is used to block the erosion of chemical agents. After the carrier is etched away, the conductive portion can be effectively prevented from being etched by covering the surface of the conductive portion with the second dry film, thereby retaining the conductive portion. It is also understandable that the limiting portion not protected by the dry film can also be removed by chemical etching, and the insulating structure located in the second space will also be detached and removed because there is no limiting portion and the carrier fixing it. The remaining insulating structure in the first space forms an insulating member for fixing the chip and isolating the chip from the conductive part.

[0030] In one embodiment, the process of "forming a conductive portion and a limiting portion on the carrier" further includes: at least one partition is also formed on the carrier, the partition is connected to the conductive portion, the partition divides the accommodating cavity into a plurality of sub-accommodating cavities, the limiting portion is disposed in the sub-accommodating cavity and is spaced from the conductive portion and the partition, the first space is formed between the limiting portion, the conductive portion and the partition, and the second space is enclosed by the limiting portion. It is understandable that when the manufactured chip packaging assembly needs to package multiple chips, a partition needs to be provided, and accordingly, each step of the manufacturing method provided in the present application is changed accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1a is a schematic diagram of the structure of a chip packaging assembly provided in an embodiment of the present application;

[0032] Figure 1b is a schematic diagram of the arrangement of the heat dissipation unit and the upper conductive layer in an embodiment;

[0033] Figure 1c is a schematic diagram of the arrangement of the heat dissipation unit and the upper conductive layer in another embodiment;

[0034] Figure 1d is a schematic diagram of a top view of the structure of a heat dissipation unit and an upper conductive layer in an embodiment;

[0035] Figure 1e is a schematic diagram of a top view of the structure of a heat dissipation unit and an upper conductive layer in another embodiment;

[0036] Figure 2 is a schematic structural diagram of a chip packaging assembly according to an embodiment;

[0037] Figure 3 yes Figure 2 A schematic top view of a conductive portion and a partition portion in the chip package assembly shown;

[0038] Figure 4 is a schematic structural diagram of a chip packaging assembly according to an embodiment;

[0039] Figure 5 yes Figure 4 A schematic top view of a conductive portion and a partition portion in the chip package assembly shown;

[0040] Figure 6 It is a schematic diagram of the assembly structure of the mainboard and chip packaging components;

[0041] Figure 7 It is a schematic diagram of a process of manufacturing a chip packaging assembly provided in an embodiment of the present application;

[0042] Figure 8 is a schematic structural diagram of a carrier board of an embodiment;

[0043] Figure 9a is a schematic diagram of a structure in which a first dry film is covered on the surface of a carrier;

[0044] Figure 9b is a schematic diagram of a structure in which a conductive portion and a limiting portion are formed at a position not covered by the first dry film;

[0045] Fig.9c is a schematic diagram of the combined structure of the carrier, the conductive part and the limiting part after the first dry film is removed;

[0046] Fig.10a is a schematic diagram of a structure in which an insulating structure is formed in a first space and a second space;

[0047] Fig.10b It is a schematic diagram of the combined structure after the conductive part and the limiting part are ground flat;

[0048] Fig.11a It is a schematic diagram of the combined structure of the insulating structure, the conductive part and the limiting part after the carrier plate is removed;

[0049] Fig.11b is a schematic diagram of a structure in which a second dry film is covered on the surface of the conductive portion;

[0050] Fig.11c is a schematic diagram of the combined structure of the conductive part, the insulating part and the second dry film after etching;

[0051] Fig.11d is a schematic diagram of the combined structure of the conductive part and the insulating part after the second dry film is removed;

[0052] Fig.12 is Fig.11d A schematic diagram of a combined structure in which a chip is installed;

[0053] Fig.13 is Fig.12 A schematic diagram of a combined structure in which an upper conductive layer and a lower conductive layer are formed on the combined structure shown;

[0054] Fig.14 is a schematic structural diagram of a chip packaging assembly according to an embodiment;

[0055] Fig.15 It is a structural schematic diagram of various manufacturing steps of a chip packaging component of another embodiment. DETAILED DESCRIPTION

[0056] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0057] First see Figure 1a An embodiment of the present application provides a chip packaging component 1000 , which includes a packaging substrate 100 , a chip 200 and a heat dissipation portion 300 .

[0058] The packaging substrate 100 includes an upper conductive layer 120, a lower conductive layer 130 and a conductive portion 110 connected between the upper conductive layer 120 and the lower conductive layer 130, and the packaging substrate 100 formed by the three is used to accommodate the chip 200. In other words, the conductive portion 110, the upper conductive layer 120 and the lower conductive layer 130 are connected to each other and enclosed to form a receiving cavity 101, and the receiving cavity 101 is used to accommodate the chip 200. Among them, the lower conductive layer 130 is usually processed into a circuit layer to realize the corresponding circuit transmission function; the upper conductive layer 120 can be processed into a circuit layer, or it can be a complete plate-like structure, which is not specifically limited here. It can be understood that the upper conductive layer 120, the lower conductive layer 130 and the conductive portion 110 all have thermal conductivity to effectively conduct the heat generated by the chip 200, thereby realizing the heat dissipation function.

[0059] The chip 200 includes a front electrode 210 and a back electrode 220 which are arranged in opposite directions. The chip 200 is embedded in the package substrate 200, and the conductive part 110 surrounds the chip 200. In other words, the chip 200 is accommodated in the accommodating cavity 101. The front electrode 210 of the chip 200 is connected to the lower conductive layer 130, and the back electrode 220 is connected to the upper conductive layer 120. It can be understood that the chip 200 generates a large amount of heat when working. The generated heat can not only be conducted to the lower conductive layer 130 through the front electrode 210 for heat dissipation, but also be conducted to the upper conductive layer 120 through the back electrode 220 for heat dissipation, thereby realizing a two-way heat dissipation function, so that the chip package component 1000 achieves a better heat dissipation effect.

[0060] The heat dissipation part 300 is connected to the surface of the upper conductive layer 120 away from the chip 200. It can be understood that, compared with the upper conductive layer 120, the heat dissipation part 300 has a larger heat exchange surface area, thereby having a stronger heat dissipation function, and the heat generated by the chip 200 can be conducted to the heat dissipation part 300 through the upper conductive layer 120 to achieve a better heat dissipation effect. It can also be understood that since the conductive part 110 is respectively connected to the upper conductive layer 120 and the lower conductive layer 130, part of the heat conducted to the lower conductive layer 130 can also be conducted to the heat dissipation part 300 through the conductive part 110 and the upper conductive layer 120 to further improve the heat dissipation effect.

[0061] The chip packaging component 1000 provided in the embodiment of the present application is configured to connect the chip 200 with the upper conductive layer 120 and the lower conductive layer 130 of the packaging substrate 100, so that the heat generated by the chip 200 can be dissipated by bidirectional conduction, and a heat dissipation portion 300 is provided on the upper conductive layer 120, so that the chip packaging component 1000 can achieve a better heat dissipation effect.

[0062] In a possible embodiment, the front electrode 210 is in contact with the upper conductive layer 120. It is understandable that when the front electrode 210 of the chip 200 is in direct contact with the upper conductive layer 120, the corresponding circuit transmission function can be effectively satisfied, and the heat generated by the chip 200 during operation can be effectively conducted to the upper conductive layer 120 via the front electrode 210 for heat dissipation. Similarly, the back electrode 220 of the chip 200 can also be in contact with the lower conductive layer 130, so that the heat generated by the chip can be effectively conducted to the lower conductive layer 130 via the back electrode 220 for bidirectional heat dissipation.

[0063] In a possible embodiment, the conductive part 110, the upper conductive layer 120 and the lower conductive layer 130 are all made of metal materials. It can be understood that since the conductive part 110, the upper conductive layer 120 and the lower conductive layer 130 surround the chip 200, when the three are made of metal materials, the packaging substrate 100 composed of the three can be regarded as a metal shielding cover, which can effectively block the electromagnetic field between the chip 200 and the external environment, thereby effectively improving the anti-interference ability of the chip packaging component 1000 to achieve a better electromagnetic shielding effect. It can also be understood that in the embodiment of the present application, the packaging substrate 100 is made of metal material, has better moisture-proof performance, can effectively prevent moisture intrusion, thereby improving the service life of the chip packaging component 1000 in a humid environment. In addition, the packaging substrate 100 has a high structural strength, so that the chip packaging component 1000 is not easy to deform during use, thereby effectively avoiding structural damage to the chip 200 due to stress.

[0064] The conductive part 110, the upper conductive layer 120 and the lower conductive layer 130 together form an integrated structure. It is understandable that the conductive part 110, the upper conductive layer 120 and the lower conductive layer 130 can form an integrated structure by electroplating, and the three together constitute the packaging substrate 100. When the packaging substrate 100 is an integrated structure, the structure of the packaging substrate 100 is relatively stable, thereby effectively improving the overall structural stability of the chip packaging component 1000. It should be noted that the conductive part 110, the upper conductive layer 120 and the lower conductive layer 130 can also be formed into an integrated structure by other methods, and the method of forming the integrated structure is not specifically limited here.

[0065] In a possible embodiment, the heat dissipation portion 300 and the upper conductive layer 120 form an integrated structure. It is understandable that when the heat dissipation portion 300 and the upper conductive layer 120 are split structures, the heat dissipation portion 300 needs to be fixedly connected to the packaging substrate 100 by corresponding fasteners. Therefore, installing the heat dissipation portion 300 on the upper conductive layer 120 will bring additional thermal resistance, thereby affecting the heat dissipation performance of the chip packaging component 1000. In this embodiment, by designing the heat dissipation portion 300 and the upper conductive layer 120 as an integrated structure, the additional thermal resistance can be effectively removed, thereby achieving a better heat dissipation effect, and the boarding steps can also be reduced, effectively improving the production efficiency of the chip packaging component 1000. It should be noted that the heat dissipation portion 300 and the upper conductive layer 120 can also be formed into an integrated structure by electroplating or other methods, and the method of forming the integrated structure is not specifically limited here.

[0066] In a possible embodiment, the heat dissipation portion 300 includes a plurality of heat dissipation monomers 310, and the plurality of heat dissipation monomers 310 are all connected to the upper conductive layer 120, and the plurality of heat dissipation monomers 310 are arranged at intervals. It is understandable that in this embodiment, the heat dissipation portion 300 is a fin-type structure, and a plurality of heat dissipation monomers 310 are arranged to effectively increase the heat exchange surface area, so that the heat dissipation portion 300 has a better heat dissipation effect, thereby avoiding safety hazards caused by poor heat dissipation of the chip packaging component 1000. It should be noted that the structure of the heat dissipation portion 300 includes but is not limited to a fin-type structure, and can also be any other structure with better heat dissipation function, and the structure of the heat dissipation portion 300 is not specifically limited here.

[0067] like Figure 1a In a possible embodiment, the extension direction of each heat dissipation unit 310 is arranged at an angle with the extension direction of the upper conductive layer 120. It can be understood that under the above structure, there is enough heat dissipation space between the heat dissipation unit 310 and the upper conductive layer 120, so as to achieve a better heat dissipation effect.

[0068] Please also read Figure 1b and Figure 1c ,like Figure 1b In a possible embodiment, all heat dissipation units 310 extend in the same direction. It is understandable that, under the above structure, the overall structure of the heat dissipation unit 300 is relatively neat and simple, thereby effectively simplifying the processing technology and improving the process production efficiency while ensuring the corresponding heat dissipation effect.

[0069] like Figure 1cIn a possible embodiment, the extension direction of part of the heat dissipation monomer 310 is the first direction 801, and the extension direction of part of the heat dissipation monomer 310 is the second direction 802, and the first direction 801 and the second direction 802 are different. It can be understood that, in some cases, a refrigeration component 500 may also be provided on the periphery of the chip packaging assembly 1000. For example, corresponding water cooling components or air cooling components are provided in the first direction 801 and the second direction 802 of the heat dissipation portion 300, respectively. In this case, part of the heat dissipation monomer 310 can be set to extend along the first direction 801, and part of the heat dissipation monomer 310 can be set to extend along the second direction 802, so that the heat dissipation monomer 310 is close to the refrigeration component 500 to achieve a better heat dissipation effect.

[0070] Please also read Figure 1d and Figure 1e It is understandable that the heat dissipation unit 310 can have various shapes as long as it can have the heat dissipation function. Figure 1d In one possible embodiment, the heat dissipation unit 310 is in the shape of a flat plate; Figure 1e In another possible embodiment, the heat dissipation unit 310 is columnar. It should be noted that the structures of the heat dissipation units 310 in the above two shapes are relatively simple, which can effectively reduce the processing cost and can also meet the corresponding heat dissipation function.

[0071] In a possible embodiment, the conductive part 110, the upper conductive layer 120, the lower conductive layer 130 and the heat dissipation part 300 are all made of copper. It is understandable that copper has good electrical and thermal conductivity. When the conductive part 110, the upper conductive layer 120, the lower conductive layer 130 and the heat dissipation part 300 are made of copper material, the chip package assembly 1000 composed of the above components can meet the corresponding circuit transmission function and heat conduction function, so that it can have a better heat dissipation effect while working normally.

[0072] In a possible embodiment, the chip package assembly 1000 further includes an insulating member 400, which is disposed between the chip 200 and the conductive portion 110 to isolate the chip 200 from the conductive portion 110. It is understandable that the conductive portion 110 generally also has a conductive property. When the chip 200 is in direct contact with the conductive portion 110, a short circuit or other circuit problems are likely to occur, thereby causing abnormal functions of the chip package assembly 1000. Therefore, by arranging the insulating member 400 between the chip 200 and the conductive portion 110, the chip 200 and the conductive portion 110 can be effectively isolated, thereby effectively ensuring the normal functions of the chip package assembly 1000. It is also understandable that, generally, the volume of the accommodating cavity 101 is greater than the volume of the chip 200, and the insulating member 400 is filled in the gap between the chip 200 and the conductive portion 110 to effectively fix the chip 200, thereby improving the structural stability of the chip package assembly 1000. In a specific embodiment, the insulating member 400 is made of a resin material to play a corresponding insulating function. It should be noted that the insulating member 400 may also be made of any other material having insulating properties, which is not specifically limited here.

[0073] Please also read Figure 2 and Figure 3 ,like Figure 2 In a possible embodiment, the packaging substrate 100 further includes at least one partition 140, the partition 140 is connected to the conductive portion 110 and surrounded by the conductive portion 110, and the partition 140 and the conductive portion 110 jointly surround a plurality of chips 200, and each two adjacent chips 200 are isolated by the partition. In other words, the partition 140 is received in the receiving cavity 101 and connected to the conductive portion 110 to divide the receiving cavity 101 into a plurality of sub-receiving cavities 111; the number of chips 200 is multiple, and each sub-receiving cavity 111 contains one chip 200. It can be understood that by providing at least one partition 140 to form a plurality of sub-receiving cavities 111, the packaging substrate 100 can simultaneously package a plurality of chips 200, so that the chip packaging assembly 1000 provided in this embodiment can effectively meet the working requirements of multiple chips 200. It should be noted that the chip 200 in each sub-accommodation cavity 111 is connected to the upper conductive layer 120 and the lower conductive layer 130, so that each chip 200 can perform bidirectional conduction heat dissipation to achieve a better heat dissipation effect. In addition, the conductive part 110, the partition part 140, the upper conductive layer 120 and the lower conductive layer 130 respectively encapsulate the multiple chips 200, so that each chip 200 can be treated with moisture-proof and electromagnetic shielding.

[0074] like Figure 3In a specific embodiment, at least one partition 140 includes a first partition 141 and a second partition 142, the first partition 141 extends along a third direction 901, and the second partition 142 extends along a fourth direction 902, wherein the third direction 901 and the fourth direction 902 are both perpendicular to the thickness direction of the chip packaging component 1000, and there is an angle between the third direction 901 and the fourth direction 902, the first partition 141 and the second partition 142 divide the accommodating cavity 101 into four sub-accommodating cavities 111, and each sub-accommodating cavity 111 is provided with a chip 200, so that the chip packaging component 1000 provided in this embodiment accommodates four chips 200. It should be noted that the number of partitions 140 and the relative positional relationship between the plurality of partitions 140 can be multiple, which are determined according to actual production requirements and are not specifically limited here.

[0075] In a possible embodiment, the insulating member 400 is disposed between the chip 200 and the conductive portion 110 and between the chip 220 and the partition 140 to isolate the chip 200 from the conductive portion 110 and the chip 200 from the partition 140. In other words, an insulating member 400 is disposed in each sub-accommodating cavity 111, and the insulating member 400 is disposed between the chip 200 and the conductive portion 110 and between the chip 200 and the partition 140 to isolate the chip 200 from the conductive portion 110 and the chip 200 from the partition 140. It can be understood that by disposing the insulating member 400 in each sub-accommodating cavity 111, each chip 200 is isolated from the conductive portion 110 and the partition 140, thereby effectively avoiding short circuits or other circuit problems, so as to ensure the normal function of the chip packaging assembly 1000. In addition, the presence of multiple insulating members 400 can limit and fix multiple chips 200, thereby effectively preventing the chip 200 from shifting in the packaging substrate 100.

[0076] Please also read Figure 4 and Figure 5 In a possible embodiment, the first partition 141 includes a first sub-partition 1411 and a second sub-partition 1412 spaced apart from each other, and the first sub-partition 1411 and the second sub-partition 1412 both extend along the third direction 901; the second partition 142 includes a third sub-partition 1421 and a fourth sub-partition 1422 spaced apart from each other, and the third sub-partition 1421 and the fourth sub-partition 1422 both extend along the fourth direction 902. It can be understood that by arranging a plurality of sub-partitions side by side to form a partition 140, the structural strength of the partition 140 is greatly improved, thereby effectively improving the overall structural stability of the chip packaging assembly 1000.

[0077] The present application also provides an electronic device, which includes a mainboard 2000 and a chip packaging assembly 1000 provided in the present application. Figure 6 , Figure 6 1 is a schematic diagram of the assembly structure of the mainboard 2000 and the chip packaging component 1000. The mainboard 2000 includes a board body 910 and a circuit structure 920 disposed on the surface of the board body 910. The chip packaging component 1000 is disposed on the side of the circuit structure 920 away from the board body 910, and a connector 3000 is also disposed between the mainboard 2000 and the chip packaging component 1000. The connector 3000 connects the lower conductive layer 130 and the circuit structure 920 to electrically connect the chip packaging component 1000 to the mainboard 2000. In the electronic device provided in the embodiment of the present application, the chip packaging component 1000 is electrically connected to the mainboard 2000 to meet the corresponding circuit transmission function, and since the electronic device provided in the embodiment of the present application adopts the chip packaging component 1000 of the above-mentioned embodiments, the electronic device also has better heat dissipation performance, moisture-proof performance and electromagnetic shielding performance, and its structural stability is strong, which can effectively prevent the chip 200 from being damaged by stress.

[0078] In a possible embodiment, the packaging substrate 100, the mainboard 2000 and the connector 3000 in the chip packaging assembly 1000 jointly surround the chip 200 to isolate the chip 200 from the outside world. It can be understood that under the above structure, the packaging substrate 100, the mainboard 2000 and the connector 3000 jointly form a complete moisture-proof barrier to effectively block the intrusion of moisture, thereby achieving a better moisture-proof effect. It should be noted that the connector 3000 can be of various types as long as it can meet the corresponding conductive and moisture-proof functions. In a specific embodiment, the connector 3000 is solder paste, that is, the lower conductive layer 130 and the circuit structure 920 are connected by soldering to achieve electrical connection between the mainboard 2000 and the chip packaging assembly 1000.

[0079] See also Figure 7 The present application also provides a method for manufacturing a chip package assembly 1000, which comprises the following steps:

[0080] Step S1: Provide a carrier board 150. Figure 8 It is understood that the carrier 150 is a flat plate structure, and the carrier 150 is used as a processing carrier, and subsequent components are formed on the surface of the carrier 150. Therefore, the carrier 150 can be made of the same material as other components. In a specific embodiment, the material of the carrier 150 is copper.

[0081] Step S2, forming a conductive part 110 and a limiting part 160 on the carrier 150, the conductive part 110 surrounds the limiting part 160 and is spaced from the limiting part 160, the conductive part 110 encloses to form a receiving cavity 101, a first space 102 is formed between the conductive part 110 and the limiting part 160, and the limiting part 160 encloses to form a second space 103. Among them, the conductive part 110, the limiting part 160 and the carrier 150 can be made of the same material. In a specific embodiment, the conductive part 110, the limiting part 160 and the carrier 150 are all made of copper, so that the conductive part 110 and the limiting part 160 can be formed on the surface of the carrier 150 by electroplating. It can be understood that under the above structure, the first space 102 and the second space 103 are both part of the receiving cavity 101, and the first space 102 and the second space 103 are both used to accommodate the insulating structure 410.

[0082] Please also read Figures 9a to 9c In a possible embodiment, step S2 may specifically include the following steps:

[0083] like Figure 9a , step S21 , covering a portion of the surface of the carrier 150 with a first dry film 170 .

[0084] like Figure 9b , step S22 , forming the conductive portion 110 and the limiting portion 160 by electroplating at the position not covered by the first dry film 170 .

[0085] like Fig.9c , step S23, removing the first dry film 170.

[0086] It can be understood that by dividing the area on the surface of the carrier 150, the first dry film 170 is covered at the position where the conductive part 110 and the limiting part 160 are not needed, and the first dry film 170 can prevent the electroplated metal from contacting the carrier 150; the first dry film 170 is not covered at the position where the conductive part 110 and the limiting part 160 are needed to be formed, so as to expose the carrier 150 at this position, thereby forming the conductive part 110 and the limiting part 160 by electroplating on the surface of the carrier 150 at this position.

[0087] Step S3: Setting an insulating structure 410 in the first space 102 and the second space 103. Fig.10a and Fig.10b In a possible embodiment, step S3 specifically includes the following steps:

[0088] like Fig.10a, step S31, filling the first space 102 and the second space 103 with insulating material and performing a pressing process to form an insulating structure 410. In a specific embodiment, the insulating material is a resin material so that the insulating structure 410 can play a corresponding insulating function. It should be noted that the insulating material can also be any other material with insulating properties, which is not specifically limited here.

[0089] like Fig.10b , step S32, grinding the conductive part 110 and the limiting part 160, so that the height of the insulating structure 410, the conductive part 110 and the limiting part 160 along the thickness direction of the carrier 150 is flush. It can be understood that by grinding, the height dimensions of the insulating structure 410, the conductive part 110 and the limiting part 160 are the same, so that when the upper conductive layer 120 is subsequently formed, the surface to which the upper conductive layer 120 is attached is smoother, which is conducive to the processing and forming of the upper conductive layer 120.

[0090] Step S4, remove the carrier 150, the limiting portion 160 and the insulating structure 410 located in the second space 103, retain the insulating structure 410 located in the first space 102 to form the insulating member 400, and retain the conductive portion 110. It is understandable that the carrier 150 does not exist in the finished product and is an intermediate structure in the manufacturing process. Therefore, the carrier 150 can be removed by etching first. It is also understandable that the limiting portion 160 does not exist in the finished product either. Its function is to form the first space 102 between it and the conductive portion 110 for forming the insulating member 400. Therefore, the limiting portion 160 also needs to be removed. Please refer to Figures 11a to 11d In a possible embodiment, step S4 specifically includes the following steps:

[0091] like Fig.11a , step S41, etching the carrier 150 to remove the carrier 150.

[0092] like Fig.11b , step S42 , covering the surface of the conductive portion 110 with a second dry film 180 .

[0093] like Fig.11c , step S43, etching the limiting portion 160 not covered by the second dry film 180 to remove the limiting portion 160 and the insulating structure 410 located in the second space 103.

[0094] like Fig.11d , step S44, removing the second dry film 180.

[0095] It is understandable that the second dry film 180 is used to block the erosion of chemical agents. After the carrier 150 is etched away, the conductive portion 110 can be effectively prevented from being etched by covering the surface of the conductive portion 110 with the second dry film 180, thereby retaining the conductive portion 110. It is also understandable that the limit portion 160 not protected by the dry film can also be removed by chemical etching, and the insulating structure 410 located in the second space 103 will also be detached and removed because it is fixed by the limit portion 160 and the carrier 150. The retained insulating structure 410 located in the first space 102 forms an insulating member 400 for fixing the chip 200 and isolating the chip 200 from the conductive portion 110.

[0096] See also Fig.12 Step S5: Place the chip 200 in the space surrounded by the insulating member 400. In a specific embodiment, the chip 200 can be mounted in the receiving cavity 101 by attaching the tape 190. After the chip 200 is mounted, the tape 190 is removed and the subsequent processing steps are performed.

[0097] See also Fig.13 , step S6, forming an upper conductive layer 120 on one side of the chip 200 and the conductive part 110, and forming a lower conductive layer 130 on the opposite side. It can be understood that the upper conductive layer 120 and the lower conductive layer 130 can be formed in a variety of ways, which are not specifically limited here. For example, the upper conductive layer 120 and the lower conductive layer 130 can be formed by electroplating.

[0098] See also Fig.14 , step S7, forming a heat dissipation portion 300 on the surface of the upper conductive layer 120 away from the chip 200, and processing the lower conductive layer 130 to form a corresponding circuit layer. It can be understood that the heat dissipation portion 300 can be formed on the upper conductive layer 120 by electroplating to achieve the heat dissipation function; the lower conductive layer 130 can be etched by etching to form a corresponding circuit layer to achieve the circuit transmission function.

[0099] See also Fig.15It can also be understood that when the manufactured chip packaging assembly 1000 needs to package multiple chips 200, a partition 140 needs to be provided. Accordingly, each step of the manufacturing method provided in this embodiment is changed accordingly. In this embodiment, step S2 also includes: at least one partition 140 is also formed on the carrier 150, the partition 140 is connected to the conductive part 110, the partition 140 divides the accommodating cavity 101 into a plurality of sub-accommodating cavities 111, the limiting part 160 is arranged in the sub-accommodating cavity 111, and is spaced from the conductive part 110 and the partition 140, a first space 102 is formed between the limiting part 160 and the conductive part 110 and the partition 140, and the limiting part 160 encloses to form a second space 103. Step S4 also includes: retaining the partition 140. The other steps are substantially the same as those in the above-mentioned embodiment and are not described in detail here.

[0100] By means of the manufacturing method of the chip packaging component 1000 provided in the embodiment of the present application, the chip packaging component 1000 provided in the embodiment of the present application can be manufactured, and the chip packaging component 1000 has better heat dissipation performance, moisture resistance and electromagnetic shielding performance, and has strong structural stability, which can effectively prevent the chip 200 from being damaged by stress and causing structural damage.

[0101] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application; in the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A chip packaging component, characterized in that: include: A packaging substrate, comprising an upper conductive layer, a lower conductive layer, and a conductive portion connected between the upper conductive layer and the lower conductive layer; A chip, comprising a front electrode and a back electrode arranged in opposite directions, wherein the chip is embedded in the packaging substrate, the conductive portion surrounds the chip, the front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer; A heat dissipation portion, the heat dissipation portion is connected to a surface of the upper conductive layer away from the chip, and the upper conductive layer, the lower conductive layer and the conductive portion all have thermal conductivity; The heat dissipation portion includes a plurality of heat dissipation monomers, each of which is connected to the upper conductive layer, and is spaced apart from each other. An extension direction of each of the heat dissipation monomers is arranged at an angle to an extension direction of the upper conductive layer. An extension direction of some of the heat dissipation monomers is a first direction, and an extension direction of some of the heat dissipation monomers is a second direction. The first direction is different from the second direction. A first refrigeration component is arranged on the periphery of the chip packaging component along the first direction, and a second refrigeration component is arranged on the periphery of the chip packaging component along the second direction.

2. The chip package assembly according to claim 1, characterized in that: The front electrode contacts the upper conductive layer.

3. The chip package assembly according to claim 1 or 2, characterized in that: The heat dissipation unit is in a flat plate shape or a column shape.

4. The chip package assembly according to claim 1, characterized in that: The heat dissipation portion and the upper conductive layer are an integrated structure.

5. The chip package assembly according to claim 4, characterized in that: The conductive part, the upper conductive layer and the lower conductive layer are all made of metal materials.

6. The chip package assembly according to claim 1, characterized in that: The chip packaging assembly further includes an insulating member disposed between the chip and the conductive portion to isolate the chip from the conductive portion.

7. The chip package assembly according to claim 6, characterized in that: The packaging substrate further includes at least one partitioning portion, which is connected to the conductive portion and surrounded by the conductive portion. The partitioning portion and the conductive portion together surround the plurality of chips, and each two adjacent chips are isolated by the partitioning portion.

8. The chip package assembly according to claim 7, characterized in that: The insulating member is provided between the chip and the conductive portion and between the chip and the partition portion to isolate the chip from the conductive portion and to isolate the chip from the partition portion.

9. The chip package assembly according to claim 7, characterized in that: At least one of the partitions includes a first partition and a second partition, the first partition extends along a third direction, and the second partition extends along a fourth direction; The third direction and the fourth direction are both perpendicular to the thickness direction of the chip packaging component, and the third direction and the fourth direction are arranged at an angle.

10. The chip package assembly according to claim 9, characterized in that: The first partition portion includes a first sub-partition plate and a second sub-partition plate spaced apart from each other, and the first sub-partition plate and the second sub-partition plate both extend along the third direction; The second partition includes a third sub-partition plate and a fourth sub-partition plate that are spaced apart from each other, and the third sub-partition plate and the fourth sub-partition plate both extend along the fourth direction.

11. The chip package assembly according to claim 1, characterized in that: The conductive portion, the upper conductive layer and the lower conductive layer together form an integrated structure.

12. An electronic device, characterized in that: It comprises a mainboard and a chip packaging assembly as described in any one of claims 1 to 11, wherein the mainboard comprises a board body and a circuit structure arranged on the surface of the board body, the chip packaging assembly is arranged on a side of the circuit structure away from the board body, and a connecting member is further provided between the mainboard and the chip packaging assembly, the connecting member connects the lower conductive layer and the circuit structure so that the chip packaging assembly is electrically connected to the mainboard.

13. The electronic device according to claim 12, characterized in that: The packaging substrate, the mainboard and the connecting member in the chip packaging assembly surround the chip together to isolate the chip from the outside.

14. A method for manufacturing a chip packaging component, characterized in that: include: Provide carrier board; A conductive portion and a limiting portion are formed on the carrier, wherein the conductive portion surrounds the limiting portion and is spaced apart from the limiting portion, the conductive portion encloses to form a receiving cavity, a first space is formed between the conductive portion and the limiting portion, and the limiting portion encloses to form a second space; providing an insulating structure in the first space and the second space; The carrier plate, the limiting portion and the insulating structure located in the second space are removed, the insulating structure located in the first space is retained to form an insulating member, and the conductive portion is retained; placing a chip in a space surrounded by the insulating member; forming an upper conductive layer on one side of the chip and the conductive portion, and forming a lower conductive layer on the opposite side; A heat dissipation portion is formed on a surface of the upper conductive layer away from the chip, and the lower conductive layer is processed to form a corresponding circuit layer, wherein the heat dissipation portion includes a plurality of heat dissipation monomers, the plurality of heat dissipation monomers are all connected to the upper conductive layer, the plurality of heat dissipation monomers are spaced apart, an extension direction of each of the heat dissipation monomers is arranged at an angle to an extension direction of the upper conductive layer, some of the heat dissipation monomers extend in a first direction, and some of the heat dissipation monomers extend in a second direction, the first direction and the second direction are different, a first refrigeration component is arranged on the periphery of the chip packaging component along the first direction, and a second refrigeration component is arranged on the periphery of the chip packaging component along the second direction.

15. The manufacturing method according to claim 14, characterized in that: Forming a conductive portion and a limiting portion on the carrier includes: Covering a portion of the surface of the carrier with a first dry film; Electroplating to form the conductive portion and the limiting portion at a position not covered by the first dry film; The first dry film is removed.

16. The manufacturing method according to claim 14, characterized in that: The step of providing an insulating structure in the first space and the second space comprises: Filling the first space and the second space with insulating material and performing a pressing process to form the insulating structure; The conductive portion and the limiting portion are ground so that the insulating structure, the conductive portion and the limiting portion are flush with each other in the thickness direction of the carrier.

17. The manufacturing method according to claim 14, characterized in that: The step of removing the carrier plate, the limiting portion, and the insulating structure located in the second space includes: etching the carrier to remove the carrier; Covering the surface of the conductive portion with a second dry film; Etching the limiting portion not covered by the second dry film to remove the limiting portion and the insulating structure located in the second space; The second dry film is removed.

18. The manufacturing method according to claim 14, characterized in that: In the process of forming the conductive part and the limiting part on the carrier, the manufacturing method further includes: At least one partition is also formed on the carrier, and the partition is connected to the conductive part. The partition divides the accommodating cavity into a plurality of sub-accommodating cavities. The limiting part is arranged in the sub-accommodating cavity and is separated from the conductive part and the partition. The first space is formed between the limiting part, the conductive part and the partition, and the second space is formed by enclosing the limiting part.

Images