Imaging device

Abstract

Provided is an imaging device capable of improving the degree of freedom in layout. The imaging device includes: a first substrate portion including sensor pixels for performing photoelectric conversion; and a second substrate portion provided on one surface side of the first substrate portion and including a read circuit for outputting a pixel signal based on charges output from the sensor pixels. The second substrate portion includes: a first semiconductor substrate on which a first transistor included in the read circuit is provided; and a second semiconductor substrate provided on one surface side of the first semiconductor substrate and on which a second transistor included in the read circuit is provided.

Description

Technical Field

[0001] The present disclosure relates to an imaging device. Background Art

[0002] Generally, in an imaging device having a two-dimensional structure, the area of each pixel is reduced due to the introduction of miniaturization processes and the increase in mounting density. In recent years, in order to reduce the size of the imaging device and increase the pixel density, an imaging device having a three-dimensional structure has been developed (for example, see Patent Document 1). The imaging device having a three-dimensional structure includes a first semiconductor substrate having a plurality of sensor pixels and a second semiconductor substrate having a read circuit for reading a signal obtained by the sensor pixels. The second semiconductor substrate is laminated on one surface side of the first semiconductor substrate.

[0003] Citation List

[0004] Patent Document

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2010-245506 Summary of the Invention

[0006] Technical Problem to be Solved by the Invention

[0007] The read circuit includes a selection transistor for selecting a sensor pixel, an amplification transistor for amplifying a signal obtained by the sensor pixel, a reset transistor for resetting a signal obtained by the sensor pixel, and the like. The arrangement and size (hereinafter referred to as layout) of the transistors included in the read circuit affect the performance of the imaging device. For example, when the gate area in the amplification transistor is set small, the noise characteristics of the imaging device may deteriorate. Therefore, it is necessary to increase the degree of freedom of the layout.

[0008] The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to provide an imaging device capable of increasing the degree of freedom of layout.

[0009] Technical Solution for Solving the Problem

[0010] An imaging device according to one aspect of the present disclosure includes: a first substrate portion including sensor pixels for performing photoelectric conversion; and a second substrate portion provided on one surface side of the first substrate portion and including a read circuit for outputting a pixel signal based on charges output from the sensor pixels. The second substrate portion includes: a first semiconductor substrate on which a first transistor included in the read circuit is provided; and a second semiconductor substrate provided on one surface side of the first semiconductor substrate and on which a second transistor included in the read circuit is provided.

[0011] Therefore, compared with the case where all the transistors included in the reading circuit are provided on a single semiconductor substrate, the area of the layout region of the transistors can be increased. Accordingly, the degree of freedom in layout on the reading circuit can be improved. For example, the amplifying transistor may be provided on the first semiconductor substrate, while the selection transistor and the reset transistor may be provided on the second semiconductor substrate. As a result, the gate area of the amplifying transistor can be maximized.

[0012] An imaging device according to another aspect of the present disclosure includes: a first substrate portion including sensor pixels for performing photoelectric conversion; and a second substrate portion provided on one surface side of the first substrate portion and including a reading circuit for outputting a pixel signal based on charges output from the sensor pixels. The second substrate portion includes: a first semiconductor substrate on which a first transistor included in the reading circuit is provided; and a semiconductor film provided on one surface side of the first semiconductor substrate, and on which a second transistor included in the reading circuit is provided.

[0013] Therefore, compared with the case where all the transistors included in the reading circuit are provided only on the substrate surface, the area of the layout region of the transistors can be increased. Accordingly, the degree of freedom in layout on the reading circuit can be improved. For example, the amplifying transistor may be provided on the first semiconductor substrate, while the selection transistor and the reset transistor may be provided on the semiconductor film laminated on the first semiconductor substrate. As a result, the gate area of the amplifying transistor can be maximized. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Figure 1 is a schematic diagram showing a configuration example of an imaging device according to a first embodiment of the present disclosure.

[0015] Figure 2 Figure 2 is a circuit diagram showing a configuration example of a pixel unit according to a first embodiment of the present disclosure.

[0016] Figure 3 Figure 3 is a cross-sectional view in the thickness direction of a configuration example of an imaging device 1 according to a first embodiment of the present disclosure.

[0017] Figure 4A Figure 4A is a cross-sectional view in the horizontal direction of a configuration example of a pixel unit according to a first embodiment of the present disclosure.

[0018] Figure 4B Figure 4B is a cross-sectional view in the horizontal direction of a configuration example of a pixel unit according to a first embodiment of the present disclosure.​​​​​​​​​​

[0019] Figure 4C Figure 4C is a cross-sectional view in the horizontal direction of a configuration example of a pixel unit according to the first embodiment of the present disclosure.

[0020] Figure 5 Figure 5 is a cross-sectional view in the horizontal direction of a layout example of a plurality of pixel units according to the first embodiment of the present disclosure.

[0021] Figure 6 Figure 6 is a cross-sectional view in the horizontal direction of a layout example of a plurality of pixel units according to the first embodiment of the present disclosure.

[0022] Figure 7 Figure 7 is a cross-sectional view in the horizontal direction of a layout example of a plurality of pixel units according to the first embodiment of the present disclosure.

[0023] Figure 8 Figure 8 is a cross-sectional view of a manufacturing method of an imaging device according to the first embodiment of the present disclosure.

[0024] Figure 9 Figure 9 is a cross-sectional view of a manufacturing method of an imaging device according to the first embodiment of the present disclosure.

[0025] Figure 10 Figure 10 is a cross-sectional view of a manufacturing method of an imaging device according to the first embodiment of the present disclosure.

[0026] Figure 11 Figure 11 is a cross-sectional view of a manufacturing method of an imaging device according to the first embodiment of the present disclosure.

[0027] Figure 12 Figure 12 is a cross-sectional view of a manufacturing method of an imaging device according to the first embodiment of the present disclosure.

[0028] Figure 13 Figure 13 is a cross-sectional view of a manufacturing method of an imaging device according to the first embodiment of the present disclosure.

[0029] Figure 14 Figure 14 is a cross-sectional view of a manufacturing method of an imaging device according to the first embodiment of the present disclosure.

[0030] Figure 15 Figure 15 ​​​​​​​​​​​​​​​​​​​​​​​​A cross-sectional view of a method for manufacturing an imaging device according to a second embodiment of the present disclosure.

[0031] Figure 16 Figure 16 A cross-sectional view of a method for manufacturing an imaging device according to a second embodiment of the present disclosure.

[0032] Figure 17 Figure 17 A cross-sectional view in the thickness direction of an exemplary configuration of an imaging device according to a third embodiment of the present disclosure.

[0033] Figure 18 Figure 18 A cross-sectional view in the thickness direction of an exemplary configuration of an imaging device according to a third embodiment of the present disclosure.

[0034] Figure 19 Figure 19 A cross-sectional view in the thickness direction of an exemplary configuration of an imaging device according to a third embodiment of the present disclosure.

[0035] Figure 20 Figure 20 A cross-sectional view in the horizontal direction of an exemplary layout of a plurality of pixel units according to a third embodiment of the present disclosure.

[0036] Figure 21 Figure 21 A cross-sectional view in the horizontal direction of an exemplary layout of a plurality of pixel units according to a third embodiment of the present disclosure.

[0037] Figure 22 Figure 22 A cross-sectional view in the horizontal direction of an exemplary layout of a plurality of pixel units according to a third embodiment of the present disclosure.

[0038] Figure 23 Figure 23 A cross-sectional view in the thickness direction of an exemplary configuration of an imaging device according to a fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings. Regarding the illustrations in the drawings to be referred to in the following description, the same or similar components are denoted by the same or similar reference numerals. However, it should be noted that since the drawings are schematic, the relationships between the thicknesses and planar dimensions shown in the drawings, the thickness ratios between layers, etc. are different from the actual ones. Therefore, the specific thickness or specific dimensions should be determined in view of the following description. In addition, it goes without saying that the dimensional relationships or ratios are different between the drawings.

[0040] ​​​​​​​​​​​​​​​​In addition, for ease of explanation, only definitions of directions such as the up-down direction are given in the following description. These definitions are not intended to limit the technical idea of the present disclosure. For example, it goes without saying that when an object is observed after being rotated by 90°, the upper side and the lower side of the object are understood as the left side and the right side, and when the object is observed after being rotated by 180°, the upper side and the lower side of the object are understood as being upside down.

[0041] In addition, in the following description, in some cases, the terms "X-axis direction", "Y-axis direction", and "Z-axis direction" are used to explain directions. For example, the Z-axis direction refers to the thickness direction of the laminate including the first substrate portion 10 and the second substrate portion 20, which will be described later. The X-axis direction and the Y-axis direction are orthogonal to the Z-axis direction respectively. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other. In the following description, the direction parallel to the X-axis direction and the Y-axis direction is also referred to as the horizontal direction. In addition, in the following description, the term "planar view" means observing from the Z-axis direction.

[0042] (First Embodiment)

[0043] Figure 1 is a schematic diagram showing a configuration example of the imaging device 1 according to the first embodiment of the present disclosure. The imaging device 1 includes a first substrate portion 10, a second substrate portion 20, and a third substrate portion 30. The imaging device 1 is an imaging device having a three-dimensional structure formed by bonding the first substrate portion 10, the second substrate portion 20, and the third substrate portion 30 together. The first substrate portion 10, the second substrate portion 20, and the third substrate portion 30 are stacked in this order.

[0044] The first substrate portion 10 includes a plurality of sensor pixels 12 for performing photoelectric conversion on a semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix in the pixel region 13 of the first substrate portion 10. The second substrate portion 20 includes a reading circuit 22 for outputting a pixel signal based on the charge from the sensor pixels 12. Each reading circuit 22 is provided for every four sensor pixels 12. The second substrate portion 20 includes a plurality of pixel driving lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. It should be noted that the third substrate portion 30 may also be referred to as the bottom substrate.

[0045] As described later, the second substrate portion 20 has a structure in which two substrates are stacked. The second substrate portion 20 includes a lower substrate 210 and an upper substrate 220. The lower substrate 210 includes a first semiconductor substrate 211 (see Figure 3 ). The upper substrate 220 includes a second semiconductor substrate 221 (see Figure 3)。A first transistor included in the read circuit 22 is provided on the first semiconductor substrate 211. A second transistor included in the read circuit 22 is provided on the second semiconductor substrate 221. It should be noted that the upper substrate 220 may also be referred to as the top substrate. The lower substrate 210 may also be referred to as the intermediate substrate.

[0046] The third substrate portion 30 includes a logic circuit 32 for processing pixel signals on the semiconductor substrate 301. For example, the logic circuit 32 includes a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (or specifically, the horizontal drive circuit 35) outputs the output voltage Vout of each sensor pixel 12 to the outside. In the logic circuit 32, a low-resistance region including a silicide formed by a self-aligned silicide process such as using CoSi 2 or NiSi can be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0047] For example, the vertical drive circuit 33 sequentially selects a plurality of sensor pixels 12 in units of rows. For example, the column signal processing circuit 34 performs correlated double sampling (CDS: Correlated Double Sampling) on the pixel signals output from the sensor pixels 12 included in the row selected by the vertical drive circuit 33. For example, by performing CDS, the column signal processing circuit 34 extracts the signal level of the pixel signal and holds the pixel data corresponding to the light reception amount of each sensor pixel 12. For example, the horizontal drive circuit 35 sequentially outputs the pixel data held by the column signal processing circuit 34 to the outside. For example, the system control circuit 36 performs drive control of the blocks (vertical drive circuit 33, column signal processing circuit 34, and horizontal drive circuit 35) included in the logic circuit 32.

[0048] Figure 2 is a circuit diagram showing a configuration example of a pixel unit PU according to a first embodiment of the present disclosure. As Figure 2 shown, in the imaging device 1, four sensor pixels 12 are electrically connected to one read circuit 22, thereby forming a pixel unit PU. The four sensor pixels 12 share one read circuit 22. The outputs from the four sensor pixels 12 are input to the common read circuit 22.

[0049] Each sensor pixel 12 has the same components. In Figure 2In order to distinguish the components of the sensor pixel 12 from each other, an identification number (1, 2, 3, or 4) is given after the reference numeral of the component of each sensor pixel 12 (e.g., PD, TG, or FD which will be described later). Hereinafter, in cases where it is necessary to distinguish the components of each sensor pixel 12 from each other, the corresponding identification number will be given after the reference numeral of the component of the sensor pixel 12. However, in cases where it is not necessary to distinguish the components of each sensor pixel 12 from each other, the identification number will be omitted after the reference numeral of the component of the sensor pixel 12.

[0050] For example, each sensor pixel 12 includes a photodiode PD (which is an example of a photoelectric conversion element), a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion section FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD performs photoelectric conversion and generates a charge corresponding to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion section FD, and the gate electrode of the transfer transistor TR is electrically connected to the pixel drive line 23. For example, the transfer transistor TR is a complementary metal oxide semiconductor (CMOS) transistor.

[0051] The respective floating diffusion sections FD of the sensor pixels 12 sharing a read circuit 22 are electrically connected to each other and are electrically connected to the input terminal of the common read circuit 22. For example, each read circuit 22 includes an amplification transistor AMP (which is an example of a first transistor), a reset transistor RST, and a selection transistor SEL (which is an example of a second transistor). It should be noted that the selection transistor SEL can be appropriately omitted.

[0052] The source of the reset transistor RST (the input terminal of the read circuit 22) is electrically connected to the floating diffusion section FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the pixel drive line 23 (see Figure 1 ). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate electrode of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the read circuit 22) is electrically connected to the vertical signal line 24, and the gate electrode of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1 ).

[0053] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge in the photodiode PD to the floating diffusion section FD. As will be described later Figure 3 As shown, the gate electrode TG of the transfer transistor TR extends from the surface of the semiconductor substrate 11 through the well layer WE to reach the depth of the photodiode PD. The reset transistor RST resets the potential of each floating diffusion section FD to a predetermined potential. When the reset transistor RST is turned on, the potential of each floating diffusion section FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the read circuit 22.

[0054] The amplification transistor AMP generates a signal having a voltage corresponding to the level of the charge held in each floating diffusion section FD as a pixel signal. The amplification transistor AMP forms a source follower type amplifier and is configured to output a pixel signal having a voltage corresponding to the level of the charge generated by each photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of each floating diffusion section FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 24. For example, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are CMOS transistors.

[0055] Figure 3 is a cross-sectional view in the thickness direction of a configuration example of the imaging device 1 according to the first embodiment of the present disclosure. Note that Figure 3 the cross-sectional view in is schematic and is not intended to precisely show the actual structure. To explain the configuration of the imaging device 1 in an easy-to-understand manner on the paper surface, in the Figure 3 cross-sectional view, the positions of the transistors and the impurity diffusion layers are intentionally changed in the horizontal direction between the position sec1 and the position sec3. Specifically, Figure 3 the cross-section of the pixel unit PU at the position sec1 in corresponds to the cross-section taken along the line A-A' described later Figure 4A in. Figure 3 the cross-section of the pixel unit PU at the position sec2 in corresponds to the cross-section taken along the line B-B' described later Figure 4B in. Figure 3 the cross-section of the pixel unit PU at the position sec3 in corresponds to the cross-section taken along the line C-C' described later Figure 4C in. Figures 4A to 4C The structure of the imaging device 1 shown in is more accurate than the structure shown in Figure 3 .

[0056] As Figure 3As shown, the second substrate portion 20 is stacked on the front surface 10a (which is an example of one surface) side of the first substrate portion (bottom substrate) 10. A photodiode PD, a transfer transistor TR, and a floating diffusion portion FD are provided on the front surface 10a side of the first substrate portion 10. The photodiode PD, the transfer transistor TR, and the floating diffusion portion FD are provided for each sensor pixel 12.

[0057] The other surface (for example, the back surface) of the first substrate portion 10 is a light incident surface. The imaging device 1 is a back-illuminated imaging device, and a color filter and a light receiving lens are provided on the back surface of the imaging device 1. The color filter and the light receiving lens are provided for each sensor pixel 12.

[0058] For example, the semiconductor substrate 11 included in the first substrate portion 10 includes a silicon substrate. A well layer WE of a first conductivity type (for example, p-type) is provided on a part of and in the vicinity of the front surface of the semiconductor substrate 11. A photodiode PD of a second conductivity type (for example, n-type) is provided in a region deeper than the well layer WE. In addition, a well contact layer having a higher p-type concentration than the well layer WE and an n-type floating diffusion portion FD are provided in the well layer WE (see Figure 2 ). The well contact layer is provided to reduce the contact resistance between the well layer WE and the wiring.

[0059] An element isolation layer 16 for electrically isolating adjacent sensor pixels 12 from each other is provided in the semiconductor substrate 11. The element isolation layer 16 has, for example, a shallow trench isolation (STI) structure, and the element isolation layer 16 extends in the depth direction of the semiconductor substrate 11. The element isolation layer 16 contains, for example, silicon oxide. In addition, in the semiconductor substrate 11, an impurity diffusion layer 17 is provided between the element isolation layer 16 and the photodiode PD. For example, the impurity diffusion layer 17 includes a p-type layer and an n-type layer extending in the thickness direction of the semiconductor substrate 11. The p-type layer is on the element isolation layer 16 side. The n-type layer is on the photodiode PD side.

[0060] An insulating film 15 is provided on the front surface 11a side of the semiconductor substrate 11. For example, the insulating film 15 is one of a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), and a silicon carbonitride film (SiCN), or a film formed by laminating at least two of these films.

[0061] As Figure 3As shown, the second substrate portion 20 includes a lower substrate (intermediate substrate) 210 and an upper substrate (top substrate) 220. The lower substrate 210 includes a first semiconductor substrate 211. For example, the first semiconductor substrate 211 is a silicon substrate containing single-crystalline silicon. On one surface (e.g., the front surface 211a) side of the first semiconductor substrate 211, an amplifying transistor AMP and an element isolation layer 213 surrounding the amplifying transistor AMP are provided. The element isolation layer 213 electrically isolates the amplifying transistor AMP of one pixel unit PU from the amplifying transistor AMP of another pixel unit PU in adjacent pixel units PU.

[0062] The lower substrate 210 includes an insulating film 215 covering the front surface 211a of the first semiconductor substrate 211. The amplifying transistor AMP and the element isolation layer 213 are covered by the insulating film 215. In addition, the lower substrate 210 includes an insulating film 217 covering the other surface (e.g., the back surface 211b) of the first semiconductor substrate 211. The insulating films 215 and 217 are respectively films containing one of the materials SiO, SiN, SiON, and SiCN, or are respectively films formed by laminating at least two of the above films. The insulating film 15 of the first substrate portion 10 and the insulating film 217 of the lower substrate 210 are joined together to form an interlayer insulating film 51.

[0063] The upper substrate 220 includes a second semiconductor substrate 221. For example, the second semiconductor substrate 221 is a silicon substrate containing single-crystalline silicon. On one surface (e.g., the front surface 221a) side of the second semiconductor substrate 221, a reset transistor RST, a selection transistor SEL, and an element isolation layer 223 are provided. For example, the element isolation layer 223 is provided between the reset transistor RST and the selection transistor SEL and between the selection transistor SEL and the well layer of the second semiconductor substrate 221.

[0064] The upper substrate 220 includes an insulating film 225 covering the front surface 221a, the back surface 221b, and the side surfaces of the second semiconductor substrate 221. For example, the insulating film 225 is a film containing one of the materials SiO, SiN, SiON, and SiCN, or is a film formed by laminating at least two of the above films. The insulating film 215 of the lower substrate 210 and the insulating film 225 of the upper substrate 220 are joined together to form an interlayer insulating film 53.

[0065] The imaging device 1 includes a plurality of wirings L1 to L10, which are provided in the interlayer insulating films 51 and 53 and are electrically connected to at least one of the first substrate portion 10 and the second substrate portion 20. As Figure 2 and Figure 3As shown, the drain of the amplifying transistor AMP and the power supply line VDD are electrically connected via the wiring L1. The four floating diffusion parts FD included in one pixel unit PU and the gate electrode AG of the amplifying transistor AMP are electrically connected via the wiring L2. The source of the amplifying transistor AMP and the drain of the selection transistor SEL are electrically connected via the wiring L3. The gate electrode SG of the selection transistor SEL and the pixel driving line 23 (see Figure 1 ) are electrically connected via the wiring L4.

[0066] The source of the selection transistor SEL and the vertical signal line 24 are electrically connected via the wiring L5. The drain of the reset transistor RST and the power supply line VDD are electrically connected via the wiring L6. The gate electrode RG of the reset transistor RST (see Figure 4A to be described later) and the pixel driving line 23 are electrically connected via the wiring L7. The source of the reset transistor RST and the wiring L2 are electrically connected via the wiring L8. The gate electrode TG of the transfer transistor TR and the pixel driving line 23 (see Figure 1 ) are electrically connected via the wiring L9 (which is an example of the first wiring). The well contact layer and the reference potential line supplying the reference potential (e.g., ground potential: 0V) are electrically connected via the wiring L10.

[0067] Among the wirings L1 to L10, the portions extending in the thickness direction of the laminate contain tungsten (W), and the portions extending in the direction orthogonal to the thickness direction of the laminate (e.g., horizontal direction) contain copper (Cu) or a Cu alloy mainly containing Cu. However, in the embodiments of the present disclosure, the materials of the wirings L1 to L10 are not limited to these materials, and any other materials can be used.

[0068] The second substrate portion 20 includes a plurality of pad electrodes 227 connected to any of the above wirings L1 to L10 (e.g., wirings L1, L4 to L7, L9, and L10). For example, the plurality of pad electrodes 227 contain Cu or a Cu alloy.

[0069] The third substrate portion 30 is provided on the side (e.g., front side) of the second substrate portion 20 opposite to the surface facing the first substrate portion 10. The third substrate portion 30 includes a semiconductor substrate 301, an insulating film 304 covering the front side 301a of the semiconductor substrate 301, a plurality of wirings L30 provided on the front side 301a of the semiconductor substrate 301, and a plurality of pad electrodes 305 connected to the plurality of wirings L30. It should be noted that, as described later, the front side of the third substrate portion 30 and the front side of the second substrate portion 20 are joined together. Therefore, in Figure 3 , the front side 301a of the semiconductor substrate 301 faces downward.

[0070] For example, the semiconductor substrate 301 is a silicon substrate containing single-crystalline silicon. An impurity diffusion layer and a plurality of transistors constituting the logic circuit 32 (see Figure 1 ) are provided on the front surface 301a side of the semiconductor substrate 301. The impurity diffusion layer and the plurality of transistors constituting the logic circuit 32 are covered with an insulating film 304. Contact holes connecting to the transistors and the impurity diffusion layer are provided in the insulating film 304.

[0071] The wiring L30 is provided in the contact holes. The portion of the wiring L30 extending in the thickness direction of the third substrate portion 30 contains titanium (Ti) or cobalt (Co), and the portion of the wiring L30 extending in a direction orthogonal to the thickness direction of the third substrate portion 30 (e.g., the horizontal direction) contains Cu or a Cu alloy mainly containing Cu. However, in the embodiments of the present disclosure, the material of the wiring L30 is not limited to these materials, and any other material can be used.

[0072] A silicide 303 (e.g., titanium silicide (TiSi) or cobalt silicide (CoSi 2 )) is formed in the connection portion between each wiring L30 and the semiconductor substrate 301. Due to the silicide 303, the connection between the wiring L30 and the semiconductor substrate 301 becomes closer to an ohmic contact, thereby reducing the contact resistance. As a result, the calculation speed of the logic circuit 32 is improved.

[0073] It should be noted that no silicide is formed in the first substrate portion 10 and the second substrate portion 20. Therefore, when forming the first substrate portion 10 and the second substrate portion 20, heat treatment or the like can be performed at a temperature higher than the heat-resistant temperature of the silicide. However, the embodiments of the present disclosure are not limited thereto, and a silicide can be formed in at least one of the first substrate portion 10 and the second substrate portion 20.

[0074] For example, the plurality of pad electrodes 305 contain Cu or a Cu alloy. In the thickness direction of the imaging device 1, the pad electrode 305 of the third substrate portion 30 faces the pad electrode 227 of the second substrate portion 20, and an electrical connection is formed therebetween. For example, the pad electrodes 305 and 227 are integrated by Cu-Cu bonding while facing each other. Therefore, the second substrate portion 20 and the third substrate portion 30 are electrically connected to each other, and the bonding strength between the second substrate portion 20 and the third substrate portion 30 is improved.

[0075] Figures 4A to 4C is a cross-sectional view in the horizontal direction showing a structural example of the pixel unit PU according to the first embodiment of the present disclosure. More specifically, Figure 4A is in Figure 3A cross-sectional view of the pixel unit PU taken horizontally at position sec1 in []. Position sec1 is at the same height as the upper surfaces of the gate electrode SG of the selection transistor SEL and the gate electrode RG of the reset transistor RST. Figure 4B is a Figure 3 cross-sectional view of the pixel unit PU taken horizontally at position sec2 in []. Position sec2 is at the same height as the upper surface of the gate electrode AG of the amplification transistor AMP. Figure 4C is a Figure 3 cross-sectional view of the pixel unit PU taken horizontally at position sec3 in []. Position sec3 is at the same height as the upper surface of the gate electrode TG of the transfer transistor TR.

[0076] Figures 4A to 4C Each shows a pixel unit PU and has a positional relationship of overlapping with each other in the thickness direction (e.g., Z-axis direction) of the laminate. Figure 4A The shown selection transistor SEL and reset transistor RST, Figure 4B the shown amplification transistor AMP, and Figure 4C the four sensor pixels 12 shown overlap with each other in the Z-axis direction. As Figure 4A shown, the transistor group including the selection transistor SEL and the reset transistor RST is located in the central portion of the pixel unit PU in the plan view. The wiring group including the wirings L2, L9, and L10 is located outside the transistor group. In the plan view, this wiring group is symmetrically arranged on the left and right sides of the transistor group including the selection transistor SEL and the reset transistor RST. In addition, a well layer electrically isolated from the source and drain of the transistor group by the element isolation layer 223 is provided in the second semiconductor substrate 221. This well layer is connected to a reference potential (e.g., ground potential: 0V) via the wiring L10.

[0077] As Figure 4B shown, the amplification transistor AMP is located in the central portion of the pixel unit PU in the plan view. The amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are positioned to overlap with each other in the thickness direction of the laminate. In addition, in the plan view, the wiring group including the wirings L2, L9, and L10 is located outside the amplification transistor AMP. This wiring group is symmetrically arranged on the left and right sides of the amplification transistor AMP in the plan view.

[0078] As Figure 4CAs shown, four sensor pixels 12 included in a pixel unit PU are arranged close to each other via an element isolation layer 16. Additionally, in each of the four sensor pixels 12, in a plan view, a gate electrode TG of a transfer transistor TR is inserted between a floating diffusion portion FD and a well layer WE. The gate electrode TG is a partition between the floating diffusion portion FD and the well layer WE. As Figure 3 shown, a photodiode PD is located below the floating diffusion portion FD, the well layer WE, and the gate electrode TG.

[0079] Figures 5 to 7 is a cross-sectional view in a horizontal direction showing layout examples of a plurality of pixel units PU according to a first embodiment of the present disclosure. More specifically, Figure 5 is a cross-sectional view of the imaging device 1 taken at a position sec1 in Figure 3 . Figure 6 is a cross-sectional view of the imaging device 1 taken at a position sec2 in Figure 3 . Figure 7 is a cross-sectional view of a first substrate portion 10 taken at a position sec3 in Figure 3 . As Figures 5 to 7 shown, a plurality of pixel units PU of the imaging device 1 are arranged at fixed intervals in the X-axis direction and the Y-axis direction. The pixel units PU are repeatedly arranged in the X-axis direction and the Y-axis direction.

[0080] Next, a manufacturing method of the imaging device 1 will be described. Note that the imaging device 1 is manufactured using various devices such as a film forming device (including a chemical vapor deposition (CVD) device and a sputtering device), an ion implantation device, a heat treatment device, an etching device, a chemical mechanical polishing (CMP) device, and a lamination device. Hereinafter, these devices will be collectively referred to as manufacturing devices.

[0081] Figures 8 to 14 is a cross-sectional view of a manufacturing method of the imaging device 1 according to a first embodiment of the present disclosure. As Figure 8 shown, by using a CMOS process, the manufacturing device forms a well layer WE, an element isolation layer 16, an impurity diffusion layer 17, a photodiode PD, a gate electrode TG of a transfer transistor TR, a floating diffusion portion FD (see Figure 4C ) and a well contact layer on the front surface 11a side of a semiconductor substrate 11. Next, the manufacturing device forms an insulating film 15 on the front surface 11a side of the semiconductor substrate 11 and planarizes the surface of the insulating film 15. For example, the insulating film 15 is formed by a CVD method. The insulating film 15 is planarized by CMP. As a result, the first substrate portion 10 is completed.

[0082] Next, as Figure 9 shown, the manufacturing apparatus bonds the first semiconductor substrate 211 to the front surface 10a side of the first substrate portion 10. For example, the back surface 211b of the first semiconductor substrate 211 is covered with an insulating film 217 such as a silicon oxide film (SiO). The manufacturing apparatus places the front surface 11a of the semiconductor substrate 11 constituting the first substrate portion 10 to face the back surface 211b of the first semiconductor substrate 211. Subsequently, the manufacturing apparatus performs a heat treatment while maintaining close contact between the insulating film 15 covering the front surface 11a of the semiconductor substrate 11 and the insulating film 217 covering the back surface 211b of the first semiconductor substrate 211. As a result, as Figure 9 shown, the insulating films 15 and 217 are integrated to form an interlayer insulating film 51, and the semiconductor substrate 11 and the first semiconductor substrate 211 are bonded together with the interlayer insulating film 51 therebetween. Thereafter, the manufacturing apparatus thins the first semiconductor substrate 211 (i.e., reduces the thickness) by grinding the front surface 211a side of the first semiconductor substrate 211. The first semiconductor substrate 211 is thinned by CMP.

[0083] Next, as Figure 10 shown, by using a CMOS process, the manufacturing apparatus forms an element isolation layer 213 and a boosting transistor AMP on the front surface 211a side of the thinned first semiconductor substrate 211. For example, after forming the element isolation layer 213, the manufacturing apparatus forms a gate electrode AG of the boosting transistor AMP on the front surface 211a of the first semiconductor substrate 211. Next, the manufacturing apparatus forms a source and a drain of the boosting transistor AMP on both sides of the gate electrode AG. Thereafter, the manufacturing apparatus forms an insulating film 215 on the front surface 211a side of the first semiconductor substrate 211 by a CVD method, and planarizes the surface of the insulating film 215 by a CMP method.

[0084] Next, as Figure 11 shown, the manufacturing apparatus bonds the second semiconductor substrate 221 to the front surface 211a side of the first semiconductor substrate 211. For example, the back surface 221b of the second semiconductor substrate 221 is covered with an insulating film 225A such as a silicon oxide film (SiO). The insulating film 225A is a part of the insulating film 225 (see Figure 3 ). The manufacturing apparatus places the front surface 211a of the first semiconductor substrate 211 to face the back surface 221b of the second semiconductor substrate 221. Subsequently, the manufacturing apparatus performs a heat treatment while maintaining close contact between the insulating film 215 covering the front surface 211a of the first semiconductor substrate 211 and the insulating film 225A covering the back surface 221b of the second semiconductor substrate 221. As a result, as Figure 11As shown, the insulating films 215 and 225A are integrated to form an interlayer insulating film 53, and the first semiconductor substrate 211 and the second semiconductor substrate 221 are bonded together with the interlayer insulating film 53 therebetween. Thereafter, the manufacturing apparatus thins the second semiconductor substrate 221 by grinding the front surface 221a side of the second semiconductor substrate 221. The second semiconductor substrate 221 is thinned by CMP.

[0085] Next, as Figure 12 shown, the manufacturing apparatus forms the second semiconductor substrate 221 into an island shape in a plan view by removing a part of the second semiconductor substrate 221. For example, a resist pattern is formed by lithography, and the second semiconductor substrate 221 is dry-etched using the resist pattern as a mask, thereby removing a part of the second semiconductor substrate 221. In this dry etching, the insulating film 225A provided under the second semiconductor substrate 221 serves as an etching stopper layer.

[0086] In addition, before or after the step of forming the second semiconductor substrate 221 into an island shape, or in parallel with this step, the manufacturing apparatus forms an element isolation layer 223, a selection transistor SEL, and a reset transistor RST on the front surface 221a side of the second semiconductor substrate 221 using a CMOS process. For example, after forming the element isolation layer 223, the manufacturing apparatus forms a gate electrode SG of the selection transistor SEL and a gate electrode RG of the reset transistor RST on the front surface 221a of the second semiconductor substrate 221. The gate electrodes SG and RG can be formed simultaneously in the same step. Next, the manufacturing apparatus forms a source and a drain of the selection transistor SEL on both sides of the gate electrode SG. In addition, the manufacturing apparatus forms a source and a drain of the reset transistor RST on both sides of the gate electrode RG. The source and drain of the selection transistor SEL and the source and drain of the reset transistor RST can be formed simultaneously in the same step.

[0087] Note that the step of forming the second semiconductor substrate 221 into an island shape can be performed before the step of forming the element isolation layer 223, the selection transistor SEL, and the reset transistor RST, which will be described later, or can be performed after this step, or can be performed in parallel with this step.

[0088] After performing the steps of forming the element isolation layer 223, the selection transistor SEL, and the reset transistor RST and the step of forming the second semiconductor substrate 221 into an island shape, the manufacturing apparatus forms an insulating film 225B on the front surface 221a side of the second semiconductor substrate 221 by a CVD method. The insulating film 225B is a part of the insulating film 225. Next, the manufacturing apparatus planarizes the surface of the insulating film 225B by a CMP method.

[0089] Next, asFigure 13 As shown, the manufacturing apparatus forms Figure 3 and Figures 4A to 4C the wirings L1 to L10, a plurality of pad electrodes 227, and the insulating film 225C shown. The insulating film 225C is a part of the insulating film 225. For example, the manufacturing apparatus repeats steps of forming contact holes in the insulating film or the semiconductor substrate, forming a metal material on the insulating film and in the contact holes, patterning the metal material, forming an insulating film, and planarizing the insulating film a plurality of times. As described above, the wirings extending in the vertical direction contain tungsten (W), and the wirings and the pad electrodes extending in the horizontal direction contain Cu or a Cu alloy. The manufacturing apparatus forms the insulating film 225C to cover the pad electrodes 227, and then planarizes the surface of the insulating film 225C by a CMP method, so that the front surface 227a of the pad electrodes 227 is exposed from the insulating film 225C. As a result, the second substrate portion 20 is completed.

[0090] Before or after the step of forming the first substrate portion 10 and the second substrate portion 20, or in parallel with this step, as Figure 14 shown, the manufacturing apparatus fabricates the third substrate portion 30. For example, the manufacturing apparatus forms a logic circuit 32 on the front surface 301a of the semiconductor substrate 301 by using a CMOS process (see Figure 1 ). In the step of forming the logic circuit 32, a silicide 303 is formed in the connection region between the semiconductor substrate 301 and the wiring L30. The silicide 303 contains a compound of the material of the semiconductor substrate 301 and the material of the wiring L30. For example, in the step of forming the logic circuit 32, a silicide formed by a self-aligned silicide process such as CoSi 2 or NiSi is formed on the surface of the impurity diffusion region in the semiconductor substrate 301.

[0091] Here, the sensor pixels 12 are formed in the first substrate portion 10, the read circuit 22 is formed in the second substrate portion 20, and the logic circuit 32 is formed in the third substrate portion 30. No silicide is formed in the sensor pixels 12 of the first substrate portion 10 and the read circuit 22 of the second substrate portion 20. Therefore, in the step of forming the sensor pixels 12 or in the step of forming the read circuit 22 described above, high-temperature processing such as thermal oxidation can be performed without being limited by the heat-resistant temperature of the silicide.

[0092] After forming the third substrate portion 30, the manufacturing apparatus places the front surface 301a of the semiconductor substrate 301 constituting the third substrate portion 30 to face the front surface 221a of the second semiconductor substrate 221 constituting the second substrate portion 20. Then, the manufacturing apparatus performs a heat treatment while maintaining close contact between the insulating film 304 on the front surface 301a side of the semiconductor substrate 301 and the insulating film 225 on the front surface 221a side of the second semiconductor substrate 221. As a result, as Figure 3 shown, the insulating films 304 and 225 are integrated to form an interlayer insulating film, and the second semiconductor substrate 221 and the semiconductor substrate 301 are bonded together with the interlayer insulating film interposed therebetween. The semiconductor substrate 11 of the first substrate portion 10, the first semiconductor substrate 211 and the second semiconductor substrate 221 of the second substrate portion 20, and the semiconductor substrate 301 of the third substrate portion 30 are sequentially stacked with insulating films interposed therebetween.

[0093] In addition, in the step of performing the heat treatment, the pad electrode 305 of the third substrate portion 30 and the pad electrode 227 of the second substrate portion 20 are integrated by Cu-Cu bonding. This Cu-Cu bonding greatly contributes to improving the bonding strength between the second substrate portion 20 and the third substrate portion 30. Through the above steps, the imaging device 1 is completed.

[0094] As described so far, the imaging device 1 according to the first embodiment of the present disclosure includes a first substrate portion 10 having sensor pixels 12 for performing photoelectric conversion and a second substrate portion 20 provided on the front surface 10a side of the first substrate portion 10 and having a reading circuit 22 for outputting a pixel signal based on the charge output from the sensor pixels 12. The second substrate portion 20 includes a first semiconductor substrate 211 on which an amplification transistor AMP included in the reading circuit 22 is provided and a second semiconductor substrate 221 provided on the front surface 211a side of the first semiconductor substrate 211 and on which a selection transistor SEL and a reset transistor RST included in the reading circuit 22 are provided.

[0095] According to the above configuration, compared with the case where all the transistors included in the reading circuit 22 are provided on one semiconductor substrate, the area of the arrangement region of the transistors can be increased. Therefore, the degree of freedom in layout on the reading circuit 22 is improved. Therefore, in each pixel unit PU, the gate area of the amplification transistor AMP can be maximized, and thus good noise characteristics can be achieved. Since the area of the amplification transistor AMP is maximized, the random noise generated in the imaging device 1 can be reduced.

[0096] (Second Embodiment)

[0097] In the above-described first embodiment, the manufacturing method of the second substrate portion 20 including laminating the second semiconductor substrate 221 on the first semiconductor substrate 211 has been described. However, the manufacturing method of the second substrate portion 20 according to an embodiment of the present disclosure is not limited to the above method.

[0098] Figure 15 and Figure 16 are cross-sectional views of a manufacturing method of the imaging device 1A according to a second embodiment of the present disclosure. In Figure 15 , the steps up to the step of forming the insulating film 215 on the front surface 211a side of the first semiconductor substrate 211 and planarizing the surface of the insulating film 215 are the same as those in the first embodiment. After planarizing the insulating film 215, the manufacturing apparatus forms a semiconductor film 221A on the insulating film 215. Examples of the semiconductor film 221A include any one of oxide semiconductors such as polysilicon (Poly-Si), polycrystalline germanium (Poly-Ge), or IGZO (InGaZnO), 2D materials (substantially two-dimensional materials having such a small thickness of one or several atoms), III-V group semiconductors, and laminated films containing at least any one of these semiconductors.

[0099] Next, as Figure 16 shown, the manufacturing apparatus forms the semiconductor film 221A into an island shape in a plan view by removing a part of the semiconductor film 221A. For example, a resist pattern is formed by photolithography, and the semiconductor film 221A is dry-etched using the resist pattern as a mask to remove a part of the semiconductor film 221A. In this dry etching, the insulating film 215 serves as an etching stopper layer.

[0100] In addition, before or after the step of forming the semiconductor film 221A into an island shape, or in parallel with this step, the manufacturing apparatus forms an element isolation layer 223, a selection transistor SEL, and a reset transistor RST (see Figure 4A ) on the front surface 221Aa side of the semiconductor film 221A by using a CMOS process. For example, after forming the element isolation layer 223, the manufacturing apparatus forms a gate electrode SG of the selection transistor SEL and a gate electrode RG of the reset transistor RST on the front surface 221Aa of the semiconductor film 221A. The gate electrodes SG and RG can be formed simultaneously in the same step. Next, the manufacturing apparatus forms a source and a drain of the selection transistor SEL on both sides of the gate electrode SG. In addition, the manufacturing apparatus forms a source and a drain of the reset transistor RST on both sides of the gate electrode RG. The source and drain of the selection transistor SEL and the source and drain of the reset transistor RST can be formed simultaneously in the same step.

[0101] Note that the step of forming the semiconductor film 221A into an island shape can be performed before the steps of forming the element isolation layer 223, the selection transistor SEL, and the reset transistor RST, which will be described later, or can be performed after that step, or can be performed in parallel with that step.

[0102] The subsequent steps are the same as those in the first embodiment. The manufacturing apparatus forms an insulating film 225B (see Figure 12 ) on the front surface 221Aa side of the semiconductor film 221A and planarizes the surface of the insulating film 225B. Next, the manufacturing apparatus forms Figure 3 and Figures 4A to 4C the wirings L1 to L10, a plurality of pad electrodes 227 (see Figure 13 ) and an insulating film 225C (see Figure 13 ) as shown. Then, the manufacturing apparatus exposes the front surface 227a (see Figure 13 ) of the pad electrode 227 from the insulating film 225C. As a result, the second substrate portion 20A is completed. After forming the second substrate portion 20A, the manufacturing apparatus bonds the third substrate portion 30 to the second substrate portion 20A. As a result, the imaging device 1A is completed.

[0103] The imaging device 1A according to the second embodiment of the present disclosure includes a first substrate portion 10 having sensor pixels for performing photoelectric conversion and a second substrate portion 20A provided on the front surface 10a side of the first substrate portion 10 and having a read circuit 22 for outputting a pixel signal based on the charge output from the sensor pixels 12. The second substrate portion 20A includes a first semiconductor substrate 211 on which an amplifier transistor AMP included in the read circuit 22 is provided, and a semiconductor film 221A provided on the front surface 211a side of the first semiconductor substrate 211 and on which a selection transistor SEL and a reset transistor RST included in the read circuit 22 are provided.

[0104] According to the above configuration, compared with the case where all the transistors included in the read circuit 22 are only provided on the substrate surface, the area of the transistor arrangement region can be increased. Therefore, the degree of freedom of the layout on the read circuit 22 is improved. Therefore, in each pixel unit PU, the gate area of the amplifier transistor AMP can be maximized, and thus good noise characteristics can be achieved. Since the area of the amplifier transistor AMP is maximized, the random noise generated in the imaging device 1A can be reduced.

[0105] The required noise characteristics of the selection transistor and the reset transistor are not as strict as those of the amplification transistor. For this reason, as in the second embodiment, even when the selection transistor SEL and the reset transistor RST are formed on a semiconductor film 221A containing polysilicon or the like instead of a single-crystal semiconductor substrate, the imaging device 1A can achieve good noise characteristics.

[0106] (Third Embodiment)

[0107] In the above-described first embodiment, a structure has been described in which wirings L2 (i.e., floating diffusion part contacts) electrically connected to the floating diffusion part FD and wirings L10 (i.e., well contacts) electrically connected to the well layer WE are provided for each of the plurality of sensor pixels 12 (see Figure 4C ). However, the embodiments of the present disclosure are not limited to this structure. In the embodiments of the present disclosure, one floating diffusion part contact may be provided for every plurality of sensor pixels 12. For example, four adjacent sensor pixels 12 may share one floating diffusion part contact. Similarly, one well contact may be provided for every plurality of sensor pixels 12. For example, four adjacent sensor pixels 12 may share one well contact.

[0108] Figures 17 to 19 FIG. 12 is a cross-sectional view in the thickness direction of a configuration example of the imaging device 1B according to the third embodiment of the present disclosure. Figures 20 to 22 FIG. 13 is a cross-sectional view in the horizontal direction of a layout example of a plurality of pixel units PU according to the third embodiment of the present disclosure. Note that Figures 17 to 19 the cross-sectional views in FIGS. 12 and 13 are schematic and are not intended to strictly show the actual structure. In the cross-sectional view of Figures 17 to 19 FIG. 12, for the sake of facilitating the explanation of the configuration of the imaging device 1B, the positions of the transistors and the impurity diffusion layers are intentionally changed in the strict horizontal direction between position sec1 and position sec3.

[0109] Specifically, in the pixel unit PU of the imaging device 1B in Figure 17 FIG. 12, the cross-section at position sec1 corresponds to the cross-section taken along the line A1 - A1' in Figure 20 FIG. 12, the cross-section at position sec2 corresponds to the cross-section taken along the line B1 - B1' in Figure 21 FIG. 12, and the cross-section at position sec3 corresponds to the cross-section taken along the line C1 - C1' in Figure 22 FIG. 12. Similarly, in the imaging device 1B in Figure 18 FIG. 13, the cross-section at position sec1 corresponds to the cross-section taken along the line A2 - A2' in Figure 20 FIG. 13, the cross-section at position sec2 corresponds to the cross-section taken along the line B2 - B2' in Figure 21The cross-section taken along line B2-B2' in, and the cross-section at position sec3 corresponds to along Figure 22 The cross-section taken along line C2-C2' in. In Figure 19 In the imaging device 1B of, the cross-section at position sec1 corresponds to along Figure 20 The cross-section taken along line A3-A3' in, the cross-section at position sec2 corresponds to along Figure 21 The cross-section taken along line B3-B3' in, and the cross-section at position sec3 corresponds to along Figure 22 The cross-section taken along line C3-C3' in.

[0110] As Figure 18 And Figure 22 As shown in, in the imaging device 1B, a common pad electrode 102 (which is an example of the "first common pad electrode" according to the present disclosure) provided across a plurality of sensor pixels 12 and a wiring L2 provided on the common pad electrode 102 are shared. For example, in a plan view, the imaging device 1B includes a region where the floating diffusion portions FD1 to FD4 of four sensor pixels 12 are adjacent to each other via an element isolation layer 16. In this region, the common pad electrode 102 is provided. The common pad electrode 102 is provided to straddle the four floating diffusion portions FD1 to FD4 and is electrically connected to each of the four floating diffusion portions FD1 to FD4. For example, the common pad electrode 102 includes a polysilicon film doped with n-type impurities or p-type impurities.

[0111] A wiring L2 (i.e., a contact for the floating diffusion portion) is provided on the central portion of the common pad electrode 102. As Figure 18 And Figures 20 to 22 As shown in, the wiring L2 provided on the central portion of the common pad electrode 102 penetrates the lower substrate 210 of the second substrate portion 20 from the first substrate portion 10 and extends to the upper substrate 220 of the second substrate portion 20. Therefore, the wiring L2 is connected to the gate electrode AG of the amplification transistor AMP via wirings provided on the upper substrate 220.

[0112] In addition, as Figure 17 And Figure 22As shown, in the imaging device 1B, a common pad electrode 110 (which is an example of the "second common pad electrode" according to the present disclosure) that spans multiple sensor pixels 12 and a wiring L10 disposed on the common pad electrode 110 are shared. For example, in a plan view, the imaging device 1B includes a region where the well layers WE of four sensor pixels 12 are adjacent to each other via the element isolation layer 16. In this region, the common pad electrode 110 is provided. The common pad electrode 110 is provided to span the well layers WE of the four sensor pixels 12 and is electrically connected to each of the well layers WE of the four sensor pixels 12. In a certain example, the common pad electrode 110 is provided between a common pad electrode 102 and another common pad electrode 102 arranged side by side in the Y-axis direction. In the Y-axis direction, the common pad electrodes 102 and 110 are alternately arranged. For example, the common pad electrode 110 includes a polysilicon film doped with n-type impurities or p-type impurities.

[0113] A wiring L10 (i.e., a contact for the well) is provided on the central portion of the common pad electrode 110. As Figure 17 and Figures 19 to 22 shown, the wiring L10 provided on the central portion of the common pad electrode 110 penetrates the lower substrate 210 of the second substrate portion 20 from the first substrate portion 10, extends to the upper substrate 220 of the second substrate portion 20, and is connected to a reference potential line that supplies a reference potential (e.g., ground potential: 0V) via wirings and the like provided on the upper substrate 220.

[0114] The wiring L10 provided on the central portion of the common pad electrode 110 is electrically connected to the upper surface of the common pad electrode 110, the inner surface of the through-hole provided in the lower substrate 210, and the inner surface of the through-hole provided in the upper substrate 220. As a result, the well layer WE in the semiconductor substrate 11 of the first substrate portion 10 and the well layers in the lower substrate 210 and the upper substrate 220 of the second substrate portion 20 are connected to the reference potential (e.g., ground potential: 0V).

[0115] The imaging device 1B according to the third embodiment of the present disclosure provides an effect similar to that provided by the imaging device 1 according to the first embodiment. In addition, the imaging device 1B further includes a common pad electrode 102 and a common pad electrode 110 that are provided on the front surface 11a side of the semiconductor substrate 11 constituting the first substrate portion 10 and are respectively provided so as to straddle a plurality of (for example, four) adjacent sensor pixels 12. The common pad electrode 102 is electrically connected to the floating diffusion portions FD of the four sensor pixels 12. The common pad electrode 110 is electrically connected to the well layers WE of the four sensor pixels 12. According to this configuration, every four sensor pixels 12 can share the wiring L2 connected to the floating diffusion portion FD. Every four sensor pixels 12 can share the common wiring L10 connected to the well layer WE. Therefore, the number of the wirings L2 and L10 can be reduced, thereby reducing the area of the sensor pixels 12 and reducing the size of the imaging device 1B.

[0116] (Fourth Embodiment)

[0117] In the above-described first embodiment, the element isolation layer 16 that electrically isolates adjacent sensor pixels 12 from each other has been described as being provided on the semiconductor substrate 11. In the embodiments of the present disclosure, the element isolation layer 16 may be provided to extend from the front surface 11a of the semiconductor substrate 11 toward the back surface 11b, or may be provided to extend from the back surface 11b toward the front surface 11a. For example, in the structure of the imaging device 1 according to the first embodiment, the element isolation layer 16 is provided to extend from the front surface 11a of the semiconductor substrate 11 toward the back surface 11b. The fourth embodiment illustrates a structure in which the element isolation layer 16 is provided to extend from the back surface 11b of the semiconductor substrate 11 toward the front surface 11a.

[0118] Figure 23 is a cross-sectional view in the thickness direction of a configuration example of the imaging device 1C according to the fourth embodiment of the present disclosure. As Figure 23 shown, in the imaging device 1C, the element isolation layer 16 is provided to extend from the back surface 11b (i.e., the light incident surface) of the semiconductor substrate 11 toward the front surface 11a. For example, the element isolation layer 16 is a deep trench isolation (DTI). The element isolation layer 16 is formed by forming a deep trench from the back surface 11b toward the front surface 11a and embedding an insulating film such as silicon oxide in the deep trench. With this configuration, the imaging device 1C can also provide an effect similar to that provided by the imaging device 1 according to the first embodiment.

[0119] Note that Figure 23shows a structure in which the element isolation layer 16 is provided to extend from the back surface 11b of the semiconductor substrate 11 into the semiconductor substrate 11, but this structure is merely an example. In the fourth embodiment, the element isolation layer 16 may reach the front surface 11a of the semiconductor substrate 11. That is, the element isolation layer 16 may penetrate the semiconductor substrate 11.

[0120] (Other embodiments)

[0121] Thus far, the present disclosure has been described based on embodiments and variations. However, the provision of the specification or drawings included in the present disclosure should not be construed as limiting the present disclosure. According to the present disclosure, various alternative embodiments, examples, and operation techniques are obvious to those skilled in the art.

[0122] For example, in the above-described first embodiment, the amplification transistor AMP is provided on the first semiconductor substrate 211, while the selection transistor SEL and the reset transistor RST are provided on the second semiconductor substrate 221. However, the embodiments of the present disclosure are not limited thereto. The selection transistor SEL and the reset transistor RST may be provided on the first semiconductor substrate 211, while the amplification transistor AMP may be provided on the second semiconductor substrate 221. Alternatively, one of the selection transistor SEL and the reset transistor RST and the amplification transistor AMP may be provided on the first semiconductor substrate 211, while the other of the selection transistor SEL and the reset transistor RST may be provided on the second semiconductor substrate 221.

[0123] In the above-described second embodiment, the amplification transistor AMP is provided on the first semiconductor substrate 211, while the selection transistor SEL and the reset transistor RST are provided on the semiconductor film 221A. However, the embodiments of the present disclosure are not limited thereto. The selection transistor SEL and the reset transistor RST may be provided on the first semiconductor substrate 211, while the amplification transistor AMP may be provided on the semiconductor film 221A. Alternatively, one of the selection transistor SEL and the reset transistor RST and the amplification transistor AMP may be provided on the first semiconductor substrate 211, while the other of the selection transistor SEL and the reset transistor RST may be provided on the semiconductor film 221A.

[0124] As described above, it goes without saying that the present technology includes various embodiments and the like not described herein. Within the gist of the above-described embodiments and variations, at least one of omission of components, replacement of components, and change of components can be performed. In addition, the effects described herein are merely examples and not restrictive. Any other effects may also be provided.

[0125] Note that the present disclosure can also have the following configuration.

[0126] (1) An imaging device, comprising:

[0127] A first substrate portion including sensor pixels for performing photoelectric conversion; and

[0128] A second substrate portion provided on one surface side of the first substrate portion and including a reading circuit for outputting a pixel signal based on charges output from the sensor pixels, wherein

[0129] The second substrate portion includes:

[0130] A first semiconductor substrate on which a first transistor included in the reading circuit is provided; and

[0131] A second semiconductor substrate provided on one surface side of the first semiconductor substrate and on which a second transistor included in the reading circuit is provided.

[0132] (2) An imaging device including:

[0133] A first substrate portion including sensor pixels for performing photoelectric conversion; and

[0134] A second substrate portion provided on one surface side of the first substrate portion and including a reading circuit for outputting a pixel signal based on charges output from the sensor pixels, wherein

[0135] The second substrate portion includes:

[0136] A first semiconductor substrate on which a first transistor included in the reading circuit is provided; and

[0137] A semiconductor film provided on one surface side of the first semiconductor substrate, and

[0138] A second transistor included in the reading circuit is provided on the semiconductor film.

[0139] (3) The imaging device according to (1) or (2), wherein

[0140] In the thickness direction of the second substrate portion, the first transistor and the second transistor overlap.

[0141] (4) The imaging device according to any one of (1) to (3), wherein

[0142] The sensor pixels include:

[0143] A photoelectric conversion element;

[0144] A transfer transistor electrically connected to the photoelectric conversion element; and

[0145] A floating diffusion section that temporarily holds charges output from the photoelectric conversion element via the transfer transistor,

[0146] The reading circuit includes:

[0147] A reset transistor that resets the potential of the floating diffusion section to a predetermined potential;

[0148] An amplification transistor that generates a signal having a voltage corresponding to the level of the charge held in the floating diffusion section as the pixel signal; and

[0149] A selection transistor that controls the output timing of the pixel signal from the amplification transistor,

[0150] The first transistor includes the amplification transistor, and

[0151] The second transistor includes the reset transistor and the selection transistor.

[0152] (5) The imaging device according to (4), wherein

[0153] One of the reading circuits is electrically connected to a plurality of the sensor pixels to form a pixel unit, and

[0154] In a plan view seen from the thickness direction of the laminate including the first substrate portion and the second substrate portion, the amplification transistor is located in the central portion of the pixel unit.

[0155] (6) The imaging device according to (5), wherein

[0156] The laminate includes a wiring group electrically connected to the sensor pixels, and

[0157] In the plan view seen from the thickness direction of the laminate, at least a part of the wiring group is arranged symmetrically with respect to the amplification transistor, sandwiching it left and right.

[0158] (7) The imaging device according to any one of (1) to (6), further comprising:

[0159] A third substrate portion provided on the side of the second substrate portion opposite to the surface facing the first substrate portion, wherein

[0160] A logic circuit for processing the pixel signal is provided on the third substrate portion.

[0161] (8) The imaging device according to (7), wherein

[0162] Silicide is provided in the third substrate portion.

[0163] (9) The imaging device according to any one of (1) to (8) further includes:

[0164] A first common pad electrode provided on the one surface side of the first substrate portion and provided to straddle a plurality of adjacent sensor pixels, wherein

[0165] Each of the sensor pixels includes:

[0166] A photoelectric conversion element;

[0167] A transfer transistor electrically connected to the photoelectric conversion element; and

[0168] A floating diffusion portion that temporarily holds charges output from the photoelectric conversion element via the transfer transistor, and

[0169] The first common pad electrode is electrically connected to the floating diffusion portions of the plurality of sensor pixels.

[0170] (10) The imaging device according to any one of (1) to (9) further includes:

[0171] A second common pad electrode provided on the one surface side of the first substrate portion and provided to straddle a plurality of adjacent sensor pixels, wherein

[0172] Each of the sensor pixels has a well layer, and

[0173] The second common pad electrode is electrically connected to the well layers of the plurality of sensor pixels.

[0174] (11) The imaging device according to any one of (1) to (10) further includes:

[0175] An element isolation layer provided in the first substrate portion and provided between a plurality of adjacent sensor pixels, wherein

[0176] The element isolation layer is provided to extend from the one surface of the first substrate portion toward the other surface on the opposite side of the one surface.

[0177] (12) The imaging device according to any one of (1) to (10) further includes:

[0178] An element isolation layer provided in the first substrate portion and provided between a plurality of adjacent sensor pixels, wherein

[0179] The element isolation layer is provided to extend from the other surface on the opposite side of the one surface of the first substrate portion toward the one surface.

[0180] List of Reference Numerals

[0181] 1, 1A, 1B, 1C: Imaging Device

[0182] 10: First Substrate Portion (Bottom Substrate)

[0183] 10a, 11a, 211a, 221a, 221Aa, 227a, 301a: Front Surface

[0184] 11, 301: Semiconductor Substrate

[0185] 12: Sensor Pixel

[0186] 13: Pixel Region

[0187] 15, 215, 217, 225, 225A, 225B, 225C, 304: Insulating Film

[0188] 16, 213, 223: Element Isolation Layer

[0189] 17: Impurity Diffusion Layer

[0190] 20, 20A: Second Substrate Portion

[0191] 22: Read Circuit

[0192] 23: Pixel Drive Line

[0193] 24: Vertical Signal Line

[0194] 30: Third Substrate Portion

[0195] 32: Logic Circuit

[0196] 33: Vertical Drive Circuit

[0197] 34: Column Signal Processing Circuit

[0198] 35: Horizontal Drive Circuit

[0199] 36: System Control Circuit

[0200] 303: Silicide

[0201] 51, 53: Interlayer Insulating Film

[0202] 102, 110: Common Pad Electrode

[0203] 210: Lower Substrate (Intermediate Substrate)

[0204] 211: First Semiconductor Substrate

[0205] 11b, 211b, 221b: Back Surface

[0206] 220: Upper substrate (top substrate)

[0207] 221: Second semiconductor substrate

[0208] 221A: Semiconductor film

[0209] 227, 305: Pad electrode

[0210] AG: Gate electrode

[0211] AMP: Amplifying transistor

[0212] FD: Floating diffusion section

[0213] L1 to L10, L30: Wiring

[0214] PD: Photodiode

[0215] PU: Pixel unit

[0216] RG: Gate electrode

[0217] RST: Reset transistor

[0218] sec1, sec2, sec3: Position

[0219] SEL: Selection transistor

[0220] SG: Gate electrode

[0221] TG: Gate electrode

[0222] TR: Transfer transistor

[0223] VDD: Power supply line

[0224] Vout: Output voltage

[0225] WE: Well layer

Claims

1. An imaging device, which comprises: a first substrate portion including sensor pixels for performing photoelectric conversion; and a second substrate portion provided on one surface side of the first substrate portion and including a read circuit for outputting a pixel signal based on charges output from the sensor pixels, wherein, the second substrate portion includes: a first semiconductor substrate on which a first transistor included in the read circuit is provided; and a second semiconductor substrate provided on one surface side of the first semiconductor substrate and on which a second transistor included in the read circuit is provided, wherein a laminate of the first substrate portion and the second substrate portion includes a wiring group electrically connected to the sensor pixels, and in a plan view seen from the thickness direction of the laminate, at least a part of the wiring group is provided symmetrically to the left and right with the amplifying transistor of the read circuit interposed therebetween.

2. The imaging device according to claim 1, wherein, in the thickness direction of the second substrate portion, the first transistor and the second transistor overlap.

3. The imaging device according to claim 1, wherein, the sensor pixels include: a photoelectric conversion element; a transfer transistor electrically connected to the photoelectric conversion element; and a floating diffusion portion for temporarily holding charges output from the photoelectric conversion element via the transfer transistor, the read circuit includes: a reset transistor for resetting the potential of the floating diffusion portion to a predetermined potential; the amplifying transistor for generating a signal having a voltage corresponding to the level of the charges held in the floating diffusion portion as the pixel signal; and a selection transistor for controlling the output timing of the pixel signal from the amplifying transistor, the first transistor includes the amplifying transistor, and the second transistor includes the reset transistor and the selection transistor.

4. The imaging device according to claim 3, wherein, one read circuit is electrically connected to a plurality of the sensor pixels to form one pixel unit, and in the plan view seen from the thickness direction of the laminate, the amplifying transistor is located in the central portion of the pixel unit.

5. The imaging device according to claim 1, which further comprises: a third substrate portion provided on the side of the second substrate portion opposite to the surface facing the first substrate portion, wherein, a logic circuit for processing the pixel signal is provided on the third substrate portion.

6. The imaging device according to claim 5, wherein, silicide is provided in the third substrate portion.

7. The imaging device according to claim 1, which further comprises: a first common pad electrode provided on the one surface side of the first substrate portion and provided to straddle a plurality of adjacent sensor pixels, wherein, the sensor pixels each include: a photoelectric conversion element; a transfer transistor electrically connected to the photoelectric conversion element; and a floating diffusion portion for temporarily holding charges output from the photoelectric conversion element via the transfer transistor, and The first common pad electrode is electrically connected to the floating diffusions of the plurality of sensor pixels.

8. The imaging device according to claim 1, further comprising: A second common pad electrode, which is provided on the one surface side of the first substrate portion and is provided to straddle a plurality of adjacent sensor pixels, wherein, The sensor pixels each have a well layer, and The second common pad electrode is electrically connected to the well layers of the plurality of sensor pixels.

9. The imaging device according to any one of claims 1 to 8, further comprising: An element isolation layer, which is provided in the first substrate portion and is provided between a plurality of adjacent sensor pixels, wherein, The element isolation layer is provided to extend from the one surface of the first substrate portion toward the other surface located on the opposite side of the one surface.

10. The imaging device according to any one of claims 1 to 8, further comprising: An element isolation layer, which is provided in the first substrate portion and is provided between a plurality of adjacent sensor pixels, wherein, The element isolation layer is provided to extend from the other surface of the first substrate portion located on the opposite side of the one surface toward the one surface.

11. An imaging device, which comprises: A first substrate portion, which includes sensor pixels for performing photoelectric conversion; and A second substrate portion, which is provided on the one surface side of the first substrate portion and includes a read circuit for outputting a pixel signal based on charges output from the sensor pixels, wherein, The second substrate portion includes: A first semiconductor substrate, on which a first transistor included in the read circuit is provided; and A semiconductor film, which is provided on the one surface side of the first semiconductor substrate, and on which a second transistor included in the read circuit is provided, wherein the laminate of the first substrate portion and the second substrate portion includes a wiring group electrically connected to the sensor pixels, and In a plan view seen from the thickness direction of the laminate, at least a part of the wiring group is provided symmetrically on the left and right with the amplifying transistor of the read circuit interposed therebetween.

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