Method of forming a fin field effect transistor

Abstract

The method of forming a fin field effect transistor includes: etching first and second semiconductor fins to form first and second recesses, epitaxially growing an n-type source / drain region, the n-type source / drain region including first and second portions from the first and second recesses and a first intermediate portion therebetween having a concave top surface. A first contact opening is formed and extends into the n-type source / drain region and has a V-shaped bottom. The method also includes: etching third and fourth semiconductor fins to form third and fourth recesses, and forming a p-type source / drain region, the p-type source / drain region including third and fourth portions from the third and fourth recesses and a second intermediate portion therebetween having a convex top surface. A second contact opening is formed and has a second V-shaped bottom, the tip of the second V-shaped bottom pointing downward.

Description

Technical Field

[0001] Embodiments of the present invention are directed to methods of forming fin field effect transistors. Background Art

[0002] In the formation of a FinFET, source / drain regions are typically constructed by forming a semiconductor fin, recessing the semiconductor fin to form a recess, and growing an epitaxial region from the recess.

[0003] The epitaxial regions grown from the recesses of the adjacent semiconductor fins may merge with each other, so that the resulting epitaxial regions may have a flat top surface. Source / drain contact plugs are formed to electrically connect to the source / drain regions. Summary of the invention

[0004] According to one aspect of an embodiment of the present invention, a method for forming a fin field effect transistor is provided, comprising: forming an n-type fin field effect transistor (FinFET), comprising: forming a first gate stack on a first semiconductor fin and a second semiconductor fin; etching first portions of the first semiconductor fin and the second semiconductor fin to form a first recess and a second recess, respectively; and performing a first epitaxial process to form an n-type source / drain region, wherein the n-type source / drain region includes a first portion grown from the first recess and a second portion grown from the second recess, and a first middle portion connected to the first portion and the second portion, wherein the first middle portion has a concave top surface; and forming a p-type FinFET, comprising: forming a second gate stack on a third semiconductor fin and a fourth semiconductor fin; etching second portions of the third semiconductor fin and the fourth semiconductor fin to form a third recess and a fourth recess, respectively; and performing a second epitaxial process to form a p-type source / drain region, wherein the source / drain region includes a third portion grown from the third recess and a fourth portion grown from the fourth recess, and a second middle portion connected to the third portion and the fourth portion, wherein the second middle portion has a convex top surface.

[0005] According to another aspect of an embodiment of the present invention, a method for forming a fin field effect transistor is provided, comprising: forming an n-type fin field effect transistor (FinFET), comprising: forming an n-type source / drain region, comprising: depositing a first epitaxial layer, wherein the first epitaxial layer includes a first portion grown in a first recess in a first semiconductor fin, a second portion grown in a second recess in a second semiconductor fin, and a first intermediate portion connecting the first portion to the second portion; and depositing a first capping layer over the first epitaxial layer, wherein the first capping layer includes a second intermediate portion directly over the first intermediate portion, and the second intermediate portion has a concave top surface; and forming a p-type FinFET, comprising forming a p-type source / drain region, comprising: depositing a second epitaxial layer, the second epitaxial layer includes a third portion grown in a third recess in a third semiconductor fin, a fourth portion grown in a fourth recess in a fourth semiconductor fin, and a third intermediate portion connecting the third portion to the fourth portion; and depositing a second capping layer over the second epitaxial layer, wherein the second capping layer includes a fourth intermediate portion directly over the third intermediate portion, and the fourth intermediate portion has a convex top surface.

[0006] According to another aspect of an embodiment of the present invention, a method for forming a fin field effect transistor is provided, comprising: etching a first semiconductor fin and a second semiconductor fin to form a first recess and a second recess, respectively; epitaxially growing an n-type source / drain region, the n-type source / drain region comprising: a first portion grown from the first recess; a second portion grown from the second recess; and a first intermediate portion located between the first portion and the second portion, wherein the first intermediate portion has a concave top surface; forming a first contact opening extending into the n-type source / drain region, wherein the first contact opening comprises a first V-shaped bottom; etching a third semiconductor fin and a fourth semiconductor fin to form a third recess and a fourth recess, respectively; forming a p-type source / drain region, the p-type source / drain region comprising: a third portion grown from the third recess; a fourth portion grown from the fourth recess; and a second intermediate portion located between the third portion and the fourth portion, wherein the second intermediate portion has a convex top surface; and forming a second contact opening extending into the p-type source / drain region, wherein the second intermediate portion having a convex top surface is etched, the second contact opening comprises a second V-shaped bottom, and the tip of the second V-shaped bottom points downward. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 , Figure 2 , Figure 3A , Figure 3B, Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B and Fig. 11C Depicted are perspective and cross-sectional views at intermediate stages in the formation of n-type FinFETs and p-type FinFETs according to some embodiments.

[0009] Fig.12 A process flow diagram for n-type FinFETs and p-type FinFETs according to some embodiments is shown. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0012] Provided are an n-type field effect transistor (FinFET), a p-type FinFET and a method for forming the same. According to some embodiments of the present disclosure, the n-type source / drain region of the n-type FinFET is deposited to have a wavy top surface, while the p-type source / drain region of the p-type FinFET is deposited to have a conical shape. This can reduce the bending of the semiconductor fin in the p-type FinFET, and at the same time, the contact area of ​​the contact plug to the n-type source / drain region and the p-type source / drain region can also be reduced. The silicide region formed on the n-type source / drain region and the p-type source / drain region can have a recessed middle portion (having a V-shaped shape). The embodiments discussed here will provide examples that can produce or use the subject matter of the present disclosure, and it is easy for a person of ordinary skill in the art to understand the improvements made within the scope of different embodiments. Throughout the various views and exemplary embodiments, similar reference numerals are used to designate similar elements. Although the method embodiments can be discussed as being implemented in a particular order, other method embodiments can be implemented in any logical order.

[0013] Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B and Fig. 11C Depicts perspective and cross-sectional views at intermediate stages in forming n-type FinFETs and p-type FinFETs according to some disclosed embodiments. Fig.12 The process flow diagram is shown.

[0014] Figure 1 A perspective view of an initial structure is shown. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 can be a semiconductor substrate, which can be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The top surface of the substrate 20 can have a (100) surface plane. The substrate 20 can be doped with p-type impurities or n-type impurities. Isolation regions 22 such as shallow trench isolation (STI) can be formed to extend from the top surface of the substrate 20 into the substrate 20. The portion of the substrate 20 located between adjacent STI regions 22 is called a semiconductor strip 24. According to some embodiments, the top surface of the semiconductor strip 24 and the top surface of the STI region 22 can be substantially flush with each other.

[0015] STI regions 22 may include a liner oxide (not shown) formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer, for example, formed using atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (FCVD). STI regions 22 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using fluid chemical vapor deposition (FCVD), spin coating, or the like.

[0016] Wafer 100 includes an n-type device region 100N for forming n-type FinFETs, and a p-type device region 100P for forming p-type FinFETs. In order to distinguish components in n-type device region 100N and p-type device region 100P from each other, components formed in n-type device region 100N may be referenced by reference numerals ending with the letter "N", and components formed in p-type device region 100P may be referenced by reference numerals ending with the letter "P". For example, semiconductor strip 24 in n-type device region 100N may be referenced as 24N, and semiconductor strip 24 in p-type device region 100P may be referenced as 24P. According to some embodiments, semiconductor strip 24N is formed of or includes silicon (without germanium), while semiconductor strip 24P is replaced with silicon germanium. According to an optional embodiment, semiconductor strips 24N and 24P are both formed of or include silicon without germanium.

[0017] Reference Figure 2 , the STI region 22 is recessed, so that the tops of the semiconductor strips 24N and 24P protrude higher than the top surface 22A of the STI region 22 to form protruding fins 24N' and 24P'. Fig.12 The process flow shown is shown as process 202. The semiconductor bands 24N and 24P portions in the STI region 22 are still referred to as semiconductor bands. Etching can be performed using a dry etching process, wherein a mixture of hydrogen fluoride HF and ammonia NH3 is used as an etching gas. The etching process can also use a mixture of nitrogen trifluoride NF3 and ammonia NH3 as an etching gas. During the etching process, plasma can be generated. Argon gas can also be included. According to some optional embodiments of the present disclosure, the recessing of the STI region 22 is performed using a wet etching process. For example, the etching chemical can include a hydrogen fluoride HF solution.

[0018] In accordance with some embodiments, fins for FinFETs may be formed / patterned using any suitable method. For example, the fins may be patterned using one or more lithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes, in combination with lithography and self-alignment processes, may allow the created pattern to have a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0019] Reference Figure 3A , Figure 3B and Figure 3C , a dummy gate stack 30 is formed on the top surface and sidewalls of the protruding fins 24N' and 24P'. Fig.12 The corresponding process is shown as process 204 in the process flow shown in FIG. According to some embodiments, a fin group used to form a FinFET may include multiple fins closely grouped together. For example, in Figure 3A The example shown shows a 2-fin group on the left and a single fin (or multi-fin fin group) on the right. The spacing of fins within the same fin group (called intra-group spacing) is smaller than the intra-group spacing between adjacent fin groups.

[0020] Figure 3B The cross-sectional view shown is for reference Figure 3A The middle BB section is obtained, and Figure 3C The cross-sectional view shown is for reference Figure 3A The pseudo gate stack 30 may include a pseudo gate dielectric 32 ( Figure 3B ) and a dummy gate electrode 34 located above the dummy gate dielectric 32. For example, the dummy gate electrode 34 can be formed using amorphous silicon or polycrystalline silicon, and other materials can also be used. Each dummy gate stack 30 can also include one (or more) hard mask layers 36 located above the dummy gate electrode 34. The hard mask layer 36 can be formed of silicon nitride, silicon carbonitride, or the like. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fin 24'.

[0021] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30 ( Figure 3A and Figure 3B ).exist Fig.12 The corresponding process is shown as process 206 in the process flow shown in FIG. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material such as silicon carbon nitride (SiCN), silicon nitride, silicon oxycarbon nitride (SiOCN), or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

[0022] According to some embodiments of the present disclosure, the gate spacers 38 are multi-layer gate spacers. For example, each gate spacer 38 may include a silicon nitride (SiN) layer and a SiOCN layer located above the silicon nitride layer. Figure 3A and Figure 3C Also shown are fin spacers 39 formed on the sidewalls of the protruding fins 24'. Fig.12 The corresponding process is also shown as process 206 in the process flow shown in FIG. 20. According to some embodiments of the present disclosure, the process of forming the fin spacer 39 is the same as the process of forming the gate spacer 38. For example, in the process of forming the gate spacer 38, a blanket dielectric layer is deposited to form the gate spacer 38. When etching is performed, some portions may remain on the sidewalls of the protruding fins 24'N and 24P', thereby forming the fin spacer 39. According to some embodiments, the fin spacer 39 includes fin spacers 39A and 39C ( Figure 3C ) are located on the outside of the outermost fins in the fin group. Fin spacers 39 further include inner fin spacers such as fin spacer 39B, which are located between fins 24N' and 24P' in the same fin group.

[0023] exist Figure 3B and the subsequent Figure 4B and Fig. 11B In the example, the plane of the top surface 22A of the STI 22 ( Figure 3A ) can be shown, and the semiconductor fin 24' is higher than the top surface 22A. The bottom surface 22B ( Figure 3A ) can also be shown in the cross-sectional view. STI region 22 is located at a level between 22A and 22B and is Figure 3B , Figure 4B and Fig. 11B are not shown because they are in a different plane than that shown.

[0024] Figure 4A , Figure 4B , Figure 4C , Figure 5 , Figure 6 , Fig. 7A and Figure 7BThe process of forming the n-type source / drain region 42N in the N-type device region 100N and the p-type source / drain region 42P in the p-type device region 100P is shown. In order to facilitate the comparison of the n-type source / drain region 42N and the p-type source / drain region 42P, the corresponding processes of forming the layers of the n-type source / drain region 42N and the p-type source / drain region 42P will be shown in the same figure. However, this does not mean that the corresponding layers in the n-type source / drain region 42N and the p-type source / drain region 42P are formed in a common process. Moreover, the n-type source / drain region 42N and the p-type source / drain region 42P are formed in independent process flows. According to some embodiments, the n-type source / drain region 42N is formed first, followed by the formation of the p-type source / drain region 42P. This means that in Figure 4A , Figure 4B , Figure 4C , Figure 5 , Figure 6 , Fig. 7A and Figure 7B The process shown in the n-type device region 100N is performed first, followed by Figure 4A , Figure 4B , Figure 4C , Figure 5 , Figure 6 , Fig. 7A and Figure 7B According to an alternative embodiment, the p-type source / drain regions 42P are formed first, followed by the formation of the n-type source / drain regions 42N.

[0025] refer to Figure 4A , Figure 4B and Figure 4C , an etching process (hereinafter also referred to as source / drain recessing process) is performed to recess the portions of the protruding fins 24N' and 24P' that are not covered by the dummy gate stack 30 and the gate spacer 38. In this way, recesses 40N and 40P are formed. Fig.12 The process flow shown in FIG. 2 is shown as processes 208N and 208P. Figure 4B and Figure 4C Shown by reference Figure 4A The cross-sectional views of BB and CC in FIG. Figure 4C The dashed lines in FIG. 1 show portions of the protruding fins 24N′ and 24P′ directly under the gate spacers 38 and the gate stack 30, shown in dashed lines because they are not in the plane shown. Likewise, the dashed lines also show recesses 40N and 40P. The recesses may be anisotropic, and thus portions of the fins 24N′ and 24P′ directly under the dummy gate stack 30 and the gate spacers 38 are protected and not etched. The recesses 40N and 40P are also located on opposite sides of the dummy gate stack 30, as shown in FIG. Figure 4AAlthough shown in the same figure, the formation of the recess 40N and the formation of the recess 40P may be performed in separate processes, such as Fig.12 The process flow is shown.

[0026] According to some embodiments of the present disclosure, the recessing process is performed by a dry etching process. The dry etching process may be performed using a process gas such as C2F6, CF4, SO2; a mixture of HBr, Cl2, and O2; a mixture of HBr, Cl2, O2, and CF2; or the like. The etching may be anisotropic. According to some embodiments of the present disclosure, such as Figure 4B As shown, the sidewalls of the protruding fins 24N' and 24P' facing the corresponding recesses 40N and 40P are substantially vertical and substantially flush with the outer sidewalls of the corresponding gate spacers 38. The sidewalls of the protruding fins 24N' and 24P' facing the recesses 40N and 40P may be at a (110) surface plane. According to some embodiments, the bottoms of the recesses 40N and 40P are higher than the top surface 22A of the STI region 22. According to alternative embodiments, the bottoms of the recesses 40N and 40P may be flush with or lower than the top surface 22A of the STI region 22.

[0027] According to some embodiments, during the etching of the protruding fin 24 ′, the fin spacer 39 is also etched so that the height of the outer spacer 39A and the inner spacer 39B is reduced. The protruding fins 24N′ and 24P′ may be more recessed than the fin spacer 39 .

[0028] Figure 5 , Figure 6 and Fig. 7A The process of depositing (sub)layers in epitaxial region 42 is shown. Again, although shown in the same view, the layers in n-type FinFET region 100N and p-type FinFET region 100P are actually formed in separate processes. For example, layers 42NA and 42PA are formed by separate deposition processes; layers 42NB and 42PB are formed by separate deposition processes; layers 42NC and 42PC are formed by separate deposition processes; Fig.12 The process flow is shown in .

[0029] refer to Figure 5 The epitaxial layer 42NA (also referred to as the epitaxial layer L1) is deposited in the n-type FinFET region 100N by an epitaxial process. Fig.12 The process flow shown is shown as process 210N. The cross-sectional shape of the epitaxial layer 42NA in reference cross section BB is Fig. 11B According to some embodiments, the deposition is performed by a non-conformal deposition process, so the bottom portion of the first layer 42NA is thicker than the sidewall portion. This occurs because the growth on the (100) surface of the semiconductor is faster than on the (110) surface.

[0030] The epitaxial layer 42NA may be deposited by reduced pressure chemical vapor deposition (RPCVD), plasma enhanced chemical vapor deposition (PECVD) or the like. Fig.11A and Fig. 11B ), phosphorus is discussed as an example of an n-type dopant, and other n-type dopants such as arsenic, antimony, or the like and combinations thereof may also be used. Fig.11A and Fig. 11B ), boron is discussed as an example of a p-type dopant, and other p-type dopants, such as indium, may be used.

[0031] According to some embodiments, epitaxial layer 42NA is formed of or includes silicon phosphide SiP. According to alternative embodiments, epitaxial layer 42NA is formed of or includes silicon arsenide SiAs. Also according to alternative embodiments, epitaxial layer 42NA is formed of or includes a silicon arsenide SiAs layer and a SiP layer above the SiAs layer. Depending on the desired composition of epitaxial layer 42NA, the process gas used to deposit epitaxial layer 42NA may include a silicon-containing gas such as silane, dichlorosilane (DCS), or the like. Epitaxial layer 42NA may have a carbon content in the range of about 1 x 10 20 / cm 3 and 8x 10 20 / cm 3 A first doping concentration (such as phosphorus or arsenic) between 0.1 and 0.2 is preferably selected from the group consisting of: a first doping concentration (such as phosphorus or arsenic) between 0.1 and 0.2. In the deposition process, an etching gas such as hydrogen chloride (HCl) is added to the process gas to achieve selective deposition on the semiconductor rather than on the dielectric. A carrier gas such as hydrogen H2 and / or N2 nitrogen may also be included in the process gas, for example with a flow rate ranging between about 50 sccm and 500 sccm.

[0032] Further references Figure 5 , the epitaxial layer 42PA (also referred to as the epitaxial layer L1) is deposited in the p-type FinFET region 100P by an epitaxial process. Fig.12The process flow shown is shown as process 210P. According to some embodiments, deposition is also performed by a non-conformal deposition process, so that the bottom portion of the first layer 42PA is thicker than the sidewall portion. The deposition can be performed using RPCVD, PECVD methods, or similar methods. According to some embodiments, the epitaxial layer 42PA is composed of or includes silicon germanium boride (SiGeB). Depending on the desired composition of the epitaxial layer 42PA, the process gas used to deposit the epitaxial layer 42PA may include: a silicon-containing gas such as silane, disilane (Si2H6), dichlorosilane (DCS) or the like; a germanium-containing gas such as germane (GeH4), digermane (Ge2H6) or the like; and a process gas containing a dopant such as B2H6 or the like. The epitaxial layer 42PA may have a range of approximately 1x 10 20 / cm 3 and 6x 10 20 / cm 3 The boron concentration may be between about 100 and about 500 Å. The germanium atomic percentage may be in a range between about 15% and about 40%.

[0033] According to some embodiments, Figure 5 As shown, the top surface of epitaxial layer 42NA is lower than the top of fin spacer 39. On the other hand, epitaxial layer 42PA grows larger than epitaxial layer 42NA, and the top surface of epitaxial layer 42PA is higher than the top of fin spacer 39. Accordingly, epitaxial layer 42PA expands laterally to form a small facet. According to some embodiments, as shown in FIG. Figure 5 In the cross-sectional view shown, the height H2 of the portion of the epitaxial layer 42PA exceeds the height H1 of the protruding fin 24 ′P by 50%, and may also exceed by about 70%.

[0034] Next, refer to Figure 6 , epitaxial layer 42NB (also labeled as epitaxial layer L2) is deposited. The corresponding process is Fig.12 The process flow is shown as process 212N. The deposition can be performed by RPCVD), PECVD, or the like. According to some embodiments, epitaxial layer 42NB includes silicon phosphide, and the second phosphorus concentration of phosphorus is higher than the first phosphorus concentration in epitaxial region 42NA. According to some embodiments, for example, the second phosphorus concentration in epitaxial region 42NB can be between about 8 x 10 20 / cm 3 and about 5x10 21 / cm 3 The process gas used to form the epitaxial layer 42NB may be similar to the process gas used to form the epitaxial layer 42NA, except that the flow rate of the process gas may be different from the flow rate of the corresponding process gas used in the formation of the epitaxial layer 42NA.

[0035] like Figure 6As shown, the top of the epitaxial layer 42NB is flush with the top of the protruding fin 24N′. Fig. 11B show Figure 6 Referring to the cross-sectional view of section BB in FIG. 1 , it is shown that the opposite ends of epitaxial layer 42NB are flush with the top surface of protruding fin 24N′, while the middle portion of the top surface of epitaxial layer 42NB may be lower than the top surface of protruding fin 24N′. Bottom end 42NB-B of epitaxial layer 42NB is also lower than bottom end 42PB-B of epitaxial layer 42PB, as shown in FIG. Fig. 11B shown.

[0036] The epitaxial layers 42NB grown from adjacent recesses merge with air gaps 44N sealed underneath the epitaxial layers 42NB. The top surface of the merged epitaxial layer 42NB may have a non-planar profile (also referred to as having a wavy shape), with the middle portion between adjacent semiconductor fins 24N' being lower than portions on opposite sides thereof.

[0037] Further references Figure 6 , epitaxial layer 42PB (also referred to as epitaxial layer L2) is deposited. The corresponding process is Fig.12 The process flow shown is shown as process 212P. The deposition can be performed by RPCVD), PECVD), or the like. According to some embodiments, epitaxial layer 42PB includes boronized silicon germanium, wherein the boron has a second boron concentration that is higher than the boron concentration in epitaxial layer 42PA. According to some embodiments, for example, the boron concentration in epitaxial region 42PB can be between about 6 x 10 20 / cm 3 and approximately 3x 10 21 / cm 3 In addition, the germanium atomic percentage in epitaxial layer 42PB is higher than the germanium atomic percentage in epitaxial layer 42PA. According to some embodiments, for example, the germanium atomic percentage in epitaxial layer 42PB is in a range between about 40% and 60%. The process gas used to form epitaxial layer 42PB can be similar to the process gas used to form epitaxial layer 42PA, except that the flow rate of the process gas can be different from the flow rate of the corresponding process gas in the formation of epitaxial layer 42NA.

[0038] The top of the epitaxial layer 42PB is flush with the top of the protruding fin 24P′. Fig. 11B show Figure 6 Referring to the cross-sectional view of section BB, it is shown that opposite ends of the epitaxial layer 42PB are flush with the top surface of the protruding fin 24P′, while a middle portion of the top surface of the epitaxial layer 42PB may be lower than the top surface of the protruding fin 24N′.

[0039] The epitaxial layer 42PB grown from adjacent recesses is fused, with the air gap 44N sealed under the epitaxial layer 42PB. The top surface of the fused epitaxial layer 42PB may have a non-planar profile (also referred to as having a wavy shape), and the middle portion between adjacent semiconductor fins 24P' (and the corresponding recess 40P) is lower than the portion on the opposite side thereof. According to an optional embodiment, the top surface of the fused epitaxial layer 42PB may have a planar profile (also referred to as having a non-wavy shape), and the corresponding planar top surface is marked with a dotted line 43.

[0040] Fig. 7A The epitaxial process for depositing epitaxial layer 42NC (also referred to as epitaxial layer L3 or capping layer) is shown. Fig.12 The process flow shown is shown as process 214N. The deposition process can be performed using RPCVD, PECVD, or the like. According to some embodiments, epitaxial layer 42NC includes silicon phosphide. In addition, metallic germanium can be added, for example, the atomic percentage of germanium is in the range of about 1% to about 5%. According to some embodiments, the phosphorus concentration in epitaxial region 42NC can be about 1x10 21 / cm 3 and approximately 3x 10 21 / cm 3 The process gas for forming epitaxial layer 42NC may be similar to the process gas for forming epitaxial layer 42NB, except that a germanium-containing gas such as germane, digermane, or the like may be added. Throughout the description, epitaxial layers 42NA, 42NB, and 42NC are collectively or individually referred to as epitaxial layers or epitaxial regions 42N, and are collectively referred to as source / drain regions 42N hereinafter.

[0041] Fig. 7A The epitaxial process for depositing the epitaxial layer 42PC (also referred to as the epitaxial layer L3 or the capping layer) is further shown. Fig.12 The process flow shown is shown as process 214P. The deposition process can be performed by RPCVD, PECVD or the like. The top surface of epitaxial layer 42PC has a non-wavy shape, the middle portion of the top surface is the highest, and the opposite portion of the top surface gradually decreases. According to some embodiments, epitaxial layer 42PC includes boronized silicon germanium. According to some embodiments, the boron concentration in epitaxial region 42PC is about 8x 10 20 / cm 3 to about 1x 10 21 / cm 3In addition, the germanium atomic percentage in epitaxial layer 42PC is lower than the germanium atomic percentage in epitaxial layer 42PB. According to some embodiments, for example, the germanium atomic percentage in epitaxial layer 42PC is in a range between about 45% and about 55%. Throughout the description, epitaxial layers 42PA, 42PB, and 42PC are collectively or individually referred to as epitaxial layers or epitaxial regions 42P, and are collectively referred to as source / drain regions 42P hereinafter. Figure 7B A perspective view of source / drain regions 42N and 42P is shown.

[0042] like Fig. 7A As shown, the top surface of the epitaxial layer 42NC remains wavy, and the middle portion of the top surface of the epitaxial layer 42NC is lower than the opposite portion. The top surface of the epitaxial layer 42NC may include a V-shaped portion. On the other hand, the epitaxial layer 42PC grows thicker, and the top surface of the epitaxial layer 42PC has a non-wavy shape. In summary, the source / drain region 42P is Fig. 7A The cross-sectional view shown has a conical cross-sectional view. Forming the epitaxial layer 42NC with a wavy top surface and the epitaxial layer 42PC being non-wavy (e.g., conical) has some beneficial properties. The wavy shape of the epitaxial layer 42NC can increase the source / drain contact plug ( Fig.11A The contact area between the source / drain region 42P and the source / drain region 42 is increased, thereby reducing the contact resistance. On the other hand, if the source / drain region 42P is formed to have a wavy shape, it will cause severe outward bending of the protruding fin 24P'. The test results show that the bending can be reduced by increasing the lifting height RH of the source / drain region 42P (thus forming a cone shape). Accordingly, the source / drain region 42P is formed to be non-wavy. On the other hand, the bending of the n-type FinFET fin is not a problem, so the source / drain region 42N can be formed to have a wavy shape.

[0043] According to some embodiments, for n-type source / drain regions 42, the wavy height WH may be in a range between about 3 nm and about 15 nm. The fusion height MHN may be in a range between about 7 nm and about 20 nm, and may be about 50% less than the height H1 of the protruding fins 24N', where the height H1 may be in a range between about 40 nm and about 100 nm. The ratio WH / (WH+MHN) may be in a range between about 0.1 and 0.4. The outer width WON of the epitaxial region 42N is less than half of the inner width WIN, which is measured on the outside of the protruding fins 24N', and the inner width WIN is the width of the epitaxial region 42N between the protruding fins 24N'. According to some embodiments, the outer width WON is in a range between about 5 nm and 15 nm, and the inner width half WIN / 2 is in a range between about 10 nm and 30 nm. Having the outer width WON less than half of the inner width facilitates the formation of the wavy profile. The total width TWN of the epitaxial region 42N (based on two fins) may be in a range between about 40 nm and about 80 nm.

[0044] For the p-type source / drain region 42P, the lift height RH (which is the height difference between the highest point of the source / drain region 42P and the top surface level of the protruding fin 24P') is controlled within a certain range. When the lift height is too small, the contact opening ( Fig.10 ), both epitaxial layers 42PC and 42PB may be etched through, and the contact plug will fall on the epitaxial layer 42PA, which may cause a series of boron loss problems. When the lift height is too large, the epitaxial layer 42PC may not be etched through, and the contact will fall on the epitaxial layer 42PC, and the doping concentration of the epitaxial layer 42PC will be lower than that of the epitaxial layer 42PB. At the same time, the contact area will not be recessed, and the benefit of reducing the contact area cannot be achieved. According to some embodiments, the lift height RH is in the range of about 5nm and about 15nm. The fusion height MHP may be in the range of about 40nm to about 80nm, and may exceed the height H1 of the protruding fin 24P' by about 50%, wherein the height H1 may be in the range of about 40nm and 100nm. The ratio RH / MHP may be in the range of about 0.1 and about 0.4. The outer width WOP of the epitaxial region 42P is greater than WIP / 2, the outer width WOP is on the outer side of the protruding fin 24P', wherein the inner width WIP is the width of the portion of the epitaxial region 42P between the protruding fins 24P'. According to some embodiments, the outer width WOP is in a range between about 15nm and about 30nm, and the inner width WI1 is in a range between about 20nm and 40nm. The total width TWP of the epitaxial region 42P may be in a range between about 40nm and about 80nm. The ratio MHN / MHP may be in a range between about 0.15 and about 0.6.

[0045] refer to Fig. 8A and Figure 8B , a contact etch stop layer (CESL) 46 and an interlayer dielectric layer (ILD) 48 are formed over the epitaxial regions 42P and 42N, and over the dummy gate stack 30 ( Figure 8B ).exist Fig.12 The corresponding process is shown as process 216 in the process flow shown in FIG. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove excess portions of CESL 46 and ILD 48 until the dummy gate stack 30 ( Figure 8B ).

[0046] refer to Fig. 9 , the dummy gate stack 30 is replaced by the replacement gate stack 56. Fig.12 The corresponding process is shown as process 218 in the process flow shown in FIG. The replacement gate stack 56 includes a gate dielectric 52, which includes an interface layer on the top surface and sidewalls of the protruding fin 24' and a high-k dielectric on the interface layer. The replacement gate stack 56 further includes a gate electrode 54 above the high-k dielectric 52. After the replacement gate stack 56 is formed, the replacement gate stack 56 is recessed to form trenches between the gate spacers 38. A dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled into the formed trenches to form a hard mask 58.

[0047] Next, refer to Fig.10 , ILD 48 and CESL 46 are etched to simultaneously form contact openings 60N and 60P, so that epitaxial layers 42NB and 42PB are exposed, respectively. Fig.12 The corresponding process is shown as process 220 in the process flow shown in FIG. The epitaxial layer 42NC is etched through, and the top surface of the epitaxial layer 42NB is exposed. Adding germanium to the epitaxial layer 42NC causes the etching rate of the epitaxial layer 42NC to be significantly higher than the etching rate of the epitaxial layer 42NB, and therefore, by controlling the etching process, the etching can be basically stopped on the epitaxial layer 42NB, and the over-etching of the epitaxial layer 42NB is very small. The top surface of the exposed epitaxial layer 42NB is wavy, and the middle part is recessed lower than the relative part on the opposite side of the middle part, so that the exposed top surface of the epitaxial layer 42NB is V-shaped in the cross-sectional view.

[0048] In the p-type device region 100P, although the source / drain region 42 is conical and the epitaxial layer 42PC is thicker than the epitaxial layer 42NC, the etching rate of the epitaxial layer 42PC is higher than that of the epitaxial layer 42NC (for example, twice as high). This compensates for the higher thickness of the epitaxial layer 42PC, so that when the epitaxial layer 42NC is etched through, the epitaxial layer 42PC is also etched through, and the exposed top surface of the epitaxial layer 42PB has a concave (wavy) shape.

[0049] Next, if Fig.11A and Fig. 11B As shown, source / drain silicide regions 64N and 64P, and source / drain contact plugs 66N and 66P are formed. Fig. 11B Shown in Fig.11A Cross-sectional view in reference section BB; Fig.11A Shown in Fig. 11B The cross-sectional view in reference section CC. Reference sections BB and CC are Figure 4A According to some embodiments of the present disclosure, the formation of the source / drain silicide regions 64N and 64P includes depositing a layer extending into the openings 60N and 60P ( Fig.10 ) is formed by forming a metal layer such as a titanium layer, a cobalt layer or the like, and then performing an annealing process so that the bottom of the metal layer reacts with the epitaxial layers 42NB and 42PB to form silicide regions 64N and 64P, respectively. Fig.12 The corresponding process is shown as process 222 in the process flow shown in FIG. The remaining unreacted metal layer may be removed.

[0050] Source / drain contact plugs 66N and 66P are then formed in trenches 60N and 60P, respectively, and are electrically connected to respective source / drain silicide regions 64N and 64P, respectively. Fig.12 The corresponding process is shown as process 224 in the process flow shown in FIG. According to some embodiments, the depth DSN of the recess in the silicide region 64N, that is, the depth of the concave recess of the top surface of the epitaxial layer 42NB, is greater than the depth DSP, which is the depth of the recess in the silicide region 64P. The depth DSP is also equal to the depth of the concave recess of the top surface of the epitaxial layer 42PB. N-type FinFET 68N and p-type FinFET 68P are thus formed. According to an optional embodiment, as shown in FIG. Figure 6 As shown by the top surface 43 of the middle dashed line, the depth DSP is equal to 0, which means that the silicide region 64P has no recess but is flat.

[0051] Embodiments of the present disclosure have several advantageous features. By forming an N-type source / drain region with a wavy top surface, the contact resistance, i.e., the resistance between the source / drain contact plug and the source / drain region, is reduced due to the increased contact area of ​​the wavy shape compared to a flat shape. By forming the p-type source / drain region with a tapered shape, the curvature of the fin of the p-type FinFET is reduced. In addition, the contact resistance between the source / drain contact plug and the p-type source / drain region does not increase (and may actually decrease), also due to the wavy shape of the contact area. In addition, with the tapered shape, the source / drain region of the p-type FinFET has an increase in strain and therefore an increase in current.

[0052] According to some embodiments of the present invention, a method includes: forming an n-type FinFET, including forming a first gate stack on a first semiconductor fin and a second semiconductor fin; etching first portions of the first semiconductor fin and the second semiconductor fin to form a first recess and a second recess, respectively; and performing a first epitaxial process to form an n-type source / drain region, wherein the n-type source / drain region includes a first portion grown from the first recess and a second portion grown from the second recess, and a first intermediate portion connected to the first portion and the second portion, wherein the first intermediate portion has a concave top surface. The method also includes forming a p-type FinFET, including forming a second gate stack on a third semiconductor fin and a fourth semiconductor fin; etching second portions of the third semiconductor fin and the fourth semiconductor fin to form a third recess and a fourth recess, respectively; and performing a second epitaxial process to form a p-type source / drain region, wherein the source / drain region includes a third portion grown from the third recess and a fourth portion grown from the fourth recess, and a second intermediate portion connected to the third portion and the fourth portion, wherein the second intermediate portion has a convex top surface. In one embodiment, the method further includes forming a first source / drain silicide region on the n-type source / drain region; forming a second source / drain silicide region on the p-type source / drain region; the first source / drain silicide region and the second source / drain silicide region have a first downwardly directed V-shape and a second downwardly directed V-shape, respectively. In one embodiment, the first downwardly directed V-shape has a greater height than the second downwardly directed V-shape. In one embodiment, the p-type source / drain region includes a first layer, a second layer located above the first layer, and a third layer located above the second layer, and wherein the first layer is laterally extended to form a small facet.

[0053] In one embodiment, the n-type source / drain region includes a fourth layer, a fifth layer located above the fourth layer, and a sixth layer located above the fifth layer, wherein a portion of the fourth layer grown from the first recess and the second recess is confined in the first recess and the second recess. In one embodiment, the p-type source / drain region includes boronized silicon germanium, and the third layer has a lower atomic percentage of germanium than the second layer, and wherein the method further includes etching through the third layer to expose the second layer, and the exposed second epitaxial layer has an additional concave top surface. In one embodiment, the p-type source / drain region includes a p-type cap layer as a top portion of the second intermediate portion, and wherein the p-type cap layer includes a convex top surface and a concave bottom surface. In one embodiment, the first epitaxial process and the second epitaxial process are performed using remote field plasma chemical vapor deposition. In one embodiment, the first outer portion is located on the first outer side of the first semiconductor fin; the first inner portion is located between the first semiconductor fin and the second semiconductor fin, wherein the first outer portion is narrower than half of the first inner portion. In one embodiment, the p-type source / drain region includes a second outer portion located on a second outer side of the second semiconductor fin, and a second inner portion located between the third semiconductor fin and the fourth semiconductor fin, the second outer portion being wider than half of the second inner portion.

[0054] According to some embodiments of the present invention, a method includes: forming an n-type source / drain region, including: depositing a first epitaxial layer, wherein the first epitaxial layer includes a first portion grown in a first recess in a first semiconductor fin, a second portion grown in a second recess in a second semiconductor fin, and a first intermediate portion connecting the first portion to the second portion; depositing a first capping layer over the first epitaxial layer, wherein the first capping layer includes a second intermediate portion directly over the first intermediate portion, and the second intermediate portion has a concave top surface; the method also includes forming a p-type FinFET, including forming a p-type source / drain region, including: depositing a second epitaxial layer, wherein the second epitaxial layer includes a third portion grown in a third recess in a third semiconductor fin, a fourth portion grown in a fourth recess in a fourth semiconductor fin, and a third intermediate portion connecting the third portion to the fourth portion, depositing a second capping layer over the second epitaxial layer, wherein the second capping layer includes a fourth intermediate portion directly over the third intermediate portion, and the fourth intermediate portion has a convex top surface. In one embodiment, the first capping layer and the first epitaxial layer include silicon phosphide, and the first capping layer has a lower phosphorus concentration than the first epitaxial layer. In one embodiment, the second capping layer and the second epitaxial layer contain boronized silicon germanium, and the second capping layer has a lower atomic percentage of germanium than the second epitaxial layer. In one embodiment, the method further includes depositing a contact etch stop layer and an interlayer dielectric over the n-type source / drain region and the p-type source / drain region; etching the contact etch stop layer, the interlayer dielectric, and the first capping layer to form a first contact opening, and the first exposed portion of the first epitaxial layer is concave; etching the contact etch stop layer, the interlayer dielectric, and the second capping layer to form a second contact opening, and the second exposed portion of the second epitaxial layer is concave. In one embodiment, the method further includes: before depositing the first epitaxial layer, depositing a third epitaxial layer into the first recess and the second recess, wherein the third epitaxial layer has a lower phosphorus concentration than the first epitaxial layer; before depositing the second epitaxial layer, depositing a fourth epitaxial layer into the third recess and the fourth recess, wherein the fourth epitaxial layer has a lower atomic percentage of germanium than the second epitaxial layer. In one embodiment, depositing the first capping layer includes depositing SiGeP.

[0055] In some embodiments of the present invention, a method includes: etching a first semiconductor fin and a second semiconductor fin to form a first recess and a second recess, respectively; epitaxially growing an n-type source / drain region, the n-type source / drain region including a first portion grown from the first recess; a second portion grown from the second recess; and a first intermediate portion located between the first portion and the second portion, wherein the first intermediate portion has a concave top surface; forming a first contact opening extending into the n-type source / drain region, wherein the first contact opening includes a first V-shaped bottom; etching a third semiconductor fin and a fourth semiconductor fin to form a third recess and a fourth recess, respectively; forming a p-type source / drain region, the p-type source / drain region including: a third portion grown from the third recess; a fourth portion grown from the fourth recess; and a second intermediate portion located between the third portion and the fourth portion, wherein the second intermediate portion has a convex top surface; and forming a second contact opening extending into the p-type source / drain region, wherein the second intermediate portion having the convex top surface is etched, and the second contact opening includes a second V-shaped bottom, with a tip of the second V-shaped bottom pointing downward.

[0056] In one embodiment, the etched second middle portion has a middle section that is thicker than sections on opposite sides of the middle section.

[0057] In one embodiment, a highest point of the second middle portion is higher than top surfaces of the third semiconductor fin and the fourth semiconductor fin. In one embodiment, a first height of the first V-shaped bottom is greater than a second height of the second V-shaped bottom.

[0058] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A method for forming a fin field effect transistor, comprising: Forming an n-type FinFET (Fin Field Effect Transistor), including: forming a first gate stack on the first semiconductor fin and the second semiconductor fin; etching first portions of the first semiconductor fin and the second semiconductor fin to form first and second recesses, respectively; and A first epitaxial process is performed to form an n-type source / drain region, wherein the n-type source / drain region comprises: A first layer including a first portion grown from the first recess and a second portion grown from the second recess and a first intermediate portion connected to the first portion and the second portion, a first gap being formed under the first layer and exposing the first layer; and a second layer overlying and contacting the first layer and comprising a concave top surface; and Forming a p-type FinFET, including: forming a second gate stack on the third semiconductor fin and the fourth semiconductor fin; etching the second portions of the third semiconductor fin and the fourth semiconductor fin to form a third recess and a fourth recess, respectively; and A second epitaxial process is performed to form a p-type source / drain region, wherein the source / drain region comprises: a third layer including a third portion grown from the third recess and a fourth portion grown from the fourth recess, wherein the third portion and the fourth portion are separated from each other, and a second gap is formed under the third layer and exposes the third layer; and A fourth layer is located above the third layer and contacts the third layer, wherein a bottom surface of the fourth layer is exposed to the second gap and the fourth layer includes a convex top surface.

2. The method according to claim 1, further comprising: forming a first source / drain silicide region on the n-type source / drain region; forming a second source / drain silicide region on the p-type source / drain region; The first source / drain silicide region and the second source / drain silicide region have a first downward-pointing V-shape and a second downward-pointing V-shape, respectively.

3. The method according to claim 2, wherein: The first downwardly directed V-shape has a greater height than the second downwardly directed V-shape.

4. The method according to claim 1, wherein: The third layer of the p-type source / drain region extends laterally to form a facet.

5. A method according to claim 4, wherein: The n-type source / drain region further includes a fifth layer located below the first layer, wherein a portion of the fifth layer grown from the first recess and the second recess is confined within the first recess and the second recess.

6. The method according to claim 4, wherein: The p-type source / drain region includes boronized silicon germanium.

7. The method according to claim 1, wherein: The p-type source / drain region further includes: A second middle portion connected to the third portion and the fourth portion, wherein the second middle portion includes a p-type cladding layer as a top portion of the second middle portion, and wherein the p-type cladding layer includes a convex top surface and a concave bottom surface.

8. The method according to claim 1, wherein: The first epitaxial process and the second epitaxial process are performed by remote-field plasma chemical vapor deposition.

9. The method according to claim 1, wherein: The n-type source / drain region comprises: a first outer portion located on a first outer side of the first semiconductor fin; and A first inner portion is located between the first semiconductor fin and the second semiconductor fin, wherein the first outer portion is narrower than half of the first inner portion.

10. The method according to claim 9, wherein: The p-type source / drain region comprises: a second outer portion located on a second outer side of the second semiconductor fin; and The second inner portion is located between the third semiconductor fin and the fourth semiconductor fin, and the second outer portion is wider than half of the second inner portion.

11. A method of forming a fin field effect transistor, comprising: Forming an n-type FinFET (Fin Field Effect Transistor), including: Forming n-type source / drain regions, including: depositing a first epitaxial layer, wherein the first epitaxial layer includes a first portion grown in a first recess in a first semiconductor fin, a second portion grown in a second recess in a second semiconductor fin, and a first intermediate portion connecting the first portion to the second portion; depositing a first capping layer over the first epitaxial layer, wherein the first capping layer includes a second intermediate portion directly over the first intermediate portion, and the second intermediate portion has a concave top surface; and forming a first silicide layer on the n-type source / drain region having the concave top surface, wherein the first silicide layer has a first additional concave top surface; and Forming a p-type FinFET, including Forming p-type source / drain regions, including: depositing a second epitaxial layer, the second epitaxial layer comprising a third portion grown in a third recess in a third semiconductor fin, a fourth portion grown in a fourth recess in a fourth semiconductor fin, and a third intermediate portion connecting the third portion to the fourth portion; depositing a second capping layer over the second epitaxial layer, wherein the second capping layer includes a fourth intermediate portion directly over the third intermediate portion, and the fourth intermediate portion has a convex top surface; and A second silicide layer is formed on the p-type source / drain region having the convex top surface, wherein the second silicide layer has a second additional concave top surface.

12. The method according to claim 11, wherein: The first capping layer and the first epitaxial layer include silicon phosphide, and the first capping layer has a lower phosphorus concentration than the first epitaxial layer.

13. The method according to claim 11, wherein: The second capping layer and the second epitaxial layer include silicon germanium boride, and the second capping layer has a lower atomic percentage of germanium than the second epitaxial layer.

14. The method according to claim 11, further comprising: depositing a contact etch stop layer and an interlayer dielectric over the n-type source / drain region and the p-type source / drain region; etching the contact etch stop layer, the interlayer dielectric and the first capping layer to form a first contact opening, wherein the first exposed portion of the first epitaxial layer is concave; The contact etch stop layer, the interlayer dielectric, and the second capping layer are etched to form a second contact opening, and a second exposed portion of the second epitaxial layer is concave.

15. The method according to claim 11, further comprising: before depositing the first epitaxial layer, depositing a third epitaxial layer into the first recess and the second recess, wherein the third epitaxial layer has a lower phosphorus concentration than the first epitaxial layer; and A fourth epitaxial layer is deposited into the third recess and the fourth recess prior to depositing the second epitaxial layer, wherein the fourth epitaxial layer has a lower atomic percentage of germanium than the second epitaxial layer.

16. The method according to claim 11, wherein: Depositing the first capping layer includes depositing SiGeP.

17. A method of forming a fin field effect transistor, comprising: etching the first semiconductor fin and the second semiconductor fin to form a first recess and a second recess, respectively; Epitaxially growing an n-type source / drain region, the n-type source / drain region comprising: a first portion grown from the first recess; a second portion grown from the second recess; and a first intermediate portion between the first portion and the second portion, wherein the first intermediate portion has a concave top surface; forming a first contact opening extending into the n-type source / drain region, wherein the first contact opening includes a first V-shaped bottom; forming a first silicide layer at a bottom of the first contact opening, wherein the first silicide layer is recessed; etching the third semiconductor fin and the fourth semiconductor fin to form a third recess and a fourth recess, respectively; A p-type source / drain region is formed, wherein the p-type source / drain region comprises: a third portion growing from the third recess; a fourth portion grown from the fourth recess; and a second intermediate portion between the third portion and the fourth portion, wherein the second intermediate portion has a convex top surface; and forming a second contact opening extending into the p-type source / drain region, wherein the second middle portion having the convex top surface is etched, the second contact opening comprising a second V-shaped bottom with a tip pointing downward; and A second silicide layer is formed at a bottom of the second contact opening, wherein the second silicide layer formed by etching the convex top surface of the p-type source / drain region is recessed.

18. The method according to claim 17, wherein: The second etched middle portion has a middle section that is thicker than sections on opposite sides of the middle section.

19. The method according to claim 17, wherein: A highest point of the second middle portion is higher than top surfaces of the third semiconductor fin and the fourth semiconductor fin.

20. The method according to claim 17, wherein: A first height of the first V-shaped bottom is greater than a second height of the second V-shaped bottom.

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