Display panel

Abstract

The present disclosure provides a display panel. The display panel includes a plurality of signal lines and a test circuit. The test circuit includes a plurality of transistors electrically connected to the plurality of signal lines. The plurality of transistors are arranged in at least two groups, and the number of transistors in each of the at least two groups is less than the total number of the plurality of signal lines. Therefore, the test circuit of the display panel of the present disclosure can reduce the circuit placement space in the horizontal direction.

Description

Technical Field

[0001] The present disclosure relates to a panel, and more particularly to a display panel provided with a test circuit. Background Art

[0002] For small-sized display devices, due to the small size of the display panel and the pixel pitch, there is not enough circuit placement space in the lower peripheral area of the display panel in the horizontal direction to set up a Light on Test (LOT) circuit. That is to say, small-sized display devices need to increase the size of the display panel to set up the light-on test circuit, resulting in the inability of small-sized display devices to achieve the effect of narrow borders. In view of this, several solutions of embodiments will be proposed below. Summary of the Invention

[0003] The present disclosure provides a display panel provided with a test circuit, which can effectively reduce the circuit placement space of the test circuit in the horizontal direction.

[0004] According to an embodiment of the present disclosure, the display panel of the present disclosure includes a plurality of signal lines and a test circuit. The test circuit includes a plurality of transistors electrically connected to the plurality of signal lines. The plurality of transistors are set to at least two groups, and the number of transistors in each of the at least two groups is less than the total number of the plurality of signal lines.

[0005] Based on the above, the display panel of the present disclosure can effectively save the circuit placement space of the test circuit in the horizontal direction in the peripheral area of the display panel by dividing the plurality of transistors of the test circuit into at least two groups and arranging them in at least two rows in the vertical direction.

[0006] To make the above features and advantages of the present disclosure more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings. Brief Description of the Drawings

[0007] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0008] Figure 1 is a schematic diagram of the test circuit according to the first embodiment of the present disclosure;

[0009] Figure 2 is a schematic diagram of the test circuit according to the second embodiment of the present disclosure;

[0010] Figure 3 is a schematic diagram of the manufacturing process layout of the circuit according to the first embodiment of the present disclosure;

[0011] Figure 4 It is a cross-sectional structure diagram of a transistor according to an embodiment of the present disclosure;

[0012] Figure 5 It is a schematic diagram of a test circuit according to the third embodiment of the present disclosure;

[0013] Figure 6 It is a schematic diagram of a test circuit according to the fourth embodiment of the present disclosure;

[0014] Figure 7 It is a schematic diagram of the process layout of a circuit according to the third embodiment of the present disclosure.

[0015] Description of Reference Numerals

[0016] 100, 200, 300, 500, 600, 700: Circuits;

[0017] 110_1 to 110_6, 210_1 to 210_6, 310_1 to 310_6, 400, 510_1 to 510_6, 610_1 to 610_6, 710_1 to 710_6: Transistors;

[0018] 111_1 to 111_6, 211_1 to 211_6, 311_1 to 311_6, 511_1 to 511_6, 611_1 to 611_6, 711_1 to 711_6: Gates;

[0019] 112_1 to 112_6, 212_1 to 212_6, 312_1 to 312_6, 512_1 to 512_6, 612_1 to 612_6, 712_1 to 712_6: Drains;

[0020] 113_1 to 113_6, 213_1 to 213_6, 313_1 to 313_6, 513_1 to 513_6, 613_1 to 613_6, 713_1 to 713_6: Sources;

[0021] 401: Substrate;

[0022] 402: Buffer layer;

[0023] 403: Gate insulating layer;

[0024] 404: Metal interlayer dielectric layer;

[0025] 405: Insulating layer;

[0026] 406: Planarization layer;

[0027] 407: Insulating layer;

[0028] 410, 420, 430: Metal layers;

[0029] D1 - D6: Signal lines;

[0030] SB, SB1, SB2: Control lines;

[0031] V1 - V6: Test signal lines;

[0032] P1, P2, P3: Directions;

[0033] h1 - h19, g1 - g21: Via holes;

[0034] R1: Lightly doped region;

[0035] R2, R2': Heavily doped regions;

[0036] RV: Reference line. Detailed implementation manners

[0037] Throughout this specification and the appended claims, certain terms will be used to refer to particular components. Those skilled in the art should understand that electronic device manufacturers may refer to the same component by different names. This document is not intended to distinguish between components that have the same function but different names. In the following specification and claims, terms such as "comprising" and "including" are open - ended terms and should therefore be interpreted as "including but not limited to...".

[0038] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions in the drawings. Therefore, the directional terms used are for illustration and not for limiting this disclosure. In the drawings, each drawing shows the general characteristics of the methods, structures, and / or materials used in a particular embodiment. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and positions of each film layer, region, and / or structure may be reduced or enlarged.

[0039] In some embodiments of this disclosure, terms related to joining and connecting, such as "connect" and "interconnect", unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact and there are other structures disposed between these two structures. And these terms related to joining and connecting may also include cases where both structures are movable, or both structures are fixed. In addition, the term "electrically connected" includes any means of direct and indirect electrical connection.

[0040] The ordinal numbers used in the description and claims, such as "first", "second", etc., are used to modify components. They do not themselves imply or represent that the component, or those components, have any previous ordinal numbers, nor do they represent the order of one component relative to another component or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish a component with a certain name from another component with the same name. The terms used in the claims and the description may not be the same. Accordingly, the first component in the description may be the second component in the claim. It should be noted that, without departing from the spirit of this disclosure, the technical features in several different embodiments may be replaced, reorganized, and mixed to complete other embodiments.

[0041] In various embodiments of the present disclosure, the display panel may, for example, include liquid crystal, light emitting diodes, quantum dots (QD), fluorescence, phosphor, other suitable materials, or combinations of the above materials, but is not limited thereto. The light emitting diodes may, for example, include organic light emitting diodes (OLED), mini light emitting diodes (mini LED), micro light emitting diodes (micro LED), or quantum dot light emitting diodes (QLED or QDLED), fluorescence, phosphor, or other suitable materials, and their materials may be arranged and combined arbitrarily, but are not limited thereto. In various embodiments of the present disclosure, the display panel may be disposed, for example, in a virtual reality (VR) device or other small-sized display devices.

[0042] Figure 1 is a schematic diagram of the test circuit of the first embodiment of the present disclosure. Refer to Figure 1 , the circuit 100 includes a test circuit and a plurality of signal lines D1 to D6. The circuit 100 is a partial circuit in the peripheral area (peripheral region) on the substrate of the display panel. In this embodiment, the test circuit includes a plurality of transistors 110_1 to 110_6 electrically connected to the signal lines D1 to D6, and includes a plurality of test signal lines V1 to V6 and a control line SB. In this embodiment, the transistors 110_1 to 110_6 are arranged in two groups, which can be divided into an odd group (transistors 110_1, 110_3, 110_5) and an even group (transistors 110_2, 110_4, 110_6). The two groups of transistors are arranged in the first direction P1 (horizontal direction), and the two groups of transistors are arranged in two rows in the second direction P2 (vertical direction). The first direction P1, the second direction P2, and the third direction P3 are perpendicular to each other. The two groups of transistors are separately disposed on both sides of the routing area of the test signal lines V1 to V6 and the control line SB.

[0043] It should be noted that the number of transistors and signal lines of the test circuit disclosed herein are only for illustrative purposes and are not limited to Figure 1 . The number of transistors and signal lines of the test circuit on a real product is much larger than Figure 1 the number presented, and it can be determined according to the panel specification or panel resolution, or special test requirements. In this embodiment, a plurality of transistors disclosed herein are set to at least two groups, and the number of transistors in each of the at least two groups is less than the total number of signal lines. In addition, extending from signal lines D1 to D6 in the second direction P2, the display panel 10 may further include a pixel array, where signal lines D1 to D6 may be coupled to, for example, multiple data lines of the first column to the sixth column of the pixel array, and the test circuit may also include, for example, another plurality of transistors along the first direction P1 by analogy, where the configuration of the another plurality of transistors may be the same as that of transistors 110_1 to 110_6, and are electrically connected to, for example, the data lines of the seventh column to the twelfth column of the pixel array.

[0044] In this embodiment, transistors 110_1 to 110_6 respectively include gates 111_1 to 111_6, drains 112_1 to 112_6, and sources 113_1 to 113_6. The gates 111_1 to 111_6 of transistors 110_1 to 110_6 are electrically connected to the control line SB to receive control signals. The drains 112_1 to 112_6 of transistors 110_1 to 110_6 are respectively electrically connected to the test signal lines V1 to V6 to receive test signals respectively. The sources 113_1 to 113_6 of transistors 110_1 to 110_6 are respectively electrically connected to signal lines D1 to D6 to respectively provide drive signals to corresponding pixel units in corresponding multiple columns of the corresponding pixel array through signal lines D1 to D6, for example, to perform a light-on test (LOT).

[0045] More specifically, in the present embodiment, the control line SB and the test signal lines V1 to V6 are arranged in sequence along the second direction P2. The transistors 110_1, 110_3, 110_5 of the odd-numbered groups are arranged on the side adjacent to the control line SB. The transistors 110_2, 110_4, 110_6 of the even-numbered groups are arranged on the side adjacent to the test signal line V6 and are closer to the pixel array than the transistors 110_1, 110_3, 110_5 of the odd-numbered groups. The drains 112_1, 112_3, 112_5 of the transistors 110_1, 110_3, 110_5 of the odd-numbered groups are electrically connected to the odd-numbered test signal lines V1, V3, V5 in sequence, and the sources 113_1, 113_3, 113_5 are electrically connected to the odd-numbered signal lines D1, D3, D5 in sequence. The drains 112_2, 112_4, 112_6 of the transistors 110_2, 110_4, 110_6 of the even-numbered groups are electrically connected to the even-numbered test signal lines V2, V4, V6 in sequence, and the sources 113_2, 113_4, 113_6 are electrically connected to the even-numbered signal lines D2, D4, D6 in sequence. Therefore, since the test circuit of the present embodiment divides the transistors 110_1 to 110_6 into odd-numbered groups (transistors 110_1, 110_3, 110_5) and even-numbered groups (transistors 110_2, 110_4, 110_6) and arranges them separately in different rows, the test circuit of the present embodiment can effectively save the circuit placement space in the first direction P1.

[0046] However, the arrangement order of the control line SB and the test signal lines V1 to V6 disclosed herein is not limited to Figure 1 . In an embodiment, the transistors 110_2, 110_4, 110_6 of the even-numbered groups are closer to the pixel array than the transistors 110_1, 110_3, 110_5 of the odd-numbered groups. However, the arrangement order of the control line SB and the test signal lines V1 to V6 can be arranged in sequence along the direction opposite to the second direction P2.

[0047] Figure 2 is a schematic diagram of the test circuit of the second embodiment disclosed herein. Refer to Figure 2, the circuit 200 includes a test circuit and multiple signal lines D1 to D6. The test circuit of this embodiment includes multiple transistors 210_1 to 210_6, multiple test signal lines V1 to V6, and a control line SB. The multiple transistors 210_1 to 210_6 are electrically connected to the signal lines D1 to D6. In this embodiment, the transistors 210_1 to 210_6 are set in two groups, which can be divided into an odd group (transistors 210_1, 210_3, 210_5) and an even group (transistors 210_2, 210_4, 210_6). The two groups of transistors are arranged in the first direction P1 (horizontal direction), and the two groups of transistors are arranged in two rows in the second direction P2 (vertical direction). The two groups of transistors are separately arranged on both sides of the routing area of the test signal lines V1 to V6 and the control line SB.

[0048] In this embodiment, the transistors 210_1 to 210_6 respectively include gates 211_1 to 211_6, drains 212_1 to 212_6, and sources 213_1 to 213_6. The gates 211_1 to 211_6 of the transistors 210_1 to 210_6 are electrically connected to the control line SB to receive control signals. The drains 212_1 to 212_6 of the transistors 210_1 to 210_6 are respectively electrically connected to the test signal lines V1 to V6 to respectively receive test signals. The sources 213_1 to 213_6 of the transistors 210_1 to 210_6 are respectively electrically connected to the signal lines D1 to D6 to respectively provide drive signals to the corresponding pixel units in the corresponding multiple columns of the pixel array via the signal lines D1 to D6, for example, to perform a lighting test. And, the electrical connection relationship between the transistors 210_1 to 210_6 and the test signal lines V1 to V6, the control line SB, and the signal lines D1 to D6 is the same as that of Figure 1 the transistors 110_1 to 110_6.

[0049] Different from Figure 1 , in this embodiment, the control line SB and the test signal lines V1 to V6 are arranged in sequence along a direction opposite to the second direction P2. The odd-group transistors 210_1, 210_3, 210_5 are arranged on the side adjacent to the test signal line V1. The even-group transistors 210_2, 210_4, 210_6 are arranged on the side adjacent to the control line SB and are farther from the pixel array than the odd-group transistors 210_1, 210_3, 210_5. Therefore, since the test circuit of this embodiment divides the transistors 210_1 to 210_6 into an odd group (transistors 210_1, 210_3, 210_5) and an even group (transistors 210_2, 210_4, 210_6) and separately arranges them in different rows, the test circuit of this embodiment can effectively save the circuit placement space in the first direction P1.

[0050] However, the arrangement order of the control line SB and the test signal lines V1 to V6 disclosed herein is not limited to Figure 2 . In one embodiment, the transistors 210_2, 210_4, and 210_6 of the even-numbered groups are also farther from the pixel array than the transistors 210_1, 210_3, and 210_5 of the odd-numbered groups. However, the arrangement order of the test signal lines V1 to V6 and the control line SB may be arranged in sequence along the direction of the second direction P2.

[0051] In addition, incidentally, in a test embodiment, when performing circuit analysis on a certain test circuit, if the test signal line of this certain test circuit is located in the middle of this certain test circuit or between two rows of transistors, and the signal lines electrically connected to the upper and lower rows of transistors are respectively spaced and jump-connected, for example, every two adjacent transistors are respectively electrically connected to two non-consecutively arranged signal lines, then this certain test circuit can be regarded as implementing the Figure 1 or Figure 2 architecture design of the test circuit disclosed herein.

[0052] Figure 3 is a schematic diagram of the process layout of the circuit of the first embodiment disclosed herein. Figure 1 The layout of the circuit 100 of Figure 3 can be as Figure 3 . Referring to

[0053] In this embodiment, in Figure 3Figures with the same bottom line pattern in [the figure] can be regarded as being located in the same metal layer of the display panel 30. Specifically, in this embodiment, the gates 311_1 to 311_6 of the transistors 310_1 to 310_6 extend to the metal traces of the control line SB through the traces of the same-layer metal layer, and are electrically connected to the control line SB through the vias h1, h8, and h15. In this embodiment, the drains 312_1 to 312_5 of the transistors 310_1 to 310_5 extend to the respective corresponding vias h2, h5, h9, h12, and h16 through the traces of the same-layer metal layer, and then extend to the metal traces of the respective corresponding test signal lines V1 to V5 through the traces of the metal layer below the test signal lines V1 to V6 and the control line SB electrically connected by the vias h2, h5, h9, h12, and h16, and finally are electrically connected to the respective corresponding test signal lines V1 to V5 through the respective corresponding vias h3, h6, h10, h13, and h17. And, since the drain 312_6 of the transistor 310_6 does not need to cross other signal lines, the drain 312_6 of the transistor 310_6 can directly extend and be electrically connected to the test signal line V6 through the traces of the same-layer metal. In this embodiment, the sources 313_1 to 313_6 of the transistors 310_1 to 310_6 extend to the respective corresponding vias h4, h7, h11, h14, h18, and h19 through the traces of the same-layer metal layer, and then are electrically connected to the respective corresponding signal lines D1 to D6 through the vias h4, h7, h11, h14, h18, and h19. And, the signal lines D1 to D6 extend in the second direction P2 to the corresponding multiple columns of pixel units in the pixel array of the display panel 30 through the traces of the metal layer above the test signal lines V1 to V6 and the control line SB. Therefore, the process layout method of the test circuit in this embodiment can effectively save the circuit placement space of the test circuit in the first direction P1.

[0054] In addition, it is worth noting that since the trace distances from the gates 311_1 to 311_6 of the transistors 310_1 to 310_5 to the drains 312_1 to 312_5 extending to their respective vias are relatively close, in order to avoid short circuits between the traces of the gates 311_1 to 311_6 of the transistors 310_1 to 310_5 and the drains 312_1 to 312_5 extending to their respective vias, the traces of the drains 312_1 to 312_5 of the transistors 310_1 to 310_5 extending to the respective corresponding vias h3, h6, h10, h13, and h17 all extend in a direction away from the gates 311_1 to 311_6 (opposite to the first direction P1) for a certain distance and then extend to the respective corresponding vias h3, h6, h10, h13, and h17.

[0055] Figure 4It is a cross-sectional structure diagram of a transistor according to an embodiment of the present disclosure. The cross-sectional structure of this embodiment can be, for example, Figure 3 The cross-sectional structure of the transistor 310_2 along the plane formed by the first direction P1 and the third direction P3 of the reference line RV (viewed in the second direction P2), but the present disclosure is not limited thereto. The transistors 310_1 to 310_6 all have the cross-sectional structure of the transistor 400 of this embodiment. Taking the cross-section of the transistor 310_2 as an example, refer to Figure 4 , the transistor 400 is formed on a substrate in the peripheral area of the display panel, where the display panel sequentially forms a substrate 401, a buffer layer 402, an active layer 4031, a gate insulating layer 403, a metal interlayer dielectric layer 404, an insulating layer 405, a planarization layer 406, and an insulating layer 407 in the third direction P3. In this embodiment, the active layer 4301 includes a lightly doped region R1 and heavily doped regions R2, R2', and the lightly doped region R1 is located between the heavily doped regions R2, R2'. In this embodiment, the metal layer 410 of the gate of the transistor 400 is formed on the gate insulating layer 403. The metal layers 420 of the drain and source of the transistor 400 are formed on the metal interlayer dielectric layer 404 and penetrate through the gate insulating layer 403 and the metal interlayer dielectric layer 404 to be electrically connected to the heavily doped regions R2, R2'. In addition, the metal layer 430 of the signal line above the drain of the transistor 400 can be formed on the insulating layer 405. That is to say, the metal layer 430 of the signal line above the drain of the transistor 400, the metal layer 410 of the gate of the transistor 400, and the metal layers 420 of the drain and source of the transistor 400 are formed on metal layers at different heights.

[0056] Figure 5 It is a schematic diagram of a test circuit according to the third embodiment of the present disclosure. Refer to Figure 5 , the circuit 500 includes a test circuit and a plurality of signal lines D1 to D6. The test circuit of this embodiment includes a plurality of transistors 510_1 to 510_6 electrically connected to the signal lines D1 to D6, and includes a plurality of test signal lines V1 to V6 and control lines SB1, SB2. In this embodiment, the transistors 510_1 to 510_6 are set in two groups, which can be divided into an odd group (transistors 510_1, 510_3, 510_5) and an even group (transistors 510_2, 510_4, 510_6). The two groups of transistors are arranged in the first direction P1 (horizontal direction), and the two groups of transistors are arranged in two rows in the second direction P2 (vertical direction). The two groups of transistors are separately arranged on both sides of the routing area of the test signal lines V1 to V6. And, the control lines SB1, SB2 are located outside the two rows of the transistors 510_1 to 510_6.

[0057] In this embodiment, the transistors 510_1 to 510_6 respectively include gates 511_1 to 511_6, drains 512_1 to 512_6, and sources 513_1 to 513_6. The gates 511_1, 511_3, 511_5 of the odd-numbered transistors 510_1, 510_3, 510_5 are electrically connected to the control line SB1 to receive control signals. The gates 511_2, 511_4, 511_6 of the even-numbered transistors 510_2, 510_4, 510_6 are electrically connected to the control line SB2 to receive another control signal. The drains 512_1 to 512_6 of the transistors 510_1 to 510_6 are respectively electrically connected to the test signal lines V1 to V6 to receive test signals respectively. The sources 513_1 to 513_6 of the transistors 510_1 to 510_6 are respectively electrically connected to the signal lines D1 to D6 to respectively provide drive signals to corresponding pixel units in corresponding multiple columns of the corresponding pixel array, for example, to perform a lighting test.

[0058] More specifically, in this embodiment, the control line SB and the test signal lines V1 to V6 are arranged in sequence along the second direction P2. The odd-numbered transistors 510_1, 510_3, 510_5 are arranged between the test signal line V1 and the control line SB1. The even-numbered transistors 510_2, 510_4, 510_6 are arranged between the test signal line V6 and the control line SB2 and are closer to the pixel array than the odd-numbered transistors 510_1, 510_3, 510_5. The drains 512_1, 512_3, 512_5 of the odd-numbered transistors 510_1, 510_3, 510_5 are sequentially electrically connected to the odd-numbered test signal lines V1, V3, V5, and the sources 513_1, 513_3, 513_5 are sequentially electrically connected to the odd-numbered signal lines D1, D3, D5. The drains 512_2, 512_4, 512_6 of the even-numbered transistors 510_2, 510_4, 510_6 are sequentially electrically connected to the even-numbered test signal lines V2, V4, V6, and the sources 513_2, 513_4, 513_6 are sequentially electrically connected to the even-numbered signal lines D2, D4, D6. Therefore, since the test circuit of this embodiment divides the transistors 510_1 to 510_6 into an odd-numbered group (transistors 510_1, 510_3, 510_5) and an even-numbered group (transistors 510_2, 510_4, 510_6) and arranges them separately in different rows, the test circuit of this embodiment can effectively save the circuit placement space in the first direction P1.

[0059] However, the arrangement order of the test signal lines V1 to V6 disclosed herein is not limited to Figure 5。In one embodiment, the transistors 510_2, 510_4, 510_6 of the even-numbered group are also closer to the pixel array than the transistors 510_1, 510_3, 510_5 of the odd-numbered group. However, the arrangement order of the test signal lines V1 to V6 can be arranged in sequence along the direction opposite to the second direction P2.

[0060] Figure 6 is a schematic diagram of the test circuit of the fourth embodiment of the present disclosure. Refer to Figure 6 , the circuit 600 includes a test circuit and a plurality of signal lines D1 to D6. The test circuit of this embodiment includes transistors 610_1 to 610_6 electrically connected to the signal lines D1 to D6, and includes a plurality of test signal lines V1 to V6 and control lines SB1, SB2. In this embodiment, the transistors 610_1 to 610_6 are set in two groups, which can be divided into an odd-numbered group (transistors 610_1, 610_3, 610_5) and an even-numbered group (transistors 610_2, 610_4, 610_6). The two groups of transistors are arranged in the first direction P1 (horizontal direction), and the two groups of transistors are arranged in two rows in the second direction P2 (vertical direction). The two groups of transistors are separately arranged on both sides of the routing area of the test signal lines V1 to V6. And, the control lines SB1, SB2 are located outside the two rows of transistors 610_1 to 610_6.

[0061] In this embodiment, the transistors 610_1 to 610_6 respectively include gates 611_1 to 611_6, drains 612_1 to 612_6, and sources 613_1 to 613_6. The gates 611_1, 611_3, 611_5 of the transistors 610_1, 610_3, 610_5 in the odd-numbered group are electrically connected to the control line SB1 to receive a control signal. The gates 611_2, 611_4, 611_6 of the transistors 610_2, 610_4, 610_6 in the even-numbered group are electrically connected to the control line SB2 to receive another control signal. The drains 612_1 to 612_6 of the transistors 610_1 to 610_6 are respectively electrically connected to the test signal lines V1 to V6 to respectively receive test signals. The sources 613_1 to 613_6 of the transistors 610_1 to 610_6 are respectively electrically connected to the signal lines D1 to D6 to respectively provide drive signals to the corresponding pixel units in the corresponding multiple columns in the corresponding pixel array, for example, for lighting tests.

[0062] Different from Figure 5 , in this embodiment, the routing positions of the control lines SB1, SB2 and Figure 5Conversely, the test signal lines V1 to V6 are arranged in sequence along a direction opposite to the second direction P2. The transistor arrays 610_2, 610_4, 610_6 of the even-numbered groups are farther from the pixel array than the transistor arrays 610_1, 610_3, 610_5 of the odd-numbered groups. Therefore, since the test circuit of the present embodiment separates the transistors 610_1 to 610_6 into odd-numbered groups (transistors 610_1, 610_3, 610_5) and even-numbered groups (transistors 610_2, 610_4, 610_6) and arranges them separately in different rows, the test circuit 600 of the present embodiment can effectively save the circuit placement space in the first direction P1.

[0063] However, the arrangement order of the test signal lines V1 to V6 disclosed herein is not limited to Figure 6 . In an embodiment, the transistor arrays 610_2, 610_4, 610_6 of the even-numbered groups are also farther from the pixel array than the odd-numbered groups 610_1, 610_3, 610_5. However, the arrangement order of the test signal lines V1 to V6 can be arranged in sequence along a direction opposite to the second direction P2.

[0064] In addition, incidentally, in a test embodiment, when performing circuit analysis on a certain test circuit, if the test signal lines of this certain test circuit are located in the middle of this certain test circuit or between two rows of transistors, and the signal lines electrically connected to the upper and lower rows of transistors are respectively spaced and jump-connected, for example, every two adjacent transistors are respectively electrically connected to two non-continuously arranged signal lines, then this certain test circuit can be regarded as implementing the Figure 5 or Figure 6 architecture design of the test circuit disclosed herein. Or, in another test embodiment, when performing circuit analysis on a certain test circuit, if this certain test circuit can have two control lines outside two rows of transistors, then this certain test circuit can also be regarded as implementing the Figure 5 or Figure 6 architecture design of the test circuits 500 and 600 disclosed herein.

[0065] Figure 7 is a schematic diagram of the process layout of the circuit of the third embodiment disclosed herein. Figure 5 The process layout of the circuit 500 can be as Figure 7 . Refer to Figure 7, in this embodiment, circuit 700 includes a test circuit and multiple signal lines D1 to D6. The test circuit of this embodiment includes multiple transistors 710_1 to 710_6 electrically connected to signal lines D1 to D6, and includes multiple test signal lines V1 to V6 and control lines SB1, SB2. In this embodiment, the gates 711_1 to 711_6 of transistors 710_1 to 710_6, the drains 712_1 to 712_6 of transistors 710_1 to 710_6, and the sources 713_1 to 713_6 are formed on metal layers at different heights, and the drains 712_1 to 712_6 and the sources 713_1 to 713_6 of transistors 710_1 to 710_6 are formed on metal layers at the same height. In this embodiment, test signal lines V1 to V6 are arranged in sequence along the second direction P2. The odd-numbered groups of transistors 710_1, 710_3, 710_5 are arranged on one side adjacent to test signal line V1. The even-numbered groups of transistors 710_2, 710_4, 710_6 are arranged on one side adjacent to test signal line V6, and are closer to the pixel array than the odd-numbered groups of transistors 710_1, 710_3, 710_5. Control line SB1 is located on the side of the odd-numbered groups of transistors 710_1, 710_3, 710_5 away from test signal line V1, and control line SB2 is located on the side of the even-numbered groups of transistors 710_2, 710_4, 710_6 away from test signal line V6.

[0066] In this embodiment, in Figure 7Graphics with the same bottom line pattern in [the figure] can be regarded as being located in the same metal layer of the display panel 70. Specifically, in this embodiment, the gates 711_1 to 711_6 of the transistors 710_1 to 710_6 extend to the metal traces of the respective corresponding control lines SB1 and SB2 through the traces of the same-layer metal layer, and are electrically connected to the respective corresponding control lines SB1 and SB2 through the vias g1, g4, g8, g12, g16, and g20. In this embodiment, the drains 712_2 to 712_5 of the transistors 710_2 to 710_5 extend to the respective corresponding vias g5, g9, g13, and g17 through the traces of the same-layer metal layer, and then extend to the metal traces of the respective corresponding test signal lines V2 to V5 through the traces of the metal layer below the test signal lines V1 to V6 and the control line SB to which the vias g5, g9, g13, and g17 are electrically connected, and finally are electrically connected to the respective corresponding test signal lines V2 to V5 through the respective corresponding vias g6, g10, g14, and g18. And, since the drains 712_1 and 712_6 of the transistors 710_1 and 710_6 do not need to cross other signal lines, the drains 712_1 and 712_6 of the transistors 710_1 and 710_6 can be directly extended and electrically connected to the test signal lines V1 and V6 through the traces of the same-layer metal respectively. In this embodiment, the sources 713_1 to 713_6 of the transistors 710_1 to 710_6 extend to the respective corresponding vias g3, g7, g11, g15, g19, and g21 through the traces of the same-layer metal layer, and then are electrically connected to the respective corresponding signal lines D1 to D6 through the vias g3, g7, g11, g15, g19, and g21. And, the signal lines D1 to D6 extend in the second direction P2 to the corresponding multiple columns of pixel units in the pixel array of the display panel 70 through the traces of the metal layer above the test signal lines V1 to V6 and the control line SB. Therefore, the manufacturing layout method of the test circuit in this embodiment can effectively save the circuit placement space of the test circuit in the first direction P1, and can effectively avoid the short circuit between the traces of the gates 711_1 to 711_6 and the drains 712_1 to 712_6 of the respective transistors 710_1 to 710_6.

[0067] In summary, the test circuit of the display panel disclosed in this disclosure can be set on both sides of the test signal line by dividing multiple transistors into two rows, so as to effectively reduce the circuit placement space in the horizontal direction, which helps to achieve the effect of a narrow border. And, the test circuit of the display panel disclosed in this disclosure can further electrically connect the two rows of transistors to two control lines respectively, and the two control lines are arranged outside the two control lines to effectively avoid the short circuit between the traces of the gates and the drains of the respective transistors.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limiting them. Among them, as long as the features between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily mixed and used; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display panel, characterized in that, Comprising: Multiple signal lines; And A test circuit, including multiple transistors, multiple test signal lines extending along a first direction, and control lines, wherein the multiple transistors are electrically connected to the multiple signal lines and the multiple test signal lines, Wherein the multiple transistors are arranged in at least two groups in a second direction, and the number of transistors in each of the at least two groups is less than the total number of the multiple signal lines, Wherein one of a group of the at least two adjacent groups of transistors includes a first transistor, and the other of the at least two adjacent groups of transistors includes a second transistor, and at least two of the multiple test signal lines and the control lines are arranged between the first transistor and the second transistor, Wherein the control line is electrically connected to the gate of the first transistor and the gate of the second transistor, one of the at least two of the multiple test signal lines is electrically connected to the drain of the first transistor, and the other of the at least two of the multiple test signal lines is electrically connected to the drain of the second transistor, Wherein the multiple sources of the multiple transistors extend to multiple vias through multiple traces of the same-layer metal layer, and then are electrically connected to the multiple signal lines through the multiple vias.

2. The display panel according to claim 1, characterized in that, The multiple transistors are arranged in at least two rows.

3. The display panel according to claim 2, characterized in that, The multiple transistors are arranged in two rows.

4. The display panel according to claim 3, characterized in that, The transistors in one row are sequentially electrically connected to the odd-numbered ones of the multiple signal lines, and the transistors in the other row are sequentially electrically connected to the even-numbered ones of the multiple signal lines.

5. The display panel according to claim 3, characterized in that, The multiple transistors are controlled by control signals from the control line.

6. The display panel according to claim 5, characterized in that, The control line is located between the two rows.

7. The display panel according to claim 5, characterized in that, The control line is located outside the two rows.

8. The display panel according to claim 5, characterized in that, The number of the control lines is two, and they are respectively located on different sides outside the two rows.

9. The display panel according to claim 3, characterized in that, The transistors in one row are sequentially electrically connected to the odd-numbered ones of the multiple test signal lines, and the transistors in the other row are sequentially electrically connected to the even-numbered ones of the multiple test signal lines.

10. The display panel according to claim 9, characterized in that, The multiple test signal lines are located between the two rows.

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