Read Threshold Calibration Using Multiple Decoders

Abstract

In one embodiment, a memory controller includes a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to connect to a memory interface having a plurality of word lines. Each of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit is configured to generate a plurality of bit error rate estimation scan (BES) hypotheses for one of the plurality of word lines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read positions of the one word line based on the BER results from the plurality of decoders.

Description

Technical Field

[0001] The present application generally relates to a controller, such as a memory controller. More specifically, the present application relates to a memory controller with read threshold calibration using multiple decoders. Background Art

[0002] QoS (Quality of Service) requirements establish the expected behavior of the flash controller. As QOS requirements increase over time, and as the number of stacked layers increases over time, NAND blocks become larger, contain more word lines, and word line to word line variations increase.

[0003] The increase in QOS requirements over time and the increase in wordline to wordline variation place an emphasis on maintaining proper read thresholds in order to maintain performance and reliability. This emphasis is also placed on read threshold calibration operations, which need to be performed more frequently as a maintenance operation of the memory controller. The read threshold is one or more read locations for reading data from a wordline at a specific voltage level. Read threshold calibration is the process of determining one or more read locations for reading data from a wordline at a specific voltage level with the lowest bit error rate (BER).

[0004] With the introduction of memories with multi-level cells, the complexity of the read threshold calibration operation has increased exponentially. Some instances of the read threshold calibration operation may even take several milliseconds, which is burdensome for read timeouts and QoS requirements. Summary of the invention

[0005] The present disclosure includes apparatus, methods, and devices with read threshold calibration using multiple decoders (e.g., a decoder pool). Read threshold calibration using multiple decoders reduces the latency of threshold calibration because the read threshold calibration performs more read threshold calibration operations in the same amount of time as conventional read threshold calibration. This increase in read threshold calibration operations can improve accuracy, which in turn reduces the BER of read data, which also results in reduced power and higher throughput of the ECC decoder, and indirectly improves the QoS of future reads. This increase in read threshold calibration operations can also be used to reduce the latency of read calibration operations, and therefore allow for a higher budget for other operations.

[0006] The present disclosure provides a memory controller. In one embodiment, the memory controller includes a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to be connected to a memory interface having a plurality of word lines. Each of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit is configured to generate a plurality of bit error rate estimation scan (BES) hypotheses for a word line in the plurality of word lines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read positions of a word line based on the BER results from the plurality of decoders.

[0007] The present disclosure also provides a method. In one embodiment, the method includes generating a plurality of bit error estimation scan (BES) hypotheses for a word line in a plurality of word lines using a controller circuit. The method includes dividing the plurality of BES hypotheses among a plurality of decoders using a controller circuit. The method includes receiving bit error rate (BER) results from a plurality of decoders based on the plurality of BES hypotheses using a controller circuit. The method also includes adjusting one or more read positions of a word line based on the BER results from the plurality of decoders using a controller circuit.

[0008] The present disclosure also provides an apparatus, which in one embodiment includes means for generating a plurality of bit error estimation scan (BES) hypotheses for a word line among a plurality of word lines, means for dividing the plurality of BES hypotheses among a plurality of decoders, means for receiving bit error rate (BER) results from a plurality of decoders based on the plurality of BES hypotheses, and means for adjusting one or more read positions based on the BER results from the plurality of decoders.

[0009] In this way, various aspects of the present disclosure provide improvements at least in the technical field of memory devices and their design and architecture. The present disclosure can be embodied in various forms, including hardware or circuits controlled by computer-implemented methods, computer program products, computer systems and networks, user interfaces, and application programming interfaces; and hardware or circuits controlled by hardware-implemented methods, signal processing circuits, memory arrays, application-specific integrated circuits, field programmable gate arrays, etc. The foregoing invention content is intended only to give a general idea of ​​various aspects of the present disclosure, and does not limit the scope of the present disclosure in any way. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a system including a data storage device having a memory for reading data based on read threshold calibration using multiple decoders according to some embodiments of the present disclosure.

[0011] Figure 2 is a diagram illustrating a decoder pool architecture 200 .

[0012] Figure 3 It shows the application Figure 2 Block diagram of a general example of a BES operating structure of a decoder pool.

[0013] Figure 4 It is to show the application of various aspects according to the present disclosure Figure 2 Block diagram of an example of the BES operating structure of a decoder pool.

[0014] Figure 5 This shows the operation after an ECC failure. Figure 2 Flowchart of a general example of a read threshold calibration process for a decoder pool.

[0015] Figure 6 FIG. 1 is a diagram showing the use of various aspects of the present disclosure after an ECC failure. Figure 2 Flowchart of an example of a read threshold calibration process for a decoder pool.

[0016] Figure 7 It is to show the application of various aspects according to the present disclosure Figure 2 A block diagram of an example of a second BES operating structure of a decoder pool.

[0017] Figure 8 is a flow chart illustrating a read threshold calibration process according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] In the following description, a large number of details (such as data storage device configuration, controller operation, etc.) are set forth in order to provide an understanding of one or more aspects of the present disclosure. It is apparent to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of the present application. Specifically, the functions associated with the data storage device may be performed by hardware (such as analog or digital circuits), a combination of hardware and software (such as non-transitory computer-readable media and electronic processors), or any other suitable components. The following description is intended only to give a general idea of ​​the various aspects of the present disclosure, without limiting the scope of the present disclosure in any way.

[0019] In order to calibrate the thresholds using the ECC code, the memory controller checks the bit error rate (BER) of various threshold combinations. For example, where a page has two thresholds and there are five threshold positions, the memory controller will need to check twenty-five (5^2=25) possible combinations (also referred to as "hypotheses"). After checking all possible combinations, the memory controller then selects the combination with the lowest BER. The read threshold calibration may be performed by a process of applying multiple sensings and then sequentially calculating a metric based on different hypotheses related to the number of sensings. Conventionally, an ECC decoder pool involving multiple independent ECC decoders serving the same command queue has been used to achieve higher throughput requirements and more stringent QoS requirements.

[0020] The memory controller of the present disclosure may check all possible combinations by performing twenty-five physical senses of a page (e.g., a NAND page). In other examples, the memory controller of the present disclosure may check all possible combinations by digitally generating all combinations / hypotheses. This process of digitally generating all combinations may be referred to as a BER estimation scan or "BES."

[0021] The memory controller of the present disclosure is described with respect to the BES method. However, the memory controller of the present disclosure is not limited to the BES method. In addition to or instead of generating all possible combinations digitally, the memory controller of the present disclosure can also read all combinations physically.

[0022] As described herein, there are two tasks that can be distributed over multiple decoders working together: 1) generate BES hypotheses from various read pages, where each hypothesis represents a read if the memory controller were to read from a particular threshold combination; 2) calculate / estimate the BER. In some examples, each of the multiple decoders can accurately calculate the BER by decoding the data and counting bit flips. In other examples, each of the multiple decoders can estimate the BER by calculating syndrome weights (SW), which are good proxies for the BER and require fewer computational resources.

[0023] The decoder of the present disclosure is generally considered to use a SW process to calculate the BER, because the SW process requires less computing resources. However, the decoder of the present disclosure is not limited to using a SW process to calculate the BER. In addition to or instead of using a SW process to calculate the BER, the decoder of the present disclosure can also calculate the BER by decoding the data and counting bit flips.

[0024] Figure 1is a block diagram of a system including a data storage device having a memory for reading data based on read threshold calibration using multiple decoders according to some embodiments of the present disclosure. Figure 1 In the example of , the system 100 includes a data storage device 102 and a host device 150. The data storage device 102 includes a controller 120 and a memory 104 (eg, non-volatile memory) coupled to the controller 120.

[0025] The data storage device 102 and the host device 150 may be operatively coupled via a connection such as a bus or a wireless connection (e.g., communication path 110). In some instances, the data storage device 102 may be embedded within the host device 150. Alternatively, in other instances, the data storage device 102 may be removable from the host device 150 (i.e., "removably" coupled to the host device 150). As an example, the data storage device 102 may be removably coupled to the host device 150 according to a removable universal serial bus (USB) configuration. In some implementations, the data storage device 102 may include or correspond to a solid-state drive (SSD), which may be used as an embedded storage drive (e.g., a mobile embedded storage drive), an enterprise storage drive (ESD), a client storage device, or a cloud storage drive, or other suitable storage drive.

[0026] The data storage device 102 may be configured to be coupled to a host device 150 via a communication path 110 (e.g., a wired communication path and / or a wireless communication path). For example, the data storage device 102 may include an interface 108 (e.g., a host interface) that enables communication via the communication path 110 between the data storage device 102 and the host device 150, such as when the interface 108 is communicatively coupled to the host device 150.

[0027] The host device 150 may include an electronic processor and a memory. The memory may be configured to store data and / or instructions that can be executed by the electronic processor. The memory may be a single memory or may include one or more memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. The host device 150 may issue one or more commands, such as one or more requests, to the data storage device 102 to erase data at the memory 104 of the data storage device 102, read data from the memory 104, or write data to the memory 104. For example, the host device 150 may be configured to provide data to be stored at the memory 104, such as user data 132, or request to read data from the memory 104. The host device 150 may include a mobile smart phone, a music player, a video player, a game console, an e-book reader, a personal digital assistant (PDA), a computer (such as a laptop or notebook computer), any combination thereof, or other suitable electronic devices.

[0028] The host device 150 communicates via a memory interface that enables reading from and writing to the memory 104. In some examples, the host device 150 may operate in accordance with industry specifications such as the Universal Flash Storage (UFS) host controller interface specification. In other examples, the host device 150 may operate in accordance with one or more other specifications such as the Secure Digital (SD) host controller specification or other suitable industry specifications. The host device 150 may also communicate with the memory 104 according to any other suitable communication protocol.

[0029] The memory 104 of the data storage device 102 may include a multi-level non-volatile memory (e.g., NOR, NAND, PCM, MRAM, 3-D XPoint, DRAM, BiCS series memory, or other suitable memory). In some examples, the memory 104 may be any type of flash memory. For example, the memory 104 may be a two-dimensional (2D) memory or a three-dimensional (3D) flash memory. The memory 104 may include one or more memory dies 103. Each of the one or more memory dies 103 may include one or more blocks (e.g., one or more erase blocks). Each block may include one or more groups of storage elements, such as a representative group of storage elements 107A to 107N. Each storage element in this group of storage elements 107A to 107N may be configured as a word line. Each storage element in this group of storage elements 107A to 107N may include a plurality of storage elements (e.g., memory cells referred to as "strings" herein), such as representative storage elements 109A and 109N.

[0030] Memory 104 may include support circuitry, such as read / write circuitry 140, for supporting the operation of one or more memory dies 103. Although depicted as a single component, read / write circuitry 140 may be divided into separate components of memory 104, such as read circuitry and write circuitry. Read / write circuitry 140 may be external to one or more memory dies 103 of memory 104. Alternatively, one or more separate memory dies may include corresponding read / write circuitry that is operable to read from and / or write to storage elements within the separate memory dies independently of any other read and / or write operations at any of the other memory dies.

[0031] The data storage device 102 includes a controller 120 coupled to a memory 104 (e.g., one or more memory dies 103) via a bus 106, an interface (e.g., interface circuitry), another structure, or a combination thereof. For example, the bus 106 may include a plurality of different channels to enable the controller 120 to communicate with each of the one or more memory dies 103 in parallel and independently with the other memory dies 103. In some implementations, the memory 104 may be flash memory.

[0032] The controller 120 is configured to receive data and instructions from the host device 150 and to send data to the host device 150. For example, the controller 120 may send data to the host device 150 via the interface 108, and the controller 120 may receive data from the host device 150 via the interface 108. The controller 120 is configured to send data and commands to the memory 104 and to receive data from the memory 104. For example, the controller 120 is configured to send data and a write command to cause the memory 104 to store data to a specified address of the memory 104. The write command may specify a physical address of a portion of the memory 104 where the data is to be stored (e.g., a physical address of a word line of the memory 104).

[0033] The controller 120 is configured to send a read command to the memory 104 to access data from a specified address of the memory 104. The read command may specify a physical address of a region of the memory 104 (e.g., a physical address of a word line of the memory 104). The controller 120 may also be configured to send data and commands to the memory 104 associated with background scan operations, garbage collection operations, and / or wear leveling operations or other suitable memory operations. For example, the controller 120 is configured to perform read operations according to the following description of the memory 104. Figure 6 The read threshold calibration process 600 described in more detail is used to perform the read threshold calibration 160 on the memory 104. Figure 4 and Figure 7The relationship between the ECC engine 126 and the read threshold calibration 160 is described in more detail.

[0034] The controller 120 may include an electronic processor 122, a memory 124, and an error correction code (ECC) engine 126 (e.g., as described below in Figure 2 The electronic processor 122 may be a microprocessor or other suitable electronic processing device. Figure 1 An example of the structural and functional features provided by the controller 120 is shown in FIG. However, the controller 120 is not limited to Figure 1 The controller 120 may include fewer or additional Figure 1 Structural and functional features not shown.

[0035] The metrics 162 may be tracked on a storage element by storage element basis, on a word line by word line basis, on a block by block basis, on a die by die basis, or on other suitable basis. The one or more metrics 162 may track a program / erase (P / E) count (PEC), a bit error rate (BER), a programming time, an erase time, a number of voltage pulses for programming a storage element, a number of voltage pulses for erasing a storage element, a combination thereof, or other suitable metrics corresponding to the memory 104.

[0036] Figure 2 is a diagram illustrating a decoder pool architecture 200. In the decoder pool architecture 200 (also referred to as an LDPC decoder), several decoding engines are used.

[0037] like Figure 2 As shown in FIG. 2 , in a decoder pool architecture 200 , instead of using a single decoder engine, the decoder engine is divided into pools 202 - 206 of independent decoders.

[0038] Conventionally, the BES hypothesis is calculated by using a BER estimation engine that is part of a single decoder. However, the conventional approach does not utilize the decoder pool architecture 200. Instead, the conventional approach runs the BES operation on a single engine of a decoder pool at the same rate as the single decoder engine.

[0039] Figure 3 It shows the application Figure 2 A block diagram of a conventional example of a BES operation structure 300 of a decoder pool architecture 200 is shown. Figure 3As shown in the BES operation structure 300 of FIG. 2 , each BES operation output by the BES state machines 302 to 306 is executed in a corresponding single decoder (i.e., one of the decoders 308 to 312) from the decoder pool architecture 200. A BES state machine, such as BES state machine 302, contains a mechanism to generate and send BES hypotheses to the decoder to calculate syndrome weights (SW), which are a proxy for BER estimation, or to accurately decode and calculate BER.

[0040] Each of the BES hypotheses represents a combination of read positions. For example, when there are seven read positions per page and two read thresholds, there will be seven squared possibilities for the combination of read positions that will provide the least amount of errors during a read operation.

[0041] like Figure 3 , the first decoder 308 may calibrate the thresholds for the first page, the second decoder 310 may calibrate the thresholds for the second page, and the third decoder 312 may calibrate the thresholds for the third page. In other words, in the BES operation structure 300, each individual decoder will calibrate the thresholds for the individual pages based on the BES assumptions from the individual BES state machines. Simultaneous BES from several frame memory units (FMUs) of the same WL is not considered.

[0042] A frame memory unit (FMU) may be a basic read unit (e.g., 4 kilobytes in size) from flash memory. An FMU may also be the smallest read unit that a host 150 can read from a data storage device 102. A flash word line includes several FMUs. For example, as described herein, a flash word line has four FMUs for a total of sixteen kilobytes per word line / page.

[0043] The disclosed read threshold calibration uses several decoders for the benefit of BES operations performed on a single FMU, thus reducing latency. The disclosed read threshold calibration can also perform BES operations on all FMUs from the same WL simultaneously, thus achieving better accuracy.

[0044] Figure 4 It is to show the application of various aspects according to the present disclosure Figure 2 4 is a block diagram of an example of a BES operation structure 400 of the decoder pool architecture 200. Figure 4 As shown in the BES operation structure 400, the centralized BES state machine 402 controls the Figure 2The centralized BES state machine 402 divides the BES hypothesis among the multiple decoders 404A to 404N to avoid any one of the multiple decoders 404A to 404N from becoming idle. In some examples, the multiple decoders 404A to 404N may also have faster or slower BER estimation modules (due to BER estimation module parallelism) so that the modules do not have to be synchronized.

[0045] Similar to BES operation structure 300, in BES operation structure 400, each of the BES hypotheses represents a certain combination of read positions. For example, when there are seven read positions per page and two read thresholds, there will be seven squared possibilities for the read position combination that will provide the least amount of error during a read operation. In some examples, instead of selecting a single BES hypothesis, interpolation may be performed between some of the BES hypotheses.

[0046] Furthermore, by dividing the BES hypotheses among multiple decoders 404A to 404N, determination of the best BES hypothesis (i.e., the read position combination that will provide the least amount of error during a read operation) can occur more quickly and more BES hypotheses can be checked during the same amount of time, resulting in better accuracy.

[0047] Since read threshold calibration typically occurs during anomalies, the latency reduction of the BES operation structure 400 may be very significant, depending on the number of decoders in the plurality of decoders 404A-404N. For example, when there are four decoding engines in a given system, the BES calculations performed in the example 400 may be four times faster than the conventional example 300.

[0048] Figure 5 This shows the operation after an ECC failure. Figure 2 Flowchart of a conventional example of a read threshold calibration process 500 for the decoder pool architecture 200. Figure 5 As shown in FIG. 5 , the read threshold calibration process 500 includes performing several reads of the same word line for different threshold positions (at block 502). The read threshold calibration process 500 includes passing the failed FMU to the controller 120 (at block 504). The read threshold calibration process 500 actually reads all four FMUs. However, because the read threshold calibration process 500 uses a single decoder that can be used to perform BES, the read threshold calibration process 500 only passes the failed FMU. In addition, the read threshold calibration process 500 does not provide the failed FMU to multiple decoders because the failed FMU will produce the same read position on multiple decoders.

[0049] The read threshold calibration process 500 includes performing BES on the failed FMU at block 506. The read threshold calibration process 500 also includes reading the word line at the read position based on the BES of the failed FMU at block 508. The accuracy of the BES read threshold is very significant because the read position with the lowest BER is necessary to reduce the number of errors in the failed FMU and improve the probability of decoding the failed FMU.

[0050] Figure 6 FIG. 1 is a diagram showing the use of various aspects of the present disclosure after an ECC failure. Figure 2 Flowchart of an example of a read threshold calibration process 600 for the decoder pool architecture 200. Figure 6 As shown in FIG. 6 , the controller 120 uses the read threshold calibration process 600 to perform several reads on different threshold locations of the same word line (at block 602 ).

[0051] However, unlike the read threshold calibration process 500, the controller 120 uses the read threshold calibration process 600 to transfer all FMUs for a given word line to the controller 120 (e.g., four FMUs per word line) at block 604. The controller 120 uses the read threshold calibration process 600 to perform BES on all FMUs simultaneously at block 606. The controller 120 also uses the read threshold calibration process 600 to read the word line at a read position based on the BES convergence of all FMUs at block 608.

[0052] By performing BES on all FMUs simultaneously, the controller 120 can aggregate the bit error rate (BER) results of the individual BES operations, and the aggregation will be more accurate than the bit error rate (BER) results using only a single BES operation. The aggregated BER results are more accurate because all FMUs are from the same word line and experience the same conditions, i.e., experience the same stress and other factors that change the condition of the word line. The read position based on the BES of all FMUs is also more accurate than the read position based on a single FMU because there is more data available when all FMUs are passed to the controller 120.

[0053] Although the read threshold calibration process 600 requires passing more FMUs than the read threshold calibration process 500, the total latency associated with the read threshold calibration process 600 may be less than the total latency associated with the read threshold calibration process 500 because the BES operation converges faster in the read threshold calibration process 600 that utilizes additional data from the additional FMUs.

[0054] Figure 7 It is to show the application of various aspects according to the present disclosure Figure 2 A block diagram of an example of a second BES operation structure 700 of the decoder pool architecture 200 is shown. Figure 7 As shown in the BES operation structure 700, the centralized BES state machine 702 controls the Figure 2 The centralized BES state machine 702 divides the work among the multiple decoders 704A to 704N to avoid any one of the multiple decoders 704A to 704N from becoming idle and achieves the fastest convergence to the BES threshold.

[0055] like Figure 7 As shown in FIG, BER results of separate operations of multiple decoders 704A-704N may be averaged or otherwise aggregated by BES state machine 702 as resulting aggregate 710. A BES threshold may be based on resulting aggregate 710, and the BES threshold will be more accurate than a BES threshold based on a single result from a single decoder.

[0056] Figure 8 8 is a flow chart illustrating a read threshold calibration process 800 according to some embodiments of the present disclosure. Figure 1 describe Figure 8 .

[0057] The read threshold calibration process 800 includes generating, using a controller circuit, a plurality of bit error estimation scan (BES) hypotheses for a word line in a plurality of word lines at block 802. For example, the electronic processor 122 generates a plurality of BES hypotheses for the storage element 107A.

[0058] The read threshold calibration process 800 includes utilizing a controller circuit to divide a plurality of BES hypotheses among a plurality of decoders at block 804. For example, the electronic processor 122 divides the plurality of BES hypotheses among the ECC engines 126.

[0059] The read threshold calibration process 800 includes using the controller circuit to receive bit error rate (BER) results from multiple decoders based on multiple BES hypotheses at block 806. For example, the electronic processor 122 receives the BER results from the ECC engine 126 based on multiple BES hypotheses. The BER results may include read position combinations that provide the least amount of error during a read operation or the BER / SW for some of the hypotheses.

[0060] The read threshold calibration process 800 also includes using the controller circuit to adjust one or more read positions of a word line based on the BER results from the plurality of decoders at block 808. For example, the electronic processor 122 adjusts one or more read positions of the storage element 107A based on the BER results from the ECC engine 126.

[0061] The read threshold calibration process 800 can be performed in at least two different use cases. The first use case is a periodic maintenance operation, where the electronic processor 122 initiates a periodic operation to calibrate the threshold of a block and / or word line. In some examples, the periodic maintenance operation can be performed without periodically reading the word line. In other examples, the periodic maintenance operation can be performed with periodic reading of the word line.

[0062] The second use case is an ECC failure, where the electronic processor 122 performs a regular read operation and fails to decode a certain FMU. In response to failing to decode a certain FMU, the electronic processor 122 initiates a recovery process that includes a read threshold calibration 800. In other words, the electronic processor 122 may first perform a read operation on a storage element 107A in a plurality of storage elements 107N having one or more read locations, and fails to decode the one storage element 107A. In response to failing to decode the one storage element 107A, the electronic processor performs the read threshold calibration process 800.

[0063] In some examples, the read threshold calibration process 800 may further include using the controller circuit to perform a second read operation on a word line at the adjusted one or more read positions. Additionally, in some examples, the read threshold calibration process 800 may further include using the controller circuit to generate a summary result by aggregating the BER results from the plurality of decoders. In these examples, adjusting the one or more read positions based on the BER results from the plurality of decoders further includes adjusting the one or more read positions based on the summary result.

[0064] In some examples, dividing the plurality of BES hypotheses among the plurality of decoders may further include dividing the plurality of BES hypotheses to keep the plurality of decoders in corresponding active states within a common time frame. In other examples, dividing the plurality of BES hypotheses among the plurality of decoders may further include dividing the plurality of BES hypotheses to control the plurality of decoders to output corresponding BER results at similar time points.

[0065] In some examples, a wordline includes a plurality of frame memory units (FMUs). In these examples, generating a plurality of BES hypotheses for a wordline in the plurality of wordlines may further include generating a plurality of BES hypotheses for each of the plurality of frame memory units (FMUs). Furthermore, in these examples, the plurality of FMUs may be four FMUs, and each FMU may have a size of four kilobytes.

[0066] With respect to the processes, systems, methods, heuristics, etc. described herein, it should be understood that although the steps of the processes, etc. have been described as being performed according to a certain ranked order, such processes may be practiced in such a way that the steps described are performed in an order other than the order described herein. It should be further understood that certain steps may be performed simultaneously, other steps may be added, or certain steps described herein may be omitted. In other words, the descriptions of the processes herein are provided for the purpose of illustrating certain embodiments and should in no way be construed as limiting the claims.

[0067] Therefore, it should be understood that the above description is intended to be illustrative and not restrictive. After reading the above description, many embodiments and applications other than the examples provided will be apparent. The scope of the present invention should not be determined with reference to the above description, but should in fact be determined with reference to the full scope of the equivalents authorized by the attached claims and the claims. It is expected and intended that future developments will be carried out for the technology discussed herein, and the disclosed system and method will be incorporated into the embodiments of the future. In a word, it should be understood that the application can be modified and varied.

[0068] Unless expressly indicated to the contrary herein, all terms used in the claims are intended to be given their broadest reasonable constructions and their ordinary meanings as understood by those knowledgeable of the technology as described herein. In particular, unless a claim recites an explicit limitation to the contrary, the use of singular articles such as "a", "the", "said", etc. should be understood to recite one or more of the indicated elements.

[0069] The abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It should be understood that the abstract will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that in various embodiments, various features are grouped together for the purpose of streamlining the disclosure. This approach to the disclosure should not be interpreted as reflecting the intention that the claimed embodiments require more features than those expressly recited in each claim. On the contrary, as reflected in the appended claims, the subject matter of the present invention lies in less than all of the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing alone as the subject matter of a separate claim.

Claims

1. A memory controller comprising: a memory interface configured to interface with a memory having a plurality of word lines; a plurality of decoders, each decoder of the plurality of decoders configured to determine a bit error rate (BER); as well as A controller circuit configured to: generating a plurality of bit error estimation scan (BES) hypotheses for one of the plurality of word lines, dividing the plurality of BES hypotheses among the plurality of decoders, receiving BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjusting one or more read locations of the one word line based on the BER results from the plurality of decoders, and wherein the one word line comprises a plurality of frame memory units (FMUs), and wherein to generate the plurality of BES hypotheses for the one word line in the plurality of word lines, the controller circuit is further configured to generate the plurality of BES hypotheses for each FMU in the plurality of frame memory units (FMUs).

2. The memory controller of claim 1 , wherein the controller circuit is further configured to: performing a read operation on the one of the plurality of word lines at a second one or more read locations, and detecting an ECC failure when performing the read operation on the one of the plurality of word lines at the second one or more read locations, and generating the plurality of BES hypotheses for the one of the plurality of word lines in response to detecting the ECC failure, Wherein the second one or more reading positions are different from the one or more reading positions. 3 . The memory controller of claim 1 , wherein the controller circuit is further configured to perform a read operation on the one word line at the adjusted one or more read locations.

4. The memory controller of claim 1 , wherein to partition the plurality of BES hypotheses among the plurality of decoders, the controller circuit is further configured to partition the plurality of BES hypotheses to keep the plurality of decoders in respective active states within a common time frame. 5 . The memory controller of claim 4 , wherein in order to divide the plurality of BES hypotheses among the plurality of decoders, the controller circuit is further configured to divide the plurality of BES hypotheses to control the plurality of decoders to output corresponding BER results at similar time points.

6. The memory controller of claim 1 , wherein to determine the BER, each of the plurality of decoders is configured to determine the BER by performing at least one of: The BER is accurately calculated by decoding the data read from the one word line and counting the bit flips, or calculating a syndrome weight (SW) of the one word line close to the BER, The BER result includes at least one of an exact BER or the SW.

7. The memory controller of claim 1 , wherein the controller circuit is further configured to generate a summary result by aggregating the BER results from the plurality of decoders, and wherein in order to adjust the one or more read positions based on the BER results from the plurality of decoders, the controller circuit is further configured to adjust the one or more read positions based on the summary result.

8. A method comprising: generating a plurality of bit error estimation scan (BES) hypotheses for a word line among the plurality of word lines using a controller circuit; dividing the plurality of BES hypotheses among a plurality of decoders using the controller circuit; employing the controller circuit to receive bit error rate (BER) results from the plurality of decoders based on the plurality of BES hypotheses; as well as employing the controller circuit to adjust one or more read locations of the one word line based on the BER results from the plurality of decoders, and Wherein the one wordline comprises a plurality of frame memory units (FMUs), and wherein generating the plurality of BES hypotheses for the one wordline of the plurality of wordlines further comprises generating the plurality of BES hypotheses for each FMU of the plurality of frame memory units (FMUs).

9. The method according to claim 8, further comprising: performing, with the controller circuit, a read operation on the one of the plurality of word lines at a second one or more read locations; detecting an ECC failure using the controller circuit when performing the read operation on the one of the plurality of word lines at the second one or more read locations; as well as generating the plurality of bit error estimation scan (BES) hypotheses for the one of the plurality of word lines in response to detecting the ECC failure, Wherein the second one or more reading positions are different from the one or more reading positions.

10. The method according to claim 8, further comprising: A second read operation is performed on the one word line at the adjusted one or more read locations using the controller circuit.

11. The method of claim 8, wherein dividing the plurality of BES hypotheses among the plurality of decoders further comprises dividing the plurality of BES hypotheses to keep the plurality of decoders in respective active states within a common time frame.

12. The method of claim 11, wherein dividing the plurality of BES hypotheses among the plurality of decoders further comprises dividing the plurality of BES hypotheses to control the plurality of decoders to output corresponding BER results at similar time points.

13. The method according to claim 8, further comprising: Determine a bit error rate (BER) using each of the plurality of decoders by performing at least one of the following: The BER is accurately calculated by decoding the data read from the one word line and counting the bit flips, or calculating a syndrome weight (SW) of the one word line close to the BER, The BER result includes at least one of an exact BER or the SW.

14. The method according to claim 8, further comprising: employing the controller circuit to generate an aggregate result by aggregating the BER results from the plurality of decoders, and Wherein adjusting the one or more read positions based on the BER results from the plurality of decoders further comprises adjusting the one or more read positions based on the aggregated results.

15. An apparatus comprising: means for generating a plurality of bit error estimation scan (BES) hypotheses for a word line among a plurality of word lines; means for dividing the plurality of BES hypotheses among a plurality of decoders; means for receiving bit error rate (BER) results from the plurality of decoders based on the plurality of BES hypotheses; as well as means for adjusting one or more read positions based on said BER results from said plurality of decoders, and wherein the one wordline comprises a plurality of frame memory units (FMUs), and wherein the means for generating the plurality of BES hypotheses for the one wordline of the plurality of wordlines further comprises means for generating the plurality of BES hypotheses for each of a plurality of frame memory units (FMUs).

16. The apparatus of claim 15, further comprising: means for performing a read operation on the one word line of the plurality of word lines having the one or more read locations; as well as means for detecting an ECC failure when performing the read operation on the one of the plurality of word lines having the one or more read locations, Wherein generating the plurality of bit error estimation scan (BES) hypotheses for the one of the plurality of word lines is in response to detecting the ECC failure.

17. The apparatus of claim 15, further comprising: Means for performing a second read operation on the one word line at the adjusted one or more read locations.

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