A high protection level unidirectional thyristor electrostatic protection device and its manufacturing method

Abstract

The invention discloses a high-protection-level unidirectional thyristor electrostatic protection device, comprising a P-type substrate; a first N-type deep well and a second N-type deep well are arranged in the substrate; a P-well is arranged on the right side of the second N-type deep well; a first P+ injection area and a first N+ injection area are arranged in the first N-type deep well; a second P+ injection area and a second N+ injection area are arranged in the second N-type deep well; a fourth N+ injection area connected across is arranged between the first N-type deep well and the second N-type deep well; a third P+ injection area and a third N+ injection area are arranged in the P-well; the first P+ injection area, the first N+ injection area, the second P+ injection area and the second N+ injection area are connected together and serve as the anode of the device, and the third P+ injection area and the third N+ injection area are connected together and serve as the cathode of the device.

Description

Technical Field

[0001] The invention relates to the field of electrostatic protection, and in particular to a high-protection-level unidirectional thyristor electrostatic protection device and a manufacturing method thereof. Background Art

[0002] With the advancement of semiconductor process technology, the failure of integrated circuit chips and electronic products caused by ESD has become more and more serious. ESD protection of electronic products and integrated circuit chips has become one of the main problems faced by product engineers.

[0003] Compared with other ESD devices, traditional thyristor devices have a dual conductance modulation mechanism, high discharge efficiency per unit area, small unit parasitic capacitance, and the best robustness. However, in order to achieve a higher level of protection, it is often necessary to make the device into a multi-finger shape, which may lead to the problem of the maintenance voltage decreasing as the number of fork indexes increases, and it consumes a lot of area, which needs to be considered during the design.

[0004] The cross-section diagram of the traditional unidirectional thyristor electrostatic protection device is shown in Figure 1 , its equivalent circuit diagram is shown in Figure 2 When an ESD pulse is applied to the SCR anode, the second N-type deep well and the P-well form a reverse biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current will be generated inside the device. The current flows through the P-well parasitic resistance to the other end, that is, the cathode. When the voltage across the parasitic well resistance is higher than the forward conduction voltage of the cb junction of the parasitic NPN transistor (composed of the P-well and the third N+ injection region), the transistor is turned on. After the transistor is turned on, it provides base current for the PNP1 transistor. After the PNP1 transistor is turned on, it also provides base current for the parasitic NPN transistor, forming a positive feedback loop. As the ESD current continues to increase, after PNP1 provides enough base current for PNP2, PNP2 is also turned on successively, forming an SCR path with NPN, which can also discharge static electricity. However, the holding voltage of the traditional SCR generally decreases with the increase of the cross index, which is easy to exceed the design window and cause latch-up. Therefore, it is necessary to avoid the holding voltage being too small. However, the method of increasing the holding voltage will reduce the robustness of the device, so its robustness also needs to be considered. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a unidirectional thyristor electrostatic protection device with a simple structure and a high protection level and a manufacturing method thereof.

[0006] The embodiment of the present invention provides a high protection level unidirectional thyristor electrostatic protection device, including a P-type substrate;

[0007] A first N-type deep well and a second N-type deep well are provided in the P-type substrate; wherein the first N-type deep well is located on the left side of the P-type substrate, and the second N-type deep well is located on the right side of the P-type substrate;

[0008] A P well is provided on the right side of the second N-type deep well;

[0009] A first P+ injection region and a first N+ injection region are provided in the first N-type deep well, wherein the first P+ injection region is located on the right side of the first N-type deep well, and the first N+ injection region is located on the left side of the first N-type deep well;

[0010] A second P+ injection region and a second N+ injection region are provided in the second N-type deep well, wherein the second P+ injection region is located on the right side of the second N-type deep well, and the second N+ injection region is located on the left side of the second N-type deep well;

[0011] A fourth N+ implantation region is provided between the first N-type deep well and the second N-type deep well;

[0012] A third P+ injection region and a third N+ injection region are provided in the P well, wherein the third P+ injection region is located on the right side of the P well, and the third N+ injection region is located on the left side of the P well;

[0013] The first P+ injection region, the first N+ injection region, the second P+ injection region and the second N+ injection region are connected together and serve as the anode of the device, and the third P+ injection region and the third N+ injection region are connected together and serve as the cathode of the device.

[0014] Among them, a first field oxygen isolation region is provided between the left side of the first N+ injection region and the left edge of the P-type substrate; the right side of the first N+ injection region is connected to the left side of the first P+ injection region, and a second field oxygen isolation region is provided between the right side of the first P+ injection region and the fourth N+ injection region spanning between the first N-type deep well and the second N-type deep well; a third field oxygen isolation region is provided between the fourth N+ injection region spanning between the first N-type deep well and the second N-type deep well and the right side of the second N+ injection region; a fourth field oxygen isolation region is provided between the right side of the second P+ injection region and the third N+ injection region, and the left side of the second P+ injection region is connected to the right side of the second N+ injection region; a fifth field oxygen isolation region is provided between the right side of the third P+ injection region on the right side and the right edge of the P-type substrate.

[0015] Among them, the left part of the first field oxygen isolation region is located on the surface of the P-type substrate, and the right part of the first field oxygen isolation region is located on the surface of the first N-type deep well; the left part of the fifth field oxygen isolation region is located on the surface of the P-well, and the right part of the fifth field oxygen isolation region is located on the surface of the P-type substrate; the second field oxygen isolation region is located on the surface of the first N-type deep well, and the third field oxygen isolation region is located on the surface of the second N-type deep well; the left part of the fourth field oxygen isolation region is located on the surface of the second N-type deep well, and the right part of the fourth field oxygen isolation region is located on the surface of the P-well.

[0016] Among them, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the second P+ injection region, the second N-type deep well and the P-well in the second N-type deep well constitute a parasitic PNP1 triode structure; the second N-type deep well, the P-well and the third N+ injection region constitute a parasitic NPN triode; the first P+ injection region, the first N-type deep well and the P-type substrate in the first N-type deep well constitute a parasitic PNP2 triode structure.

[0017] Wherein, the distance between the P well and the third N+ implantation region is S1.

[0018] The embodiment of the present invention further provides a method for manufacturing a high protection level unidirectional thyristor electrostatic protection device according to any one of the present inventions, comprising the following steps:

[0019] Step 1: forming a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region and a fifth field oxygen isolation region in sequence from left to right in the substrate;

[0020] Step 2: forming a first N-type deep well and a second N-type deep well in the substrate;

[0021] Step 3: generating a P well on the right side of the second N-type deep well;

[0022] Step 4: performing annealing treatment on the first N-type deep well, the second N-type deep well, and the P-well to eliminate diffusion of impurities;

[0023] Step 5: forming a first N+ injection region and a first P+ injection region in the first N-type deep well; forming a second N+ injection region and a second P+ injection region in the second N-type deep well; forming a third N+ injection region and a third P+ injection region in the P-well; forming a fourth N+ injection region at the junction of the right side of the first N-type deep well and the left side of the second N-type deep well;

[0024] Step six: performing annealing treatment on the first N+ implantation region, the first P+ implantation region, the second N+ implantation region, the second P+ implantation region, the third N+ implantation region, the third P+ implantation region, and the fourth N+ implantation region to eliminate the migration of impurities in the implantation region;

[0025] Step seven: The first P+ injection region, the first N+ injection region, the second P+ injection region and the second N+ injection region are connected together and serve as the anode of the device, and the third P+ injection region and the third N+ injection region are connected together and serve as the cathode of the device.

[0026] Wherein, the step 1 also includes the following steps:

[0027] A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

[0028] The beneficial effects of the present invention are:

[0029] 1. The present invention can increase or decrease the number of N-type deep wells and their N+ injection areas and P+ injection areas according to different protection levels. That is, if the protection level is high, the number of N-type deep wells and their N+ injection areas and P+ injection areas is increased to improve the uniform distribution of device current and enhance the robustness of the device. If the protection level is low, the number of N-type deep wells and their N+ injection areas and P+ injection areas is reduced to reduce the layout area.

[0030] 2. The distance S1 between the P well and the third N+ injection region of the present invention is adjustable. When S1 increases, the base width of the NPN transistor also increases, reducing the amplification factor of the vertical NPN transistor and increasing the holding voltage.

[0031] 3. The holding voltage of the device of the present invention will not decrease with the increase of the fork index, and the magnitude of the holding voltage is determined by the length of the inner SCR path that is turned on first. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic protection device.

[0033] Figure 2 This is the equivalent circuit diagram of the traditional unidirectional SCR electrostatic protection device.

[0034] Figure 3 A cross-sectional view of a high protection level unidirectional thyristor electrostatic protection device provided by an embodiment of the present invention.

[0035] Figure 4 The equivalent circuit diagram of a high protection level unidirectional thyristor electrostatic protection device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0037] like Figure 3 As shown, a high protection level unidirectional thyristor electrostatic protection device includes a P-type substrate 101; a first N-type deep well 201 and a second N-type deep well 202 are provided in the substrate; a P-well 301 is provided on the right side of the second N-type deep well 202; a first P+ injection area 402 and a first N+ injection area 401 are provided in the first N-type deep well 201; a second P+ injection area 405 and a second N+ injection area 404 are provided in the second N-type deep well 202; a fourth N+ injection area 403 is provided between the first N-type deep well 201 and the second N-type deep well 202; a third P+ injection area 407 and a third N+ injection area 406 are provided in the P-well 301; the first P+ injection area 402, the first N+ injection area 401, the second P+ injection area 405 and the second N+ injection area 404 are connected together and serve as the anode of the device, and the third P+ injection area 407 and the third N+ injection area 406 are connected together and serve as the cathode of the device.

[0038] A first field oxygen isolation region 501 is provided between the left side of the first N+ injection region 401 and the left edge of the P-type substrate 101; the right side of the first N+ injection region 401 is connected to the left side of the first P+ injection region 402, and a second field oxygen isolation region 502 is provided between the right side of the first P+ injection region 402 and the fourth N+ injection region 403 bridging between the first N-type deep well 201 and the second N-type deep well 202; a third field oxygen isolation region 503 is provided between the fourth N+ injection region 403 bridging between the first N-type deep well 201 and the second N-type deep well 202 and the right side of the second N+ injection region 404; a fourth field oxygen isolation region 504 is provided between the right side of the second P+ injection region 405 and the third N+ injection region 406, and the left side of the second P+ injection region 405 is connected to the right side of the second N+ injection region 404; a fifth field oxygen isolation region 505 is provided between the right side of the third P+ injection region 407 located on the far right and the right edge of the P-type substrate 101.

[0039] The left portion of the first field oxygen isolation region 501 is located on the surface of the P-type substrate 101, and the right portion of the first field oxygen isolation region 501 is located on the surface of the first N-type deep well 201; the left portion of the fifth field oxygen isolation region 505 is located on the surface of the P-well 301, and the right portion of the fifth field oxygen isolation region 505 is located on the surface of the P-type substrate 101; the second field oxygen isolation region 502 is located on the surface of the first N-type deep well 201, and the third field oxygen isolation region 503 is located on the surface of the second N-type deep well 202; the left portion of the fourth field oxygen isolation region 504 is located on the surface of the second N-type deep well 202, and the right portion of the fourth field oxygen isolation region 504 is located on the surface of the P-well 301.

[0040] like Figure 4 As shown, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the second P+ injection region 405, the second N-type deep well 202, and the P-well 301 in the second N-type deep well 202 form a parasitic PNP1 triode structure; the second N-type deep well 202, the P-well 301, and the third N+ injection region 406 form a parasitic NPN triode; at the same time, the first P+ injection region 402, the first N-type deep well 201, and the P-type substrate 101 in the first N-type deep well 301 also form a parasitic PNP2 triode structure. The parasitic PNP2 transistor in the first N-type deep well 201 and the parasitic PNP1 transistor in the second N-type deep well 202 can form a bidirectional SCR structure with the NPN transistor in the P-well 301.

[0041] When the ESD high voltage pulse reaches the anode of the device, the first P+ injection area, the first N+ injection area, the second P+ injection area and the second N+ injection area are at high potential, and the third P+ injection area and the third N+ injection area are at low potential cathode. The second N-type deep well 202 and the P well 301 are reverse biased. When the pulse voltage is higher than the avalanche breakdown voltage of the junction, a large amount of avalanche current will be generated inside the device, causing the two parasitic resistors R n阱1 , R p阱 The voltage at both ends increases, and one of the parasitic transistors is turned on first, further providing base current for the other parasitic transistor. Since the innermost SCR path is shorter and the on-resistance is smaller, the SCR formed by the innermost T1 and T2 is turned on first, and the inner parasitic PNP1 transistor is turned on and provides trigger current to the outer T3 transistor. Then T2 and T3 also form an SCR structure to continue to discharge the electrostatic current, so that the entire device is turned on.

[0042] Compared with the traditional unidirectional thyristor electrostatic protection device, this device adds a parasitic transistor at the anode. Since the inner SCR path is shorter, it is turned on first, and the device's holding voltage is determined by the inner SCR path. When the current continues to increase, the inner parasitic transistor PNP1 provides base current for the outer parasitic transistor PNP2, and the outer SCR will also turn on. At the same time, since there is a discharge path, both are turned on, the current distribution is more uniform, and static electricity can be better discharged, so that the device protection level will also be higher.

[0043] This device can increase or decrease the number of N-type deep wells and their N+ injection areas and P+ injection areas according to the requirements of the ESD design window in different application scenarios and the different protection levels. That is, if the protection level is high, the number of N-type deep wells and their N+ injection areas and P+ injection areas will be increased to improve the uniform distribution of device current and enhance the robustness of the device. If the protection level is low, the number of N-type deep wells and their N+ injection areas and P+ injection areas will be reduced to reduce the layout area.

[0044] A method for manufacturing a high-protection-level unidirectional thyristor electrostatic protection device comprises the following steps:

[0045] Step 1: grow a layer of silicon dioxide film on the P-type substrate 101, and then deposit a layer of silicon nitride; spin-coat a photoresist layer on the wafer, expose and develop it with a mask to form an isolation shallow groove; etch the silicon dioxide, silicon nitride and isolation shallow groove to remove the photoresist layer, deposit a layer of silicon dioxide, and then perform chemical polishing until the silicon nitride layer is formed, and remove the silicon nitride layer;

[0046] Step 2: forming a first field oxygen isolation region 501, a second field oxygen isolation region 502, a third field oxygen isolation region 503, a fourth field oxygen isolation region 504, and a fifth field oxygen isolation region 505 in the substrate from left to right;

[0047] Step 3: forming a first N-type deep well 201 and a second N-type deep well 202 in the substrate;

[0048] Step 4: performing annealing treatment on the first N-type deep well 201 and the second N-type deep well 202 to eliminate diffusion of impurities;

[0049] Step 5: forming a first N+ injection region 401 and a first P+ injection region 402 in the first N-type deep well 201; forming a second N+ injection region 404 and a second P+ injection region 405 in the second N-type deep well 202; forming a third N+ injection region 406 and a third P+ injection region 407 in the P well 301; forming a fourth N+ injection region 403 at the right side of the first N-type deep well 201 and the left side of the second N-type deep well 202;

[0050] Step 6: Annealing the first N+ implantation region 401, the first P+ implantation region 402, the second N+ implantation region 404, the second P+ implantation region 405, the third N+ implantation region 406, the third P+ implantation region 407, and the fourth N+ implantation region 403 to eliminate the migration of impurities in the implantation regions;

[0051] Step seven: The first P+ injection region 402, the first N+ injection region 401, the second P+ injection region 405 and the second N+ injection region 404 are connected together and serve as the anode of the device, and the third P+ injection region 407 and the third N+ injection region 406 are connected together and serve as the cathode of the device.

[0052] The manufacturing method of the high protection level unidirectional thyristor electrostatic protection device of the present invention is simple and easy to operate. The manufactured unidirectional thyristor electrostatic protection device structure can improve the current uniformity of the device and the robustness of the device by increasing the number of N-type deep wells and their N+ injection areas and P+ injection areas; if the required protection level is lower, the number of N-type deep wells and their N+ injection areas and P+ injection areas can be reduced to achieve the purpose of reducing the layout area; the holding voltage can be increased by increasing the S1 distance. This device can be used in ESD protection design to effectively protect the internal chip and keep away from the risk of latch-up. The example device of the present invention adopts a 0.5μm CMOS process.

Claims

1. A high protection level unidirectional thyristor electrostatic protection device, characterized in that: including a P-type substrate; A first N-type deep well and a second N-type deep well are provided in the P-type substrate; wherein the first N-type deep well is located on the left side of the P-type substrate, and the second N-type deep well is located on the right side of the P-type substrate; A P well is provided on the right side of the second N-type deep well; A first P+ injection region and a first N+ injection region are provided in the first N-type deep well, wherein the first P+ injection region is located on the right side of the first N-type deep well, and the first N+ injection region is located on the left side of the first N-type deep well; A second P+ injection region and a second N+ injection region are provided in the second N-type deep well, wherein the second P+ injection region is located on the right side of the second N-type deep well, and the second N+ injection region is located on the left side of the second N-type deep well; A fourth N+ implantation region is provided between the first N-type deep well and the second N-type deep well; A third P+ injection region and a third N+ injection region are provided in the P well, wherein the third P+ injection region is located on the right side of the P well, and the third N+ injection region is located on the left side of the P well; The first P+ injection region, the first N+ injection region, the second P+ injection region and the second N+ injection region are connected together and serve as the anode of the device, and the third P+ injection region and the third N+ injection region are connected together and serve as the cathode of the device.

2. The high protection level unidirectional thyristor electrostatic protection device according to claim 1 is characterized in that: A first field oxygen isolation region is provided between the left side of the first N+ injection region and the left edge of the P-type substrate; the right side of the first N+ injection region is connected to the left side of the first P+ injection region, and a second field oxygen isolation region is provided between the right side of the first P+ injection region and the fourth N+ injection region spanning between the first N-type deep well and the second N-type deep well; a third field oxygen isolation region is provided between the fourth N+ injection region spanning between the first N-type deep well and the second N-type deep well and the right side of the second N+ injection region; a fourth field oxygen isolation region is provided between the right side of the second P+ injection region and the third N+ injection region, and the left side of the second P+ injection region is connected to the right side of the second N+ injection region; a fifth field oxygen isolation region is provided between the right side of the third P+ injection region on the right side and the right edge of the P-type substrate.

3. The high protection level unidirectional thyristor electrostatic protection device according to claim 2 is characterized in that: The left portion of the first field oxygen isolation region is located on the surface of the P-type substrate, and the right portion of the first field oxygen isolation region is located on the surface of the first N-type deep well; the left portion of the fifth field oxygen isolation region is located on the surface of the P-well, and the right portion of the fifth field oxygen isolation region is located on the surface of the P-type substrate; the second field oxygen isolation region is located on the surface of the first N-type deep well, and the third field oxygen isolation region is located on the surface of the second N-type deep well; the left portion of the fourth field oxygen isolation region is located on the surface of the second N-type deep well, and the right portion of the fourth field oxygen isolation region is located on the surface of the P-well.

4. The high protection level unidirectional thyristor electrostatic protection device according to claim 2 is characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the second P+ injection region, the second N-type deep well and the P-well in the second N-type deep well constitute a parasitic PNP1 triode structure; the second N-type deep well, the P-well and the third N+ injection region constitute a parasitic NPN triode; the first P+ injection region, the first N-type deep well and the P-type substrate in the first N-type deep well constitute a parasitic PNP2 triode structure.

5. The high protection level unidirectional thyristor electrostatic protection device according to claim 4 is characterized in that: The distance between the P well and the third N+ implantation region is S1.

6. A method for manufacturing a high protection level unidirectional thyristor electrostatic protection device according to any one of claims 1 to 5, characterized in that: The following steps are involved: Step 1: forming a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region and a fifth field oxygen isolation region in sequence from left to right in the substrate; Step 2: forming a first N-type deep well and a second N-type deep well in the substrate; Step 3: generating a P well on the right side of the second N-type deep well; Step 4: performing annealing treatment on the first N-type deep well, the second N-type deep well, and the P-well to eliminate diffusion of impurities; Step 5: forming a first N+ injection region and a first P+ injection region in the first N-type deep well; forming a second N+ injection region and a second P+ injection region in the second N-type deep well; forming a third N+ injection region and a third P+ injection region in the P well; forming a fourth N+ injection region at the junction of the right side of the first N-type deep well and the left side of the second N-type deep well; Step six: performing annealing treatment on the first N+ implantation region, the first P+ implantation region, the second N+ implantation region, the second P+ implantation region, the third N+ implantation region, the third P+ implantation region, and the fourth N+ implantation region to eliminate the migration of impurities in the implantation region; Step seven: The first P+ injection region, the first N+ injection region, the second P+ injection region and the second N+ injection region are connected together and serve as the anode of the device, and the third P+ injection region and the third N+ injection region are connected together and serve as the cathode of the device.

7. The method for manufacturing a high protection level unidirectional thyristor electrostatic protection device according to claim 6, characterized in that: The step 1 also includes the following steps: A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

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