Light receiving element

Abstract

The present invention relates to a light receiving element. The light receiving element may include: a semiconductor layer having a light receiving surface; a multilayer wiring layer provided at a surface of the semiconductor layer opposite to the light receiving surface; and a plurality of pixels; wherein the pixels include: a first voltage applying portion configured to apply a first voltage to the semiconductor layer; a second voltage applying portion configured to apply a second voltage to the semiconductor layer; a first charge detecting portion provided adjacent to the first voltage applying portion; a second charge detecting portion provided in the semiconductor layer and adjacent to the second voltage applying portion; and a first separating portion provided between the first voltage applying portion and the first charge detecting portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a divisional application of Chinese patent application No. 201880004031.0. The application date of patent application No. 201880004031.0 is January 5, 2018, and the name of the invention is “Light receiving element, imaging element and imaging device”. Technical Field

[0003] The present technology relates to a light receiving element, an imaging element, and an imaging device, and more particularly to a light receiving element, an imaging element, and an imaging device capable of improving characteristics. Background Art

[0004] In the prior art, distance measurement systems using the indirect time-of-flight (ToF) method are known. In such distance measurement systems, sensors capable of classifying signal charges into different areas at high speed are absolutely necessary, the signal charges being obtained by receiving active light emitted by a light emitting diode (LED) or a laser using a specific phase and reflected on an object.

[0005] Therefore, for example, a technology has been proposed in which a voltage is directly applied to a substrate of a sensor and a current is generated in the substrate, and thus a wide range of regions within the substrate can be modulated at high speed (for example, see Patent Document 1). Such a sensor is also called a current-assisted photon demodulator (CAPD) sensor.

[0006] Citation list

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2011-86904 Summary of the invention

[0009] Problem that the invention aims to solve

[0010] However, in the above-mentioned techniques, it is difficult to obtain a CAPD sensor having sufficient characteristics.

[0011] For example, the above-mentioned CAPD sensor is a front-illuminated type sensor in which wiring and the like are arranged on the surface of the substrate on the side that receives light from the outside.

[0012] In order to ensure the photoelectric conversion area, it is desirable that no component, such as wiring, that blocks the optical path of the light to be incident is provided on the light receiving surface side of the photodiode (PD) (i.e., the photoelectric conversion unit). However, in the front-illuminated CAPD sensor, it is necessary to configure wiring for charge extraction, various control lines, or signal lines on the light receiving surface side of the PD according to the structure, and therefore, the photoelectric conversion area is limited. That is, it is impossible to ensure a sufficient photoelectric conversion area, and there is a case where characteristics such as pixel sensitivity are reduced.

[0013] In addition, when considering the case where the CAPD sensor is used in the presence of external light, the external light component becomes a noise component for the indirect ToF method of measuring the distance by using active light, and therefore, in order to obtain distance information by ensuring a sufficient signal-to-noise ratio (SN ratio), it is necessary to ensure a sufficient saturation signal amount (Qs). However, in the front-illuminated CAPD sensor, there are limitations on the wiring layout, and therefore, it is necessary to devise a method other than using wiring capacitance, for example, a method of providing an additional transistor for ensuring capacitance.

[0014] In addition, in the front-irradiated CAPD sensor, a signal extraction section called a tap is arranged on the light-incident side of the substrate. On the other hand, when considering the photoelectric conversion within the Si substrate, there is a difference in the attenuation rate at the wavelength of light, but the proportion of photoelectric conversion performed on the light incident surface side increases. For this reason, in the front-type CAPD sensor, there is a possibility that in the well area where the signal extraction section is set, the probability of performing photoelectric conversion in the inactivated well area as a well area where the signal charge is not classified increases. In the indirect ToF sensor, distance measurement information is obtained by using signals classified into each charge accumulation area according to the phase of the active light, and therefore, the component that is directly photoelectrically converted in the inactivated well area becomes noise, and as a result, there is a possibility that the distance measurement accuracy is deteriorated. That is, there is a possibility that the characteristics of the CAPD sensor are reduced.

[0015] This technology was developed in consideration of this situation and aims to improve the characteristics.

[0016] Solutions to the problem

[0017] A light receiving element according to a first aspect of the present technology includes:

[0018] On-chip lens;

[0019] Wiring layer; and

[0020] a semiconductor layer disposed between the on-chip lens and the wiring layer,

[0021] The semiconductor layer comprises

[0022] a first voltage applying unit to which a first voltage is applied,

[0023] a second voltage applying section to which a second voltage different from the first voltage is applied,

[0024] a first charge detection section disposed around the first voltage applying section, and

[0025] a second charge detection unit disposed around the second voltage applying unit,

[0026] The wiring layer includes

[0027] at least one layer having a first voltage applying wiring configured to supply a first voltage, a second voltage applying wiring configured to supply a second voltage, and a reflective member, and

[0028] The reflective member is disposed so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

[0029] In a first aspect of the present technology, an on-chip lens, a wiring layer, and a semiconductor layer disposed between the on-chip lens and the wiring layer are provided, and a first voltage applying portion to which a first voltage is applied, a second voltage applying portion to which a second voltage different from the first voltage is applied, a first charge detection portion disposed around the first voltage applying portion, and a second charge detection portion disposed around the second voltage applying portion are provided in the semiconductor layer. At least one layer having a first voltage applying wiring configured to supply a first voltage, a second voltage applying wiring configured to supply a second voltage, and a reflective member is provided in the wiring layer, and the reflective member is provided to overlap with the first charge detection portion or the second charge detection portion in a plan view.

[0030] The imaging element according to the second aspect of the present technology includes:

[0031] a pixel array section including a plurality of pixels configured to perform photoelectric conversion on incident light,

[0032] The pixels include

[0033] a substrate configured to perform photoelectric conversion on incident light, and

[0034] A signal extraction unit includes a voltage application unit for generating an electric field by applying a voltage to the substrate and a charge detection unit for detecting signal carriers generated by photoelectric conversion, and the signal extraction unit is arranged inside the substrate on the surface of the substrate opposite to the incident surface of the substrate where light is incident.

[0035] Two signal extraction sections may be formed in the pixel.

[0036] A signal extraction portion may be formed in the pixel.

[0037] Three or more signal extraction sections may be formed in the pixel.

[0038] The signal extraction section may be shared between the pixel and another pixel adjacent to the pixel.

[0039] The voltage applying section may be shared between the pixel and another pixel adjacent to the pixel.

[0040] In the signal extraction section, a P-type semiconductor region as the voltage application section and an N-type semiconductor region as the charge detection section may be provided, the N-type semiconductor region being formed so as to surround the P-type semiconductor region.

[0041] In the signal extraction section, an N-type semiconductor region as the charge detection section and a P-type semiconductor region as the voltage application section may be provided, the P-type semiconductor region being formed so as to surround the N-type semiconductor region.

[0042] In the signal extraction unit, a first N-type semiconductor region and a second N-type semiconductor region as the charge detection unit and a P-type semiconductor region as the voltage application unit can be set, and the P-type semiconductor region is formed at a position sandwiched between the first N-type semiconductor region and the second N-type semiconductor region.

[0043] In the signal extraction unit, a first P-type semiconductor region and a second P-type semiconductor region as the voltage application unit and an N-type semiconductor region as the charge detection unit can be set, and the N-type semiconductor region is formed at a position sandwiched between the first P-type semiconductor region and the second P-type semiconductor region.

[0044] A voltage may be applied to the incident surface side in the substrate.

[0045] In the pixel, a reflective member configured to reflect light incident on the substrate from the incident surface may be further provided, the reflective member being formed on a surface of the substrate on the side opposite to the incident surface.

[0046] The signal carriers may include electrons.

[0047] The signal carriers may include holes.

[0048] In the pixel, a lens configured to condense light and make the light incident on the substrate may be further provided.

[0049] In the pixel, an inter-pixel light shielding portion configured to shield incident light may be further provided, the inter-pixel light shielding portion being formed at an end portion of the pixel on the incident surface of the substrate.

[0050] In the pixel, a pixel separation region configured to penetrate at least a portion of the substrate and shield incident light may be further provided, the pixel separation region being formed at an end portion of the pixel in the substrate.

[0051] The substrate may include a P-type semiconductor substrate having a resistance greater than or equal to 500 [Ωcm].

[0052] The substrate may include an N-type semiconductor substrate having a resistance greater than or equal to 500 [Ωcm].

[0053] In a second aspect of the present technology,

[0054] A pixel array section including a plurality of pixels configured to perform photoelectric conversion on incident light is provided in the imaging element, and

[0055] A substrate configured to perform photoelectric conversion on incident light and an extraction section including a signal extraction section are provided in the pixel,

[0056] The signal extraction unit includes a voltage application unit for generating an electric field by applying a voltage to the substrate and a charge detection unit for detecting signal carriers generated by photoelectric conversion, and the extraction unit is arranged within the substrate on the surface of the substrate opposite to the incident surface of the substrate where light is incident.

[0057] The imaging device of the third aspect of the present technology includes:

[0058] a pixel array section including a plurality of pixels configured to perform photoelectric conversion on incident light; and

[0059] a signal processing section configured to calculate distance information to an object based on the signal output from the pixel,

[0060] The pixels include

[0061] a substrate configured to perform photoelectric conversion on incident light, and

[0062] A signal extraction unit includes a voltage application unit for generating an electric field by applying a voltage to the substrate and a charge detection unit for detecting signal carriers generated by photoelectric conversion, and the signal extraction unit is arranged inside the substrate on the surface of the substrate opposite to the incident surface of the substrate where light is incident.

[0063] In a third aspect of the present technology,

[0064] A pixel array section including a plurality of pixels configured to perform photoelectric conversion on incident light and a signal processing section configured to calculate distance information to a subject based on signals output from the pixels is provided in the imaging device, and

[0065] A substrate configured to perform photoelectric conversion on incident light and an extraction section including a signal extraction section are provided in the pixel,

[0066] The signal extraction unit includes a voltage application unit for generating an electric field by applying a voltage to the substrate and a charge detection unit for detecting signal carriers generated by photoelectric conversion, and the extraction unit is arranged within the substrate on the surface of the substrate opposite to the incident surface of the substrate where light is incident.

[0067] Effects of the Invention

[0068] According to the first to third aspects of the present technology, characteristics can be improved.

[0069] Furthermore, the effects described here are not necessarily limited but may include any effects described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 It is a diagram showing a configuration example of a solid-state imaging element.

[0071] Figure 2 A diagram showing an example of the configuration of a pixel.

[0072] Figure 3 It is a diagram showing a configuration example of a part of a pixel signal extraction unit.

[0073] Figure 4 It is a graph showing the improvement in sensitivity.

[0074] Figure 5 It is a graph explaining the improvement of charge separation efficiency.

[0075] Figure 6 This is a diagram illustrating the improvement in electron extraction efficiency.

[0076] Figure 7 This is a diagram for explaining the moving speed of signal carriers in the front irradiation type.

[0077] Figure 8 This is a diagram for explaining the migration speed of signal carriers in the back-illuminated type.

[0078] Fig. 9 FIG. 1 is a diagram showing another configuration example of a part of a pixel signal extraction unit.

[0079] Fig.10 is a diagram illustrating the relationship between pixels and on-chip lenses.

[0080] Fig.11 FIG. 1 is a diagram showing another configuration example of a part of a pixel signal extraction unit.

[0081] Fig.12FIG. 1 is a diagram showing another configuration example of a part of a pixel signal extraction unit.

[0082] Fig.13 FIG. 1 is a diagram showing another configuration example of a part of a pixel signal extraction unit.

[0083] Fig.14 FIG. 1 is a diagram showing another configuration example of a part of a pixel signal extraction unit.

[0084] Fig.15 FIG. 1 is a diagram showing another configuration example of a part of a pixel signal extraction unit.

[0085] Fig.16 A diagram showing another configuration example of a pixel.

[0086] Fig.17 A diagram showing another configuration example of a pixel.

[0087] Fig.18 A diagram showing another configuration example of a pixel.

[0088] Fig.19 A diagram showing another configuration example of a pixel.

[0089] Fig. 20 A diagram showing another configuration example of a pixel.

[0090] Fig.21 A diagram showing another configuration example of a pixel.

[0091] Fig. 22 A diagram showing another configuration example of a pixel.

[0092] Fig.23 A diagram showing another configuration example of a pixel.

[0093] Fig.24 A diagram showing another configuration example of a pixel.

[0094] Fig.25 A diagram showing another configuration example of a pixel.

[0095] Fig.26 A diagram showing another configuration example of a pixel.

[0096] Fig. 27 A diagram showing another configuration example of a pixel.

[0097] Fig.28 A diagram showing another configuration example of a pixel.

[0098] Fig.29 A diagram showing another configuration example of a pixel.

[0099] Fig.30A diagram showing another configuration example of a pixel.

[0100] Fig.31 is a diagram showing an equivalent circuit of a pixel.

[0101] Fig.32 is a diagram showing another equivalent circuit of a pixel.

[0102] Fig.33 1 is a diagram showing an example of arrangement of voltage supply lines used in a periodic arrangement.

[0103] Fig.34 1 is a diagram showing an example of arrangement of voltage supply lines adopted in the mirror arrangement.

[0104] Fig.35 It is a diagram for explaining the characteristics of the periodic configuration and the mirror configuration.

[0105] Fig.36 It is a cross-sectional view of a plurality of pixels in the fourteenth embodiment.

[0106] Fig.37 It is a cross-sectional view of a plurality of pixels in the fourteenth embodiment.

[0107] Fig.38 It is a cross-sectional view of a plurality of pixels in the ninth embodiment.

[0108] Fig.39 It is a cross-sectional view of a plurality of pixels in variation 1 of the ninth embodiment.

[0109] Fig.40 It is a cross-sectional view of multiple pixels in the fifteenth implementation scheme.

[0110] Fig.41 It is a cross-sectional view of a plurality of pixels in the tenth embodiment.

[0111] Fig.42 It is a diagram for explaining five layers of metal films of the multilayer wiring layer.

[0112] Fig.43 It is a diagram for explaining five layers of metal films of the multilayer wiring layer.

[0113] Fig.44 It is a diagram for explaining a polysilicon layer.

[0114] Fig.45 FIG. 1 is a diagram showing a modified example of a reflective member formed on a metal film.

[0115] Fig.46 FIG. 1 is a diagram showing a modified example of a reflective member formed on a metal film.

[0116] Fig.47 It is a diagram for explaining the substrate structure of the solid-state imaging element.

[0117] Fig.48 : is a block diagram showing a configuration example of a distance measurement module.

[0118] Fig.49 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0119] Fig.50 1 is a diagram illustrating an example of the installation positions of the vehicle exterior information detection unit and the imaging portion. DETAILED DESCRIPTION

[0120] Hereinafter, embodiments to which the present technology is applicable will be described with reference to the drawings.

[0121] <First embodiment>

[0122] <Configuration Example of Solid-State Imaging Element>

[0123] This technology aims to improve characteristics such as pixel sensitivity through a CAPD sensor with a back-illuminated configuration.

[0124] For example, the present technology can be applied to a solid-state imaging element constituting a distance measurement system that measures a distance by an indirect ToF method, an imaging device including such a solid-state imaging element, and the like.

[0125] For example, the distance measurement system is installed on a vehicle and can be applied to an in-vehicle system that measures the distance to an object outside the vehicle, a gesture recognition system that measures the distance to an object (e.g., a user's hand) and recognizes the user's gesture based on the measurement result, etc. In this case, the result of the gesture recognition can be used, for example, to operate a car navigation system, etc.

[0126] Figure 1 It is a diagram showing a configuration example of one embodiment of a solid-state imaging element (light receiving element) to which the present technology is applied.

[0127] Figure 1 The solid-state imaging element 11 shown is a back-illuminated CAPD sensor, and is provided in an imaging device having a distance measurement function.

[0128] The solid-state imaging element 11 includes a pixel array section 21 formed on a semiconductor substrate (not shown) and a peripheral circuit section integrated on a semiconductor substrate (which is the same as the semiconductor substrate of the pixel array section 21). The peripheral circuit section includes, for example, a vertical drive section 22, a column processing section 23, a horizontal drive section 24, and a system control section 25.

[0129] A signal processing unit 26 and a data storage unit 27 are also provided in the solid-state imaging element 11. In addition, the signal processing unit 26 and the data storage unit 27 may be mounted on the same substrate as the substrate of the solid-state imaging element 11 or may be arranged on a substrate of the imaging device different from the substrate of the solid-state imaging element 11.

[0130] In the pixel array section 21, unit pixels (hereinafter, also simply referred to as pixels) that generate charges corresponding to the amount of received light and output signals corresponding to the charges are arranged two-dimensionally in the row direction and the column direction, that is, in a matrix shape. In other words, the pixel array section 21 includes a plurality of pixels that perform photoelectric conversion on incident light and output signals based on the charges obtained by the photoelectric conversion.

[0131] Here, the row direction refers to the pixel arrangement direction of the pixel row (ie, the horizontal direction), and the column direction refers to the pixel arrangement direction of the pixel column (ie, the vertical direction). The row direction is the horizontal direction in the figure, and the column direction is the vertical direction in the figure.

[0132] In the pixel array section 21, with respect to the matrix-like pixel array, a pixel drive line 28 is wired in the row direction for each pixel row, and two vertical signal lines 29 are wired in the column direction for each pixel column. For example, the pixel drive line 28 transmits a drive signal for performing drive when a signal is read out from a pixel. Figure 1 , the pixel driving line 28 is shown as one wiring, but is not limited to one wiring. One end of the pixel driving line 28 is connected to an output end corresponding to each row of the vertical driving section 22.

[0133] The vertical drive section 22 includes a shift register, an address decoder, etc., and drives each pixel of the pixel array section 21 simultaneously for all pixels, in units of rows, etc. That is, the vertical drive section 22 constitutes a drive section that controls the operation of each pixel of the pixel array section 21 together with the system control section 25 that controls the vertical drive section 22.

[0134] In addition, in the distance measurement of the indirect ToF method, the number of high-speed driven elements (CAPD elements) connected to one control line affects the controllability or driving accuracy of the high-speed drive. There are many cases in which the solid-state imaging element used in the distance measurement of the indirect ToF method is formed as a long pixel array in the horizontal direction. Therefore, in this case, the vertical signal line 29 or other control lines that are long in the vertical direction can be used in the control line of the element to be driven at high speed. In this case, for example, a plurality of pixels arranged in the vertical direction are connected to the vertical signal line 29 or other control lines that are long in the vertical direction, and the pixels are driven by a drive unit, a horizontal drive unit 24, etc. that are separately provided from the vertical drive unit 22 via the vertical signal line 29 or other control lines, that is, the CAPD sensor is driven.

[0135] Signals output from each pixel of the pixel row in response to drive control of the vertical drive section 22 are input to the column processing section 23 through the vertical signal line 29. The column processing section 23 performs predetermined signal processing on the signals output from each pixel through the vertical signal line 29, and temporarily holds the pixel signals after the signal processing.

[0136] Specifically, the column processing section 23 performs noise removal processing, analog-to-digital (AD) conversion processing, and the like as signal processing.

[0137] The horizontal driving section 24 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column processing section 23. According to the selection scanning of the horizontal driving section 24, the unit circuits in the column processing section 23 sequentially output pixel signals after signal processing.

[0138] The system control section 25 includes a timing generator that generates various timing signals and the like, and performs drive control of the vertical drive section 22 , the column processing section 23 , the horizontal drive section 24 and the like based on the various timing signals generated by the timing generator.

[0139] The signal processing section 26 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing based on the pixel signal output from the column processing section 23. For the signal processing in the signal processing section 26, the data storage section 27 temporarily stores data necessary for the processing.

[0140] <Pixel Configuration Example>

[0141] Next, a configuration example of pixels provided in the pixel array section 21 is described. The pixels provided in the pixel array section 21 have, for example, Figure 2 The composition shown.

[0142] Figure 2 A cross section of one pixel 51 provided in the pixel array section 21 is shown, and the pixel 51 receives light incident from the outside, particularly infrared light, performs photoelectric conversion on the light, and outputs a signal corresponding to charges obtained by the photoelectric conversion.

[0143] The pixel 51 includes, for example, a silicon substrate, that is, a substrate 61 (semiconductor layer) which is a P-type semiconductor substrate including a P-type semiconductor region, and an on-chip lens 62 formed on the substrate 61 .

[0144] For example, in the figure, the thickness of the substrate 61 in the longitudinal direction, that is, the thickness of the substrate 61 in the direction perpendicular to the surface of the substrate 61 is less than or equal to 20 μm. In addition, the thickness of the substrate 61 may be greater than or equal to 20 μm, and it is sufficient to set the thickness according to the target characteristics of the solid-state imaging element 11, etc.

[0145] In addition, the substrate 61 includes, for example, a P-Epi substrate having a high resistance with a substrate concentration of 1E+13 order or less, and the resistance (resistivity) of the substrate 61 is, for example, greater than or equal to 500 [Ωcm].

[0146] Here, in the relationship between the substrate concentration of the substrate 61 and the resistance, for example, when the substrate concentration is 6.48E+12 [cm 3 ], the resistance is 2000[Ωcm], and when the substrate concentration is 1.30E+13[cm 3 ], the resistance is 1000[Ωcm], and when the substrate concentration is 2.59E+13[cm 3 ], the resistance is 500[Ωcm], and when the substrate concentration is 1.30E+14[cm 3 ], the resistance is 100[Ωcm], etc.

[0147] In the figure, an upper front surface of the substrate 61, that is, a surface of the substrate 61 on which light from the outside is incident (hereinafter, also referred to as an incident surface) is formed with an on-chip lens 62 that collects incident light from the outside and allows the light to be incident on the substrate 61.

[0148] Furthermore, in the pixel 51 , an inter-pixel light shielding portion 63 - 1 and an inter-pixel light shielding portion 63 - 2 for preventing color mixture between adjacent pixels are formed at the end portions of the pixel 51 on the incident surface of the substrate 61 .

[0149] In this example, light from the outside is incident on the substrate 61 via the on-chip lens 62, but the incident light from the outside does not pass through the on-chip lens 62 or a portion of the substrate 61 and is incident on the region of another pixel disposed adjacent to the pixel 51 of the substrate 61. In other words, light incident on the on-chip lens 62 from the outside and directed to another pixel adjacent to the pixel 51 is blocked by the inter-pixel light shielding portion 63-1 or the inter-pixel light shielding portion 63-2, and is not incident on another adjacent pixel. In the following, in the absence of a need for special distinction, the inter-pixel light shielding portion 63-1 and the inter-pixel light shielding portion 63-2 are also referred to as the inter-pixel light shielding portion 63.

[0150] The solid-state imaging element 11 is a back-illuminated CAPD sensor, and therefore, the incident surface of the substrate 61 is the so-called back surface, and a wiring layer including wirings, etc. is not formed on the back surface. In addition, in a portion of the surface of the substrate 61 on the side opposite to the incident surface, wiring layers such as wirings for driving transistors formed in the pixels 51, wirings for reading out signals from the pixels 51, etc. are stacked.

[0151] On the surface of the substrate 61 opposite to the incident surface, that is, a portion inside the lower surface in the figure, an oxide film 64 and signal extraction portions 65 - 1 and 65 - 2 called taps are formed.

[0152] In this example, the oxide film 64 is formed in the central portion near the surface of the pixel 51 opposite to the incident surface of the substrate 61 , and the signal extraction section 65 - 1 and the signal extraction section 65 - 2 are formed at both ends of the oxide film 64 , respectively.

[0153] Here, the signal extraction section 65-1 includes an N+ semiconductor region 71-1 as an N-type semiconductor region, an N- semiconductor region 72-1 having a lower donor impurity concentration than the N+ semiconductor region 71-1, a P+ semiconductor region 73-1 as a P-type semiconductor region, and a P- semiconductor region 74-1 having a lower acceptor impurity concentration than the P+ semiconductor region 73-1. Here, examples of donor impurities include elements belonging to Group 5 of the periodic table, such as phosphorus (P) or arsenic (As) relative to Si, and examples of acceptor impurities include elements belonging to Group 3 of the periodic table, such as boron (B) relative to Si. An element that is a donor impurity is referred to as a donor element, and an element that is an acceptor impurity is referred to as an acceptor element.

[0154] In other words, the N+ semiconductor region 71-1 is formed in a position adjacent to the right side of the oxide film 64 in the figure in the front inner portion of the surface on the side opposite to the incident surface of the substrate 61. In addition, the N- semiconductor region 72-1 is formed on the upper side of the N+ semiconductor region 71-1 in the figure to cover (surround) the N+ semiconductor region 71-1.

[0155] In addition, the P+ semiconductor region 73-1 is formed in a position adjacent to the right side of the N+ semiconductor region 71-1 in the figure in the front inner portion of the surface on the side opposite to the incident surface of the substrate 61. In addition, the P- semiconductor region 74-1 is formed on the upper side of the P+ semiconductor region 73-1 in the figure to cover (surround) the P+ semiconductor region 73-1.

[0156] In addition, although not shown here, in more detail, when the substrate 61 is observed from a direction perpendicular to the surface of the substrate 61, the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 are formed to surround the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 with the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 as the center.

[0157] Similarly, the signal extraction unit 65-2 includes an N+ semiconductor region 71-2 as an N-type semiconductor region, an N- semiconductor region 72-2 having a donor impurity concentration lower than that of the N+ semiconductor region 71-2, a P+ semiconductor region 73-2 as a P-type semiconductor region, and a P- semiconductor region 74-2 having an acceptor impurity concentration lower than that of the P+ semiconductor region 73-2.

[0158] In other words, the N+ semiconductor region 71-2 is formed in a position adjacent to the left side of the oxide film 64 in the figure in the front inner portion of the surface on the side opposite to the incident surface of the substrate 61. In addition, the N- semiconductor region 72-2 is formed on the upper side of the N+ semiconductor region 71-2 in the figure to cover (surround) the N+ semiconductor region 71-2.

[0159] In addition, the P+ semiconductor region 73-2 is formed in a position adjacent to the left side of the N+ semiconductor region 71-2 in the figure in the front inner portion of the surface on the side opposite to the incident surface of the substrate 61. In addition, the P- semiconductor region 74-2 is formed on the upper side of the P+ semiconductor region 73-2 in the figure to cover (surround) the P+ semiconductor region 73-2.

[0160] In addition, although not shown here, in more detail, when the substrate 61 is observed from a direction perpendicular to the surface of the substrate 61, the N+ semiconductor region 71-2 and the N- semiconductor region 72-2 are formed to surround the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 with the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 as the center.

[0161] Hereinafter, in the case where there is no need to particularly distinguish between the signal extraction section 65 - 1 and the signal extraction section 65 - 2 , the signal extraction section 65 - 1 and the signal extraction section 65 - 2 are also simply referred to as the signal extraction section 65 .

[0162] In addition, in the following text, when there is no need to specifically distinguish between the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2, the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2 are also referred to as the N+ semiconductor region 71, and when there is no need to specifically distinguish between the N- semiconductor region 72-1 and the N- semiconductor region 72-2, the N- semiconductor region 72-1 and the N- semiconductor region 72-2 are also referred to as the N- semiconductor region 72.

[0163] In addition, in the following text, when there is no need to specifically distinguish between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2 are also referred to as the P+ semiconductor region 73, and when there is no need to specifically distinguish between the P- semiconductor region 74-1 and the P- semiconductor region 74-2, the P- semiconductor region 74-1 and the P- semiconductor region 74-2 are also referred to as the P- semiconductor region 74.

[0164] In addition, in the substrate 61, the separation portion 75-1 for separating the region between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 includes an oxide film, etc. Similarly, the separation portion 75-2 for separating the region between the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 includes an oxide film, etc. Hereinafter, in the case where there is no need to particularly distinguish the separation portion 75-1 and the separation portion 75-2, the separation portion 75-1 and the separation portion 75-2 are also simply referred to as the separation portion 75.

[0165] The N+ semiconductor region 71 provided on the substrate 61 is used as a charge detection section for detecting the amount of light incident on the pixel 51 from the outside, that is, the amount of signal carriers generated by the photoelectric conversion of the substrate 61. In addition to the N+ semiconductor region 71, the N- semiconductor region 72 having a low donor impurity concentration can also be regarded as a charge detection section. In addition, the P+ semiconductor region 73 is used as a voltage application section for injecting a plurality of carrier currents into the substrate 61, that is, generating an electric field in the substrate 61 by directly applying a voltage to the substrate 61. In addition, in addition to the P+ semiconductor region 73, the P- semiconductor region 74 having a low acceptor impurity concentration can also be regarded as a voltage application section.

[0166] In pixel 51, a floating diffusion (FD) portion (hereinafter also specifically referred to as FD portion A) serving as a floating diffusion region (not shown) is directly connected to the N+ semiconductor region 71-1, and the FD portion A is also connected to the vertical signal line 29 via an amplifying transistor (not shown) or the like.

[0167] Similarly, another FD portion different from the FD portion A (hereinafter specifically referred to as the FD portion B) is directly connected to the N+ semiconductor region 71-2, and the FD portion B is connected to the vertical signal line 29 via an amplifying transistor (not shown) etc. Here, the FD portion A and the FD portion B are connected to vertical signal lines 29 different from each other.

[0168] For example, in the case of measuring the distance to an object by the indirect ToF method, infrared light is emitted toward the object from an imaging device provided with the solid-state imaging element 11. Then, in the case where the infrared light is reflected on the object and returns to the imaging device as reflected light, the substrate 61 of the solid-state imaging element 11 receives the incident reflected light (infrared light) and performs photoelectric conversion.

[0169] At this time, the vertical drive section 22 drives the pixel 51, and classifies the signal corresponding to the charge obtained by the photoelectric conversion into the FD section A and the FD section B. In addition, as described above, the pixel 51 may be driven not by the vertical drive section 22 but by a separately provided drive section, the horizontal drive section 24, or the like via the vertical signal line 29 or another control line long in the vertical direction.

[0170] For example, at a certain timing, the vertical drive section 22 applies a voltage to the two P+ semiconductor regions 73 via a contact point, etc. Specifically, for example, the vertical drive section 22 applies a voltage of 1.5V to the P+ semiconductor region 73-1 and a voltage of 0V to the P+ semiconductor region 73-2.

[0171] Then, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, holes in the substrate 61 move in the direction of the P+ semiconductor region 73-2, and therefore, electrons move in the direction of the P+ semiconductor region 73-1.

[0172] Therefore, in this state, when infrared light (reflected light) from the outside is incident on the substrate 61 via the on-chip lens 62 and the infrared light undergoes photoelectric conversion in the substrate 61 and is converted into electron and hole pairs, the resulting electrons are guided in the direction of the P+ semiconductor region 73-1 by the electric field between the P+ semiconductor regions 73 and move to the N+ semiconductor region 71-1.

[0173] In this case, the electrons generated by the photoelectric conversion are used as signal carriers for detecting a signal corresponding to the amount of infrared light incident on the pixel 51 , that is, the received light amount of infrared light.

[0174] With this configuration, charges corresponding to electrons moving into the N+ semiconductor region 71 - 1 are accumulated in the N+ semiconductor region 71 - 1 , and the charges are detected by the column processing section 23 via the FD section A, the amplification transistor, the vertical signal line 29 , and the like.

[0175] In other words, the accumulated charge of the N+ semiconductor region 71-1 is transferred to the FD portion A directly connected to the N+ semiconductor region 71-1, and a signal corresponding to the charge transferred to the FD portion A is read out by the column processing portion 23 via the amplification transistor or the vertical signal line 29. Then, processing such as AD conversion processing is performed on the read signal in the column processing portion 23, and the pixel signal obtained by the processing is supplied to the signal processing portion 26.

[0176] The pixel signal is a signal indicating the amount of charge corresponding to the electrons detected by the N+ semiconductor region 71 - 1 , that is, the amount of charge accumulated on the FD portion A. In other words, the pixel signal may be a signal indicating the amount of infrared light received by the pixel 51 .

[0177] Furthermore, at this time, like the N+ semiconductor region 71 - 1 , the pixel signal corresponding to the electrons detected by the N+ semiconductor region 71 - 2 can be appropriately used to measure the distance.

[0178] Furthermore, at the next timing, a voltage is applied to the two P+ semiconductor regions 73 via the contact point or the like by the vertical drive section 22, so that an electric field is generated in a direction opposite to the electric field that has been generated in the substrate 61. Specifically, for example, a voltage of 1.5 V is applied to the P+ semiconductor region 73-2, and a voltage of 0 V is applied to the P+ semiconductor region 73-1.

[0179] With this configuration, an electric field is generated between the two P + semiconductor regions 73 of the substrate 61 , and current flows from the P + semiconductor region 73 - 2 to the P + semiconductor region 73 - 1 .

[0180] In this state, when infrared light (reflected light) from the outside is incident on the substrate 61 via the on-chip lens 62 and the infrared light undergoes photoelectric conversion in the substrate 61 and is converted into electron and hole pairs, the electrons obtained by the electric field between the P+ semiconductor regions 73 are guided in the direction of the P+ semiconductor region 73-2 and move to the N+ semiconductor region 71-2.

[0181] With this configuration, charges corresponding to electrons moving into the N+ semiconductor region 71 - 2 are accumulated in the N+ semiconductor region 71 - 2 , and the charges are detected by the column processing section 23 via the FD section B, the amplification transistor, the vertical signal line 29 , and the like.

[0182] In other words, the accumulated charges of the N+ semiconductor region 71-2 are transferred to the FD portion B directly connected to the N+ semiconductor region 71-2, and a signal corresponding to the charges transferred to the FD portion B is read out by the column processing section 23 via the amplification transistor or the vertical signal line 29. Then, processing such as AD conversion processing is performed on the read signal in the column processing section 23, and the pixel signal obtained by the processing is supplied to the signal processing section 26.

[0183] Furthermore, at this time, like the N+ semiconductor region 71 - 2 , the pixel signal corresponding to the electrons detected by the N+ semiconductor region 71 - 1 can be appropriately used to measure the distance.

[0184] Therefore, when pixel signals obtained by photoelectric conversion of different time periods are obtained in the same pixel 51 , the signal processing section 26 calculates distance information indicating the distance to the object based on the pixel signal, and outputs the distance information to the subsequent stage.

[0185] Therefore, a method of sorting signal carriers into different N+ semiconductor regions 71 and calculating distance information based on signals corresponding to the signal carriers is called an indirect ToF method.

[0186] In addition, here, the following example has been described: the application of voltage relative to the P+ semiconductor region 73 is controlled by the vertical drive section 22, and as described above, the drive section (block) serving as a voltage application control section for controlling the application of voltage relative to the P+ semiconductor region 73 can be set in the solid-state imaging element 11 separately from the vertical drive section 22.

[0187] In addition, when Figure 2 When a portion of the signal extraction portion 65 of the pixel 51 is observed in the top-to-bottom direction (i.e., the direction perpendicular to the surface of the substrate 61), it can be seen that the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71, for example, Figure 3 In addition, Figure 3 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0188] exist Figure 3 In the example shown, an oxide film 64 (not shown) is formed in the central portion of the pixel 51, and a signal extracting section 65 is formed in a portion slightly on the end side from the center of the pixel 51. Specifically, two signal extracting sections 65 are formed in the pixel 51 here.

[0189] Thus, in each signal extraction section 65, the P+ semiconductor region 73 is formed in a rectangular shape at the central position, and the P+ semiconductor region 73 is surrounded by the rectangular N+ semiconductor region 71, more specifically, a rectangular frame shape surrounding the P+ semiconductor region 73. In other words, the N+ semiconductor region 71 is formed to surround the P+ semiconductor region 73.

[0190] Furthermore, in the pixel 51, the on-chip lens 62 is formed so that the infrared light incident from the outside is converged to the central portion of the pixel 51, that is, the portion indicated by the arrow A11. In other words, the infrared light incident on the on-chip lens 62 from the outside is converged by the on-chip lens 62 to the position indicated by the arrow A11, that is, at the center of the pixel 51. Figure 2 middle, Figure 2 The upper side position of oxide film 64.

[0191] Therefore, infrared light is focused to a position between the signal extraction section 65-1 and the signal extraction section 65-2. With this configuration, infrared light can be prevented from being incident on pixels adjacent to the pixel 51 to cause color mixing, and infrared light can also be prevented from being directly incident on the signal extraction section 65.

[0192] For example, in the case where infrared light is directly incident on the signal extraction portion 65, the charge separation efficiency (ie, the contrast between the active well and the deactivated well (Cmod)) or the modulation contrast (Modulation contrast) is reduced.

[0193] Here, the signal extraction section 65 (well) that reads out a signal corresponding to the charge (electrons) obtained by the photoelectric conversion, that is, the signal extraction section 65 that detects the charge obtained by the photoelectric conversion, is also referred to as an active well.

[0194] In contrast, the signal extraction portion 65 (well) that does not substantially read out a signal corresponding to the charge obtained by photoelectric conversion, that is, the signal extraction portion 65 that is not an active well, is also referred to as an inactive well.

[0195] In the above-described example, the signal extraction section 65 that applies a voltage of 1.5 V to the P+ semiconductor region 73 is an active well, and the signal extraction section 65 that applies a voltage of 0 V to the P+ semiconductor region 73 is an inactive well.

[0196] Cmod is an indicator indicating what % of the charges generated by the photoelectric conversion of the incident infrared light can be detected by the N+ semiconductor region 71 of the signal extraction unit 65 as an active well, that is, whether a signal corresponding to the charge is extracted, and indicates the charge separation efficiency.

[0197] Therefore, for example, in the case where infrared light incident from the outside is incident on the region of the inactivation well and photoelectric conversion is performed in the inactivation well, there is a high possibility that electrons, which are signal carriers generated by the photoelectric conversion, move to the N+ semiconductor region 71 in the inactivation well. Then, the charges of a part of the electrons obtained by the photoelectric conversion are not detected by the N+ semiconductor region 71 in the active well, and therefore, Cmod (i.e., charge separation efficiency) is reduced.

[0198] Therefore, in the pixel 51, the infrared light is converged near the central part of the pixel 51 at a position approximately equidistant from the two signal extraction sections 65, and therefore, the probability of the infrared light incident from the outside undergoing photoelectric conversion in the region of the inactivation well is reduced, and the charge separation efficiency can be improved. In addition, in the pixel 51, the modulation contrast can also be improved. In other words, the electrons obtained by photoelectric conversion can be easily conducted to the N+ semiconductor region 71 in the active well.

[0199] According to the solid-state imaging element 11 as described above, the following effects can be obtained.

[0200] In other words, first, the solid-state imaging element 11 is a back-illuminated sensor, and therefore, quantum efficiency (QE)×aperture ratio (fill factor (FF)) can be maximized and the distance measurement characteristics of the solid-state imaging element 11 can be improved.

[0201] For example, Figure 4As shown by arrow W11 in FIG. 1 , a general front-illuminated image sensor has a structure in which the wiring 102 or the wiring 103 is formed on the incident surface side of the PD 101 as a photoelectric conversion unit, to which light from the outside is incident.

[0202] For this reason, for example, as indicated by arrow A21 or arrow A22 , there is a case where part of light obliquely incident on the PD 101 from the outside at a certain angle does not enter the PD 101 due to shielding by the wiring 102 or the wiring 103 .

[0203] In contrast, the backside illumination type image sensor has a structure in which the wiring 105 or the wiring 106 is formed on the surface of the PD 104 as a photoelectric conversion unit opposite to the incident surface to which light is incident from the outside, for example, as indicated by arrow W12.

[0204] Therefore, compared with the front-illuminated image sensor, a sufficient aperture ratio can be ensured. That is, for example, as shown by arrow A23 or arrow A24, light incident on PD 104 at an angle from the outside is incident on PD 104 without being blocked by wiring. With this configuration, pixel sensitivity can be improved by receiving more light.

[0205] Such an improvement effect of pixel sensitivity obtained by the back-illuminated image sensor can also be obtained in the solid-state imaging element 11 which is a back-illuminated CAPD sensor.

[0206] In addition, for example, in the front irradiation type CAPD sensor, as indicated by arrow W13, in the PD 111 as the photoelectric conversion unit, the signal extraction section 112 called a well, more specifically, the P+ semiconductor region or the N+ semiconductor region of the well is formed on the incident surface side where light from the outside is incident. In addition, the front irradiation type CAPD sensor has a structure in which the wiring 113 or the wiring 114 (such as a contact point or metal) connected to the signal extraction section 112 is formed on the incident surface side.

[0207] To this end, for example, there is a situation as shown by arrow A25 or arrow A26, in which a portion of light incident on PD 111 from the outside at a certain angle does not enter PD 111 due to obstruction by wiring 113, etc., and as shown by arrow A27, light incident vertically on PD 111 also does not enter PD 111 due to obstruction by wiring 114.

[0208] In contrast, the back-illuminated CAPD sensor, for example, as indicated by arrow W14, has a structure in which a signal extraction section 116 is formed in a portion of a surface of a PD 115 as a photoelectric conversion unit on the side opposite to the incident surface on which light from the outside is incident. In addition, a wiring 117 or a wiring 118 (e.g., a contact point or metal) connected to the signal extraction section 116 is formed on the surface of the PD 115 on the side opposite to the incident surface.

[0209] Here, PD 115 corresponds to Figure 2 The substrate 61 shown in FIG. 1 and the signal extraction unit 116 correspond to Figure 2 The signal extraction section 65 shown in FIG.

[0210] In a back-illuminated CAPD sensor having such a structure, a sufficient aperture ratio can be ensured compared with a front-illuminated sensor. Therefore, it is possible to maximize quantum efficiency (QE)×aperture ratio (FF) and improve distance measurement characteristics.

[0211] In other words, for example, as shown by arrow A28 or arrow A29, light incident on PD 115 at an angle from the outside is incident on PD 115 without being blocked by wiring. Similarly, as shown by arrow A30, light incident on PD 115 vertically is also incident on PD 115 without being blocked by wiring or the like.

[0212] Therefore, in the back-illuminated CAPD sensor, not only light incident at a certain angle can be received, but also light vertically incident on the PD 115 and reflected on the wiring connected to the signal extraction part (well) in the front-illuminated sensor can be received. With this configuration, pixel sensitivity can be improved by receiving more light. In other words, quantum efficiency (QE) × aperture ratio (FF) can be maximized, thereby improving distance measurement characteristics.

[0213] In particular, when the well is arranged near the center of the pixel rather than at the outer edge of the pixel, in the front-illuminated CAPD sensor, it is impossible to ensure a sufficient aperture ratio and the pixel sensitivity is reduced, but in the solid-state imaging element 11 which is a back-illuminated CAPD sensor, regardless of the arrangement position of the well, a sufficient aperture ratio can be ensured and the pixel sensitivity can be improved.

[0214] In addition, the signal extraction section 65 is formed near the surface of the substrate 61 on the side opposite to the incident surface where infrared light from the outside is incident in the back-illuminated solid-state imaging element 11, so that the occurrence of photoelectric conversion of infrared light in the deactivation well region can be reduced. With this configuration, Cmod (i.e., charge separation efficiency) can be improved.

[0215] Figure 5Pixel cross-sectional views of a front-illuminated CAPD sensor and a back-illuminated CAPD sensor are shown.

[0216] exist Figure 5 In the front-illuminated CAPD sensor on the left side in the figure, the upper side of the substrate 141 is the light incident surface, and a wiring layer 152 including multi-layer wiring, an inter-pixel light shielding portion 153 and an on-chip lens 154 are stacked on the incident surface side of the substrate 141.

[0217] exist Figure 5 In the back-illuminated CAPD sensor on the right, in the figure, a wiring layer 152 including multilayer wiring is formed on the lower side of the substrate 142 opposite to the light incident surface, and an inter-pixel light shielding portion 153 and an on-chip lens 154 are stacked on the upper side of the light incident surface side of the substrate 142.

[0218] In addition, Figure 5 In FIG. 1 , the gray trapezoid shows a region where infrared light is converged by the on-chip lens 154 and thus the light intensity is strong.

[0219] For example, in a front-illuminated CAPD sensor, a region R11 where an inactivation well and an active well exist is provided on the incident surface side of the substrate 141. For this reason, in the presence of many components directly incident on the inactivation well and photoelectric conversion is performed in the region of the inactivation well, signal carriers obtained by photoelectric conversion are not detected by the N+ semiconductor region of the active well.

[0220] In the front irradiation type CAPD sensor, the intensity of infrared light is strong in the region R11 near the incident surface of the substrate 141, and therefore, the probability of performing photoelectric conversion of infrared light in the region R11 increases. That is, the amount of infrared light incident near the inactivation well is large, and therefore, the signal carriers that cannot be detected in the active well increase, and the charge separation efficiency decreases.

[0221] In contrast, in the back-illuminated CAPD sensor, the region R12 where the inactivation well and the active well exist is provided at a position away from the incident surface of the substrate 142, that is, near the surface opposite to the incident surface side. Here, the substrate 142 corresponds to Figure 2 The substrate 61 shown in FIG.

[0222] In this example, region R12 is provided in a portion of the surface of the substrate 142 opposite to the incident surface side, and region R12 is located away from the incident surface, so the intensity of the incident infrared light becomes relatively weak near region R12.

[0223] In areas where the intensity of infrared light is strong, such as near the center of substrate 142 or near the incident surface, signal carriers obtained by photoelectric conversion are guided to the active well by the electric field generated in substrate 142 and detected by the N+ semiconductor region of the active well.

[0224] On the other hand, near the region R12 including the deactivation well, the intensity of the incident infrared light is relatively weak, and therefore, the probability of photoelectric conversion of the infrared light in the region R12 is reduced. That is, the amount of infrared light incident near the deactivation well is small, and therefore, the number of signal carriers (electrons) generated by photoelectric conversion near the deactivation well and moved to the N+ semiconductor region of the deactivation well is reduced, and the charge separation efficiency can be improved. As a result, the distance measurement characteristics can be improved.

[0225] Furthermore, in the back-illuminated solid-state imaging element 11 , thinning of the substrate 61 can be achieved, and therefore, extraction efficiency of electrons (charges) as signal carriers can be improved.

[0226] For example, in a front-illuminated CAPD sensor, the aperture ratio cannot be sufficiently ensured, so Figure 6 As shown by arrow W31 in , in order to ensure higher quantum efficiency and suppress the decrease in quantum efficiency×aperture ratio, the thickness of substrate 171 needs to be increased to a certain extent.

[0227] Then, in the region near the surface of the substrate 171 on the side opposite to the incident surface, for example, a portion of the region R21, the inclination of the potential becomes gentle, and the electric field becomes weak in a direction substantially perpendicular to the substrate 171. In this case, the movement speed of the signal carrier becomes slow, and therefore, the time required to detect the signal carrier in the N+ semiconductor region of the active well after performing photoelectric conversion becomes longer. In addition, in Figure 6 In FIG. 1 , the arrow inside the substrate 171 represents the electric field in the direction perpendicular to the substrate 171 .

[0228] In addition, when the substrate 171 is thick, the moving distance of the signal carrier from the position away from the active well in the substrate 171 to the N+ semiconductor region in the active well becomes longer. Therefore, at the position away from the active well, the time required to detect the signal carrier in the N+ semiconductor region of the active well after performing photoelectric conversion becomes longer.

[0229] Figure 7 The relationship between the position in the thickness direction of the substrate 171 and the moving speed of the signal carrier is shown. The region R21 corresponds to the diffusion current region.

[0230] Therefore, in the case where the substrate 171 becomes thicker, for example, when the driving frequency is high, that is, when the switching between the active state and the inactive state of the well (signal extraction part) is performed at a high speed, the electrons generated in the position away from the active well (such as the region R21) cannot be completely attracted to the N+ semiconductor region of the active well. That is, in the case where the time for which the well is in the active state is short, the electrons (charges) generated in the region R21 and the like cannot be detected in the N+ semiconductor region of the active well, and the extraction efficiency of the electrons is reduced.

[0231] In contrast, in a back-illuminated CAPD sensor, a sufficient aperture ratio can be ensured, so that, for example, Figure 6 As shown by arrow W32 in FIG. 1 , even when substrate 172 is thin, sufficient quantum efficiency × aperture ratio can be ensured. Here, substrate 172 corresponds to Figure 2 The substrate 61 in the figure, and the arrow in the substrate 172 represents the electric field in a direction perpendicular to the substrate 172.

[0232] Figure 8 The relationship between the position in the thickness direction of the substrate 172 and the moving speed of the signal carriers is shown.

[0233] Therefore, in the case where the thickness of the substrate 172 in the direction perpendicular to the substrate 172 is thin, the electric field in the direction substantially perpendicular to the substrate 172 becomes strong, and only the electrons (charges) in the drift current region where the moving speed of the signal carrier is fast are used, and the electrons in the diffusion current region where the moving speed of the signal carrier is slow are not used. Only the electrons (charges) in the drift current region are used, and therefore, the time required to detect the signal carrier in the N+ semiconductor region of the active well after performing the photoelectric conversion becomes shorter. In addition, in the case where the substrate 172 becomes thinner, the moving distance of the signal carrier to the N+ semiconductor region in the active well also becomes shorter.

[0234] Therefore, in the back-illuminated CAPD sensor, even when the driving frequency is high, signal carriers (electrons) generated in various regions within the substrate 172 can be sufficiently attracted in the N+ semiconductor region of the active well, and the extraction efficiency of electrons can be improved.

[0235] Furthermore, according to the thinning of the substrate 172 , sufficient electron extraction efficiency can be ensured even at a higher driving frequency, and high-speed driving resistance can be improved.

[0236] In particular, in the back-illuminated CAPD sensor, a voltage can be directly applied to the substrate 172 (i.e., the substrate 61), so the response speed of switching between the active state and the inactivated state of the well is fast, and the drive can be performed at a high drive frequency. In addition, a voltage can be directly applied to the substrate 61, so the adjustable area in the substrate 61 is widened.

[0237] Furthermore, in the back-illuminated solid-state imaging element 11 (CAPD sensor), a sufficient aperture ratio can be obtained, and therefore, the pixel can be miniaturized, and the miniaturization resistance of the pixel can be improved.

[0238] In addition, the solid-state imaging element 11 is a back-illuminated type sensor, and therefore, the back-end-of-line (BEOL) capacity design can be liberalized, and with this configuration, the degree of freedom in design of the saturation signal amount (Qs) can be improved.

[0239] <Variation 1 of the First Embodiment>

[0240] <Pixel Configuration Example>

[0241] In addition, in the above description, Figure 3 As shown, the case where a part of the signal extraction section 65 in the substrate 61 is a rectangular shape of the N+ semiconductor region 71 and the P+ semiconductor region 73 has been described as an example. However, when viewed from a direction perpendicular to the substrate 61, the shapes of the N+ semiconductor region 71 and the P+ semiconductor region 73 may be any shape.

[0242] Specifically, for example, Fig. 9 As shown, the N+ semiconductor region 71 and the P+ semiconductor region 73 may be circular in shape. Fig. 9 In the same reference numerals as in Figure 3 , and its description will be appropriately omitted.

[0243] Fig. 9 The N+ semiconductor region 71 and the P+ semiconductor region 73 are shown when a part of the signal extraction section 65 in the pixel 51 is viewed from a direction perpendicular to the substrate 61 .

[0244] In this example, an oxide film 64 (not shown) is formed in the central portion of the pixel 51, and a signal extraction section 65 is formed in a portion slightly on the end side from the center of the pixel 51. Specifically, here, two signal extraction sections 65 are formed in the pixel 51.

[0245] Thus, in each signal extraction unit 65 , a circular P+ semiconductor region 73 is formed at the center, and the P+ semiconductor region 73 is surrounded by a circular N+ semiconductor region 71 , more specifically, a ring-shaped N+ semiconductor region 71 , with the P+ semiconductor region 73 as the center.

[0246] Fig.10 is a plan view of the on-chip lens 62 overlapping a portion of the pixel array section 21, including Fig. 9 The pixels 51 of the signal extraction unit 65 shown are two-dimensionally arranged in a matrix shape.

[0247] like Fig.10 As shown, the on-chip lens 62 is formed in pixel units. In other words, a unit area in which one on-chip lens 62 is formed corresponds to one pixel.

[0248] In addition, Figure 2 In the embodiment, the separation portion 75 including an oxide film or the like is arranged between the N+ semiconductor region 71 and the P+ semiconductor region 73 , but the separation portion 75 is not limited thereto.

[0249] <Variation 2 of the First Embodiment>

[0250] <Pixel Configuration Example>

[0251] Fig.11 1 is a plan view showing a modification of the planar shape of the signal extraction section 65 in the pixel 51 .

[0252] Apart from Figure 3 The rectangular shape shown and Figure 7 In addition to the circular shape shown, the planar shape of the signal extraction portion 65 may be, for example, Fig.11 Octagonal shape shown.

[0253] in addition, Fig.11 A plan view is shown in the case where a separation portion 75 including an oxide film or the like is formed between the N+ semiconductor region 71 and the P+ semiconductor region 73 .

[0254] exist Fig.11 In the figure, line A-A' represents the Fig.37 The section line in the figure, line BB' represents the following Fig.36 The section line in .

[0255] <Second Implementation Method>

[0256] <Pixel Configuration Example>

[0257] Furthermore, in the above description, in the signal extraction section 65, the configuration in which the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71 has been described as an example, but the N+ semiconductor region may be surrounded by the P+ semiconductor region.

[0258] In this case, the pixel 51 is, for example, Fig.12 In addition, Fig.12 In the same reference numerals as in Figure 3 , and its description will be appropriately omitted.

[0259] Fig.12 The configuration of the N+ semiconductor region and the P+ semiconductor region when a part of the signal extraction section 65 in the pixel 51 is observed from a direction perpendicular to the substrate 61 is shown.

[0260] In this example, an oxide film 64 (not shown) is formed in the central portion of the pixel 51, a signal extraction section 65-1 is formed in a portion slightly on the upper side in the figure from the center of the pixel 51, and a signal extraction section 65-2 is formed in a portion slightly on the lower side in the figure from the center of the pixel 51. Specifically, in this example, the formation position of the signal extraction section 65 in the pixel 51 is different from that of the pixel 51. Figure 3 The same position in .

[0261] In the signal extraction section 65-1, a Figure 3 The N+ semiconductor region 71-1 shown corresponds to the rectangular N+ semiconductor region 201-1. Thus, the N+ semiconductor region 201-1 is surrounded by the rectangular P+ semiconductor region 202-1. More specifically, Figure 3 The P+ semiconductor region 73-1 shown in FIG. 1 is a P+ semiconductor region 202-1 in the shape of a rectangular frame. That is, the P+ semiconductor region 202-1 is formed to surround the N+ semiconductor region 201-1.

[0262] Similarly, in the signal extraction section 65-2, a signal corresponding to Figure 3 The N+ semiconductor region 71-2 shown in FIG. 201-2 is a rectangular N+ semiconductor region 201-2. Thus, the N+ semiconductor region 201-2 is surrounded by a rectangular P+ semiconductor region 202-2. More specifically, Figure 3 The P+ semiconductor region 73 - 2 shown is a P+ semiconductor region 202 - 2 in the shape of a rectangular frame.

[0263] In addition, hereinafter, when there is no need to particularly distinguish between the N+ semiconductor region 201-1 and the N+ semiconductor region 201-2, the N+ semiconductor region 201-1 and the N+ semiconductor region 201-2 are also referred to as the N+ semiconductor region 201. In addition, hereinafter, when there is no need to particularly distinguish between the P+ semiconductor region 202-1 and the P+ semiconductor region 202-2, the P+ semiconductor region 202-1 and the P+ semiconductor region 202-2 are also referred to as the P+ semiconductor region 202.

[0264] Even if the signal extraction unit 65 has Fig.12 In the case of the configuration shown, Figure 3 As in the case of the illustrated configuration, the N+ semiconductor region 201 functions as a charge detection unit for detecting the amount of signal carriers, and the P+ semiconductor region 202 functions as a voltage application unit for generating an electric field by directly applying a voltage to the substrate 61 .

[0265] <Variation 1 of the Second Embodiment>

[0266] <Pixel Configuration Example>

[0267] In addition, as Fig. 9 Even in the case of a configuration in which the N+ semiconductor region 201 is surrounded by the P+ semiconductor region 202 as in the illustrated example, the shapes of the N+ semiconductor region 201 and the P+ semiconductor region 202 may be any shapes.

[0268] In other words, for example, Fig.13 As shown, the N+ semiconductor region 201 and the P+ semiconductor region 202 may be circular in shape. Fig.13 In the same reference numerals as in Fig.12 , and its description will be appropriately omitted.

[0269] Fig.13 The N+ semiconductor region 201 and the P+ semiconductor region 202 are shown when a part of the signal extraction section 65 in the pixel 51 is observed from a direction perpendicular to the substrate 61 .

[0270] In this example, an oxide film 64 (not shown) is formed in the central portion of the pixel 51, and a signal extraction section 65 is formed in a portion located slightly on the end side of the center of the pixel 51. Specifically, two signal extraction sections 65 are formed in the pixel 51 here.

[0271] Thus, in each signal extraction section 65 , a circular N+ semiconductor region 201 is formed at the center, and the N+ semiconductor region 201 is surrounded by a circular P+ semiconductor region 202 , more specifically, a ring-shaped P+ semiconductor region 202 , with the N+ semiconductor region 201 as the center.

[0272] <Third Implementation Method>

[0273] <Pixel Configuration Example>

[0274] Furthermore, the N+ semiconductor region and the P+ semiconductor region formed in the signal extraction section 65 may be formed in a line shape (rectangular shape).

[0275] In this case, for example, pixel 51 is Fig.14 In addition, Fig.14 In the same reference numerals as in Figure 3 , and its description will be appropriately omitted.

[0276] Fig.14 The configuration of the N+ semiconductor region and the P+ semiconductor when a part of the signal extraction section 65 in the pixel 51 is observed from a direction perpendicular to the substrate 61 is shown.

[0277] In this example, an oxide film 64 (not shown) is formed in the central portion of the pixel 51, and a signal extraction section 65-1 is formed in a portion slightly on the upper side in the figure from the center of the pixel 51. A signal extraction section 65-2 is formed in a portion slightly on the lower side in the figure from the center of the pixel 51. Specifically, in this example, the formation position of the signal extraction section 65 in the pixel 51 is different from that of the signal extraction section 65-2. Figure 3 The same position in .

[0278] In the signal extraction section 65-1, a Figure 3 The P+ semiconductor region 73-1 shown in FIG. 2 is a linear P+ semiconductor region 231 corresponding to the P+ semiconductor region 73-1. Figure 3 The linear N+ semiconductor region 232-1 and the linear N+ semiconductor region 232-2 of the N+ semiconductor region 71-1 are shown so that the P+ semiconductor region 231 is inserted between the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2. That is, the P+ semiconductor region 231 is formed at a position sandwiched between the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2.

[0279] In addition, hereinafter, in the case where there is no need to particularly distinguish between the N+ semiconductor region 232 - 1 and the N+ semiconductor region 232 - 2 , the N+ semiconductor region 232 - 1 and the N+ semiconductor region 232 - 2 are also simply referred to as the N+ semiconductor region 232 .

[0280] exist Figure 3 In the example shown, the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71, but in Fig.14 In the example shown, the P+ semiconductor region 231 is interposed between two N+ semiconductor regions 232 disposed adjacent to each other.

[0281] Similarly, in the signal extraction section 65-2, a signal corresponding to Figure 3 The P+ semiconductor region 233 is a linear P+ semiconductor region 73-2 shown in FIG. Thus, a corresponding P+ semiconductor region 233 is formed around the P+ semiconductor region 233. Figure 3The N+ semiconductor region 71 - 2 shown has a linear N+ semiconductor region 234 - 1 and a linear N+ semiconductor region 234 - 2 , so that the P+ semiconductor region 233 is interposed between the N+ semiconductor region 234 - 1 and the N+ semiconductor region 234 - 2 .

[0282] In addition, hereinafter, in the case where there is no need to particularly distinguish the N+ semiconductor region 234 - 1 and the N+ semiconductor region 234 - 2 , the N+ semiconductor region 234 - 1 and the N+ semiconductor region 234 - 2 are also simply referred to as the N+ semiconductor region 234 .

[0283] exist Fig.14 In the signal extraction unit 65, the P+ semiconductor region 231 and the P+ semiconductor region 233 are used as corresponding Figure 3 The voltage applying portion of the P+ semiconductor region 73 shown in the figure, the N+ semiconductor region 232 and the N+ semiconductor region 234 are used as corresponding Figure 3 The charge detection portion of the N+ semiconductor region 71 shown. In this case, for example, both the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2 are connected to the FD portion A.

[0284] In addition, in the figure, the length in the lateral direction of each of the linear P+ semiconductor region 231, the linear N+ semiconductor region 232, the linear P+ semiconductor region 233 and the linear N+ semiconductor region 234 can be any length, and the regions may not have the same length.

[0285] <Fourth Implementation Plan>

[0286] <Pixel Configuration Example>

[0287] In addition, Fig.14 In the illustrated example, a structure in which the P+ semiconductor region 231 or the P+ semiconductor region 233 is inserted between the N+ semiconductor region 232 or the N+ semiconductor region 234 has been described as an example, but conversely, an N+ semiconductor region may be inserted between P+ semiconductor regions.

[0288] In this case, for example, pixel 51 is Fig.15 In addition, Fig.15 In the same reference numerals as in Figure 3 , and its description will be appropriately omitted.

[0289] Fig.15 The configuration of the N+ semiconductor region and the P+ semiconductor region when a part of the signal extraction section 65 in the pixel 51 is observed from a direction perpendicular to the substrate 61 is shown.

[0290] In this example, an oxide film 64 (not shown) is formed in the central portion of the pixel 51, and a signal extraction section 65 is formed in a portion located slightly on the end side of the center of the pixel 51. In particular, in this example, the formation position of each of the two signal extraction sections 65 in the pixel 51 is different from that of the pixel 51. Figure 3 The same position in .

[0291] In the signal extraction section 65-1, a signal corresponding to Figure 3 The N+ semiconductor region 261 is a linear N+ semiconductor region 71-1. Figure 3 The P+ semiconductor region 73-1 shown has a linear P+ semiconductor region 262-1 and a linear P+ semiconductor region 262-2, so that the N+ semiconductor region 261 is inserted between the P+ semiconductor region 262-1 and the P+ semiconductor region 262-2. That is, the N+ semiconductor region 261 is formed at a position sandwiched by the P+ semiconductor region 262-1 and the P+ semiconductor region 262-2.

[0292] In addition, hereinafter, in the case where there is no need to particularly distinguish the P+ semiconductor region 262 - 1 and the P+ semiconductor region 262 - 2 , the P+ semiconductor region 262 - 1 and the P+ semiconductor region 262 - 2 are also simply referred to as the P+ semiconductor region 262 .

[0293] Similarly, in the signal extraction section 65-2, a signal corresponding to Figure 3 The N+ semiconductor region 71-2 shown in FIG. 263 is a linear N+ semiconductor region. Then, a corresponding Figure 3 The P+ semiconductor region 73 - 2 shown has a linear P+ semiconductor region 264 - 1 and a linear P+ semiconductor region 264 - 2 , so that the N+ semiconductor region 263 is interposed between the P+ semiconductor region 264 - 1 and the P+ semiconductor region 264 - 2 .

[0294] In addition, hereinafter, in the case where there is no need to particularly distinguish the P+ semiconductor region 264 - 1 and the P+ semiconductor region 264 - 2 , the P+ semiconductor region 264 - 1 and the P+ semiconductor region 264 - 2 are also simply referred to as the P+ semiconductor region 264 .

[0295] exist Fig.15 In the signal extraction unit 65, the P+ semiconductor region 262 and the P+ semiconductor region 264 are used as corresponding Figure 3 The voltage applying portion of the P+ semiconductor region 73 shown in the figure, the N+ semiconductor region 261 and the N+ semiconductor region 263 are used as corresponding Figure 3The charge detection portion of the N+ semiconductor region 71 shown. In addition, in the figure, the length of each of the linear N+ semiconductor region 261, the linear P+ semiconductor region 262, the linear N+ semiconductor region 263 and the linear P+ semiconductor region 264 can be any length in the lateral direction, and each region may not have the same length.

[0296] <Fifth Implementation Plan>

[0297] <Pixel Configuration Example>

[0298] Furthermore, in the above description, an example has been described in which two signal extraction sections 65 are each provided in each pixel constituting the pixel array section 21, but the number of signal extraction sections to be provided in a pixel may be one, or may be three or more.

[0299] For example, in the case where a signal extraction section is formed in a pixel, for example, a pixel portion such as Fig.16 In addition, Fig.16 In the same reference numerals as in Figure 3 , and its description will be appropriately omitted.

[0300] Fig.16 There is shown the configuration of the N+ semiconductor region and the P+ semiconductor region when a part of the signal extraction section in a part of the pixels provided in the pixel array section 21 is viewed from a direction perpendicular to the substrate.

[0301] In this example, a pixel 51 provided in the pixel array section 21 , pixels 291 - 1 to 291 - 3 adjacent to the pixel 51 are shown, and one signal extraction section is formed in each pixel.

[0302] In other words, in the pixel 51, a signal extraction section 65 is formed in the central portion of the pixel 51. Thus, in the signal extraction section 65, a circular P+ semiconductor region 301 is formed at the center position, and the P+ semiconductor region 301 is surrounded by a circular N+ semiconductor region 302, more specifically, a ring-shaped N+ semiconductor region 302, with the P+ semiconductor region 301 as the center.

[0303] Here, the P+ semiconductor region 301 corresponds to Figure 3 The P+ semiconductor region 73 shown in FIG. 1 is used as a voltage applying section. In addition, the N+ semiconductor region 302 corresponds to Figure 3 The N+ semiconductor region 71 shown in FIG. 1 is used as a charge detection section. In addition, the P+ semiconductor region 301 or the N+ semiconductor region 302 may be in any shape.

[0304] In addition, pixels 291 - 1 to 291 - 3 around the pixel 51 have a structure similar to that of the pixel 51 .

[0305] In other words, for example, a signal extraction section 303 is formed in the central portion of the pixel 291-1. Thus, in the signal extraction section 303, a circular P+ semiconductor region 304 is formed at the center, and the P+ semiconductor region 304 is surrounded by a circular N+ semiconductor region 305, more specifically, a ring-shaped N+ semiconductor region 305, with the P+ semiconductor region 304 as the center.

[0306] The P+ semiconductor region 304 and the N+ semiconductor region 305 correspond to the P+ semiconductor region 301 and the N+ semiconductor region 302 , respectively.

[0307] In addition, hereinafter, in the case where there is no need to particularly distinguish the pixel 291 - 1 to the pixel 291 - 3 , the pixel 291 - 1 to the pixel 291 - 3 are also simply referred to as the pixel 291 .

[0308] Therefore, in the case where one signal extraction portion (well) is formed in each pixel, several pixels adjacent to each other are used when measuring the distance to an object by the indirect ToF method, and distance information is calculated based on pixel signals obtained with respect to the pixels.

[0309] For example, focusing on pixel 51, when the signal extraction unit 65 of pixel 51 is an active well, for example, each pixel is driven so that the signal extraction units 303 of several pixels 291 adjacent to pixel 51 including pixel 291-1 become inactive wells.

[0310] As an example, for example, the pixel 291 - 1 , the pixel 291 - 3 , and so on are driven so that the signal extraction portions of the pixels adjacent to the pixel 51 on the left, right, top, and bottom in the figure become inactivation wells.

[0311] Thereafter, when the voltage to be applied is switched so that the signal extraction section 65 of the pixel 51 becomes an inactive well, at this time, the signal extraction sections 303 of several pixels 291 adjacent to the pixel 51 including the pixel 291 - 1 become active wells.

[0312] Then, the distance information is calculated based on the pixel signal read out from the signal extraction section 65 when the signal extraction section 65 is an active well and the pixel signal read out from the signal extraction section 303 when the signal extraction section 303 is an active well.

[0313] Therefore, even in the case where the number of signal extraction sections (wells) provided in a pixel is one, the distance can be measured according to the indirect ToF method by using pixels adjacent to each other.

[0314] <Sixth Implementation Plan>

[0315] <Pixel Configuration Example>

[0316] In addition, as described above, three or more signal extraction sections (wells) may be provided in each pixel.

[0317] For example, when four signal extraction units (wells) are provided in a pixel, each pixel of the pixel array unit 21 is as follows: Fig.17 In addition, Fig.17 In the same reference numerals as in Fig.16 , and its description will be appropriately omitted.

[0318] Fig.17 There is shown the arrangement of the N+ semiconductor region and the P+ semiconductor region when a part of the signal extraction section of a part of the pixels provided in the pixel array section 21 is viewed from a direction perpendicular to the substrate.

[0319] Fig.17 The cross-sectional view along the line CC' shown in FIG. Fig.36 .

[0320] In this example, the pixel 51 and the pixel 291 provided in the pixel array section 21 are shown, and four signal extraction sections are formed in each pixel.

[0321] In other words, in pixel 51, signal extraction unit 331-1, signal extraction unit 331-2, signal extraction unit 331-3 and signal extraction unit 331-4 are formed at positions between the center of pixel 51 and the ends of pixel 51, that is, at the lower left side, the upper left side, the upper right side and the lower right side in the figure of the center of pixel 51.

[0322] The signal extraction units 331-1 to 331-4 correspond to Fig.16 The signal extraction unit 65 is shown.

[0323] For example, in the signal extraction section 331 - 1 , a circular P+ semiconductor region 341 is formed at the center, and the P+ semiconductor region 341 is surrounded by a circular N+ semiconductor region 342 , more specifically, a ring-shaped N+ semiconductor region 342 , with the P+ semiconductor region 341 as the center.

[0324] Here, the P+ semiconductor region 341 corresponds to Fig.16 The P+ semiconductor region 301 shown in FIG. 1 is used as a voltage applying section. In addition, the N+ semiconductor region 342 corresponds to Fig.16 The N+ semiconductor region 302 shown in FIG. 3 is formed by a P+ semiconductor region 341 or a N+ semiconductor region 342, and serves as a charge detection portion. In addition, the P+ semiconductor region 341 or the N+ semiconductor region 342 may be in any shape.

[0325] In addition, the signal extraction units 331-2 to 331-4 also have a configuration similar to the signal extraction unit 331-1, and each includes a P+ semiconductor region used as a voltage application unit and an N+ semiconductor region used as a charge detection unit. In addition, the pixel 291 formed around the pixel 51 has a structure similar to that of the pixel 51.

[0326] Furthermore, hereinafter, in the case where there is no need to particularly distinguish the signal extraction sections 331 - 1 to 331 - 4 , the signal extraction sections 331 - 1 to 331 - 4 are also simply referred to as the signal extraction section 331 .

[0327] Therefore, in the case where four signal extraction sections are provided in each pixel, for example, when measuring a distance according to the indirect ToF method, distance information is calculated by using the four signal extraction sections in the pixel.

[0328] As an example, focusing on the pixel 51, for example, in a state where the signal extraction section 331-1 and the signal extraction section 331-3 are active wells, the pixel 51 is driven so that the signal extraction section 331-2 and the signal extraction section 331-4 become inactive wells.

[0329] Thereafter, the voltage to be applied to each signal extraction section 331 is switched. That is, the pixel 51 is driven so that the signal extraction section 331-1 and the signal extraction section 331-3 become inactive wells, and the signal extraction section 331-2 and the signal extraction section 331-4 become active wells.

[0330] Therefore, in a state where the signal extraction unit 331-1 and the signal extraction unit 331-3 are active wells, the distance information is calculated based on the pixel signals read out from the signal extraction unit 331-1 and the signal extraction unit 331-3 and the pixel signals read out from the signal extraction unit 331-2 and the signal extraction unit 331-4 in a state where the signal extraction unit 331-2 and the signal extraction unit 331-4 are active wells.

[0331] <Seventh Implementation Plan>

[0332] <Pixel Configuration Example>

[0333] Furthermore, the signal extraction section (well) may be shared between pixels adjacent to each other in the pixel array section 21 .

[0334] In this case, each pixel of the pixel array section 21 is, for example, Fig.18 In addition, Fig.18 In the same reference numerals as in Fig.16 , and its description will be appropriately omitted.

[0335] Fig.18The configuration of the N+ semiconductor region and the P+ semiconductor region when a part of the signal extraction section of a part of the pixels provided in the pixel array section 21 is viewed from a direction perpendicular to the substrate is shown.

[0336] In this example, the pixel 51 and the pixel 291 provided in the pixel array section 21 are shown, and two signal extraction sections are formed in each pixel.

[0337] For example, in the pixel 51 , the signal extraction section 371 is formed at the upper end of the pixel 51 in the figure, and the signal extraction section 372 is formed at the lower end of the pixel 51 in the figure.

[0338] The signal extraction section 371 is shared between the pixel 51 and the pixel 291-1. That is, the signal extraction section 371 is used as a well for the pixel 51 and also as a well for the pixel 291-1. In addition, the signal extraction section 372 is shared between the pixel 51 and a pixel (not shown) adjacent to the lower side of the pixel 51 in the figure.

[0339] In the signal extraction unit 371, a signal is formed at the center position. Fig.14 The P+ semiconductor region 231 shown in FIG. 3 is a linear P+ semiconductor region 381 corresponding to the P+ semiconductor region 231. Fig.14 The linear N+ semiconductor region 382-1 and the linear N+ semiconductor region 382-2 of the N+ semiconductor region 232 shown in the figure make the P+ semiconductor region 381 inserted between the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2 at the upper and lower positions of the P+ semiconductor region 381.

[0340] Specifically, in this example, the P+ semiconductor region 381 is formed in the boundary portion between the pixel 51 and the pixel 291-1. In addition, the N+ semiconductor region 382-1 is formed in the region within the pixel 51, and the N+ semiconductor region 382-2 is formed in the region within the pixel 291-1.

[0341] Here, the P+ semiconductor region 381 is used as a voltage applying portion, and the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2 are used as charge detecting portions. In addition, hereinafter, in the case where there is no need to particularly distinguish between the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2, the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2 are also referred to as the N+ semiconductor region 382.

[0342] In addition, the P+ semiconductor region 381 or the N+ semiconductor region 382 may be of any shape. In addition, the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2 may be connected to the same FD portion, or may be connected to different FD portions from each other.

[0343] In the signal extraction section 372 , a P+ semiconductor region 383 , an N+ semiconductor region 384 - 1 , and an N+ semiconductor region 384 - 2 are formed in a line shape.

[0344] The P+ semiconductor region 383, the N+ semiconductor region 384-1, and the N+ semiconductor region 384-2 correspond to the P+ semiconductor region 381, the N+ semiconductor region 382-1, and the N+ semiconductor region 382-2, respectively, and have similar configurations, similar shapes, and similar functions. In addition, hereinafter, in the case where there is no need to particularly distinguish between the N+ semiconductor region 384-1 and the N+ semiconductor region 384-2, the N+ semiconductor region 384-1 and the N+ semiconductor region 384-2 are also referred to as the N+ semiconductor region 384.

[0345] As described above, even in the case where the signal extraction section (well) is shared between adjacent pixels, it is possible to obtain the signal by using a method similar to Figure 3 The operation of the illustrated example measures distance via an indirect ToF method.

[0346] like Fig.18 As shown, in the case where the signal extraction portion is shared between pixels, for example, the distance between a pair of P+ semiconductor regions for generating an electric field (i.e., current) becomes longer, such as the distance between the P+ semiconductor region 381 and the P+ semiconductor region 383. In other words, the signal extraction portion is shared between pixels, and therefore, the distance between the P+ semiconductor regions can be maximized.

[0347] With this configuration, it is difficult for current to flow between the P+ semiconductor regions, so the power consumption of the pixel can be reduced and it is also advantageous for miniaturization of the pixel.

[0348] In addition, here, an example in which one signal extraction unit is shared between two adjacent pixels has been described, but one signal extraction unit may be shared among three or more adjacent pixels. In addition, in the case where the signal extraction unit is shared among two or more adjacent pixels, in the signal extraction unit, only the charge detection unit for detecting signal carriers may be shared, or only the voltage application unit for generating an electric field may be shared.

[0349] <Eighth Implementation Plan>

[0350] <Pixel Configuration Example>

[0351] Furthermore, an on-chip lens or an inter-pixel light shielding portion provided in each pixel such as the pixel 51 of the pixel array section 21 may not be particularly provided.

[0352] Specifically, for example, the pixel 51 may be Fig.19 In addition, Fig.19 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0353] Except that the on-chip lens 62 is not provided, Fig.19 The structure of the pixel 51 shown is similar to Figure 2 The pixel 51 shown has the same structure.

[0354] exist Fig.19 In the pixel 51 shown, the on-chip lens 62 is not provided on the incident surface side of the substrate 61, and therefore, the attenuation of infrared light incident on the substrate 61 from the outside can be further reduced. With this configuration, the amount of infrared light received by the substrate 61 can be increased, and the sensitivity of the pixel 51 can be improved.

[0355] <Variation 1 of the Eighth Implementation Method>

[0356] <Pixel Configuration Example>

[0357] In addition, the structure of the pixel 51 may be, for example, Fig. 20 In addition, Fig. 20 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0358] Except that the inter-pixel light shielding portion 63-1 and the inter-pixel light shielding portion 63-2 are not provided, Fig. 20 The structure of the pixel 51 shown in FIG. Figure 2 The configuration of the pixel 51 shown in FIG. 5 is the same.

[0359] exist Fig. 20 In the example shown, the inter-pixel shading portion 63 is not arranged on the incident surface side of the substrate 61, so the effect of suppressing color mixing is reduced, but the infrared light blocked by the inter-pixel shading portion 63 is also incident on the substrate 61, so the sensitivity of the pixel 51 can be improved.

[0360] Furthermore, it is obvious that both the on-chip lens 62 and the inter-pixel light shielding portion 63 may not be provided in the pixel 51 .

[0361] <Variation 2 of the Eighth Implementation Method>

[0362] <Pixel Configuration Example>

[0363] In addition, for example, Fig.21 As shown, the thickness of the on-chip lens in the optical axis direction can be optimized. Fig.21 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0364] In addition to providing an on-chip lens 411 instead of the on-chip lens 62, Fig.21 The structure of the pixel 51 shown is similar to Figure 2 The pixel 51 shown has the same structure.

[0365] exist Fig.21 In the pixel 51 shown in FIG. 1 , the on-chip lens 411 is formed on the incident surface side of the substrate 61, that is, on the upper side in the figure. Figure 2 Compared with the on-chip lens 62 shown, the thickness of the on-chip lens 411 in the optical axis direction, that is, the thickness of the on-chip lens 411 in the longitudinal direction in the figure is thinner.

[0366] Generally, as the on-chip lens provided on the front surface of the substrate 61 becomes thicker, convergence of light incident on the on-chip lens is facilitated. However, as the on-chip lens 411 becomes thinner, the transmittance becomes higher and the sensitivity of the pixel 51 can be improved, it is sufficient to appropriately set the thickness of the on-chip lens 411 according to the thickness of the substrate 61, the position where the infrared light converges, etc.

[0367] <Ninth Implementation Plan>

[0368] <Pixel Configuration Example>

[0369] Furthermore, a separation region for improving separation characteristics between adjacent pixels and for suppressing color mixture may be provided between pixels formed in the pixel array section 21 .

[0370] In this case, the pixel 51 is, for example, Fig. 22 In addition, Fig. 22 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0371] In addition to providing the separation region 441-1 and the separation region 441-2 in the substrate 61, Fig. 22 The structure of the pixel 51 shown is similar to Figure 2 The pixel 51 shown has the same structure.

[0372] exist Fig. 22 In the pixel 51 shown, a separation region 441-1 and a separation region 441-2 that penetrate at least a portion of the substrate 61 are formed in the substrate 61 through a light shielding film or the like in a boundary portion between the pixel 51 and another pixel adjacent to the pixel 51, that is, the left and right ends in the figure of the pixel 51. In addition, hereinafter, in the case where there is no need to particularly distinguish the separation region 441-1 and the separation region 441-2, the separation region 441-1 and the separation region 441-2 are also simply referred to as the separation region 441.

[0373] For example, when forming the separation region 441, a longitudinal groove (groove) is formed in a downward direction (in a direction perpendicular to the surface of the substrate 61) from the incident surface side of the substrate 61, that is, the surface on the upper side in the figure of the substrate 61, and a light shielding film is formed by burying in the groove portion, thereby forming the separation region 441. The separation region 441 serves as a pixel separation region configured to shield infrared light incident on the substrate 61 from the incident surface and directed toward another pixel adjacent to the pixel 51.

[0374] The buried separation region 441 is formed as described above, and therefore, the separation characteristics of infrared light between pixels can be improved and the occurrence of color mixture can be suppressed.

[0375] <Variation 1 of the Ninth Implementation Method>

[0376] <Pixel Configuration Example>

[0377] Furthermore, in the case where a buried separation region is formed in the pixel 51, for example, Fig.23 As shown, a separation area 471-1 and a separation area 471-2 that penetrate the entire substrate 61 may be provided. Fig.23 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0378] In addition to providing the separation region 471-1 and the separation region 471-2 in the substrate 61, Fig.23 The structure of the pixel 51 shown is similar to Figure 2 The structure of the pixel 51 shown is the same. Fig.23 In the pixel 51 shown, a separation area 471-1 and a separation area 471-2 are provided instead of Fig. 22 Separation region 441 of pixel 51 is shown.

[0379] exist Fig.23 In the pixel 51 shown, the separation region 471-1 and the separation region 471-2 that penetrate the entire substrate 61 are formed in the substrate 61 through a light shielding film or the like in the boundary portion between the pixel 51 and another pixel adjacent to the pixel 51, that is, the right end and the left end in the figure of the pixel 51. In addition, hereinafter, in the case where there is no need to particularly distinguish the separation region 471-1 and the separation region 471-2, the separation region 471-1 and the separation region 471-2 are also simply referred to as the separation region 471.

[0380] For example, when forming the separation region 471, a longitudinal groove (groove) is formed in the upward direction in the figure from the surface of the substrate 61 on the side opposite to the incident surface side, that is, the surface on the lower side in the figure of the substrate 61. At this time, such a groove is formed so as to reach the incident surface of the substrate 61, that is, to penetrate the substrate 61. Then, a light shielding film is formed by embedding in the groove portion formed as described above, thereby forming the separation region 471.

[0381] According to the buried separation region 471, the separation characteristics of infrared light between pixels can be improved, and the occurrence of color mixture can be suppressed.

[0382] <Tenth Implementation Plan>

[0383] <Pixel Configuration Example>

[0384] Furthermore, the thickness of the substrate on which the signal extraction section 65 is formed may be set according to various characteristics of pixels and the like.

[0385] So, for example, Fig.24 As shown, the substrate 501 constituting the pixel 51 may be Figure 2 The substrate 61 shown is thick. Fig.24 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0386] In addition to providing substrate 501 instead of substrate 61, Fig.24 The structure of the pixel 51 shown is similar to Figure 2 The pixel 51 shown has the same structure.

[0387] That is, in Fig.24 In the illustrated pixel 51, an on-chip lens 62 and an inter-pixel light shielding portion 63 are formed on the incident surface side of the substrate 501. In addition, an oxide film 64, a signal extracting portion 65, and a separating portion 75 are formed near the front surface of the substrate 501 on the side opposite to the incident surface side.

[0388] Substrate 501, for example, includes a P-type semiconductor substrate having a thickness greater than or equal to 20 μm, substrate 501 and substrate 61 differ from each other only in the thickness of the substrate, and the positions at which oxide film 64, signal extraction unit 65 and separation unit 75 are formed are the same positions between substrate 501 and substrate 61.

[0389] Furthermore, the film thickness and the like of various layers (films) appropriately formed on the incident surface side and the like of the substrate 501 or the substrate 61 may be optimized according to the characteristics of the pixel 51 and the like.

[0390] <Eleventh Implementation Plan>

[0391] <Pixel Configuration Example>

[0392] Furthermore, in the above description, an example has been described in which the substrate constituting the pixel 51 includes a P-type semiconductor substrate, but for example, Fig.25 As shown, the substrate may include an N-type semiconductor substrate. Fig.25 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0393] In addition to providing a substrate 531 instead of the substrate 61, Fig.25 The structure of the pixel 51 shown is similar to Figure 2 The pixel 51 shown has the same structure.

[0394] exist Fig.25 In the illustrated pixel 51 , for example, an on-chip lens 62 and an inter-pixel light shielding portion 63 are formed on the incident surface side of a substrate 531 which is a silicon substrate (ie, an N-type semiconductor substrate including an N-type semiconductor region).

[0395] In addition, the oxide film 64, the signal extraction portion 65, and the separation portion 75 are formed near the front surface of the substrate 531 on the side opposite to the incident surface side. The positions where the oxide film 64, the signal extraction portion 65, and the separation portion 75 are formed are the same positions between the substrate 531 and the substrate 61, and the configuration of the signal extraction portion 65 is the same as that of the substrate 531 and the substrate 61.

[0396] The thickness of the substrate 531 in the longitudinal direction in the figure, that is, the thickness of the substrate 531 in the direction perpendicular to the surface of the substrate 531 , for example, is less than or equal to 20 μm.

[0397] In addition, the substrate 531 includes, for example, an N-Epi substrate with a high resistance whose substrate concentration is less than or equal to 1E+13 order, and the resistance (resistivity) of the substrate 531 is, for example, greater than or equal to 500 [Ωcm]. With this configuration, the power consumption of the pixel 51 can be reduced.

[0398] Here, in the relationship between the substrate concentration of the substrate 531 and the resistance, for example, when the substrate concentration is 2.15E+12 [cm 3 ], the resistance is 2000[Ωcm], and when the substrate concentration is 4.30E+12[cm 3 ], the resistance is 1000[Ωcm], and when the substrate concentration is 8.61E+12[cm 3 ], the resistance is 500[Ωcm], and when the substrate concentration is 4.32E+13[cm 3 ], the resistance is 100[Ωcm], etc.

[0399] Therefore, even in the case where the substrate 531 of the pixel 51 is configured as an N-type semiconductor substrate, according to Figure 2 The operation of the illustrated example can also achieve similar effects.

[0400] <Twelfth Implementation Plan>

[0401] <Pixel Configuration Example>

[0402] In addition, as referenced Fig.24 As in the described example, the thickness of the N-type semiconductor substrate may be set according to various characteristics of the pixel.

[0403] So, for example, Fig.26 As shown, the substrate 561 constituting the pixel 51 may be Fig.25 The substrate 531 shown is thick. Fig.26 In the same reference numerals as in Fig.25 , and its description will be appropriately omitted.

[0404] In addition to providing a substrate 561 instead of the substrate 531, Fig.26 The structure of the pixel 51 shown is similar to Fig.25 The pixel 51 shown has the same structure.

[0405] In other words, Fig.26 In the illustrated pixel 51, an on-chip lens 62 and an inter-pixel light shielding portion 63 are formed on the incident surface side of a substrate 561. In addition, an oxide film 64, a signal extracting portion 65, and a separating portion 75 are formed near the front surface of the substrate 561 on the side opposite to the incident surface side.

[0406] Substrate 561, for example, includes an N-type semiconductor substrate having a thickness greater than or equal to 20 μm, substrate 561 and substrate 531 differ from each other only in the thickness of the substrate, and the positions at which oxide film 64, signal extraction unit 65 and separation unit 75 are formed are the same positions between substrate 561 and substrate 531.

[0407] <Thirteenth Implementation Plan>

[0408] <Pixel Configuration Example>

[0409] In addition, for example, a bias voltage is applied to the incident surface side of the substrate 61 , and therefore, in the substrate 61 , an electric field in a direction perpendicular to the surface of the substrate 61 (hereinafter, also referred to as a Z direction) can be enhanced.

[0410] In this case, for example, pixel 51 is Fig. 27 In addition, Fig. 27 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0411] exist Fig. 27middle, Figure 2 The pixel 51 shown in is shown in the portion indicated by arrow W61 , and the arrow in the substrate 61 of the pixel 51 indicates the electric field intensity in the Z direction in the substrate 61 .

[0412] In contrast, the configuration of the pixel 51 when a bias (voltage) is applied to the incident surface is shown in the portion indicated by arrow W62. Figure 2 The pixel 51 shown has basically the same configuration, but includes a configuration for applying a voltage to the incident surface side of the substrate 61. The arrow in the substrate 61 of the pixel 51 indicates the electric field intensity in the Z direction in the substrate 61, that is, the intensity of the bias to be applied.

[0413] In the example indicated by arrow W62 , the P+ semiconductor region 601 is formed right below the incident surface of the substrate 61 (ie, the upper surface of the substrate 61 in the figure).

[0414] For example, a film having a positive fixed charge is stacked, and the P+ semiconductor region 601 is set to cover the entire incident surface, and the incident surface side of the substrate 61 is set to a hole accumulation state, thereby suppressing the occurrence of dark current. In addition, it is obvious that the P+ semiconductor region 601 is also formed on Figure 2 In the substrate 61 shown.

[0415] Here, a bias is applied by applying a voltage less than or equal to 0V to the P+ semiconductor region 601 within the pixel array or from the outside, thereby enhancing the electric field in the Z direction. In other words, it is known that the thickness of the arrow shown in the substrate 61 is also greater than the thickness of the example of the arrow W61, and the electric field in the Z direction becomes stronger. Therefore, a voltage is applied to the incident surface side of the substrate 61, that is, the P+ semiconductor region 601, and therefore, the electric field in the Z direction is enhanced, and the extraction efficiency of electrons in the signal extraction unit 65 can be improved.

[0416] In addition, the configuration for applying a voltage to the incident surface side of the substrate 61 is not limited to the configuration of providing the P+ semiconductor region 601, and may be any other configuration. For example, by forming a transparent electrode film by stacking between the incident surface of the substrate 61 and the on-chip lens 62, and applying a voltage to the transparent electrode film, a bias voltage can be applied.

[0417] <Fourteenth Implementation Plan>

[0418] <Pixel Configuration Example>

[0419] Furthermore, in order to improve the sensitivity of the pixel 51 with respect to infrared rays, a reflective member having a large area may be provided on the surface of the substrate 61 on the side opposite to the incident surface.

[0420] In this case, the pixel 51 is, for example, Fig.28 In addition, Fig.28 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0421] In addition to providing a reflective member 631 on the surface of the substrate 61 opposite to the incident surface, Fig.28 The structure of the pixel 51 shown is similar to Figure 2 The pixel 51 shown has the same structure.

[0422] exist Fig.28 In the example shown, a reflective member 631 that reflects infrared light is provided to cover the entire surface of the substrate 61 on the side opposite to the incident surface.

[0423] The reflective member 631 may be any reflective member as long as it has a high infrared light reflectivity. For example, a metal such as copper or aluminum provided in a multilayer wiring layer stacked on the surface of the substrate 61 opposite to the incident surface may be used as the reflective member 631, or a reflective structure such as polysilicon or an oxide film may be formed on the surface of the substrate 61 opposite to the incident surface and may be used as the reflective member 631.

[0424] Therefore, the reflective member 631 is provided in the pixel 51, and thus the infrared light that is incident on the substrate 61 from the incident surface via the on-chip lens 62 and passes through the substrate 61 without undergoing photoelectric conversion in the substrate 61 can be incident on the substrate 61 again by being reflected on the reflective member 631. With this configuration, the amount of infrared light to be photoelectrically converted in the substrate 61 is increased, and therefore, the quantum efficiency (QE), that is, the sensitivity of the pixel 51 with respect to infrared light can be improved.

[0425] <Fifteenth Implementation Plan>

[0426] <Pixel Configuration Example>

[0427] Furthermore, a P-well region including a P-type semiconductor region may be provided in the substrate 61 of the pixel 51 instead of the oxide film 64 .

[0428] In this case, the pixel 51 is, for example, Fig.29 In addition, Fig.29 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0429] In addition to providing a P-well region 671, a separation portion 672-1, and a separation portion 672-2 instead of the oxide film 64, Fig.29 The structure of the pixel 51 shown is similar to Figure 2The pixel 51 shown has the same structure.

[0430] exist Fig.29 In the example shown, a P-well region 671 including a P-type semiconductor region is formed in the substrate 61 in the central portion of the surface side opposite to the incident surface, that is, the inner side of the lower surface in the figure. In addition, a separation portion 672-1 for separating the P-well region 671 from the N+ semiconductor region 71-1 is formed between the P-well region 671 and the N+ semiconductor region 71-1 by an oxide film or the like. Similarly, a separation portion 672-2 for separating the P-well region 671 from the N+ semiconductor region 71-2 is formed between the P-well region 671 and the N+ semiconductor region 71-2 by an oxide film or the like. Fig.29 In the pixel 51 shown, in the figure, the P-semiconductor region 74 is a region wider than the N-semiconductor region 72 in the upward direction.

[0431] <Sixteenth Implementation Plan>

[0432] <Pixel Configuration Example>

[0433] In addition, in addition to the oxide film 64 in the substrate 61 of the pixel 51 , a P well region including a P type semiconductor region may be provided.

[0434] In this case, the pixel 51 is, for example, Fig.30 In addition, Fig.30 In the same reference numerals as in Figure 2 , and its description will be appropriately omitted.

[0435] In addition to the newly set P-well region 701, Fig.30 The structure of the pixel 51 shown is similar to Figure 2 The structure of the pixel 51 shown is the same. Fig.30 In the illustrated example, a P-well region 701 including a P-type semiconductor region is formed on the upper side in the figure of the oxide film 64 in the substrate 61 .

[0436] As described above, according to the present technology, the CAPD sensor is configured as a back-illuminated type sensor, and therefore, characteristics such as pixel sensitivity can be improved.

[0437] <Equivalent Circuit Configuration Example of Pixel>

[0438] Fig.31 An equivalent circuit of the pixel 51 is shown.

[0439] With respect to the signal extraction section 65 - 1 including the N+ semiconductor region 71 - 1 , the P+ semiconductor region 73 - 1 , etc., the pixel 51 includes a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplification transistor 724A, and a selection transistor 725A.

[0440] In addition, with respect to the signal extraction section 65 - 2 including the N+ semiconductor region 71 - 2 , the P+ semiconductor region 73 - 2 , and the like, the pixel 51 includes a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplification transistor 724B, and a selection transistor 725B.

[0441] The vertical drive section 22 applies a predetermined voltage MIX0 (first voltage) to the P+ semiconductor region 73-1, and applies a predetermined voltage MIX1 (second voltage) to the P+ semiconductor region 73-2. In the above example, one of the voltages MIX0 and MIX1 is 1.5 V, and the other is 0 V. The P+ semiconductor regions 73-1 and 73-2 are voltage applying sections to which the first voltage or the second voltage is applied.

[0442] The N+ semiconductor regions 71 - 1 and 71 - 2 are charge detection portions that detect charges generated by performing photoelectric conversion on light incident on the substrate 61 and accumulate the charges.

[0443] When the drive signal TRG to be supplied to the gate is in an activated state, the transfer transistor 721A is in an on state, and thus the charges accumulated in the N+ semiconductor region 71-1 are transferred to the FD 722A. When the drive signal TRG to be supplied to the gate is in an activated state, the transfer transistor 721B is in an on state, and thus the charges accumulated in the N+ semiconductor region 71-2 are transferred to the FD 722B.

[0444] FD 722A temporarily holds the charge supplied from the N+ semiconductor region 71-1. FD 722B temporarily holds the charge supplied from the N+ semiconductor region 71-2. FD 722A corresponds to reference Figure 2 The FD section A of the description, FD 722B corresponds to the FD section B.

[0445] When the drive signal RST to be supplied to the gate is in an activated state, the reset transistor 723A is in an on state, and thus the potential of the FD 722A is reset to a predetermined level (reset voltage VDD). When the drive signal RST to be supplied to the gate is in an activated state, the reset transistor 723B is in an on state, and thus the potential of the FD 722B is reset to a predetermined level (reset voltage VDD). In addition, when the reset transistors 723A and 723B are in an activated state, the transfer transistors 721A and 721B are also in an activated state at the same time.

[0446] In the amplifier transistor 724A, the source is connected to the vertical signal line 29A via the selection transistor 725A, and thus the amplifier transistor 724A constitutes a source follower circuit together with the load MOS of the constant current source circuit section 726A connected to one end of the vertical signal line 29A. In the amplifier transistor 724B, the source is connected to the vertical signal line 29B via the selection transistor 725B, and thus the amplifier transistor 724B constitutes a source follower circuit together with the load MOS of the constant current source circuit section 726B connected to one end of the vertical signal line 29B.

[0447] The selection transistor 725A is connected between the source of the amplification transistor 724A and the vertical signal line 29A. When the selection signal SEL supplied to the gate is in an active state, the selection transistor 725A is in an on state and outputs the pixel signal output from the amplification transistor 724A to the vertical signal line 29A.

[0448] The selection transistor 725B is connected between the source of the amplification transistor 724B and the vertical signal line 29B. When the selection signal SEL supplied to the gate is in an active state, the selection transistor 725B is in an on state and outputs the pixel signal output from the amplification transistor 724B to the vertical signal line 29B.

[0449] For example, transfer transistors 721A and 721B, reset transistors 723A and 723B, amplification transistors 724A and 724B, and selection transistors 725A and 725B of the pixel 51 are controlled by the vertical drive section 22 .

[0450] <Other equivalent circuit configuration examples of pixels>

[0451] Fig.32 Another equivalent circuit of the pixel 51 is shown.

[0452] exist Fig.32 In the same reference numerals as in Fig.31 , and its description will be appropriately omitted.

[0453] Fig.32 The equivalent circuit in corresponds to Fig.31 The equivalent circuit in FIG. 1 is formed by adding an additional capacitor 727 and a switching transistor 728 that controls the connection thereof to the signal extracting sections 65 - 1 and 65 - 2 .

[0454] Specifically, the additional capacitance 727A is connected between the transfer transistor 721A and the FD 722A via the switch transistor 728A, and the additional capacitance 727B is connected between the transfer transistor 721B and the FD 722B via the switch transistor 728B.

[0455] When the drive signal FDG to be supplied to the gate is in an activated state, the switch transistor 728A is in an on state, thereby connecting the additional capacitor 727A to the FD 722A. When the drive signal FDG to be supplied to the gate is in an activated state, the switch transistor 728B is in an on state, thereby connecting the additional capacitor 727B to the FD 722B.

[0456] For example, under high illuminance with a large amount of incident light, the vertical drive section 22 sets the switching transistors 728A and 728B to an active state, and connects the FD 722A and the additional capacitor 727A together, and connects the FD 722B and the additional capacitor 727B together. With this configuration, more charge can be accumulated under high illuminance.

[0457] On the other hand, under low illumination with a small amount of incident light, the vertical drive section 22 sets the switching transistors 728A and 728B to an inactive state, and disconnects the additional capacitances 727A and 727B from the FDs 722A and 722B, respectively.

[0458] as Fig.31 As in the equivalent circuit in , the additional capacitor 727 can be omitted, but the additional capacitor 727 is provided and used differently depending on the amount of incident light, so that a high dynamic range can be ensured.

[0459] <Configuration Example of Voltage Supply Line>

[0460] Next, refer to Figure 33 to Figure 35 The configuration of a voltage supply line for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73 - 1 and 73 - 2 as a voltage applying portion of the signal extracting portion 65 of each pixel 51 is described.

[0461] In addition, Fig.33 and Fig.34 In Fig. 9 Although the circular structure shown in FIG. 1 is described as the structure of the signal extraction unit 65 of each pixel 51 , it is obvious that other structures may be adopted.

[0462] Fig.33 A is a plan view showing a first configuration example of voltage supply lines.

[0463] In the first arrangement example, with respect to a plurality of pixels 51 two-dimensionally arranged in a matrix shape, the voltage supply line 741 - 1 or 741 - 2 is wired along the vertical direction between two pixels adjacent in the horizontal direction (on the boundary).

[0464] The voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1 which is one of the two signal extraction sections 65 in the pixel 51. The voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65-2 which is the other of the two signal extraction sections 65 in the pixel 51.

[0465] In the first arrangement example, two voltage supply lines 741 - 1 and 741 - 2 are arranged for two columns of pixels, and therefore, in the pixel array section 21 , the number of voltage supply lines 741 to be arranged is substantially the same as the number of columns of pixels 51 .

[0466] Fig.33 B is a plan view showing a second configuration example of the voltage supply line.

[0467] In the second arrangement example, two voltage supply lines 741 - 1 and 741 - 2 are wired in the vertical direction with respect to one pixel column of a plurality of pixels 51 arranged two-dimensionally in a matrix shape.

[0468] The voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1, which is one of the two signal extraction units 65 within the pixel 51, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2, which is the other of the two signal extraction units 65 within the pixel 51.

[0469] In the second arrangement example, two voltage supply lines 741 - 1 and 741 - 2 are wired for one pixel column, and thus four voltage supply lines 741 are arranged for two columns of pixels. In the pixel array section 21 , the number of voltage supply lines 741 to be arranged is approximately twice the number of columns of pixels 51 .

[0470] Fig.33 The two configuration examples A and B are periodic configurations, in which the configuration of connecting the voltage supply line 741-1 to the P+ semiconductor region 73-1 of the signal extraction section 65-1 and connecting the voltage supply line 741-2 to the P+ semiconductor region 73-2 of the signal extraction section 65-2 is repeated periodically relative to the pixels arranged in the vertical direction.

[0471] exist Fig.33 In the first configuration example of A, the number of voltage supply lines 741 - 1 and 741 - 2 to be wired with respect to the pixel array section 21 can be reduced.

[0472] exist Fig.33In the second configuration example of B, the number of voltage supply lines 741-1 and 741-2 to be wired increases compared to the first configuration example, but the number of signal extraction units 65 to be connected to one voltage supply line 741 becomes 1 / 2, so the load on the wiring can be reduced, and the second configuration example is effective under high-speed driving or when the total number of pixels of the pixel array unit 21 is large.

[0473] Fig.34 A is a plan view showing a third configuration example of the voltage supply lines.

[0474] The third configuration example is an example in which two voltage supply lines 741-1 and 741-2 are configured with respect to two columns of pixels, as shown in FIG. Fig.33 As in the first configuration example of A.

[0475] The third configuration example Fig.33 The first configuration example of A is different in that the connection destinations of the signal extraction sections 65 - 1 and 65 - 2 are different in two pixels arranged in the vertical direction.

[0476] Specifically, for example, in a certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65-2, and in the pixels 51 above and below the certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1.

[0477] Fig.34 B is a plan view showing a fourth configuration example of the voltage supply lines.

[0478] The fourth configuration example is an example in which two voltage supply lines 741-1 and 741-2 are configured with respect to two columns of pixels. Fig.33 As in the second configuration example of B.

[0479] The fourth configuration example is Fig.33 The second configuration example of B is different in that the connection destinations of the signal extraction sections 65 - 1 and 65 - 2 are different in two pixels arranged in the vertical direction.

[0480] Specifically, for example, in a certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65-2, and in the pixels 51 above and below the certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal extraction section 65-1.

[0481] exist Fig.34 In the third configuration example of A, the number of voltage supply lines 741 - 1 and 741 - 2 to be wired with respect to the pixel array section 21 can be reduced.

[0482] exist Fig.34 In the fourth configuration example of B, the number of voltage supply lines 741-1 and 741-2 to be wired increases compared to the third configuration example, but the number of signal extraction units 65 to be connected to one voltage supply line 741 becomes 1 / 2, so the load on the wiring can be reduced, and the fourth configuration example is effective under high-speed driving or when the total number of pixels of the pixel array unit 21 is large.

[0483] Fig.34 The two configuration examples of A and B are mirror configurations in which connection destinations of two pixels adjacent to each other vertically (in the vertical direction) are mirror-inverted.

[0484] like Fig.35 As shown in A, in the periodic configuration, the voltages to be applied to the two adjacent signal extraction units 65 inserted in the pixel boundary are different voltages, so that charge exchange occurs between adjacent pixels. For this reason, the transfer efficiency of the charge is more excellent in the periodic configuration than in the mirror configuration, but the color mixing characteristics of the adjacent pixels are worse in the periodic configuration than in the mirror configuration.

[0485] On the other hand, Fig.35 As shown in FIG. 1B, in the mirror configuration, the voltage to be applied to the two adjacent signal extraction units 65 inserted in the pixel boundary is the same voltage, so the charge exchange between the adjacent pixels is suppressed. For this reason, the transfer efficiency of the charge is worse in the mirror configuration than in the periodic configuration, but the color mixing characteristics of the adjacent pixels are better in the mirror configuration than in the periodic configuration.

[0486] <Cross-sectional Structure of Multiple Pixels of Fourteenth Embodiment>

[0487] exist Figure 2In the cross-sectional structure of the pixel shown in FIG. 1 , one of the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 surrounding the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 with the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 as the center is not shown. In addition, the multilayer wiring layer formed on the surface of the substrate 61 opposite to the incident surface is not shown.

[0488] Therefore, in the following, in the above-mentioned several embodiments, a cross-sectional view of multiple adjacent pixels is shown, in which the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 region 74-1 or the multi-layer wiring layer around the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 are not shown.

[0489] first, Fig.36 and Fig.37 Shows Fig.28 A cross-sectional view of a plurality of pixels according to the fourteenth embodiment is shown in FIG.

[0490] Fig.28 The fourteenth embodiment shown is a configuration of a pixel including a reflective member 631 having a large area on the side of the substrate 61 opposite to the incident surface.

[0491] Fig.36 Corresponds to Fig.11 The cross-section of line B-B' in Fig.37 Corresponds to Fig.11 In addition, Fig.17 The cross-sectional view of the line C-C' in can also be shown as Fig.36 shown.

[0492] like Fig.36 As shown, in each pixel 51 , an oxide film 64 is formed in the central portion, and a signal extraction portion 65 - 1 and a signal extraction portion 65 - 2 are formed on both sides of the oxide film 64 , respectively.

[0493] In the signal extraction section 65-1, the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 are formed to surround the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 with the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 as the center. The P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are in contact with the multilayer wiring layer 811. The P- semiconductor region 74-1 is arranged on the upper side of the P+ semiconductor region 73-1 (on the on-chip lens 62 side) to cover the P+ semiconductor region 73-1, and the N- semiconductor region 72-1 is arranged on the upper side of the N+ semiconductor region 71-1 (on the on-chip lens 62 side) to cover the N+ semiconductor region 71-1. In other words, the P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are arranged on the multilayer wiring layer 811 side in the substrate 61, and the N- semiconductor region 72-1 and the P- semiconductor region 74-1 are arranged on the on-chip lens 62 side in the substrate 61. In addition, a separation portion 75-1 for separating the N+ semiconductor region 71-1 from the P+ semiconductor region 73-1 is formed between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 by an oxide film or the like.

[0494] In the signal extraction section 65-2, the N+ semiconductor region 71-2 and the N- semiconductor region 72-2 are formed to surround the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 with the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 as the center. The P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are in contact with the multilayer wiring layer 811. The P- semiconductor region 74-2 is arranged on the upper side of the P+ semiconductor region 73-2 (on the on-chip lens 62 side) to cover the P+ semiconductor region 73-2, and the N- semiconductor region 72-2 is arranged on the upper side of the N+ semiconductor region 71-2 (on the on-chip lens 62 side) to cover the N+ semiconductor region 71-2. In other words, the P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are arranged on the multilayer wiring layer 811 side in the substrate 61, and the N- semiconductor region 72-2 and the P- semiconductor region 74-2 are arranged on the on-chip lens 62 side in the substrate 61. In addition, a separation portion 75-2 for separating the N+ semiconductor region 71-2 from the P+ semiconductor region 73-2 is formed between the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 by an oxide film or the like.

[0495] The oxide film 64 is also formed between the N+ semiconductor region 71 - 1 of the signal extraction portion 65 - 1 of a predetermined pixel 51 and the N+ semiconductor region 71 - 2 of the signal extraction portion 65 - 2 of a pixel 51 adjacent to the predetermined pixel 51 , which is a boundary region between adjacent pixels 51 .

[0496] A film having a positive fixed charge is stacked, and therefore a P+ semiconductor region 601 covering the entire light incident surface is formed on the light incident surface side of the substrate 61 ( Fig.36 and Fig.37 On the boundary surface of the upper surface in the figure.

[0497] like Fig.36 As shown, when the on-chip lens 62 formed on the light incident surface side of the substrate 61 in each pixel is divided into a flat portion 821 having a uniform and flat thickness in the entire region within the pixel and a curved portion 822 having a different thickness depending on the position within the pixel in the height direction, the thickness of the flat portion 821 is formed to be smaller than the thickness of the curved portion 822. As the thickness of the flat portion 821 becomes thinner, oblique incident light is easily reflected on the inter-pixel light shielding portion 63, and therefore, the thickness of the flat portion 821 is formed to be thin, and therefore, oblique incident light can also be combined within the substrate 61. In addition, as the thickness of the curved portion 822 becomes thicker, the incident light can be converged to the center of the pixel.

[0498] The multilayer wiring layer 811 is formed on the surface of the substrate 61 on the side opposite to the light incident surface side where the on-chip lens 62 is formed in each pixel. In other words, the substrate 61 as a semiconductor layer is arranged between the on-chip lens 62 and the multilayer wiring layer 811. The multilayer wiring layer 811 includes five layers of metal films M1 to M5 and an interlayer insulating film 812 therebetween. Fig.36 In the embodiment, among the five metal films M1 to M5 of the multilayer wiring layer 811, the outermost metal film M5 is located in an unseen position and is therefore not shown, but is used as a Fig.36 Cross-section diagram of cross-section diagram in different directions Fig.37 Shown in.

[0499] like Fig.37 As shown in FIG. 1 , the pixel transistor Tr is formed in a pixel boundary region of a boundary surface portion of the multilayer wiring layer 811 with respect to the substrate 61. The pixel transistor Tr is Fig.31 and Fig.32 Any one of the transfer transistor 721, the reset transistor 723, the amplification transistor 724 and the selection transistor 725 shown.

[0500] Among the five metal films M1 to M5 of the multilayer wiring layer 811, the metal film M1 closest to the substrate 61 includes a power supply line 813 for supplying a power supply voltage, a voltage applying wiring 814 for supplying a predetermined voltage to the P+ semiconductor region 73-1 or 73-2, and a reflective member 815 as a member for reflecting incident light. Fig.36In the metal film M1, wirings other than the power supply line 813 and the voltage application wiring 814 are shown as reflective members 815, but some reference numerals are omitted to prevent the drawing from being complicated. The reflective member 815 is a dummy wiring provided to reflect incident light and corresponds to Fig.28 The reflective member 631 shown. In the plan view, the reflective member 815 is arranged on the lower side of the N+ semiconductor regions 71-1 and 71-2 so as to overlap with the N+ semiconductor regions 71-1 and 71-2 as the charge detection section. In addition, in the metal film M1, the charge accumulated in the N+ semiconductor region 71 is transferred to the FD 722, and thus, a charge extraction wiring ( Fig.36 not shown).

[0501] Furthermore, in this example, the reflective member 815 (reflective member 631 ) and the charge extraction wiring are arranged on the same layer of the metal film M1 , but are not necessarily limited to being arranged on the same layer.

[0502] In the metal film M2 of the second layer from the substrate 61 side, for example, a voltage application wiring 816 connected to the voltage application wiring 814 of the metal film M1, a control line 817 for transmitting a drive signal TRG, a drive signal RST, a selection signal SEL, a drive signal FDG, etc., a ground line, etc. are formed. In addition, in the metal film M2, an FD 722B or an additional capacitor 727A is formed.

[0503] In the metal film M3 of the third layer from the substrate 61 side, for example, the vertical signal line 29 , the shielding wiring, and the like are formed.

[0504] In the metal films M4 and M5 of the fourth and fifth layers from the substrate 61 side, for example, voltage supply lines 741-1 and 741-2 ( Fig.33 and Fig.34 ).

[0505] In addition, reference will be made later Fig.42 and Fig.43 The planar arrangement of the five metal films M1 to M5 of the multilayer wiring layer 811 will be described.

[0506] <Cross-sectional Structure of Multiple Pixels of Ninth Embodiment>

[0507] Fig.38 is a graph showing the relative position of multiple pixels. Fig. 22 1 is a cross-sectional view of a pixel structure of the ninth embodiment shown in which the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 or the multi-layer wiring layer are not omitted.

[0508] Fig. 22 The ninth embodiment shown is a configuration of a pixel including a separation area 441 on a pixel boundary in a substrate 61, wherein an elongated groove (groove) is formed to a predetermined depth from the back side (incident surface) side of the substrate 61, and a light shielding film is buried in the groove.

[0509] The other structures including the signal extraction units 65-1 and 65-2, the five metal films M1 to M5 of the multilayer wiring layer 811, etc. are similar to those of Fig.36 The composition shown in .

[0510] <Cross-sectional Structure of Multiple Pixels in Modification 1 of Ninth Implementation>

[0511] Fig.39 is a graph showing the relative position of multiple pixels. Fig.23 1 is a cross-sectional view of a pixel structure of Modification 1 of the ninth embodiment, in which the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 or the multi-layer wiring layer are not omitted.

[0512] Fig.23 The modification 1 of the ninth embodiment shown is a configuration in which a pixel includes a separation region 471 penetrating the entire substrate 61 at a pixel boundary in the substrate 61 .

[0513] The other structures including the signal extraction units 65-1 and 65-2, the five metal films M1 to M5 of the multilayer wiring layer 811, etc. are similar to those of Fig.36 The composition shown in .

[0514] <Cross-sectional structure of multiple pixels according to the fifteenth embodiment>

[0515] Fig.40 is a graph showing the relative position of multiple pixels. Fig.29 1 is a cross-sectional view of a pixel structure of the fifteenth embodiment shown in which the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 or the multi-layer wiring layer are not omitted.

[0516] Fig.29 The fifteenth embodiment shown is a configuration including a P-well region 671 in the central portion of the surface side opposite to the incident surface (i.e., the inner side of the lower surface in the figure) of the substrate 61. In addition, a separation portion 672-1 is formed between the P-well region 671 and the N+ semiconductor region 71-1 by an oxide film or the like. Similarly, a separation portion 672-2 is formed between the P-well region 671 and the N+ semiconductor region 71-2 by an oxide film or the like. The P-well region 671 is also formed on the pixel boundary of the surface on the lower side of the substrate 61.

[0517] The other structures including the signal extraction units 65-1 and 65-2, the five metal films M1 to M5 of the multilayer wiring layer 811, etc. are similar to those of Fig.36 The composition shown in .

[0518] <Cross-sectional Structure of Multiple Pixels of the Tenth Embodiment>

[0519] Fig.41 is a graph showing the relative position of multiple pixels. Fig.24 1 is a cross-sectional view of a pixel structure of the tenth embodiment shown in which the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 or the multi-layer wiring layer are not omitted.

[0520] Fig.24 The tenth embodiment shown is a pixel configuration in which a substrate 501 having a large substrate thickness is provided instead of the substrate 61 .

[0521] The other structures including the signal extraction units 65-1 and 65-2, the five metal films M1 to M5 of the multilayer wiring layer 811, etc. are similar to those of Fig.36 The composition shown in .

[0522] <Example of Planar Configuration of Five-Layer Metal Films M1 to M5>

[0523] Next, we will refer to Fig.42 and Fig.43 illustrate Figure 36 to Figure 41 An example of a planar arrangement of five metal films M1 to M5 of the multilayer wiring layer 811 shown in FIG.

[0524] Fig.42 A shows a planar arrangement example of the metal film M1 as the first layer among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0525] Fig.42 B shows a planar arrangement example of the metal film M2 as the second layer among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0526] Fig.42 C shows a planar arrangement example of a metal film M3 as the third layer among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0527] Fig.43 A shows a planar arrangement example of a metal film M4 as a fourth layer among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0528] Fig.43 B in FIG. 8 shows a planar arrangement example of the metal film M5 as the fifth layer among the five metal films M1 to M5 of the multilayer wiring layer 811 .

[0529] In addition, Fig.42 A~C and Fig.43 A and B, the area of ​​pixel 51 and Fig.11 The regions of the signal extraction sections 65 - 1 and 65 - 2 having an octagonal shape shown in FIG. 8 are indicated by dotted lines.

[0530] exist Fig.42 A~C and Fig.43 In A and B, the longitudinal direction in the figure is the vertical direction of the pixel array section 21, and the lateral direction in the figure is the horizontal direction of the pixel array section 21.

[0531] like Fig.42 As shown in A, a reflective member 631 that reflects infrared light is formed in the metal film M1 that is the first layer of the multilayer wiring layer 811. In the region of the pixel 51, two reflective members 631 are formed with respect to each of the signal extraction sections 65-1 and 65-2, and the two reflective members 631 of the signal extraction section 65-1 and the two reflective members 631 of the signal extraction section 65-1 are formed symmetrically with respect to the vertical direction.

[0532] In addition, the pixel transistor wiring region 831 is arranged between the reflective members 631 of the adjacent pixels 51 in the horizontal direction. Wiring for connecting the pixel transistor Tr of the transfer transistor 721, the reset transistor 723, the amplification transistor 724, or the selection transistor 725 is formed in the pixel transistor wiring region 831. The wiring for the pixel transistor Tr is also formed symmetrically with respect to the vertical direction with the middle line (not shown) of the two signal extraction sections 65-1 and 65-2 as a reference.

[0533] In addition, wirings such as ground line 832, power supply line 833 and ground line 834 are formed in the vertical direction between reflective members 631 of adjacent pixels 51. Each wiring is also formed symmetrically with respect to the vertical direction with respect to the middle line of the two signal extracting sections 65-1 and 65-2.

[0534] Therefore, the metal film M1 of the first layer is symmetrically arranged in the area on the signal extraction section 65-1 side and the area on the signal extraction section 65-2 side within the pixel, so that the wiring load is uniformly adjusted by the signal extraction sections 65-1 and 65-2. With this arrangement, the driving variation in the signal extraction sections 65-1 and 65-2 is reduced.

[0535] In the metal film M1 of the first layer, a reflective member 631 having a large area is formed on the lower side of the signal extraction sections 65-1 and 65-2 formed on the substrate 61, and therefore, infrared light that is incident on the substrate 61 via the on-chip lens 62 and is transmitted through the substrate 61 without undergoing photoelectric conversion within the substrate 61 can be incident on the substrate 61 again by being reflected on the reflective member 631. With this configuration, the amount of infrared light to be photoelectrically converted within the substrate 61 is increased, and therefore, the quantum efficiency (QE), that is, the sensitivity of the pixel 51 with respect to infrared light can be improved.

[0536] like Fig.42 As shown in FIG. 1B, in the metal film M2 as the second layer of the multilayer wiring layer 811, a control line region 851 in which control lines 841 to 844 for transmitting a predetermined signal in the horizontal direction are formed is arranged at a position between the signal extraction sections 65-1 and 65-2. The control lines 841 to 844 are, for example, lines for transmitting a drive signal TRG, a drive signal RST, a selection signal SEL, or a drive signal FDG.

[0537] In the second layer of the metal film M2, the control line region 851 is arranged in the boundary region of the adjacent pixels 51, and the influence on each signal extraction section 65-1 and 65-2 becomes uniform, so the driving variation in the signal extraction sections 65-1 and 65-2 can be reduced.

[0538] In addition, the capacitor region 852 in which the FD 722B or the additional capacitor 727A is formed is arranged in a predetermined region different from the control line region 851. In the capacitor region 852, the pattern of the metal film M2 is formed in the shape of comb teeth, thereby constituting the FD 722B or the additional capacitor 727A.

[0539] The FD 722B or the additional capacitor 727A is disposed on the metal film M2 as the second layer. Therefore, the pattern of the FD 722B or the additional capacitor 727A can be freely arranged according to the wiring capacitance required in design, thereby improving the degree of freedom in design.

[0540] like Fig.42 As shown in FIG. 3 , in the metal film M3 as the third layer of the multilayer wiring layer 811, at least a vertical signal line 29 for transmitting a pixel signal output from each pixel 51 to the column processing unit 23 is formed. In order to improve the readout speed of the pixel signal, three or more vertical signal lines 29 may be configured for one pixel column. In addition, a shielding wiring may be configured in addition to the vertical signal line 29, so that the coupling capacitance may be reduced.

[0541] In the fourth and fifth metal films M4 and M5 of the multilayer wiring layer 811 , voltage supply lines 741 - 1 and 741 - 2 for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73 - 1 and 73 - 2 of the signal extraction section 65 of each pixel 51 are formed.

[0542] Fig.43 The metal film M4 and the metal film M5 shown in A and B show the metal film M4 and the metal film M5 shown in A and B. Fig.33 An example of the case where the voltage supply line 741 is the first configuration example shown in A.

[0543] The voltage supply line 741-1 of the metal film M4 is connected to the voltage applying wiring 814 (for example, Fig.36 ), and the voltage applying wiring 814 is connected to the P+ semiconductor region 73-1 of the signal extracting section 65-1 of the pixel 51. Similarly, the voltage supply line 741-2 of the metal film M4 is connected to the voltage applying wiring 814 of the metal film M1 via the metal films M3 and M2 (for example, Fig.36 ), and the voltage applying wiring 814 is connected to the P+ semiconductor region 73-2 of the signal extraction section 65-2 of the pixel 51.

[0544] The voltage supply lines 741-1 and 741-2 of the metal film M5 are connected to the driving section of the peripheral circuit section of the periphery of the pixel array section 21. The voltage supply line 741-1 of the metal film M4 and the voltage supply line 741-1 of the metal film M5 are connected to each other through a through hole (not shown) or the like at a predetermined position in which the two metal films exist in a plane region. A predetermined voltage (voltage MIX0 or MIX1) from the driving section of the peripheral circuit section of the periphery of the pixel array section 21 is transmitted to the voltage supply lines 741-1 and 741-2 of the metal film M5, supplied to the voltage supply lines 741-1 and 741-2 of the metal film M4 through the transmission, and supplied from the voltage supply lines 741-1 and 741-2 to the voltage applying wiring 814 of the metal film M1 via the metal films M3 and M2.

[0545] As described above, the pixel 51 may be driven only by the vertical drive section 22 , and may be controlled by the horizontal drive section 24 or by a drive section provided independently of the vertical drive section 22 and the horizontal drive section 24 via a control line wired in the vertical direction.

[0546] The solid-state imaging element 11 is configured as a back-illuminated CAPD sensor, and therefore, for example, Fig.43As shown in A and B of FIG. 5 , the voltage supply lines 741-1 and 741-2 for applying a predetermined voltage MIX0 or MIX1 to the signal extraction unit 65 of each pixel 51 can be wired in the vertical direction, for example, and the wiring width and layout of the drive wiring can be freely designed. In addition, it can also be wiring suitable for high-speed driving or wiring considering load reduction.

[0547] <Planar Configuration Example of Pixel Transistors>

[0548] Fig.44 Among them Fig.42 A is a plan view showing that the first layer metal film M1 and the polysilicon layer formed on the metal film M1 and the like of the gate electrode of the pixel transistor Tr formed on the metal film M1 overlap with each other.

[0549] Fig.44 A is one of Fig.44 The metal film M1 in C and Fig.44 A plan view of the polysilicon layers in B overlapping each other, Fig.44 B is a plan view of polysilicon only, Fig.44 C is a plan view of only the metal film M1. Fig.44 The plan view of the metal film M1 in C is Fig.42 The same plan view as shown in A, but with hatching omitted.

[0550] As reference Fig.42 As shown in FIG. 8A , the pixel transistor wiring region 831 is formed between the reflective members 631 of each pixel.

[0551] like Fig.44 As shown in FIG. 8B , for example, a pixel transistor Tr corresponding to each of the signal extraction sections 65 - 1 and 65 - 2 is arranged in the pixel transistor wiring region 831 .

[0552] exist Fig.44 In B, with the middle line (not shown) of the two signal extraction parts 65-1 and 65-2 as a reference, the reset transistor, the transfer transistors 721A and 721B, the switch transistors 728A and 728B, the selection transistors 725A and 725B and the gates 723A and 723B of the amplification transistors 724A and 724B are formed from the side close to the middle line.

[0553] Taking the middle line (not shown) of the two signal extraction sections 65-1 as a reference, Fig.44 The wiring lines connecting the pixel transistors Tr of the metal film M1 shown in C are connected symmetrically with respect to the vertical direction.

[0554] Therefore, the plurality of pixel transistors Tr in the pixel transistor wiring region 831 are symmetrically arranged in the region on the signal extraction section 65-1 side and the region on the signal extraction section 65-2 side, and therefore, driving variations of the signal extraction sections 65-1 and 65-2 can be reduced.

[0555] <Modification of Reflection Member 631>

[0556] Next, we will refer to Fig.45 and Fig.46 A modification example of the reflective member 631 formed on the metal film M1 will be described.

[0557] In the above example, if Fig.42 As shown in FIG. 8A , a reflective member 631 having a large area is arranged in a region around the signal extraction section 65 in the pixel 51 .

[0558] In contrast, for example, Fig.45 As shown in A, the reflective member 631 can be configured in a lattice pattern. Therefore, the reflective member 631 is formed in a lattice pattern, and therefore, the pattern anisotropy can be eliminated, and the XY anisotropy of the reflective ability can be reduced. In other words, the reflective member 631 is formed in a lattice pattern, and therefore, the reflection of the incident light on the biased partial area can be reduced, and isotropic reflection can be easily performed, and therefore, the distance measurement accuracy is improved.

[0559] In addition, if Fig.45 As shown in B, the reflective member 631 can be configured in a stripe pattern, for example. Therefore, the reflective member 631 is formed in a stripe pattern, and therefore, the pattern of the reflective member 631 can also be used as a wiring capacitor, and therefore, a configuration in which the dynamic range is extended to the maximum value can be achieved.

[0560] also, Fig.45 B is an example of a stripe-like shape in the vertical direction, but may be a stripe-like shape in the horizontal direction.

[0561] In addition, if Fig.45 As shown in C, the reflective member 631 can be configured, for example, only in the pixel center area, more specifically, only between the two signal extraction units 65. Therefore, the reflective member 631 is formed in the pixel center area and is not formed on the pixel end, so that the component reflected on the adjacent pixel can be suppressed in the case of oblique light incidence, and a configuration focusing on suppressing color mixing can be achieved while obtaining a sensitivity improvement effect relative to the reflective member 631 in the pixel center area.

[0562] In addition, if Fig.46As shown in FIG. 1A , a portion of the reflective member 631 is arranged in a comb-tooth pattern, for example, so that a portion of the metal film M1 can be allocated to the wiring capacitance of the FD 722 or the additional capacitor 727. Fig.46 In A, the comb-tooth shape in the areas 861 to 864 surrounded by solid circles constitutes at least a part of the FD 722 or the additional capacitor 727. The FD 722 or the additional capacitor 727 can be configured by appropriately classifying into the metal film M1 and the metal film M2. The pattern of the metal film M1 can be configured in the reflective member 631 and the capacitance of the FD 722 or the additional capacitor 727 with excellent balance.

[0563] Fig.46 B shows a pattern of the metal film M1 in the case where the reflective member 631 is not provided. In order to increase the amount of infrared light to be photoelectrically converted in the substrate 61 and to improve the sensitivity of the pixel 51, it is preferable to provide the reflective member 631, but a configuration in which the reflective member 631 is not provided may also be adopted.

[0564] <Example of Substrate Configuration of Solid-State Imaging Element>

[0565] exist Figure 1 In the solid-state imaging element 11, it is possible to use Fig.47 The invention can be composed of any substrate of A to C.

[0566] Fig.47 A shows an example in which the solid-state imaging element 11 includes a semiconductor substrate 911 and a supporting substrate 912 located below the semiconductor substrate 911 .

[0567] In this case, a pixel array region 951 corresponding to the pixel array unit 21 , a control circuit 952 for controlling each pixel in the pixel array region 951 , and a logic circuit 953 including a signal processing circuit for pixel signals are formed in the upper semiconductor substrate 911 .

[0568] The control circuit 952 includes the vertical drive section 22, the horizontal drive section 24, etc. as described above. The logic circuit 953 includes a column processing section 23 that performs AD conversion processing of pixel signals, etc., and a signal processing section 26 that performs distance calculation processing of calculating the distance from the ratio of pixel signals acquired from each of the two or more signal extraction sections 65 within the pixel, calibration processing, etc.

[0569] In addition, if Fig.47As shown in FIG. 1B, in the solid-state imaging element 11, a first semiconductor substrate 921 on which a pixel array region 951 and a control circuit 952 are formed and a second semiconductor substrate 922 on which a logic circuit 953 is formed may be stacked. In addition, the first semiconductor substrate 921 and the second semiconductor substrate 922 are electrically connected to each other, for example, by a through hole or a Cu-Cu metal bond.

[0570] In addition, if Fig.47 As shown in FIG. 3C, in the solid-state imaging element 11, a first semiconductor substrate 931 on which only a pixel array region 951 is formed and a second semiconductor substrate 932 on which an area control circuit 954 in which a control circuit for controlling each pixel and a signal processing circuit for processing pixel signals are provided in an area unit of one pixel or a plurality of pixels can be stacked. The first semiconductor substrate 931 and the second semiconductor substrate 932 are electrically connected to each other, for example, by a through hole or a Cu-Cu metal bond.

[0571] and Fig.47 By setting the control circuit and the signal processing circuit in one pixel unit or area unit, as in the solid-state imaging element 11 in C, the optimal drive timing or gain can be set in each divided control unit, and the optimized distance information can be obtained regardless of the distance or reflectivity. In addition, the distance information can be calculated by driving only a part of the area instead of the entire pixel array area 951, so the power consumption can also be suppressed according to the operation mode.

[0572] <Configuration Example of Distance Measurement Module>

[0573] Fig.48 is shown by using Figure 1 A block diagram of an example of the configuration of a distance measurement module in which the solid-state imaging element 11 outputs distance measurement information.

[0574] The distance measurement module 1000 includes a light emitting section 1011 , a light emitting control section 1012 , and a light receiving section 1013 .

[0575] The light emitting unit 1011 includes a light source that emits light of a predetermined wavelength, emits irradiation light with periodic fluctuations in brightness, and irradiates an object with the irradiation light. For example, the light emitting unit 1011 includes a light emitting diode that emits infrared light with a wavelength in the range of 780 nm to 1000 nm as a light source, and generates the irradiation light in synchronization with the rectangular wave light emission control signal CLKp supplied from the light emission control unit 1012.

[0576] In addition, the light emission control signal CLKp is not limited to a rectangular wave, and can be any signal as long as it is a periodic signal. For example, the light emission control signal CLKp can be a sine wave.

[0577] The light control unit 1012 supplies the light control signal CLKp to the light emitting unit 1011 and the light receiving unit 1013, and controls the irradiation timing of the irradiation light. The frequency of the light control signal CLKp is, for example, 20 megahertz (MHz). In addition, the frequency of the light control signal CLKp is not limited to 20 megahertz (MHz), and can be 5 megahertz (MHz) or the like.

[0578] The light receiving unit 1013 receives reflected light from an object, calculates distance information of each pixel based on the light reception result, generates a depth image indicating the distance to the object using the grayscale value of each pixel, and outputs the depth image.

[0579] The above-mentioned solid-state imaging element 11 is used in the light receiving unit 1013, and the solid-state imaging element 11 as the light receiving unit 1013 calculates the distance information of each pixel based on the signal intensity detected by the charge detection unit (N+ semiconductor region 71) of each of the signal extraction units 65-1 and 65-2 of each pixel 51 of the pixel array unit 21, for example, based on the light emission control signal CLKp.

[0580] As mentioned above, Figure 1 The solid-state imaging element 11 in the embodiment can be used as the light receiving unit 1013 of the distance measuring module 1000 that obtains and outputs the distance information to the object by the indirect ToF method. By using the solid-state imaging element 11 of each of the above-mentioned embodiments (specifically, a solid-state imaging element as a back-illuminated sensor with improved pixel sensitivity) as the light receiving unit 1013 of the distance measuring module 1000, the distance measuring characteristics of the distance measuring module 1000 can be improved.

[0581] As described above, according to the present technology, the CAPD sensor is configured as a back-illuminated light receiving element, and therefore, the distance measurement characteristics can be improved.

[0582] In addition, in the present technology, it is obvious that the above-mentioned embodiments can be appropriately combined. In other words, for example, depending on which characteristics such as pixel sensitivity are prioritized, the number of signal extraction units to be set in the pixel or the configuration position of the signal extraction unit, whether to set the shape or shared structure of the signal extraction unit, the presence or absence of an on-chip lens, the presence or absence of a light shielding unit between pixels, the presence or absence of a separation area, the thickness of the on-chip lens or substrate, the type or film design of the substrate, the presence or absence of an offset relative to the incident surface, the presence or absence of a reflective member, etc. can be appropriately selected.

[0583] In addition, in the above description, an example of using electrons as signal carriers has been described, but holes generated by photoelectric conversion may be used as signal carriers. In this case, it is sufficient that the charge detection section for detecting signal carriers includes a P+ semiconductor region and the voltage application section for generating an electric field in the substrate includes an N+ semiconductor region, and therefore, holes as signal carriers are detected in the charge detection section provided in the signal extraction section.

[0584] <Application examples for mobile objects>

[0585] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is implemented as a device to be installed on any type of mobile body such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0586] Fig.49 This is a block diagram showing an exemplary configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0587] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.49 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0588] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for devices such as a drive force generating device for generating a drive force of the vehicle such as an internal combustion engine or a drive motor, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0589] The main body system control unit 12020 controls the operation of various devices installed to the vehicle body according to various programs. For example, the main body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a direction indicator, or a fog light. In this case, a radio wave or a signal of various switches emitted from a portable machine instead of a key may be input to the main body system control unit 12020. The main body system control unit 12020 receives the input of the radio wave or the signal and controls the door lock device, the power window device, the light, etc. of the vehicle.

[0590] The vehicle exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the image outside the vehicle and receive the image. The vehicle exterior information detection unit 12030 can perform detection processing or distance detection processing of objects such as people, cars, obstacles, signs, or text on the road based on the received image.

[0591] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, and can also output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0592] The in-vehicle information detection unit 12040 detects in-vehicle information. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the state of the driver. For example, the driver state detection unit 12041 includes a camera for imaging the driver, and based on the detection information input by the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or can determine whether the driver is dozing off.

[0593] For example, the microcomputer 12051 may calculate a control target value of a driving force generating device, a steering mechanism, or a braking device based on information inside and outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and may output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 may perform coordinated control to implement functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of a vehicle, tracking driving based on a distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane departure warning.

[0594] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040 to perform coordinated control such as automatic driving in which the vehicle travels autonomously without relying on the driver's operation.

[0595] In addition, the microcomputer 12051 can output a control instruction to the main system control unit 12020 based on the information outside the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlights according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030 to perform coordinated control to prevent glare such as switching the high beam to the low beam.

[0596] The audio and video output unit 12052 transmits an output signal as at least one of audio and video to an output device that can visually or auditorily notify the vehicle occupants or the outside of the vehicle of information. Fig.49 In the example of FIG. 1 , an audio speaker 12061, a display unit 12062, and a dashboard 12063 are illustrated as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0597] Fig.50 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0598] exist Fig.50 In the figure, vehicle 12100 includes imaging units 12101, 12102, 12103, 12104 and 12105 as imaging section 12031.

[0599] For example, the imaging units 12101, 12102, 12103, 12104 and 12105 are arranged at positions such as the front of the vehicle 12100, the side mirrors, the rear bumper, the rear door and the upper part of the windshield in the vehicle. The imaging unit 12101 arranged in the front of the vehicle and the imaging unit 12105 arranged in the upper part of the windshield in the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged in the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 arranged in the rear bumper or the rear door mainly obtains images on the rear of the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used to detect front vehicles, pedestrians, obstacles, traffic lights, traffic signs, traffic lanes, etc.

[0600] also, Fig.50An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front of the vehicle, the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided in the rear bumper or the rear door. For example, the image data imaged by the imaging units 12101 to 12104 are superimposed, so that a bird's-eye view image of the vehicle 12100 seen from above can be obtained.

[0601] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for detecting phase differences.

[0602] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 obtains the distance to each solid object within each imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100), and thus, among the closest solid objects on the driving route of the specific vehicle 12100, a solid object traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in a direction substantially the same as the driving direction of the vehicle 12100 can be extracted as the front vehicle. In addition, the microcomputer 12051 can set the distance between the vehicles in front of the front vehicle that should be ensured in advance, and thus can perform automatic braking control (also including tracking travel stop control), automatic acceleration control (also including tracking travel start control), etc. Therefore, coordinated control such as automatic driving in which the vehicle autonomously travels without relying on the operation of the driver can be performed.

[0603] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as electric poles and extract the three-dimensional object data, so that the three-dimensional object data can be used in automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to be visually recognized by the driver. Then, the microcomputer 12051 determines the collision risk indicating the degree of collision risk with each obstacle, and when the collision risk is equal to or higher than a predetermined value and there is a possibility of collision, by outputting a warning to the driver via the audio speaker 12061 and the display unit 12062, or by forcibly decelerating or avoiding steering via the drive system control unit 12010, driving support for avoiding collision can be performed.

[0604] At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared light. For example, the microcomputer 12051 may determine whether a pedestrian exists in the imaging images of the imaging units 12101 to 12104, and thus, the pedestrian may be identified. For example, the identification of pedestrians is performed by extracting feature points in the imaging images of the imaging units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether it is a pedestrian. In the case where the microcomputer 12051 determines that a pedestrian exists in the imaging images of the imaging units 12101 to 12104 and identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 so that the emphasized square outline is superimposed and displayed on the identified pedestrian. In addition, the sound image output unit 12052 may control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0605] As described above, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. In the above configuration, the technology according to the present disclosure can be applied to the imaging unit 12031. Specifically, for example, Figure 1 The solid-state imaging element 11 shown is applied to the imaging portion 12031, so that characteristics such as sensitivity can be improved.

[0606] In addition, the embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made within the scope not departing from the gist of the present technology.

[0607] In addition, the effects described here are merely examples and are not limited, and other effects may be provided.

[0608] Furthermore, the present technology can also have the following configurations.

[0609] (A1)

[0610] A light receiving element, comprising:

[0611] On-chip lens;

[0612] Wiring layer; and

[0613] a semiconductor layer disposed between the on-chip lens and the wiring layer,

[0614] The semiconductor layer comprises

[0615] a first voltage applying unit to which a first voltage is applied,

[0616] a second voltage applying section to which a second voltage different from the first voltage is applied,

[0617] a first charge detection section disposed around the first voltage applying section, and

[0618] a second charge detection unit disposed around the second voltage applying unit,

[0619] The wiring layer includes

[0620] at least one layer having a first voltage applying wiring configured to supply a first voltage, a second voltage applying wiring configured to supply a second voltage, and a reflective member, and

[0621] The reflective member is disposed so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

[0622] (A2)

[0623] The light receiving element according to (A1), wherein the first voltage applying section, the second voltage applying section, the first charge detecting section, and the second charge detecting section are in contact with the wiring layer.

[0624] (A3)

[0625] The light receiving element according to (A1) or (A2), wherein the one layer having the first voltage applying wiring, the second voltage applying wiring, and the reflecting member includes a layer closest to the semiconductor layer.

[0626] (A4)

[0627] The light receiving element according to any one of (A1) to (A3), wherein the first voltage applying section or the second voltage applying section includes

[0628] a first region including an acceptor element at a first impurity concentration on the wiring layer side, and

[0629] A second region on the on-chip lens side includes an acceptor element at a second impurity concentration lower than the first impurity concentration.

[0630] (A5)

[0631] The light receiving element according to any one of (A1) to (A4), wherein the first charge detection section or the second charge detection section includes

[0632] a third region containing a donor element at a third impurity concentration on the wiring layer side, and

[0633] A fourth region on the on-chip lens side includes a donor element at a second impurity concentration lower than the third impurity concentration.

[0634] (A6)

[0635] The light receiving element according to any one of (A1) to (A5), wherein the reflecting member includes a metal film.

[0636] (A7)

[0637] The light receiving element according to any one of (A1) to (A6), wherein the reflecting member is symmetrically arranged in a region on the first charge detection portion side and a region on the second charge detection portion side.

[0638] (A8)

[0639] The light receiving element according to any one of (A1) to (A7), wherein the reflecting members are arranged in a lattice pattern.

[0640] (A9)

[0641] The light receiving element according to any one of (A1) to (A7), wherein the reflecting member is arranged in a stripe pattern.

[0642] (A10)

[0643] The light receiving element according to any one of (A1) to (A7), wherein the reflective member is arranged only in a pixel center region.

[0644] (A11)

[0645] The light receiving element according to any one of (A1) to (A7), wherein the wiring layer further includes a wiring capacitor on the same layer as the reflective member.

[0646] (A12)

[0647] The light receiving element according to any one of (A1) to (A11), wherein the wiring layer further includes a wiring capacitor on a different layer from the reflective member.

[0648] (A13)

[0649] The light receiving element according to any one of (A1) to (A12), wherein the wiring layer further includes a voltage supply line configured to supply the first voltage or the second voltage to the first voltage applying wiring and the second voltage applying wiring.

[0650] (A14)

[0651] The light receiving element according to (A13), wherein the voltage supply line is arranged in a mirror configuration in which a connection destination with respect to two pixels adjacent to each other above and below is mirror-inverted.

[0652] (A15)

[0653] The light receiving element according to (A13), wherein the voltage supply line is arranged in a periodic arrangement that is periodically repeated with respect to pixels arranged in a vertical direction.

[0654] (A16)

[0655] The light receiving element according to any one of (A13) to (A15), wherein the two voltage supply lines are arranged with respect to two columns of pixels.

[0656] (A17)

[0657] The light receiving element according to any one of (A13) to (A15), wherein four voltage supply lines are arranged with respect to two columns of pixels.

[0658] (A18)

[0659] The light receiving element according to any one of (A1) to (A17), wherein the wiring layer further includes

[0660] a first pixel transistor configured to drive the first charge detection portion, and

[0661] a second pixel transistor configured to drive the second charge detection portion, and

[0662] The first pixel transistor and the second pixel transistor are arranged symmetrically.

[0663] (B1)

[0664] An imaging element, comprising:

[0665] A pixel array section including a plurality of pixels configured to perform photoelectric conversion on incident light, wherein the pixels include

[0666] a substrate configured to perform photoelectric conversion on incident light, and

[0667] A signal extraction unit includes a voltage application unit for generating an electric field by applying a voltage to the substrate and a charge detection unit for detecting signal carriers generated by photoelectric conversion, and the signal extraction unit is arranged inside the substrate on the surface of the substrate opposite to the incident surface of the substrate where light is incident.

[0668] (B2)

[0669] The imaging element according to (B1), wherein two signal extraction sections are formed in the pixel.

[0670] (B3)

[0671] The imaging element according to (B1), wherein one signal extraction section is formed in the pixel.

[0672] (B4)

[0673] The imaging element according to (B1), wherein three or more signal extraction sections are formed in the pixel.

[0674] (B5)

[0675] The imaging element according to (B1), wherein the signal extraction section is shared between the pixel and another pixel adjacent to the pixel.

[0676] (B6)

[0677] The imaging element according to (B1), wherein the voltage applying section is shared between the pixel and another pixel adjacent to the pixel.

[0678] (B7)

[0679] An imaging element according to any one of (B1) to (B6), wherein the signal extraction section includes a P-type semiconductor region as the voltage application section and an N-type semiconductor region as the charge detection section, the N-type semiconductor region being formed to surround the P-type semiconductor region.

[0680] (B8)

[0681] An imaging element according to any one of (B1) to (B6), wherein the signal extraction section includes an N-type semiconductor region as the charge detection section and a P-type semiconductor region as the voltage application section, the P-type semiconductor region being formed to surround the N-type semiconductor region.

[0682] (B9)

[0683] An imaging element according to any one of (B1) to (B6), wherein the signal extraction unit includes a first N-type semiconductor region and a second N-type semiconductor region as the charge detection unit and a P-type semiconductor region as the voltage application unit, and the P-type semiconductor region is formed at a position sandwiched between the first N-type semiconductor region and the second N-type semiconductor region.

[0684] (B10)

[0685] An imaging element according to any one of (B1) to (B6), wherein the signal extraction unit includes a first P-type semiconductor region and a second P-type semiconductor region as the voltage application unit and an N-type semiconductor region as the charge detection unit, and the N-type semiconductor region is formed at a position sandwiched between the first P-type semiconductor region and the second P-type semiconductor region.

[0686] (B11)

[0687] The imaging element according to any one of (B1) to (B10), wherein a voltage is applied to the incident surface side in the substrate.

[0688] (B12)

[0689] An imaging element according to any one of (B1) to (B11), wherein the pixel further includes a reflective member configured to reflect light incident on the substrate from the incident surface, the reflective member being formed on a surface of the substrate opposite to the incident surface.

[0690] (B13)

[0691] The imaging element according to any one of (B1) to (B12), wherein the signal carriers include electrons.

[0692] (B14)

[0693] The imaging element according to any one of (B1) to (B12), wherein the signal carriers include holes.

[0694] (B15)

[0695] The imaging element according to any one of (B1) to (B14), wherein the pixel further includes a lens configured to converge light and make the light incident on the substrate.

[0696] (B16)

[0697] The imaging element according to any one of (B1) to (B15), wherein the pixel further includes an inter-pixel light shielding portion configured to shield incident light, the inter-pixel light shielding portion being formed at an end portion of the pixel on the incident surface of the substrate.

[0698] (B17)

[0699] An imaging element according to any one of (B1) to (B16), wherein the pixel further includes a pixel separation region configured to penetrate at least a portion of the substrate and shield incident light, the pixel separation region being formed at a pixel end within the substrate.

[0700] (B18)

[0701] The imaging element according to any one of (B1) to (B17), wherein the substrate includes a P-type semiconductor substrate having a resistance of 500 [Ωcm] or more.

[0702] (B19)

[0703] The imaging element according to any one of (B1) to (B17), wherein the substrate includes an N-type semiconductor substrate having a resistance of 500 [Ωcm] or more.

[0704] (B20)

[0705] An imaging device, comprising:

[0706] a pixel array section including a plurality of pixels configured to perform photoelectric conversion on incident light; and

[0707] a signal processing section configured to calculate distance information to an object based on the signal output from the pixel,

[0708] The pixels include

[0709] a substrate configured to perform photoelectric conversion on incident light, and

[0710] A signal extraction unit includes a voltage application unit for generating an electric field by applying a voltage to the substrate and a charge detection unit for detecting signal carriers generated by photoelectric conversion, and the signal extraction unit is arranged inside the substrate on the surface of the substrate opposite to the incident surface of the substrate where light is incident.

[0711] Reference numerals list

[0712] 11 Solid-state imaging element

[0713] 21 Pixel array unit

[0714] 22 Vertical drive unit

[0715] 51 pixels

[0716] 61 substrate

[0717] 62 On-chip lens

[0718] 71-1, 71-2, 71 N+ semiconductor area

[0719] 73-1, 73-2, 73 P+ semiconductor region

[0720] 441-1, 441-2, 441 Separation Area

[0721] 471-1, 471-2, 471 Separation Area

[0722] 631 Reflective component

[0723] 721 Pass transistor

[0724] 722 FD

[0725] 723 Reset transistor

[0726] 724 Amplifier Transistor

[0727] 725 Select transistor

[0728] 727 Additional Capacitor

[0729] 728 Switching transistor

[0730] 741 Voltage supply line

[0731] 811 Multi-layer wiring layer

[0732] 812 Interlayer insulation film

[0733] 813 Power Cord

[0734] 814 Voltage application wiring

[0735] 815 Reflective component

[0736] 816 Voltage application wiring

[0737] 817 Control Line

[0738] M1~M5 Metal film

Claims

1. A light receiving element, comprising: a semiconductor layer having a light receiving surface; a multilayer wiring layer provided at a surface of the semiconductor layer opposite to the light receiving surface; as well as Multiple pixels; Among them, pixels include: a first voltage applying unit configured to apply a first voltage to the semiconductor layer; a second voltage applying section configured to apply a second voltage to the semiconductor layer; a first charge detection section, the first charge detection section being disposed adjacent to the first voltage application section; a second charge detection section provided in the semiconductor layer and adjacent to the second voltage applying section; and a first separation section provided between the first voltage applying section and the first charge detecting section, wherein the first separation portion comprises an oxide film, The reflective member is located in the multi-layer wiring layer, and at least a portion of the reflective member is symmetrically disposed below the first charge detection portion and the second charge detection portion.

2. The light receiving element according to claim 1, wherein The first separation portion is formed near a surface of the semiconductor layer opposite to the light receiving surface.

3. The light receiving element according to claim 1, wherein The pixel further includes a second separation section provided between the second voltage applying section and the second charge detecting section.

4. The light receiving element according to claim 3, wherein The second separation portion includes an oxide film.

5. The light receiving element according to claim 3, wherein The second separation portion is formed near a surface of the semiconductor layer opposite to the light receiving surface.

6. The light receiving element according to claim 1, wherein The first voltage applying unit or the second voltage applying unit includes: a first region including an acceptor element at a first impurity concentration on the multilayer wiring layer side, and A second region on the light receiving surface side contains an acceptor element at a second impurity concentration lower than the first impurity concentration.

7. The light receiving element according to claim 1, wherein The first charge detection section or the second charge detection section includes: a third region containing a donor element at a third impurity concentration on the multilayer wiring layer side, and A fourth region on the light receiving surface side contains a donor element at a fourth impurity concentration lower than the third impurity concentration.

8. The light receiving element according to claim 1, wherein The pixel further includes an oxide film provided between the first charge detection portion and the second charge detection portion.

9. A light receiving element, comprising: a semiconductor layer having a light receiving surface; a multilayer wiring layer provided at a surface of the semiconductor layer opposite to the light receiving surface; as well as Multiple pixels; Among them, pixels include: a first voltage applying unit configured to apply a first voltage to the semiconductor layer; a second voltage applying section configured to apply a second voltage to the semiconductor layer; a first charge detection section, the first charge detection section being disposed adjacent to the first voltage application section; a second charge detection section provided in the semiconductor layer and adjacent to the second voltage applying section; and an oxide film provided between the first charge detection portion and the second charge detection portion, The reflective member is located in the multi-layer wiring layer, and at least a portion of the reflective member is symmetrically disposed below the first charge detection portion and the second charge detection portion.

10. The light receiving element according to claim 9, wherein The oxide film is formed near a surface of the semiconductor layer opposite to the light receiving surface.

11. The light receiving element according to claim 9, wherein The reflective member is disposed on a surface of the semiconductor layer opposite to the light receiving surface.

12. The light receiving element according to claim 9, wherein The pixel further includes a well region provided between the first charge detection portion and the second charge detection portion.

13. The light receiving element according to claim 12, wherein The well region is formed on the oxide film.

14. The light receiving element according to claim 12, wherein The oxide film includes a first separation portion adjacent to the first charge detection portion and a second separation portion adjacent to the second charge detection portion, and the well region is formed between the first separation portion and the second separation portion.

15. The light receiving element according to any one of claims 9 to 14, wherein The pixel also includes: a third separation section located between the first voltage applying section and the first charge detecting section; and A fourth separation section is located between the second voltage applying section and the second charge detecting section.

16. The light receiving element according to claim 15, wherein The third separation portion and the fourth separation portion include oxide films.

17. The light receiving element according to claim 9, wherein The first voltage applying unit or the second voltage applying unit includes: a first region including an acceptor element at a first impurity concentration on the multilayer wiring layer side, and A second region on the light receiving surface side contains an acceptor element at a second impurity concentration lower than the first impurity concentration.

18. The light receiving element according to claim 9, wherein The first charge detection section or the second charge detection section includes: a third region containing a donor element at a third impurity concentration on the multilayer wiring layer side, and A fourth region on the light receiving surface side contains a donor element at a fourth impurity concentration lower than the third impurity concentration.

Images