Anti-inrush switch circuit and chip

Abstract

The application relates to a reverse flow prevention switch circuit and a chip, the reverse flow prevention switch circuit comprising a controllable switch unit, a first switch subunit and a second switch subunit connected in parallel, a first end of the first switch subunit and a first end of the second switch subunit being electrically connected and serving as a first signal end; a control signal processing unit, which is electrically connected with a control end of the first switch subunit and a first voltage boosting unit respectively, is used for outputting a first voltage control signal to the control end of the first switch subunit according to an input external control signal, outputting a first voltage signal and a second voltage control signal to the first voltage boosting unit respectively; and the first voltage boosting unit is electrically connected with the control end of the second switch subunit and the first signal end, and is used for controlling the second switch subunit to be turned off according to the first voltage control signal and the second voltage control signal when the first voltage control signal is a preset level signal, so that the reverse flow prevention capability of the circuit is improved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, specifically to an anti-backflow switch circuit and chip. Background Technology

[0002] In MCUs (Microcontroller Units) and on-chip systems, analog switches serve as core control components for analog signal paths, controlling the on / off state of analog signals and selecting multiple analog signal paths. The simplest analog switch is implemented using a transmission gate.

[0003] However, when using the commonly used transmission gate structure, if the signal voltage to be transmitted is higher than the power supply voltage of the internal control signal of the chip, one of the switching transistors constituting the transmission gate will not be able to be completely turned off. At this time, as the external input signal voltage increases, the reverse current from the outside to the inside will become larger and larger, which will increase the power consumption of the entire chip system and thus affect or damage the analog circuit structure inside the chip. Summary of the Invention

[0004] In view of this, this application provides an anti-backflow switching circuit and chip to solve the technical problem of current backflow caused by a certain switching transistor in the existing transmission gate circuit structure being unable to be turned off.

[0005] An anti-backflow switch circuit, comprising:

[0006] A controllable switching unit includes a first switching subunit and a second switching subunit connected in parallel. The first end of the first switching subunit and the first end of the second switching subunit are electrically connected and serve as a first signal terminal. The second end of the first switching subunit and the second end of the second switching subunit are electrically connected and serve as a second signal terminal.

[0007] The control signal processing unit is electrically connected to the control terminal of the first switching subunit and has a first electrical connection and a second electrical connection with the first boost unit, respectively. It is used to output a first voltage control signal to the control terminal of the first switching subunit according to the input external control signal, output the first voltage control signal to the first boost unit through the first electrical connection, and output a second voltage control signal to the first boost unit through the second electrical connection. The first voltage control signal and the second voltage control signal are electrically opposite.

[0008] The first boost unit is electrically connected to the control terminal and the first signal terminal of the second switch subunit. When the first voltage control signal is a preset level signal, it adjusts the voltage of the control terminal of the second switch subunit to be the same as the voltage of the first signal terminal according to the first voltage control signal and the second voltage control signal so that the second switch subunit is turned off.

[0009] In one embodiment, the controllable switching unit further includes a third switching subunit and a fourth switching subunit connected in parallel. The third switching subunit has the same circuit structure as the first switching subunit, and the fourth switching subunit has the same circuit structure as the second switching subunit. The first terminals of each of the third and fourth switching subunits are electrically connected to a second signal terminal. The second terminals of the third and fourth switching subunits are electrically connected and serve as the third signal terminal. The control signal processing unit is electrically connected to the control terminal of the third switching subunit to output a first voltage control signal. The control signal processing unit is also used to establish an electrical connection with the control terminal of the fourth switching subunit to output a second voltage control signal.

[0010] The backflow prevention switch circuit also includes an isolation unit. The first terminal of the isolation unit is electrically connected to the second signal terminal, and the second terminal of the isolation unit is grounded. The control signal processing unit is electrically connected to the control terminal of the isolation unit to output a second voltage control signal.

[0011] In one embodiment, the anti-backflow switch circuit further includes a second boost unit;

[0012] The control signal processing unit is also used to disconnect the electrical connection with the control terminal of the fourth switch subunit and establish an electrical connection with the second boost unit to output the first voltage control signal and the second voltage control signal to the second boost unit respectively.

[0013] The second boost unit and the control signal processing unit are also used to disconnect the electrical connection with the control terminal of the fourth switch subunit, and establish a third electrical connection and a fourth electrical connection with the second boost unit respectively, so as to output a first voltage control signal to the second boost unit through the third electrical connection and output a second voltage control signal to the second boost unit through the fourth electrical connection.

[0014] In one embodiment, the first boost unit includes: a fifth switch subunit, a sixth switch subunit, a seventh switch subunit, and an eighth switch subunit. The first terminals of the fifth switch subunit and the sixth switch subunit are electrically connected to a first signal terminal. The second terminal of the fifth switch subunit is electrically connected to the control terminal of the second switch subunit, the control terminal of the sixth switch subunit, and the first terminal of the seventh switch subunit. The second terminal of the sixth switch subunit is electrically connected to the control terminal of the fifth switch subunit and the first terminal of the eighth switch subunit. A second electrical connection is established between the control terminal of the seventh switch subunit and the control signal processing unit. A first electrical connection is established between the control terminal of the eighth switch subunit and the control signal processing unit. The second terminals of the seventh switch subunit and the eighth switch subunit are both grounded.

[0015] In one embodiment, the second boost unit has the same circuit structure as the first boost unit.

[0016] In one embodiment, the fifth and sixth switching subunits both use PMOS transistors, while the seventh and eighth switching subunits both use NMOS transistors.

[0017] In one embodiment, the fifth and sixth switching subunits both use PNP transistors, while the seventh and eighth switching subunits both use NPN transistors.

[0018] In one embodiment, the isolation unit uses an NMOS transistor.

[0019] In one embodiment, the control signal processing unit includes a first inverter and a second inverter that are electrically connected. The first inverter is used to receive a first voltage control signal generated by an external control terminal to generate a second voltage control signal and output the second voltage control signal to the first boost unit.

[0020] The second inverter is used to output the first voltage control signal to the control terminal of the first switching subunit and the first boost unit.

[0021] In one embodiment, the first switching subunit uses an NMOS transistor, and the second switching subunit uses a PMOS transistor.

[0022] In addition, a chip is provided, which includes an analog circuit unit, at least one of the above-mentioned anti-backflow switch circuits, and at least one input / output interface. Each input / output interface is connected to an anti-backflow switch circuit to form a path with the analog circuit unit. The anti-backflow switch circuit is used to shut down when the analog function of at least one input / output interface is not in use, so as to isolate the analog circuit unit.

[0023] The aforementioned backflow prevention switch circuit includes: a controllable switch unit, a control signal processing unit, and a first boost unit. The controllable switch unit includes a first switch subunit and a second switch subunit connected in parallel. The first terminal of the first switch subunit and the first terminal of the second switch subunit are electrically connected and serve as a first signal terminal. The second terminal of the first switch subunit and the second terminal of the second switch subunit are electrically connected and serve as a second signal terminal. The control signal processing unit is electrically connected to the control terminal of the first switch subunit and the first boost unit, and is used to output a first voltage control signal to the control terminal of the first switch subunit and output a first voltage control signal and a second voltage control signal to the first boost unit based on the input external control signal. The first boost unit, which is electrically connected to the control terminal and the first signal terminal of the second switching subunit, is opposite to the first voltage control signal. When the first voltage control signal is at a preset level, it adjusts the voltage at the control terminal of the second switching subunit to the first preset voltage signal to turn off the second switching subunit based on the first voltage control signal and the second voltage control signal. Through the cooperation of the control signal processing unit and the first boost unit, when the first voltage control signal is at a preset level, the voltage at the control terminal of the second switching subunit in the controllable switching unit is adjusted to be the same as the voltage at the first signal terminal, thereby turning off the second switching subunit, thus isolating the influence of external input signals and overcoming the technical problem of current backflow. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the first circuit structure of an anti-backflow switch circuit according to an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of a second circuit structure of an anti-backflow switch circuit provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of a third circuit structure of an anti-backflow switch circuit provided in one embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the fourth circuit structure of an anti-backflow switch circuit provided in one embodiment of this application;

[0029] Figure 5This is a schematic diagram of the fifth circuit structure of an anti-backflow switch circuit provided in an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of the sixth circuit structure of an anti-backflow switch circuit provided in an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of the seventh circuit structure of an anti-backflow switch circuit provided in an embodiment of this application;

[0032] Figure 8 This is a structural block diagram of a chip provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0034] like Figure 1 As shown, an anti-backflow switch circuit 100 is provided, the anti-backflow switch circuit 100 includes:

[0035] The controllable switch unit 110 includes a first switch subunit 111 and a second switch subunit 112 connected in parallel. The first end 11 of the first switch subunit 111 and the first end 21 of the second switch subunit 112 are electrically connected and serve as a first signal terminal A1. The second end 12 of the first switch subunit 111 and the second end 22 of the second switch subunit 112 are electrically connected and serve as a second signal terminal A2.

[0036] The control signal processing unit 120 establishes an electrical connection with the control terminal 13 of the first switch subunit 111, and establishes a first electrical connection and a second electrical connection with the first boost unit 130, respectively. It is used to output a first voltage control signal to the control terminal 13 of the first switch subunit 111 according to the input external control signal, output the first voltage control signal to the first boost unit 130 through the first electrical connection, and output a second voltage control signal to the first boost unit 130 through the second electrical connection. The first voltage control signal and the second voltage control signal have opposite electrical properties.

[0037] The first boost unit 130 is electrically connected to the control terminal 23 and the first signal terminal A1 of the second switch subunit 112. When the first voltage control signal is a preset level signal, it adjusts the voltage of the control terminal 23 of the second switch subunit 112 to be the same as the voltage of the first signal terminal A1 according to the first voltage control signal and the second voltage control signal so that the second switch subunit 112 is turned off.

[0038] In one embodiment, the controllable switch unit 110 adopts a transmission gate structure. The preset level signal is a low level signal, that is, the first voltage control signal is a low level signal and the second voltage control signal is a high level signal. The control terminal 13 of the first switch subunit 111 can only be turned on when it is a high level signal and can only be turned off when it is a low level signal. Correspondingly, the control terminal 23 of the second switch subunit 112 can only be turned on when it is a low level signal and can only be turned off when it is a high level signal. In other words, the level signals of the control terminal 13 of the first switch subunit 111 and the control terminal 23 of the second switch subunit 112 are opposite.

[0039] Since the first boost unit 130 is electrically connected to the control terminal 23 and the first signal terminal A1 of the second switch subunit 112 respectively, the second switch subunit 112 can be turned off by adjusting the voltage of the control terminal 23 of the second switch subunit 112 to be the same as the voltage of the first signal terminal A1. In this way, when the preset level signal is a low level signal, the first signal terminal A1 inputs a signal voltage, and the voltage of the control terminal of the second switch subunit 112 is pulled up to a high level signal by the voltage of the first signal terminal A1. At this time, the second switch subunit 112 will be completely turned off.

[0040] In this embodiment, when the first voltage control signal is a high-level signal, the control terminal 13 of the first switch subunit 111 is a high-level signal, and the control terminal 23 of the second switch subunit 112 is a low-level signal. Both the first switch subunit 111 and the second switch subunit 112 can be turned on, and the current direction is from the first signal terminal A1 to the second signal terminal A2.

[0041] In this embodiment, the current direction is from the first signal terminal A1 to the second signal terminal A2. At this time, the anti-backflow switch circuit 100 only isolates the influence of the external input signal of the first signal terminal A1 to overcome the technical problem of current backflow in the first signal terminal A1. The voltage of the first signal terminal A1 should be greater than the voltage of the second signal terminal, and the anti-backflow switch circuit 100 is only a unidirectional switch circuit.

[0042] The first switching subunit 111 typically uses an NMOS switching transistor, but an NPN transistor can also be used. The second switching subunit 112 typically uses a PMOS switching transistor, but a PNP transistor can also be used.

[0043] In one embodiment, such as Figure 2 As shown, the first switching subunit 111 uses an NMOS transistor. The first terminal 11 of the first switching subunit 111 is the drain of the NMOS transistor, the second terminal 12 of the first switching subunit 111 is the source of the NMOS transistor, and the third terminal 13 of the first switching subunit 111 is the gate of the NMOS transistor. Similarly, the second switching subunit 112 uses a PMOS transistor. The first terminal 21 of the second switching subunit 112 is the source of the PMOS transistor, and the second terminal 22 of the second switching subunit 112 is the gate of the PMOS transistor. The drain of the switching transistor and the third terminal 23 of the second switching subunit 112 are the gate of the PMOS switching transistor. The substrate voltage of the PMOS switching transistor is directly electrically connected to the first signal terminal A1. In this way, when the preset level signal is a low level signal, the first signal terminal A1 receives a signal voltage, and the gate voltage of the PMOS transistor in the second switching subunit 112 is pulled up to a high level signal by the voltage of the first signal terminal A1 and is the same as the corresponding substrate voltage. At this time, the PMOS switching transistor in the second switching subunit 112 will be completely turned off.

[0044] The aforementioned anti-backflow switch circuit 100, through the cooperation of the control signal processing unit 120 and the first boost unit 130, enables the second switch subunit 112 in the controllable switch unit 110 to adjust the voltage of the control terminal 23 of the second switch subunit 112 to be the same as the voltage of the first signal terminal A1 when the first voltage control signal is a preset level signal, thereby turning off the second switch subunit 112, thus isolating the influence of the external input signal of the first signal terminal A1 and overcoming the technical problem of current backflow.

[0045] In one embodiment, such as Figure 3 As shown, the controllable switch unit 110 also includes a third switch subunit 113 and a fourth switch subunit 114 connected in parallel. The third switch subunit 113 has the same circuit structure as the first switch subunit 111, and the fourth switch subunit 114 has the same circuit structure as the second switch subunit 112. The first terminal 31 of the third switch subunit 113 and the first terminal 41 of the fourth switch subunit 114 are both electrically connected to the second signal terminal A2. The second terminal 32 of the third switch subunit 113 and the second terminal 42 of the fourth switch subunit 114 are electrically connected and serve as the third signal terminal A3. The control signal processing unit 120 is electrically connected to the control terminal 33 of the third switch subunit 113 to output a first voltage control signal. The control signal processing unit 120 is also used to establish an electrical connection with the control terminal 43 of the fourth switch subunit 114 to output a second voltage control signal.

[0046] The anti-backflow switch circuit 100 also includes an isolation unit 140. The first end of the isolation unit 140 is electrically connected to the second signal terminal A2, and the second end of the isolation unit 140 is grounded. The control signal processing unit 120 is electrically connected to the control terminal of the isolation unit 140 to output a second voltage control signal.

[0047] Among them, Figure 1 In the illustrated embodiment, the backflow prevention switch circuit 100 is a one-way switch circuit; therefore, as shown... Figure 3 As shown, in the controllable switch unit 110, by further setting a third switch subunit 113 and a fourth switch subunit 114 connected in parallel, the above-mentioned backflow prevention switch circuit 100 is transformed into a bidirectional switch circuit. At this time, the first terminal 31 of the third switch subunit 113 and the first terminal 41 of the fourth switch subunit 114 are both electrically connected to the second signal terminal A2. The second terminal 32 of the third switch subunit 113 and the second terminal 42 of the fourth switch subunit 114 are electrically connected and serve as the third signal terminal A3. At this time, since the circuit structure of the third switch subunit 113 is the same as that of the first switch subunit 111, and the circuit structure of the fourth switch subunit 114 is the same as that of the second switch subunit 112, the above-mentioned backflow prevention switch circuit 100 becomes a bidirectional switch circuit. External input signals can also be input from the third signal terminal A3 and output from the first signal terminal A1.

[0048] exist Figure 3 In the illustrated embodiment, the controllable switching unit 110 adopts a transmission gate structure. The first switching subunit 111 and the second switching subunit 112 constitute a transmission gate circuit, and the third switching subunit 113 and the fourth switching subunit 114 constitute another transmission gate circuit. The first switching subunit 111, the second switching subunit 112, the third switching subunit 113, and the fourth switching subunit 114 all use MOS switching transistors. Since MOS switching transistors have parasitic capacitance, when the external input signal is a high-frequency signal, current will flow through the parasitic capacitance from the first signal terminal A1 to the second signal terminal A2, or through the parasitic capacitance from the second signal terminal A2 to the first signal terminal A1. Therefore, an isolation unit 140 is further provided. The first terminal of the isolation unit 140 is electrically connected to the second signal terminal A2, and the second terminal of the isolation unit 140 is grounded. The control signal processing unit 120 is electrically connected to the control terminal of the isolation unit 140 to output the second voltage control signal. When the second switch subunit 112 is turned off, a current path is formed between the isolation unit 140 and the first signal terminal A1, so that the corresponding parasitic current flows directly to the ground. Similarly, when the fourth switch subunit 114 is turned off, a current path is formed between the isolation unit 140 and the third signal terminal A3, so that the corresponding parasitic current also flows directly to the ground. In other words, by setting the isolation unit 140, the potential of the second signal terminal A2 in the above transmission gate structure is pulled to the ground level, thereby achieving a good isolation effect.

[0049] In one embodiment, such as Figure 4 As shown, the anti-backflow switch circuit 100 also includes a second boost unit 150;

[0050] The control signal processing unit 120 is also used to disconnect the electrical connection with the control terminal 43 of the fourth switch subunit 114, and establish a third electrical connection and a fourth electrical connection with the second boost unit 150, so as to output the first voltage control signal to the second boost unit 150 through the third electrical connection, and output the second voltage control signal to the second boost unit 150 through the fourth electrical connection.

[0051] The second boost unit 150 is electrically connected to the third signal terminal A3 and the control terminal 43 of the fourth switch subunit 114, respectively. When the first voltage control signal is a preset level signal, it adjusts the voltage of the control terminal 43 of the fourth switch subunit 114 to be the same as the voltage of the third signal terminal A3 according to the first voltage control signal and the second voltage control signal so that the fourth switch subunit 114 is turned off.

[0052] Among them, Figure 2 In the illustrated embodiment, since the anti-backflow switch circuit 100 is a bidirectional switch circuit, if an external input signal can be input from the third signal terminal A3 and output from the first signal terminal A1, if the fourth switch subunit cannot be completely turned off, there will still be a problem of current backflow from the third signal terminal A3. At this time, a second boost unit 150 is also needed to prevent current backflow from the third signal terminal A3. At this time, the control signal processing unit 120 is also used to disconnect the electrical connection with the control terminal 43 of the fourth switch subunit 114 and establish a third electrical connection and a fourth electrical connection with the second boost unit 150, so as to output a first voltage control signal through the third electrical connection and a second voltage control signal through the fourth electrical connection to the second boost unit 150. When the first voltage control signal is a preset level signal, the second boost unit 150 adjusts the voltage of the control terminal 43 of the fourth switch subunit 114 to be the same as the voltage of the third signal terminal A3 according to the first voltage control signal and the second voltage control signal so that the fourth switch subunit 114 is completely turned off. In this embodiment, the anti-backflow switch circuit 100 is a bidirectional switch. By simultaneously setting the first boost unit 130 and the second boost unit 150, when the first voltage control signal is a preset level signal, the second switch subunit 112 and the fourth switch subunit 114 can be completely turned off, thereby preventing current backflow when there is an external signal input at the first signal terminal A1 or the third signal terminal A3.

[0053] In one embodiment, such as Figure 5As shown, the first boost unit 130 includes: a fifth switch subunit 131, a sixth switch subunit 132, a seventh switch subunit 133, and an eighth switch subunit 134. The first terminal 51 of the fifth switch subunit 131 and the first terminal 61 of the sixth switch subunit 132 are both electrically connected to the first signal terminal A1. The second terminal 52 of the fifth switch subunit 131 is electrically connected to the control terminal 23 of the second switch subunit 112, the control terminal 63 of the sixth switch subunit 132, and the first terminal 71 of the seventh switch subunit 133, respectively. The second terminal 62 of the sixth switch subunit 132 is electrically connected to the control terminal 53 of the fifth switch subunit 131 and the first terminal 81 of the eighth switch subunit 134, respectively. The control signal processing unit 120 has a second electrical connection with the control terminal 73 of the seventh switch subunit 133 and a first electrical connection with the control terminal 83 of the eighth switch subunit 134. The second terminal 72 of the seventh switch subunit 133 and the second terminal 82 of the eighth switch subunit 134 are both grounded.

[0054] Preferably, the fifth switch subunit 131 and the sixth switch subunit 132 both use PMOS transistors, and the seventh switch subunit 133 and the eighth switch subunit 134 both use NMOS transistors.

[0055] In this configuration, the first terminal 51 of the fifth switch subunit 131 is the source of the corresponding PMOS switch, the second terminal 52 of the fifth switch subunit 131 is the drain of the corresponding PMOS switch, and the control terminal 53 of the fifth switch subunit 131 is the gate of the corresponding PMOS switch. The first terminal 61 of the sixth switch subunit 132 is the source of the corresponding PMOS switch, the second terminal 62 of the sixth switch subunit 132 is the drain of the corresponding PMOS switch, and the control terminal 63 of the sixth switch subunit 132 is the gate of the corresponding PMOS switch.

[0056] In this configuration, the first terminal 71 of the seventh switch subunit 133 is the drain of the corresponding NMOS switch, the second terminal 72 of the seventh switch subunit 133 is the source of the corresponding NMOS switch, the control terminal 73 of the seventh switch subunit 134 is the gate of the corresponding NMOS switch, the first terminal 81 of the eighth switch subunit 134 is the drain of the corresponding NMOS switch, the second terminal 82 of the eighth switch subunit 134 is the source of the corresponding NMOS switch, and the control terminal 83 of the eighth switch subunit 134 is the gate of the corresponding NMOS switch.

[0057] In the fifth switch subunit 131, the sixth switch subunit 132, the seventh switch subunit 133 and the eighth switch subunit 134 mentioned above, the substrate voltage of each switch transistor is usually directly connected to the source.

[0058] In the first boost unit 130, the control signal processing unit 120 outputs a second voltage control signal to the control terminal 73 of the seventh switch subunit 133 and outputs a first voltage control signal to the control terminal 83 of the eighth switch subunit 134. Since the first and second voltage control signals are electrically opposite, when the first voltage control signal is low, the second voltage control signal is high. At this time, the control terminal 83 of the eighth switch subunit 134 is the gate of the NMOS transistor, and is disconnected due to its low-level state. The control terminal 73 of the seventh switch subunit 133 is then... Since the gate of the NMOS transistor is in a high-level state, the seventh switch sub-unit 133 is naturally turned on. The voltage of the first terminal 71 of the seventh switch sub-unit 133 is pulled down to the ground voltage and is in a low-level state. The control terminal 63 of the sixth switch sub-unit 132 is a low-level signal and is turned on accordingly. Since the first terminal of the sixth switch sub-unit 132 is connected to the first signal terminal A1, the second terminal of the sixth switch sub-unit 132 is pulled up to the same voltage as the first signal terminal A1 and is in a high-level state. The control terminal of the second switch sub-unit 112 is completely turned off due to the high-level signal.

[0059] In such Figure 5 In the embodiment shown, the second switching sub-unit 112 is a PMOS switch. Since the substrate voltage and gate voltage of the PMOS switch are the same as the voltage of the first signal terminal A1, the second switching sub-unit 112 will be completely turned off at this time.

[0060] In another embodiment, such as Figure 6 As shown, the fifth switch subunit 131 and the sixth switch subunit 132 can also be PNP transistors, and the seventh switch subunit 133 and the eighth switch subunit 134 can also be NPN transistors. In this case, the first terminal 51 of the fifth switch subunit 131 is the emitter of the corresponding PNP transistor, the second terminal 52 of the fifth switch subunit 131 is the collector of the corresponding PNP transistor, and the control terminal 53 of the fifth switch subunit 131 is the base of the corresponding PNP transistor. The first terminal 61 of the sixth switch subunit 132 is the emitter of the corresponding PNP transistor, the second terminal 62 of the sixth switch subunit 132 is the collector of the corresponding PNP transistor, and the control terminal 63 of the sixth switch subunit 132 is the base of the corresponding PNP transistor.

[0061] In this circuit, the first terminal 71 of the seventh switch subunit 133 is the collector of the corresponding NPN transistor, the second terminal 72 of the seventh switch subunit 133 is the emitter of the corresponding NPN transistor, the control terminal 73 of the seventh switch subunit 133 is the base of the corresponding NPN transistor, the first terminal 81 of the eighth switch subunit 134 is the collector of the corresponding NPN transistor, the second terminal 82 of the eighth switch subunit 134 is the emitter of the corresponding NPN transistor, and the control terminal 83 of the eighth switch subunit 134 is the base of the corresponding NPN transistor.

[0062] In the first boost unit 130, the control signal processing unit 120 outputs a second voltage control signal to the control terminal 73 of the seventh switch subunit 133 and outputs a first voltage control signal to the control terminal 83 of the eighth switch subunit 134. Since the first and second voltage control signals are electrically opposite, when the first voltage control signal is low, the second voltage control signal is high. At this time, the control terminal 83 of the eighth switch subunit 134 is the base of the NPN transistor, and is disconnected due to its low-level state. The control terminal 73 of the seventh switch subunit 133 is then... Since the base of the NPN transistor is at a high level, the seventh switch subunit 133 is naturally turned on. The voltage of the first terminal 71 of the seventh switch subunit 133 is pulled down to the ground voltage and is at a low level. The control terminal 63 of the sixth switch subunit 132 is a low-level signal and is turned on accordingly. Since the first terminal of the sixth switch subunit 132 is connected to the first signal terminal A1, the second terminal of the sixth switch subunit 132 is pulled up to the same voltage as the first signal terminal A1 and is at a high level. The control terminal of the second switch subunit 112 is completely turned off due to the high-level signal.

[0063] In one embodiment, the second boost unit 150 has the same circuit structure as the first boost unit 130.

[0064] For example, such as Figure 7As shown, each switching subunit in the first boost unit 130 uses a MOS transistor circuit. The second boost unit 150 has the same circuit structure as the first boost unit 130. The second boost unit 150 includes a ninth switching subunit 151, a tenth switching subunit 152, an eleventh switching subunit 153, and a twelfth switching subunit 154. The ninth switching subunit 151 and the tenth switching subunit 152 both use PMOS transistors, while the eleventh switching subunit 153 and the twelfth switching subunit 154 both use NMOS transistors. The ninth switching subunit 151 corresponds to the fifth switching subunit 131, and the eleventh switching subunit 153 corresponds to the sixth switching subunit 132. Correspondingly, the eleventh switch subunit 153 corresponds to the seventh switch transistor 133, and the twelfth switch subunit 154 corresponds to the eighth switch subunit 134. The control signal processing unit 120 has a fourth electrical connection with the gate of the NMOS switch transistor in the eleventh switch subunit 153 to receive the corresponding second voltage control signal, and the control signal processing unit 120 has a third electrical connection with the gate of the NMOS switch transistor in the twelfth switch subunit 154 to receive the corresponding first voltage control signal. Since the circuit structure of the second boost circuit 150 is the same as that of the first boost unit 130, the corresponding working process and principle are also the same, and will not be described again here.

[0065] When the first voltage control signal is a low-level signal, the second voltage control signal is a high-level signal, and the second boost unit 150 operates, pulling up the voltage of the control terminal of the fourth switch subunit 114 to be the same as the voltage of the third signal terminal A3, thereby making the control terminal 43 of the fourth switch subunit 114 in a high-level state, thus making the fourth switch subunit 114 completely turn off, thereby overcoming the technical disadvantage of current backflow at the third signal terminal A3.

[0066] In another embodiment, when each switching subunit in the second boost unit 150 uses a transistor, each switching subunit in the first boost unit 130 can also use a MOSFET; similarly, when each switching subunit in the second boost unit 150 uses a MOSFET, each switching subunit in the first boost unit 130 can also use a transistor. The circuit structures of the corresponding first boost unit 130 and the second boost unit 150 refer to the circuit structures of the corresponding boost units in the above-described corresponding embodiments.

[0067] In one embodiment, such as Figures 5 to 7As shown in any of the attached figures, the isolation unit 140 uses an NMOS transistor. The first terminal of the isolation unit 140 is the drain of the NMOS transistor and is connected to the second signal terminal A2. The second terminal of the isolation unit 140 is the source of the NMOS transistor and is grounded. The control terminal of the isolation unit 140 is the gate of the NMOS transistor and is connected to the control signal processing unit 120. The isolation unit 140 receives the second voltage control signal output by the control signal processing unit 120 through the control terminal. When the second voltage control signal is a high-level signal, the isolation unit 140 is turned on, so that when the second switch subunit 112 is turned off, a current path is formed between the isolation unit 140 and the first signal terminal A1, so that the corresponding parasitic current flows directly to ground. Similarly, when the fourth switch subunit 114 is turned off, a current path is formed between the isolation unit 140 and the third signal terminal A3, so that the corresponding parasitic current also flows directly to ground.

[0068] In one embodiment, such as Figures 5 to 7 As shown in any of the figures, the control signal processing unit 120 includes a first inverter D1 and a second inverter D2 that are electrically connected. The first inverter D1 is used to receive a first voltage control signal generated by an external control terminal to generate a second voltage control signal, and output the second voltage control signal to the first boost unit 130.

[0069] The second inverter D2 is used to output a first voltage control signal to the control terminal 13 of the first switching subunit 111 and the first boost unit 130 according to the second voltage control signal output by the first inverter D1.

[0070] In addition, such as Figure 8 As shown, a chip 200 is also provided. The chip 200 includes an analog circuit unit 210, at least one of the above-mentioned anti-backflow switch circuits 100, and at least one input / output interface (I / O). Each input / output interface (I / O) is connected to an anti-backflow switch circuit 100 to form a path with the analog circuit unit 210. The anti-backflow switch circuit 100 is used to shut down when the analog function of at least one input / output interface (I / O) is not in use, so as to isolate the analog circuit unit 210.

[0071] For the sake of simplicity, Figure 8 The diagram only shows one backflow prevention switch circuit 100 and one corresponding input / output interface (I / O).

[0072] When the analog function of any input / output interface I / O is not used, the current path between the input / output interface I / O and the analog circuit unit 210 can be completely shut off by the corresponding anti-backflow switch circuit 100 to achieve a good isolation effect.

[0073] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0074] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0075] In this application, the word "for example" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "for example" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to make and use it. Various details are set forth in the above description for purposes of explanation.

[0076] It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A backflow prevention switch circuit, characterized in that, The backflow prevention switch circuit includes: A controllable switching unit includes a first switching subunit and a second switching subunit connected in parallel. The first terminal of the first switching subunit and the first terminal of the second switching subunit are electrically connected and serve as a first signal terminal. The second terminal of the first switching subunit and the second terminal of the second switching subunit are electrically connected and serve as a second signal terminal. The first switching subunit uses an NMOS transistor, and the second switching subunit uses a PMOS transistor; or, the first switching subunit uses an NPN transistor, and the second switching subunit uses a PNP transistor. The control signal processing unit is electrically connected to the control terminal of the first switch subunit and has a first electrical connection and a second electrical connection with the first boost unit, respectively. It is used to output a first voltage control signal to the control terminal of the first switch subunit according to the input external control signal, output the first voltage control signal to the first boost unit through the first electrical connection, and output a second voltage control signal to the first boost unit through the second electrical connection. The first voltage control signal and the second voltage control signal are electrically opposite. The first boost unit is electrically connected to the control terminal and the first signal terminal of the second switch subunit. When the first voltage control signal is a preset level signal, it adjusts the voltage of the control terminal of the second switch subunit to be the same as the voltage of the first signal terminal according to the first voltage control signal and the second voltage control signal to turn off the second switch subunit.

2. The anti-backflow switch circuit according to claim 1, characterized in that, The controllable switch unit further includes a third switch subunit and a fourth switch subunit connected in parallel. The third switch subunit has the same circuit structure as the first switch subunit, and the fourth switch subunit has the same circuit structure as the second switch subunit. The first terminal of each of the third and fourth switch subunits is electrically connected to the second signal terminal. The second terminal of the third switch subunit and the second terminal of the fourth switch subunit are electrically connected and serve as the third signal terminal. The control signal processing unit is electrically connected to the control terminal of the third switch subunit to output the first voltage control signal. The control signal processing unit is also used to establish an electrical connection with the control terminal of the fourth switch subunit to output the second voltage control signal. The backflow prevention switch circuit also includes an isolation unit. The first end of the isolation unit is electrically connected to the second signal terminal, and the second end of the isolation unit is grounded. The control signal processing unit is electrically connected to the control terminal of the isolation unit to output the second voltage control signal.

3. The anti-backflow switch circuit according to claim 2, characterized in that, The anti-backflow switch circuit also includes a second boost unit; The control signal processing unit is also used to disconnect the electrical connection with the control terminal of the fourth switch subunit, and establish a third electrical connection and a fourth electrical connection with the second boost unit respectively, so as to output the first voltage control signal to the second boost unit through the third electrical connection and output the second voltage control signal to the second boost unit through the fourth electrical connection; The second boost unit is electrically connected to the control terminal of the third signal terminal and the control terminal of the fourth switch subunit, respectively. When the first voltage control signal is a preset level signal, it adjusts the voltage of the control terminal of the fourth switch subunit to be the same as the voltage of the third signal terminal according to the first voltage control signal and the second voltage control signal so that the fourth switch subunit is turned off.

4. The anti-backflow switch circuit according to claim 3, characterized in that, The first boost unit includes a fifth switch subunit, a sixth switch subunit, a seventh switch subunit, and an eighth switch subunit. The first terminals of the fifth and sixth switch subunits are each electrically connected to the first signal terminal. The second terminal of the fifth switch subunit is electrically connected to the control terminal of the second switch subunit, the control terminal of the sixth switch subunit, and the first terminal of the seventh switch subunit. The second terminal of the sixth switch subunit is electrically connected to the control terminal of the fifth switch subunit and the first terminal of the eighth switch subunit. The control signal processing unit and the control terminal of the seventh switch subunit have a second electrical connection, and the control signal processing unit and the control terminal of the eighth switch subunit have a first electrical connection. The second terminals of the seventh and eighth switch subunits are both grounded.

5. The anti-backflow switch circuit according to claim 4, characterized in that, The second boost unit has the same circuit structure as the first boost unit.

6. The anti-backflow switch circuit according to claim 4, characterized in that, The fifth and sixth switch subunits both use PMOS transistors, while the seventh and eighth switch subunits both use NMOS transistors.

7. The anti-backflow switch circuit according to claim 4, characterized in that, The fifth and sixth switch subunits both use PNP transistors, while the seventh and eighth switch subunits both use NPN transistors.

8. The anti-backflow switch circuit according to claim 2, characterized in that, The isolation unit uses an NMOS transistor.

9. The anti-backflow switch circuit according to claim 1, characterized in that, The control signal processing unit includes a first inverter and a second inverter that are electrically connected. The first inverter is used to receive a first voltage control signal generated by an external control terminal to generate a second voltage control signal, and output the second voltage control signal to the first boost unit. The second inverter is used to output the first voltage control signal to the control terminal of the first switching subunit and the first boost unit.

10. A chip, characterized in that, The chip includes an analog circuit unit, at least one anti-backflow switch circuit according to any one of claims 1 to 9, and at least one input / output interface, wherein each input / output interface is correspondingly connected to an anti-backflow switch circuit to form a path with the analog circuit unit, and the anti-backflow switch circuit is used to shut down when the analog function of at least one input / output interface is not in use, so as to isolate the analog circuit unit.

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