Separation method and assembly for chip-on-wafer processing

Abstract

The present disclosure relates to a separation method and assembly for chip-on-wafer processing. A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, partition walls are arranged in a pattern on a first surface of a device wafer so that areas between the partition walls define mounting locations. The die stacks are mounted to the device wafer, wherein each die stack is located at a corresponding mounting location between the partition walls. The device wafer is cut through from a second surface opposite to the first surface of the device wafer, and the partition walls are removed from between the die stacks to form an empty channel between adjacent die stacks.

Description

Technical Field

[0001] The present technology relates to semiconductor device packaging. More specifically, some embodiments of the present technology relate to techniques for holding a die stack in place to reduce damage to the die during dicing. Background Art

[0002] Semiconductor die including memory chips, microprocessor chips, logic chips and imager chips are usually assembled by mounting multiple semiconductor die individually or in a die stack in a grid pattern on a substrate. The mounted die stack is then loaded into a polymeric material (e.g., resin) in a wafer-level molding process. As more die are stacked together to increase capacity, the height of the die stack increases. This may cause the wafer to bend after the molding process, which in turn may cause the die stack to shift position, making them improperly aligned when cutting. Therefore, when a rotating blade is used to separate the die stack, chipping or cracking may occur along the edge of the die. Summary of the invention

[0003] In one aspect, the present disclosure relates to a method for separating semiconductor die stacks of chip components on a wafer, comprising: arranging partition walls in a pattern on a first surface of a device wafer so that areas between the partition walls define mounting positions; mounting the die stacks to the device wafer, wherein each die stack is located at a corresponding mounting position between the partition walls; cutting through the device wafer from a second surface opposite to the first surface of the device wafer; and removing the partition walls from between the die stacks to form empty channels between adjacent die stacks.

[0004] On the other hand, the present disclosure relates to a method for separating semiconductor die stacks of chip-on-wafer components, comprising: mounting a carrier wafer on a second surface of a device wafer; mounting a die stack to a first surface of the device wafer, the die stack having channels between them defining a pattern of crossing lines; dispensing partition wall material into the channels between the die stacks to form partition walls; and cutting through the device wafer from the second surface to the first surface of the device wafer to separate the die stacks.

[0005] On the other hand, the present disclosure relates to a chip-on-wafer (COW) component, comprising: a device wafer having a first surface and a second surface opposite to the first surface; die stacks mounted to the first surface of the device wafer in a pattern, wherein each die stack is located at a corresponding mounting position, wherein each of the die stacks includes at least one semiconductor die; and partition walls forming intersection lines of the pattern between the die stacks on the first surface of the device wafer, the partition walls comprising a partition wall material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Many aspects of the present technology may be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale. Instead, emphasis is placed on illustrating the principles of the present technology.

[0007] Figure 1A is a cross-sectional view of a die stack attached to a device wafer with separation walls between die stacks in a chip-on-wafer (COW) assembly in accordance with the present technology.

[0008] Figure 1B According to this technology Figure 1A Cross-sectional view of a two-die stack of a COW assembly.

[0009] Figure 2 is a cross-sectional view of a COW assembly after separation walls have been formed on the surface of a device wafer but before a die stack has been placed on the device wafer in accordance with the present technology.

[0010] Figure 3 is a top view of partition walls arranged in a grid pattern according to the present technology.

[0011] Figure 4A A cross-sectional view of an example of an overmolded COW assembly in accordance with the present technology is shown.

[0012] Figure 4B It shows that according to the present technology Figure 4A Part of the overmolded COW assembly.

[0013] Figure 5 Shown is a cross-sectional view of an overmolded COW component with a portion of the molding material removed in accordance with the present technology.

[0014] Figure 6 A cross-sectional view of a COW assembly according to the present technique is shown, wherein the partition walls have been removed.

[0015] Figure 7 The following diagram shows the removal of the partition wall and the carrier wafer according to the present technology. Figure 6 A cross-sectional view of a COW assembly with reversed orientation is shown.

[0016] Figure 8 It shows that according to the present technology Figure 5 A cross-sectional view of a COW assembly with reversed orientation is shown, ready for dicing.

[0017] Fig. 9 shows a device wafer after it has been cut from the back side with the partition walls remaining in place according to the present technology Figure 8 COW components.

[0018] Fig.10 is a flow chart of a method for separating a die stack of a COW assembly according to the present technology. DETAILED DESCRIPTION

[0019] The specific details of several embodiments for preventing wafer bending and cutting defects of chip on wafer (COW) packaging are described below. In one example, a method for separating semiconductor die stacks in a COW assembly includes arranging partition walls in a pattern (e.g., a grid) on a first surface of a device wafer so that the area between the partition walls defines the mounting position. The method also includes installing each die stack at a corresponding mounting position so that each die stack is separated from each other by the partition wall. The die stack may be separated from the partition wall by a gap, and the partition wall may have the same height as the die stack or be higher than the die stack. Then, the die stack and the partition wall are loaded into a polymer material that covers the die stack and fills the gap between the die stack and the partition wall. The partition wall suppresses the bending of the device wafer and maintains the orientation of the die stack. Then, the die stacks are separated from each other by etching or dissolving the partition wall. For example, the partition wall may be made of a material that is soluble in water or another solvent, so that a saw is not required to cut the die stacks from each other. Therefore, COW is expected to have less damage to the die caused by dicing (if any).

[0020] Figure 1A 1 is a cross-sectional view of a COW assembly 10 having a device wafer 104, partition walls 130 arranged in a grid array on the device wafer 104, and die stacks 106 (identified as 106a, 106b, and 106c, respectively) mounted on the device wafer 104 at mounting locations in the areas between the partition walls 130. In most applications, several hundred die stacks 106 are mounted on the device wafer 104 for packaging.

[0021] At this stage of packaging COW assembly 10, temporary carrier wafer 100 supports and protects device wafer 104 during processing. More specifically, second side 136 of device wafer 104 is attached to carrier wafer 100 by adhesive 102. Carrier wafer 100 may be silicon (Si), glass, or other suitable material. Then, partition walls 130 and die stacks 106 are attached to device wafer 104. Die stacks 106 may each have several individual semiconductor dies 110. Figure 1A In the embodiment illustrated in , die stacks 106 may each include four dies 110 (individually identified as dies 110a-d), but it should be understood that die stacks 106 may have any number of dies (e.g., 2, 3, 4, 5, 6, 7, 8, 10, 12, or more) based on the requirements of the system. Die 110 may be a memory die, including any known type of memory die.

[0022] The device wafer 104 may be a silicon wafer having one or more through silicon vias (TSVs) 107 extending therethrough, to which solder balls, pillars, and pads (not shown) may be attached at the second surface 136. Thus, the device wafer 104 may be used as an interposer. In other embodiments, the device wafer 104 may itself have dies, such as logic dies, processors, or other types of dies for operating the memory die 110.

[0023] The die stack 106 may be formed on the device wafer 104 by attaching the die 110a to the device wafer 104, and then stacking the dies 110b-d in series with each other to form the die stack 106 at the appropriate location on the device wafer 104. Alternatively, the dies 110a-d may be stacked together while separate from the device wafer 104, and then the die stack 106 may be attached to the device wafer 104.

[0024] Figure 1B A portion of the COW assembly 10 including die stacks 106a and 106b is shown in more detail. The die stack 106 may have a non-conductive film (NCF) 120 between the die 110a and the device wafer 104 and between each of the die 110a-d to adhere the die 110a-d to the device wafer 104 and to each other. The NCF 120 under the die 110a may be the same or different from the NCF 120 between the die 110a-110d. Other materials such as bottom fill materials may be used in place of the NCF 120. The die 110a-d are also electrically connected to each other and to the device wafer 104 by conductive pillars or bumps (not shown), which are arranged to correspond to an array of TSVs and / or an array of ball pads between each of the components.

[0025] The die stack 106 is connected through a channel 112 (also in Figure 1A The width of the channels 112 may be uniform to precisely separate the die stacks 106 from each other. In another embodiment, the widths of some of the channels 112 may be different relative to each other.

[0026] At this stage of processing the COW assembly 10, the partition wall 130 may occupy the channel 112 so that one side 142 of the die stack 106a contacts one side of the partition wall 130, thereby forming an integral interface, and one side 144 of the adjacent die stack 106b contacts the other side of the same partition wall 130, thereby forming another integral interface. In some embodiments, the partition wall 130 may be formed by dispensing the partition wall material into the channel 112 between the die stacks 106 after the die stacks 106 have been mounted to the device wafer 104. For example, the partition wall 130 may be formed in situ on the device wafer 104 using inkjet printing, 3D printing, mask printing, or other suitable processes. In other embodiments, the partition wall 130 may be preformed as a complete unit or independent wall separated from the device wafer 104. For example, a sheet of the partition wall material may be processed to form a specific pattern of mounting locations having a predetermined size. Alternatively, the partition wall material may be dispensed into a mold and then dried (cured) to have a desired configuration. The preformed partition walls may then be adhered to the device wafer 104 before mounting the die stack 106 to the device wafer 104. In one embodiment, the partition walls 130 may be glued or adhered to the first surface 138 ( Figure 1A In some embodiments, the partition walls 130 may prevent the NCF 120 from extending into the channels 112 between adjacent die stacks 106 .

[0027] The partition wall material is soluble in water or other solvents, or the partition wall material can be carbon-based, silicon (Si) or other materials suitable for dry etching removal. The example of a water-soluble partition wall material is HogoMax. The examples of other solvent-soluble partition wall materials are Brewer Science Wafer Bond HT-10.10 and Nissan Chemical NAD7009. In other examples, the dry-etchable partition wall material can include transparent carbon and polyimide. The materials suitable for use as partition wall materials are not limited to these examples.

[0028] Figure 2 is a cross-sectional view of the COW assembly 10 at a processing stage after the partition walls 130 have been formed on the first surface 138 of the device wafer 104 , but before the die stack 106 has been placed on the device wafer 104 . Figure 3 1 is a top view of the grid 140 of the partition wall 130 according to the present technology. Figure 2 and Figure 3 The grid 140 of the partition wall 130 defines a first dimension W configured to receive the die stack 106. S1 (only Figure 3) and the second dimension W S2 The mounting area 146 is generally configured to receive one or more die stacks 106. For example, the mounting area 146 may be a straight line (eg, square or rectangular) to accommodate the footprint of the die stack 106.

[0029] The grid pattern 140 may be formed by a plurality of intersecting lines configured to reside in the channels 112 between the die stacks 106. Figure 3 As shown, substantially parallel lines extending along the first direction 174 may intersect substantially parallel lines extending along the second direction 176 at a 90 degree angle. The partition wall 130 may have a width W W (See Figure 2 ), which may be wide enough to contact the sides of the adjacent die stack 106, as previously discussed. In another embodiment, the width W W may be smaller than the channel 112 ( Figure 1B ) in width, thereby leaving a space or gap between the die stack 106 and the partition wall 130.

[0030] The partition wall 130 may have a shape corresponding to the die stack 106 ( Figure 1B ) s Height H w (See Figure 2 In some embodiments, the partition wall height H of the partition wall 130 is w Can be equal to the die stack height H s , while in other embodiments, the partition wall height H w Can be smaller or larger than the die stack height H s .

[0031] In some embodiments, as described above, the grid 140 of the partitions 130 may be a preformed component that is cut, molded, built up from layers, or otherwise formed separately to provide the grid pattern 140. The preformed grid 140 may be adhered to the device wafer 104 before the die stack 106 is attached to the device wafer 104, or alternatively, the preformed grid 140 may be attached to the device wafer 104 after some or all of the die stacks 106 are in place. The preformed grid 140 may be a single piece or multiple pieces.

[0032] Figure 4A A cross-sectional view of another example of an overmolded COW assembly 10 according to the present technology is shown after wafer level molding. Figures 1A-4B1, like reference numerals refer to like components. In this example, a molding material 150 is molded on the die stack 106 and the partition wall 130. The molding material 150 may cover a top surface 158 of the die stack 106 and a top surface of the partition wall 130, as well as the sides of the die stack 106. Thus, the molding material 150 may have outer sides 152 and 154 and a top 156, respectively.

[0033] like Figure 4B As shown in more detail in the figure, the partition wall width W W smaller than the channel width W of the channel 112 between the die stacks 106 L , so that there is a gap between the side of the die stack 106 and the partition wall 130. Therefore, during the molding process, some of the molding material 150 may flow in the gap between the side of the die stack 106 and the partition wall 130 to form side portions 157 (individually labeled as 157a and 157b) of the molding material 150.

[0034] Figure 5 A cross-sectional view of the overmolded COW component 10 is illustrated after a portion of the molding material 150 has been removed to expose the partition wall 130 in accordance with the present technology. The molding material 150 above the uppermost die 110d can be removed while leaving at least a portion of the molding material 150 along the outer sides 152 and 154. The molding material 150 can be completely removed from the top of the die stack 106, or a thin layer of the molding material 150 can remain on top of the uppermost die 110d. In some embodiments, a small amount of the uppermost die 110d can also be removed. This thinning process can be used to bring the die stack 106 to a desired thickness or height H S The partition walls 130 are exposed. The molding material 150 may be removed using back grinding, chemical mechanical planarization, or other suitable processes. The partition walls 130 between the die stacks 106 may inhibit flexing or bending of the COW assembly 10 during the overmolding process and when the COW assembly 10 cools after the overmolding process.

[0035] Figure 6A cross-sectional view of the COW assembly 10 after the partition wall 130 has been removed to open the channel 112 between the die stacks 106 to form an empty channel between adjacent die stacks 106 is shown. The partition wall 130 can be removed before the COW assembly 10 is attached to the dicing frame and removed from the carrier wafer 100. The partition wall 130 can be removed without sawing or mechanically cutting the partition wall material. For example, water or other solvents can be used to dissolve the partition wall material in a wet process or wet cleaning. For example, a solvent can be used to remove a photosensitive material or a temporary adhesive. In other embodiments, if the partition wall material is an organic carbon-based material, plasma etching can be used to remove the partition wall material. Other materials can be used for the partition wall material, such as a laser ablated material. In each of these cases, the partition wall 130 is chemically removed or thermally removed without a rotating blade or other mechanical cutting device. Therefore, the die stack can be separated into individual units without chipping or cracking the edges of the die 110.

[0036] Figure 7 Shown with Figure 5 and 6 1. A cross-sectional view of the COW assembly 10 in the reverse orientation in FIG. 1. At this stage of packaging the COW assembly 10, the tape film or carrier film 200 supported by the dicing frame 202 has been attached to the top surface 178 of the die stack 106, and the carrier wafer 100 has been removed. The back side 180 (e.g., Figure 7 The device wafer 104 is cut (with the upper surface facing upward in the middle) to form a space 212 that is at least approximately aligned with the channel 112 between the tube core stacks 106. The space 212 extends through the thickness "T" of the device wafer 104 to completely separate the tube core stacks 106 from each other. The device wafer 104 can be cut using a laser, a rotary saw, or other suitable technology to cut through the thickness T of the device wafer 104 without penetrating the tube core 110a. Therefore, when cutting the device wafer 104, the blade does not cut along the side of the tube core stack 106. Because the partition wall 130 has been removed, it is not necessary to cut below the thickness T of the device wafer 104 in some embodiments. Therefore, it is expected that the method of the present technology reduces the chipping of the tube core 110a-d.

[0037] Figure 8 and 9 Shows Figure 6 and 7 Another embodiment of the stage shown, wherein Figure 5 The COW assembly 10 shown has been connected to the carrier film 200, and the carrier wafer 100 has been removed before the partition wall 130 is removed. Figure 8 As shown, the COW component 10 and Figure 5 The orientation shown is reversed, with the separation walls 130 and die stack 106 contacting the carrier film 200 . Fig. 9 Shown is a view from the back side 220 (e.g., Fig. 9 The COW assembly 10 after dicing the device wafer 104 (the upward-facing surface in FIG. 1 ) to form the spacers 212 at least approximately aligned with the partition walls 130. The device wafer 104 may be diced as described above, such as by using a laser or a rotating blade to cut through only the thickness T of the device wafer 104. After the spacers 212 are formed in the device wafer 104, the partition walls 130 may be removed using a wet process or dry etching to open the channels 112 between the die stacks 106 (e.g., similar to Figure 7 112 shown). When the partition wall 130 is made of a water-soluble material, the wet process will also remove debris caused by cutting the device wafer 104 from the surface 222 of the device wafer 104. Therefore, the final cleaning of the COW assembly 10 can be completed at the dicing tool. This embodiment provides the advantage of not adding additional cleaning steps.

[0038] Figure 8 and 9 One expected advantage of the illustrated embodiment is that maintaining the partition walls 130 until the device wafer 104 is cut provides additional structural support to the COW assembly 10 to avoid bending or warping. It is also expected that the additional structural support provided by the partition walls 130 prevents or at least inhibits cracking and / or breaking of the device wafer 104 during peeling of the carrier wafer 100. In addition, the partition walls 130 may also protect the sides of the die stack 106 from cracking or breaking while the device wafer 104 is being cut.

[0039] Fig.10 1 is a flow chart of a method 1000 for processing a COW component 10 according to the present technology. The method 1000 includes applying a partition wall 130 and attaching a die stack 106 to a device wafer 104 (block 1010). The partition wall 130 may be applied to the device wafer 104 before or after the die stack 106 is attached to the device wafer 104. Then, a molding material is molded on the die stack 106 and the device wafer 104 (block 1020), and the upper portion of the molding material 150 is thinned, such as by back grinding (block 1030). After the molding material is thinned, there are two options. Option 1 includes removing the partition wall material (block 1040) and then dicing the device wafer 104 from the back (block 1042). Option 2 alternatively includes attaching the COW assembly 10 to the carrier tape 200 and removing the carrier wafer 100 (block 1050 ), dicing the device wafer 104 from the backside before removing the partition walls 130 (block 1052 ), and then removing the partition walls 130 (block 1054 ).

[0040] The present invention is not intended to be exhaustive or limit the present technology to the precise form disclosed herein. Although specific embodiments are disclosed herein for the purpose of illustration, various equivalent modifications are possible without departing from the present technology as will be appreciated by those skilled in the relevant art. In some cases, well-known structures and functions are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although the steps of the method may be presented in a particular order herein, alternative embodiments may perform these steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of a particular embodiment may be combined or removed in other embodiments. In addition, although advantages associated with certain embodiments of the present technology have been disclosed in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments must exhibit such advantages or other advantages disclosed herein that fall within the scope of the present technology. Therefore, the present disclosure and related technologies may encompass other embodiments not explicitly shown or described herein.

[0041] Throughout the present invention, the singular terms "a / an" and "the" include plural indicators unless the context clearly indicates otherwise. Similarly, unless the word "or" is explicitly limited to only represent a single item exclusive with other items when referring to a list of two or more items, the use of "or" in such a list will be interpreted as including any single item in (a) the list, all items in (b) the list, or any combination of items in (c) the list. In addition, the term "including" is used throughout the text to indicate that at least the described features are included, so that additional types of any greater number of the same features and / or other features are not excluded. References to "one embodiment", "some embodiments" or similar expressions herein mean that the specific features, structures, operations or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present technology. Therefore, the appearance of these phrases or expressions herein does not necessarily all relate to the same embodiment. In addition, various specific features, structures, operations or characteristics may be combined in one or more embodiments in any suitable manner.

[0042] From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without departing from the scope of the invention.The technology is not to be limited, except in the appended claims.

Claims

1. A method for separating a semiconductor die stack of a chip assembly on a wafer, comprising: mounting a carrier wafer on the second surface of the device wafer; arranging partition walls in a pattern on a first surface of the device wafer such that areas between the partition walls define mounting locations, the first surface being opposite the second surface; mounting the die stacks to the first surface of the device wafer after arranging the partition walls, wherein each individual one of the die stacks is located at a respective mounting location between the partition walls; removing the carrier wafer from the second surface of the device wafer; cutting through the device wafer from the second surface after removing the carrier wafer from the device wafer; as well as After cutting through the device wafer, the separation walls are removed from between the die stacks, thereby forming empty channels between adjacent pairs in the die stacks. 2 . The method of claim 1 , wherein the partition walls are disposed on the first surface of the device wafer before mounting the die stack.

3. The method according to claim 1, further comprising: preforming the partition walls into the pattern before arranging the partition walls on the first surface of the device wafer; as well as The partition wall is adhered to the first surface of the device wafer. 4 . The method of claim 1 , further comprising molding a molding material on top surfaces of each of the die stacks and the partition walls, and wherein the cutting through the device wafer is accomplished after applying the molding material. The method of claim 1 , wherein the partition walls have a height greater than a height of the die stack.

6. The method of claim 1 , wherein the width of the partition wall between each of the die stacks is less than the distance between the die stacks, the method further comprising molding a molding material over each of the die stacks and a top surface of the partition wall, the molding material extending between the partition wall and a side of each of the die stacks.

7. The method of claim 1, wherein the partition wall is water-soluble, solvent-soluble, or removable using an etching process.

8. The method according to claim 1, further comprising: molding a molding material over each of the die stacks and a top surface of the partition wall; as well as At least the molding material is thinned to expose at least a top surface of the partition wall.

9. The method of claim 1, wherein the partition wall forms an integral interface with at least one side of an adjacent die stack.

10. A method for separating a semiconductor die stack of a chip assembly on a wafer, comprising: mounting a carrier wafer on the second surface of the device wafer; dispensing a partition material into the intersections of the pattern to form partitions on the first surface of the device wafer; mounting the die stack to the first surface of the device wafer after dispensing the partition wall material, the die stack having vias therebetween defining the cross-wires of the pattern; separating the carrier wafer from the device wafer; after separating the carrier wafer from the device wafer, cutting through the device wafer from the second surface to the first surface of the device wafer; as well as After cutting through the device wafer, the partition walls are removed. 11 . The method of claim 10 , further comprising removing the partition wall using water, a solvent, dry etching or plasma etching.

12. The method according to claim 10, further comprising: Prior to removing the carrier wafer, a carrier film is applied on the top surface of the die stack, the carrier film being attached to a dicing frame. 13 . The method of claim 10 , further comprising applying a molding material over top surfaces of each of the die stacks and the partition walls, wherein the molding material does not extend between each of the die stacks and the partition walls. 14 . The method of claim 10 , further comprising applying a molding material over top surfaces of each of the die stacks and the partition walls, wherein the molding material forms side portions between each of the die stacks and the partition walls.

Images