A high-pixel capacitance electronic paper panel and manufacturing method thereof

Abstract

The present invention discloses an electronic paper panel with high pixel capacitance and a manufacturing method thereof, wherein the electronic paper panel comprises: a substrate; a gate layer and a second pixel electrode are arranged at intervals on the substrate; an insulating layer is arranged above the gate layer and the second pixel electrode, a source layer, a drain layer and a semiconductor layer matching the gate layer are arranged in the insulating layer, and a common electrode is arranged in the insulating layer above the second pixel electrode; a first pixel electrode is arranged above the insulating layer, and a first via hole for connecting the first pixel electrode and the drain layer and a second via hole for connecting the first pixel electrode and the second pixel electrode are arranged in the insulating layer. The present invention increases the pixel capacitance by adding a second pixel electrode on a substrate of the same area and connecting it to the first pixel electrode at the same time, so that the common electrode can form a pixel capacitance with the first pixel electrode and the second pixel electrode.

Description

Technical Field

[0001] The present invention relates to the field of electronic paper display, and in particular to an electronic paper panel with high pixel capacitance and a manufacturing method thereof. Background Art

[0002] The electronic paper display mode is different from the conventional LCD liquid crystal. Its refresh frequency is very low, but the pixel needs to maintain the potential for a long time after charging, so the pixels of the electronic paper panel usually need to be designed with a larger pixel capacitor. The current conventional design is that the first metal layer is used as the common electrode, and the second metal layer (thin film transistor layer) and the pixel ITO (indium oxide material, Indium Tin Oxide, referred to as ITO) are connected through vias as pixel electrodes. A pixel capacitor is formed between the pixel electrode and the common electrode to store charge. When the pixel size is small, the area of ​​the first metal layer and the second metal layer used as the capacitor part is limited, and there may be insufficient capacitance. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide an electronic paper panel with high pixel capacitance, so as to solve the problem of insufficient pixel capacitance of conventional electronic paper panels when the pixel size is small.

[0004] The technical solution adopted by the present invention to solve the above-mentioned problem is as follows: the electronic paper panel comprises: a substrate; a gate layer and a second pixel electrode are arranged on the substrate at intervals; an insulating layer is arranged above the gate layer and the second pixel electrode, a source layer, a drain layer and a semiconductor layer matching the gate layer are arranged in the insulating layer, the source layer and the drain layer are respectively connected to the two sides of the semiconductor layer, and a common electrode is arranged in the insulating layer above the second pixel electrode; a first pixel electrode is arranged above the insulating layer, and a first via hole for connecting the first pixel electrode and the drain layer and a second via hole for connecting the first pixel electrode and the second pixel electrode are arranged in the insulating layer.

[0005] Compared with the prior art, the advantages of the present invention are: on a substrate of the same area, by adding a second pixel electrode and connecting it to the first pixel electrode, the common electrode can form a pixel capacitor with the first pixel electrode and the second pixel electrode, thereby increasing the size of the pixel capacitor; at the same time, the first pixel electrode and the second pixel electrode are respectively arranged on the upper and lower sides of the common electrode to avoid interference between the first pixel electrode and the second pixel electrode.

[0006] Preferably, the insulating layer includes a first insulating layer, and the first insulating layer is arranged between the second pixel electrode and the common electrode, between the source electrode layer and the substrate, between the drain electrode layer and the substrate, and between the semiconductor layer and the gate layer. In this way, through the arrangement of the first insulating layer, the second pixel electrode and the common electrode can be combined to form a pixel capacitor, thereby increasing the effective area of ​​the overall pixel capacitor and improving the capacitance value of the overall pixel capacitor; at the same time, the connection between the gate layer, the source electrode layer, the drain electrode layer and the semiconductor layer can also be isolated, ensuring that they can work as a thin film transistor.

[0007] Preferably, the insulating layer includes a second insulating layer, and the second insulating layer is arranged between the common electrode and the first pixel electrode and between the source electrode layer, the drain electrode layer and the semiconductor layer and the first pixel electrode. In this way, by arranging the second insulating layer, the common electrode and the first pixel electrode can be combined to form a pixel capacitor, and in combination with the second pixel electrode, a larger effective area of ​​the pixel capacitor can be obtained, thereby increasing the capacitance value of the overall pixel capacitor; at the same time, the second insulating layer is also used to isolate the influence between the source electrode layer, the drain electrode layer and the semiconductor layer and the first pixel electrode.

[0008] Preferably, the insulating layer includes a third insulating layer, and the third insulating layer is arranged between the second insulating layer and the first pixel electrode. Thus, by further adding the third insulating layer, it is ensured that the operation of the thin film transistor will not affect the first pixel electrode.

[0009] Preferably, a through hole is provided in the third insulating layer, the through hole is located above the second insulating layer where the common electrode is located, a thickened first pixel electrode is provided in the through hole, the upper end of the thickened first pixel electrode is connected to the first pixel electrode, and the lower end of the thickened first pixel electrode abuts against the second insulating layer. In this way, the through hole is provided so that the first pixel electrode and the corresponding area of ​​the common electrode can directly abut against each other through the second insulating layer, thereby reducing the distance between the first pixel electrode and the drain layer and the common electrode, and increasing the capacitance value of the pixel capacitor.

[0010] Preferably, the first via hole and the second via hole are arranged on the second insulating layer, the first via hole is used to connect the thickened first pixel electrode above the second insulating layer and the drain layer below the second insulating layer, and the second via hole is used to connect the thickened first pixel electrode above the second insulating layer and the second pixel electrode below the second insulating layer. In this way, the first via hole and the second via hole are directly arranged in the second insulating layer, reducing the number of via hole arrangements and facilitating manufacturing.

[0011] Preferably, the common electrode is located directly above the second pixel electrode, and any cross-sectional area of ​​the common electrode is smaller than any cross-sectional area of ​​the second pixel electrode. In this way, the area of ​​the second pixel electrode is larger than that of the common electrode, which can maximize the effective area of ​​the capacitor between the second pixel electrode and the common electrode, and improve the charge storage capacity of the pixel capacitor.

[0012] The second technical problem to be solved by the present invention is to provide a method for manufacturing an electronic paper panel with high pixel capacitance, so as to solve the problem of insufficient pixel capacitance of conventionally designed electronic paper panels when the pixel size is small.

[0013] The technical solution adopted by the present invention to solve the above problem is: a method for manufacturing an electronic paper panel with high pixel capacitance, comprising the following steps:

[0014] S1, providing a substrate, and forming a gate layer and a second pixel electrode on the substrate at intervals;

[0015] S2, disposing a first insulating layer on the gate layer and the second pixel electrode; disposing a semiconductor layer on the first insulating layer where the gate layer is located;

[0016] S3, forming a common electrode on the first insulating layer where the second pixel electrode is located, and forming a source electrode layer and a drain electrode layer on the semiconductor layer, wherein the source electrode layer is connected to one side of the semiconductor layer, and the drain electrode layer is connected to the other side of the semiconductor layer;

[0017] S4, forming a second insulating layer on the common electrode, the source electrode layer, the drain electrode layer and the semiconductor layer, forming a first via hole connected to the drain electrode layer in the second insulating layer, and forming a second via hole connected to the second pixel electrode in the second insulating layer;

[0018] S5. Form a first pixel electrode on the second insulating layer, wherein the first pixel electrode is connected to the drain electrode layer through a first via hole, and the first pixel electrode is connected to the second pixel electrode through a second via hole.

[0019] In this way, without changing the usual mask process and technology of the electronic paper panel, the pixel capacitance can be greatly improved. A second pixel electrode is added to form a pixel capacitor with the common electrode to improve the charge storage capacity of the pixel capacitor; the common electrode is changed from being arranged in the same layer as the gate layer to being arranged in the same layer as the source layer and the drain layer, giving the second pixel electrode space to occupy, and at the same time making full use of the upper and lower sides of the common electrode. The upper side of the common electrode forms a pixel capacitor with the first pixel electrode, and the lower side of the common electrode forms a pixel capacitor with the second pixel electrode, thereby increasing the effective area of ​​the pixel electrode and increasing the utilization rate.

[0020] Preferably, a third insulating layer is first formed on the second insulating layer, and then the first pixel electrode is formed on the third insulating layer. In this way, by further adding the third insulating layer, it is ensured that the operation of the thin film transistor affects the first pixel electrode.

[0021] Preferably, the third insulating layer is formed with a through hole on the second insulating layer where a part or all of the drain layer is located, and the third insulating layer is also formed with a through hole on the second insulating layer where a part or all of the common electrode is located, and the first pixel electrode also penetrates through the through hole and abuts against the second insulating layer. In this way, the through hole is provided so that the first pixel electrode can directly abut against the corresponding area of ​​the drain layer and the common electrode through the second insulating layer, reducing the distance between the first pixel electrode and the drain layer and the common electrode, and increasing the capacitance value of the pixel capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of the second pixel electrode and the gate layer in the electronic paper panel with high pixel capacitance of the present invention;

[0023] Figure 2 It is a schematic diagram of the structure of the semiconductor layer covering the gate layer in the electronic paper panel with high pixel capacitance of the present invention;

[0024] Figure 3 It is a schematic diagram of the structure of thin film transistors and common electrodes in the electronic paper panel with high pixel capacitance of the present invention;

[0025] Figure 4 It is a schematic diagram of the connection between the first via hole and the second via hole in the electronic paper panel with high pixel capacitance of the present invention;

[0026] Figure 5 It is a schematic diagram of the connection structure of the third insulating layer in the electronic paper panel with high pixel capacitance of the present invention;

[0027] Figure 6 It is a schematic diagram of the overall structure of the electronic paper panel with high pixel capacitance of the present invention;

[0028] Figure 7 It is a cross-sectional view of an electronic paper panel with high pixel capacitance according to the present invention.

[0029] Explanation of numbers in the figure: 1. substrate, 2. thin film transistor, 21. gate layer, 22. source layer, 23. drain layer, 24. semiconductor layer, 3. second pixel electrode, 4. common electrode, 5. first insulating layer, 6. second insulating layer, 7. third insulating layer, 8. first pixel electrode, 81. thickened first pixel electrode, 91. first via hole, 92. second via hole. DETAILED DESCRIPTION

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. The embodiments of the present invention are further described below in conjunction with the accompanying drawings. Example

[0031] like Figure 1-7 As shown, this embodiment relates to an electronic paper panel with high pixel capacitance, and the electronic paper panel includes:

[0032] substrate1;

[0033] A gate layer 21 and a second pixel electrode 3 are arranged on the substrate 1 in intervals;

[0034] An insulating layer is provided above the gate layer 21 and the second pixel electrode 3, and a source layer 22, a drain layer 23 and a semiconductor layer 24 matching the gate layer 21 are provided in the insulating layer. The semiconductor layer 24 is provided above the gate layer 21, and the source layer 22 and the drain layer 23 are provided above the semiconductor layer 24 and are respectively connected to two sides of the semiconductor layer 24. A common electrode 4 is provided in the insulating layer above the second pixel electrode 3;

[0035] A first pixel electrode 8 is disposed above the insulating layer, a first via hole 91 for connecting the first pixel electrode 8 and the drain layer 23 is disposed in the insulating layer, and a second via hole 92 for connecting the first pixel electrode 8 and the second pixel electrode 3 is also disposed in the insulating layer.

[0036] In the present embodiment, the gate layer 21, the source layer 22, the drain layer 23 and the semiconductor layer 24 are all internal structures of the thin film transistor 2. This internal structure is of conventional design and will not be described here. The thin film transistor 2 and the common electrode 4 are both arranged in the insulating layer, and the two do not overlap and are not connected. Compared with the traditional thin film transistor 2 covering the entire substrate 1, the common electrode 4 is arranged below the thin film transistor 2. The present application is designed in this way, so that the thin film transistor 2 and the common electrode 4 are arranged separately in the same layer, and the common electrode 4 replaces part of the coverage area of ​​the traditional thin film transistor 2, and then the second pixel electrode 3 replaces the position of the traditional common electrode 4, so that the overall thickness of the entire electronic paper panel remains unchanged.

[0037] The drain layer 23 is connected to the first pixel electrode 8 through the first via hole 91. When a positive voltage is input to the gate layer 21 and a voltage is input to the source layer 22, the TFT thin film transistor 2 is turned on to charge the drain layer 23, and the drain layer 23 is connected to the first pixel electrode 8 through the first via hole 91, so that a pixel capacitor is formed between the first pixel electrode 8 and the common electrode 4 to store charge.

[0038] On the substrate 1 with the same area, the effective area of ​​the pixel capacitor is increased by adding the second pixel electrode 3. In the traditional design, the first pixel electrode 8 is connected to the drain layer 23 on the thin film transistor 2 through a via hole, and a pixel capacitor is formed between the common electrode 4 and the first pixel electrode 8, and its effective area is limited.

[0039] In this embodiment, the additional second pixel electrode 3 is arranged on the other side of the common electrode 4, and the second pixel electrode 3 is connected to the first pixel electrode 8 through a via hole, and its effective area includes the pixel capacitance formed between the common electrode 4 and the first pixel electrode 8 and the pixel capacitance formed between the common electrode 4 and the second pixel electrode 3, the effective area is greatly increased, and the capacitance value of the pixel capacitance is also increased. At the same time, the first pixel electrode 8 and the second pixel electrode 3 are respectively arranged on the upper and lower sides of the common electrode 4 to avoid interference between the first pixel electrode 8 and the second pixel electrode 3.

[0040] The insulating layer includes a first insulating layer 5 , which is disposed between the second pixel electrode 3 and the common electrode 4 , between the source layer 22 and the substrate 1 , between the drain layer 23 and the substrate 1 , and between the semiconductor layer 24 and the gate layer 21 .

[0041] The common electrode 4 is insulated from the second pixel electrode 3 by the first insulating layer 5, so as to ensure that a pixel capacitor can be formed between the common electrode 4 and the second pixel electrode 3. Furthermore, the capacitance value of the pixel capacitor formed between the common electrode 4 and the second pixel electrode 3 can be changed by changing the thickness of the first insulating layer 5 between the common electrode 4 and the second pixel electrode 3.

[0042] The electronic paper panel made of high pixel capacitors can ensure the potential is maintained because of sufficient charge storage capacity, and can reliably drive the electronic paper panel to display, thereby ensuring a stable display effect. In this embodiment, the substrate 1 can be a glass substrate.

[0043] At the same time, the first insulating layer 5 can also isolate the connection between the gate layer 21 , the source layer 22 , the drain layer 23 and the semiconductor layer 24 , ensuring that they can work as a thin film transistor 2 .

[0044] In actual design, the first insulating layer 5 between the second pixel electrode 3 and the common electrode 4, the first insulating layer 5 between the source layer 22 and the substrate 1, the first insulating layer 5 between the drain layer 23 and the substrate 1, and the first insulating layer 5 between the semiconductor layer 24 and the gate layer 21 can all be connected as one for easy manufacturing.

[0045] In this embodiment, the gate layer 21 and the second pixel electrode 3 are both directly disposed on the substrate 1. This facilitates fabrication and formation in the same fabrication process and facilitates observation, ensuring that the gate layer 21 and the second pixel electrode 3 do not overlap.

[0046] The insulating layer includes a second insulating layer 6, which is disposed between the common electrode 4 and the first pixel electrode 8 and between the source layer 22, the drain layer 23 and the semiconductor layer 24 and the first pixel electrode 8. The second insulating layer 6 is similar to the first insulating layer 5 and also plays an isolating and insulating role to ensure that the common electrode 4 can form a pixel electrode with the first pixel electrode 8.

[0047] The common electrode 4, the gate layer 21, the source layer 22, the drain layer 23 and the semiconductor layer 24 are all arranged between the first insulating layer 5 and the second insulating layer 6. In the actual production process, for the convenience of design, the second insulating layer 6 and the first insulating layer 5 use the same insulating glue, so that when pressing and manufacturing, the first insulating layer 5 and the second insulating layer 6 can be merged at the commonly connected part, which can wrap the thin film transistor 2 and the common electrode 4 between the two, and the insulation effect is better.

[0048] The insulating layer includes a third insulating layer 7, and the third insulating layer 7 is disposed between the second insulating layer 6 and the first pixel electrode 8. By further adding the third insulating layer 7, it is ensured that the operation of the thin film transistor 2 will not affect the first pixel electrode 8. In order to further improve the insulation, the material of the third insulating layer 7 is different from that of the second insulating layer 6.

[0049] As one of the embodiments, the third insulating layer 7 can be fully covered on the second insulating layer 6, restoring the manufacturing process of the traditional electronic paper panel. In this case, the first via hole 91 and the second via hole 92 not only penetrate the second insulating layer 6, but also need to penetrate the third insulating layer 7 to connect with the first pixel electrode 8.

[0050] As another embodiment, the third insulating layer 7 can partially cover the second insulating layer 6. Specifically, a through hole is provided in the third insulating layer 7, and the through hole is located above the second insulating layer 6 where the common electrode 4 is located. A thickened first pixel electrode 81 is provided in the through hole, and the upper end of the thickened first pixel electrode 81 is connected to the first pixel electrode 8, and the lower end of the thickened first pixel electrode 81 is in contact with the second insulating layer 6. The through hole is also located above the second insulating layer 6 where the drain layer 23 is located. The through hole is provided so that the first pixel electrode 8 can directly contact the corresponding areas of the drain layer 23 and the common electrode 4 through the second insulating layer 6, thereby reducing the distance between the first pixel electrode 8 and the drain layer 23 and the common electrode 4, and improving the capacitance value of the pixel capacitor.

[0051] In the above process, the first via hole 91 and the second via hole 92 are arranged on the second insulating layer 6, the first via hole 91 is used to connect the thickened first pixel electrode 81 above the second insulating layer 6 and the drain layer 23 below the second insulating layer 6, and the second via hole 92 is used to connect the thickened first pixel electrode 81 above the second insulating layer 6 and the second pixel electrode 3 below the second insulating layer 6. The first via hole 91 and the second via hole 92 are directly arranged in the second insulating layer 6, reducing the multi-layer via hole arrangement and facilitating the manufacturing.

[0052] In this embodiment, the common electrode 4 is located directly above the second pixel electrode 3, and any cross-sectional area of ​​the common electrode 4 is smaller than any cross-sectional area of ​​the second pixel electrode 3. By designing in this way, the area of ​​the second pixel electrode 3 is larger than that of the common electrode 4, and the effective area of ​​the capacitor between the second pixel electrode 3 and the common electrode 4 can be maximized, thereby improving the charge storage capacity of the pixel capacitor. Example

[0053] See also Figure 1-7 As shown, a method for manufacturing an electronic paper panel with high pixel capacitance includes the following steps:

[0054] S1. Provide a substrate 1, and form a gate layer 21 and a second pixel electrode 3 on the substrate 1 at intervals.

[0055] This process can be seen in Figure 1 As shown, in order to increase the effective area of ​​the pixel capacitor, the area of ​​the second pixel electrode 3 is as large as possible. The second pixel electrode 3 and the gate layer 21 are collectively referred to as the first metal layer.

[0056] S2, disposing a first insulating layer 5 on the gate layer 21 and the second pixel electrode 3; and disposing a semiconductor layer 24 on the first insulating layer 5 where the gate layer 21 is located.

[0057] This process can be seen in Figure 2 As shown, this step mainly manufactures the first insulating layer 5 and the semiconductor layer 24. Since the first insulating layer 5 has a large area, Figure 2 There is no mark in it.

[0058] S3. A common electrode 4 is formed on the first insulating layer 5 where the second pixel electrode 3 is located, and a source layer 22 and a drain layer 23 are formed on the semiconductor layer 24. The source layer 22 is connected to one side of the semiconductor layer 24, and the drain layer 23 is connected to the other side of the semiconductor layer 24.

[0059] This process can be seen in Figure 3 As shown, the semiconductor layer 24 is mainly used to conduct the source layer 22 and the drain layer 23. The common electrode 4 is disposed on the second pixel electrode 3, and through the first insulating layer 5, the common electrode 4 and the second pixel electrode 3 form a pixel capacitor, increasing the effective area of ​​the pixel capacitor.

[0060] S4, forming a second insulating layer 6 on the common electrode 4, the source layer 22 and the drain layer 23, forming a first via hole 91 connected to the drain layer 23 in the second insulating layer 6, and forming a second via hole 92 connected to the second pixel electrode 3 in the second insulating layer 6.

[0061] This process can be seen in Figure 4 As shown, the first via hole 91, the second via hole 92 and the second insulating layer 6 are mainly formed. Figure 4 There is no mark in it.

[0062] S5 . Form a first pixel electrode 8 on the second insulating layer 6 . The first pixel electrode 8 is connected to the drain layer 23 through the first via hole 91 . The first pixel electrode 8 is connected to the second pixel electrode 3 through the second via hole 92 .

[0063] The specific step S5 includes the following steps:

[0064] S51 , first forming a third insulating layer 7 on the second insulating layer 6 , and then forming a first pixel electrode 8 on the third insulating layer 7 .

[0065] This process can be seen in Figure 5 As shown, a third insulating layer 7 is further fabricated to ensure that the thin film transistor 2 and the common electrode 4 can be isolated and insulated from the first pixel electrode 8 to be fabricated later, and to ensure that the operation of the thin film transistor 2 will not affect the first pixel electrode 8.

[0066] S52. A through hole is formed in the third insulating layer 7 above the second insulating layer 6 where a part or all of the drain layer 23 is located. The third insulating layer 7 also forms a through hole above the second insulating layer 6 where a part or all of the common electrode 4 is located. The first pixel electrode 8 also passes through the through hole and abuts against the second insulating layer 6. The first pixel electrode 8 is connected to the drain layer 23 through the first via hole 91, and the first pixel electrode 8 is connected to the second pixel electrode 3 through the second via hole 92.

[0067] This process can be seen in Figure 6 As shown, the first pixel electrode 8 is on the top and fully covers the layers of structure below, ensuring the maximization of the effective area of ​​the first pixel electrode 8. A through hole is provided so that the first pixel electrode 8 can directly contact the corresponding areas of the drain layer 23 and the common electrode 4 through the second insulating layer 6, reducing the distance between the first pixel electrode 8 and the drain layer 23 and the common electrode 4, and increasing the capacitance value of the pixel capacitor.

[0068] Without changing the usual masking process and technology of the electronic paper panel, the pixel capacitance can be greatly improved. A second pixel electrode 3 is added to form a pixel capacitor with the common electrode 4 to improve the charge storage capacity of the pixel capacitor; the common electrode 4 is changed from being arranged in the same layer with the gate layer 21 to being arranged in the same layer with the source layer 22 and the drain layer 23, giving the second pixel electrode 3 space to occupy, and at the same time making full use of the upper and lower sides of the common electrode 4. The upper side of the common electrode 4 forms a pixel capacitor with the first pixel electrode 8, and the lower side of the common electrode 4 forms a pixel capacitor with the second pixel electrode 3, thereby increasing the effective area of ​​the pixel electrode and increasing the utilization rate.

[0069] In this embodiment, the common electrode 4, the gate layer 21, the source layer 22, the drain layer 23 and the semiconductor layer 24 are arranged between the second insulating layer 6 and the first insulating layer 5 to form an enclosed shape, which has a better insulation effect. At the same time, in order to further improve the bonding between the two, the second insulating layer 6 and the first insulating layer 5 use the same insulating glue. In this way, when the first insulating layer 5 and the second insulating layer 6 are pressed together, the thin film transistor 2 and the common electrode 4 between the two can be wrapped in a shape, which has a better insulation effect.

[0070] In order to further improve the insulation performance, the material of the third insulating layer 7 is different from the material used for the second insulating layer 6 .

[0071] The electronic paper panel is manufactured in this way. Taking the pixel size of 0.138*0.138mm as an example, the conventional pixel capacitor area is 8459um², and the new pixel capacitor effective area is 13015um², which is an increase of 53.86%. If the second insulating layer 6 has the same film thickness as the first insulating layer 5, the pixel storage capacitance is increased by 53.86%.

[0072] The beneficial effects of the present invention are as follows: on a substrate 1 with the same area, by adding a second pixel electrode 3 and connecting it to the first pixel electrode 8 at the same time, the common electrode 4 can form a pixel capacitor with the first pixel electrode 8 and the second pixel electrode 3, thereby increasing the size of the pixel capacitance; at the same time, the first pixel electrode 8 and the second pixel electrode 3 are respectively arranged on the upper and lower sides of the common electrode 4 to avoid interference between the first pixel electrode 8 and the second pixel electrode 3.

[0073] The above description shows and describes several preferred embodiments of the present invention, but as mentioned above, it should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the invention concept described herein through the above teachings or the technology or knowledge of the relevant field. Changes and variations made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

[0074] Although the disclosure is disclosed as above, the protection scope of the disclosure is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the disclosure, and these changes and modifications will fall within the protection scope of the present invention.

Claims

1. An electronic paper panel with high pixel capacitance, characterized in that: The electronic paper panel comprises: substrate(1); A gate layer (21) and a second pixel electrode (3) are arranged on the substrate (1) in a spaced relationship; An insulating layer is provided above the gate layer (21) and the second pixel electrode (3); a source layer (22), a drain layer (23) and a semiconductor layer (24) matching the gate layer (21) are provided in the insulating layer; the source layer (22) and the drain layer (23) are respectively connected to two sides of the semiconductor layer (24); and a common electrode (4) is provided in the insulating layer above the second pixel electrode (3); A first pixel electrode (8) is provided above the insulating layer, and a first via hole (91) for connecting the first pixel electrode (8) and the drain electrode layer (23) and a second via hole (92) for connecting the first pixel electrode (8) and the second pixel electrode (3) are provided in the insulating layer; The insulating layer comprises a first insulating layer (5), and the insulating layer further comprises a second insulating layer (6), wherein the second insulating layer (6) is arranged between the common electrode (4) and the first pixel electrode (8), and between the source electrode layer (22), the drain electrode layer (23), the semiconductor layer (24) and the first pixel electrode (8); The insulating layer further comprises a third insulating layer (7), wherein the third insulating layer (7) is arranged between the second insulating layer (6) and the first pixel electrode (8); A through hole is provided in the third insulating layer (7), the through hole is located above the second insulating layer (6) where the common electrode (4) is located, a thickened first pixel electrode (81) is provided in the through hole, the upper end of the thickened first pixel electrode (81) is connected to the first pixel electrode (8), and the lower end of the thickened first pixel electrode (81) is in contact with the second insulating layer (6); The insulating glue used in both the second insulating layer (6) and the first insulating layer (5) is the same, and the material of the third insulating layer (7) is different from the material used in the second insulating layer (6).

2. The electronic paper panel with high pixel capacitance according to claim 1, characterized in that: The first insulating layer (5) is arranged between the second pixel electrode (3) and the common electrode (4), between the source electrode layer (22) and the substrate (1), between the drain electrode layer (23) and the substrate (1), and between the semiconductor layer (24) and the gate layer (21).

3. The electronic paper panel with high pixel capacitance according to claim 1, characterized in that: The first via hole (91) and the second via hole (92) are arranged on the second insulating layer (6); the first via hole (91) is used to connect the thickened first pixel electrode (81) above the second insulating layer (6) and the drain layer (23) below the second insulating layer (6); and the second via hole (92) is used to connect the thickened first pixel electrode (81) above the second insulating layer (6) and the second pixel electrode (3) below the second insulating layer (6).

4. The electronic paper panel with high pixel capacitance according to claim 1, characterized in that: The common electrode (4) is located directly above the second pixel electrode (3), and any cross-sectional area of ​​the common electrode (4) is smaller than any cross-sectional area of ​​the second pixel electrode (3).

5. A method for manufacturing an electronic paper panel with high pixel capacitance, characterized in that: The steps include: S1, providing a substrate (1), and forming a gate layer (21) and a second pixel electrode (3) on the substrate (1) at intervals; S2, providing a first insulating layer (5) on the gate layer (21) and the second pixel electrode (3); providing a semiconductor layer (24) above the first insulating layer (5) where the gate layer (21) is located; S3, forming a common electrode (4) on the first insulating layer (5) where the second pixel electrode (3) is located, and forming a source electrode layer (22) and a drain electrode layer (23) on the semiconductor layer (24), wherein the source electrode layer (22) is connected to one side of the semiconductor layer (24), and the drain electrode layer (23) is connected to the other side of the semiconductor layer (24); S4, forming a second insulating layer (6) on the common electrode (4), the source electrode layer (22), the drain electrode layer (23) and the semiconductor layer (24), forming a first via hole (91) connected to the drain electrode layer (23) in the second insulating layer (6), and forming a second via hole (92) connected to the second pixel electrode (3) in the second insulating layer (6); S5, forming a first pixel electrode (8) on the second insulating layer (6), wherein the first pixel electrode (8) is connected to the drain electrode layer (23) through a first via hole (91), and the first pixel electrode (8) is connected to the second pixel electrode (3) through a second via hole (92); Firstly, a third insulating layer (7) is formed on the second insulating layer (6), and then a first pixel electrode (8) is formed on the third insulating layer (7); The third insulating layer (7) is formed to form a through hole above the second insulating layer (6) where a partial area or the entire area of ​​the drain electrode layer (23) is located. The third insulating layer (7) is also formed to form a through hole above the second insulating layer (6) where a partial area or the entire area of ​​the common electrode (4) is located. The first pixel electrode (8) also penetrates the through hole and abuts against the second insulating layer (6).

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