Multi-trench Schottky diode

Abstract

A multi-trench Schottky diode comprises a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer is stacked on the semiconductor base layer, and comprises a terminal trench structure, a first trench structure, a second trench structure and a third trench structure. The interlayer dielectric layer is stacked on the epitaxial layer in a terminal region. The first metal layer is stacked on the terminal trench structure and the interlayer dielectric layer, and extends between the second trench structure and the third trench structure. The passivation layer is stacked on the first metal layer and the interlayer dielectric layer. The second metal layer is stacked on the first metal layer and the passivation layer, and extends to the first trench structure. By arranging multiple trench structures in the terminal region, the electric field can be effectively dispersed and the breakdown voltage can be avoided from occurring prematurely.

Description

Technical Field

[0001] The invention relates to a Schottky diode, in particular to a multi-trench Schottky diode with multiple trenches. Background Art

[0002] Generally speaking, an ideal rectifier should have characteristics such as low forward voltage drop, high reverse breakdown voltage and zero leakage current. Among them, Schottky diodes, which use metal-semiconductor junctions as Schottky barriers, have the characteristics of low forward voltage drop and high-speed switching, and are therefore widely used in power rectifier components. However, Schottky diodes still have the disadvantages of low reverse bias voltage and large reverse leakage current, which limits the application of Schottky diodes.

[0003] As mentioned above, Schottky diodes can be mainly divided into traditional planar Schottky diodes and trench Schottky diodes. Planar Schottky diodes are mainly formed by stacking semiconductors and metals layer by layer. It is often necessary to make a trade-off between forward voltage drop and leakage current. Therefore, increasing the breakdown voltage without increasing the leakage current is the main research direction.

[0004] Trench Schottky diodes are mainly made by etching trenches in the silicon crystal layer and then filling them with polysilicon. The polysilicon in the trenches can effectively deplete the drift electrons in the drift region and make the electric field evenly distributed. Compared with traditional planar Schottky diodes, they have lower forward voltage drop (Low VF) and reverse leakage current (Low IR).

[0005] See also Figure 1 , Figure 1 As shown in the figure, a trench Schottky diode PA100 includes a semiconductor base PA1, a back metal layer PA2, an epitaxial layer PA3, a dielectric layer PA4, a first metal layer PA5, a passivation layer PA6 and a second metal layer PA7.

[0006] The back metal layer PA2 is formed on the back side of the semiconductor substrate PA1. The epitaxial layer PA3 is formed on the front side of the semiconductor substrate PA1 and has an adjacent unit cell region PA3a and a terminal region PA3b. The epitaxial layer PA3 also includes a plurality of unit cell structures PA31 (only two are shown in the figure), a terminal groove structure PA32 and a guard ring structure PA33. The plurality of unit cell structures PA31 are located in the unit cell region PA3a at intervals from each other, and the terminal groove structure PA32 is located at the junction of the unit cell region PA3a and the terminal region PA3b, and is spaced apart from the plurality of unit cell structures PA31 adjacent to the terminal region PA3b. The guard ring structure PA33 is adjacent to the terminal groove structure PA32.

[0007] The dielectric layer PA4 is stacked on the terminal trench structure PA32 and the guard ring structure PA33 in the terminal area PA3b. The first metal layer PA5 is stacked on the epitaxial layer PA3 in the cell area PA3a and extends to the dielectric layer PA4 in the terminal area PA3b. The passivation layer PA6 is stacked on the first metal layer PA5 and extends from the cell area PA3a to the dielectric layer PA4 in the terminal area PA3b. The second metal layer PA7 is stacked on the first metal layer PA5 and the passivation layer PA6 and extends from the cell area PA3a to the terminal area PA3b.

[0008] As described above, the existing trench Schottky diode PA100 mainly extends the first metal layer PA5 and the second metal layer PA7 to the terminal area to increase the reverse bias, and provides a guard ring structure PA33 on the epitaxial layer PA3 to disperse the potential. However, due to the limited potential buffering capacity of the guard ring structure PA33, the charge of the trench Schottky diode PA100 is still easily concentrated in the edge terminal area and is prone to premature collapse. Summary of the invention

[0009] In view of the fact that in the prior art, the trench Schottky diode of the prior art extends the first metal layer and the second metal layer to the terminal region in order to increase the reverse bias voltage, but this also makes it easy for surface charges to accumulate on the surface of the epitaxial layer. Although the existing trench Schottky diode is provided with a guard ring structure to prevent drastic changes in potential, its effect is still limited. Therefore, the main purpose of the present invention is to provide a Schottky diode that can reduce the accumulation of surface charges and avoid premature collapse through structural changes.

[0010] The present invention solves the problems of the prior art by adopting a necessary technical means to provide a multi-trench Schottky diode, comprising a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric (ILD), a first metal layer, a passivation layer and a second metal layer.

[0011] The back metal layer is formed on one side of the semiconductor base layer. The epitaxial layer is formed on the other side of the semiconductor base layer relative to the back metal layer and has a cell region and a terminal region, and the epitaxial layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure.

[0012] The terminal groove structure is located at the junction of the cell region and the terminal region. The first groove structure is spaced apart from the terminal groove structure in the terminal region and has a first width. The second groove structure is spaced apart from the first groove structure in the terminal region and has a second width smaller than the first width. The third groove structure is spaced apart from the second groove structure in the terminal region and has a third width smaller than the second width.

[0013] The interlayer dielectric layer is stacked on the terminal trench structure, the first trench structure, the second trench structure and the third trench structure in the terminal area, and a first interlayer dielectric layer trench, a second interlayer dielectric layer trench and a third interlayer dielectric layer trench are formed at the first trench structure, the second trench structure and the third trench structure respectively.

[0014] The first metal layer is stacked on the terminal groove structure in the cell area and extends from the cell area to between the second groove structure and the third groove structure in the terminal area. The first metal layer further forms a first metal layer groove and a second metal layer groove at the first interlayer dielectric layer groove and the second interlayer dielectric layer groove respectively.

[0015] The passivation layer is partially stacked on the first metal layer in the cell area, and extends from the cell area to the terminal area and is stacked on the first metal layer and the third interlayer dielectric layer groove. The passivation layer further forms a first passivation layer groove, a second passivation layer groove and a third passivation layer groove at the first metal layer, the second metal layer groove and the third interlayer dielectric layer groove respectively.

[0016] The second metal layer covers the first metal layer and the passivation layer in the cell region, extends from the cell region to the terminal region and is partially stacked on the first passivation layer trench.

[0017] In an auxiliary technical means derived from the above necessary technical means, the ratio of the first width, the second width and the third width is 7:5:3.

[0018] In an auxiliary technical means derived from the above necessary technical means, the interlayer dielectric layer includes a tetraethyl orthosilicate (TEOS) film and a borophosphosilicate glass (BPSG) film. The tetraethyl orthosilicate film covers the epitaxial layer in the terminal region, and the borophosphosilicate glass film covers the tetraethyl orthosilicate film in the terminal region.

[0019] In an auxiliary technical means derived from the above necessary technical means, the epitaxial layer further includes a plurality of cell trench structures, each of which includes a gate oxide layer and a low-doped polysilicon layer. The gate oxide layer is formed in the cell region. The low-doped polysilicon layer is formed in the gate oxide layer.

[0020] In an auxiliary technical means derived from the above necessary technical means, the terminal trench structure further includes a gate oxide layer and a low-doped polysilicon layer. The gate oxide layer is formed in the cell region and the terminal region. The low-doped polysilicon layer is formed in the gate oxide layer. Preferably, the first metal layer includes a nickel-platinum alloy layer, which is stacked on the epitaxial layer and electrically contacts the low-doped polysilicon layer. In addition, the first metal layer includes a titanium metal layer, a titanium-tungsten alloy layer and an aluminum metal layer, the titanium metal layer is stacked on the nickel-platinum alloy layer and the interlayer dielectric layer, and extends from the cell region to the second trench structure and the third trench structure in the terminal region, the titanium-tungsten alloy layer is stacked on the titanium metal layer, and the aluminum metal layer is stacked on the titanium-tungsten alloy layer.

[0021] In an auxiliary technical means derived from the above-mentioned necessary technical means, the second metal layer includes a titanium metal layer, a nickel metal layer and a silver metal layer. The titanium metal layer is stacked on the first metal layer and the passivation layer, and extends from the cell area to the terminal area and is partially stacked on the first passivation layer groove. The nickel metal layer is stacked on the titanium metal layer, and the silver metal layer is stacked on the nickel metal layer.

[0022] In an auxiliary technical means derived from the above necessary technical means, the epitaxial layer further includes a plurality of cell trench structures, and the cell trench structures are located in the cell region.

[0023] In summary, the multi-trench Schottky diode of the present invention can effectively disperse the electric field in the terminal region by opening the first trench structure, the second trench structure and the third trench structure in the terminal region, and extending the first metal layer to between the second trench structure and the third trench structure, thereby avoiding excessive concentration of the electric field on the surface of the terminal region; in addition, by gradually reducing the width of the first trench structure, the second trench structure and the third trench structure, the potential of the terminal region can also be effectively increased gradually, thereby effectively avoiding the premature occurrence of the breakdown voltage.

[0024] The specific embodiments of the present invention will be further described through the following embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic cross-sectional view showing a conventional trench Schottky diode;

[0026] Figure 2 is a cross-sectional schematic diagram showing a multi-trench Schottky diode provided by a preferred embodiment of the present invention;

[0027] Figure 3 is a schematic diagram showing an electromagnetic field distribution curve of a multi-trench Schottky diode provided in a preferred embodiment of the present invention; and

[0028] Figure 4It is a schematic diagram showing a potential curve of a multi-trench Schottky diode provided in a preferred embodiment of the present invention.

[0029] The reference numerals are described as follows:

[0030] PA100: Trench Schottky Diode

[0031] PA1: semiconductor substrate

[0032] PA2: Back metal layer

[0033] PA3: Epitaxial layer

[0034] PA3a: Unit cell area

[0035] PA3b: Terminal Area

[0036] PA31: Unit cell structure

[0037] PA32: Terminal groove structure

[0038] PA33: Guard ring structure

[0039] PA4: Dielectric layer

[0040] PA5: First metal layer

[0041] PA6: Passivation layer

[0042] PA7: Second metal layer

[0043] 100: Multi-trench Schottky diode

[0044] 1: Semiconductor base

[0045] 11: Back

[0046] 12: Front

[0047] 2: Back metal layer

[0048] 3: Epitaxial layer

[0049] 3a: Unit cell area

[0050] 3b: Terminal Area

[0051] 31: Cell groove structure

[0052] 311: Gate Oxide

[0053] 312: Low-doped polysilicon layer

[0054] 32: Terminal groove structure

[0055] 321: Gate Oxide

[0056] 322: Low-doped polysilicon layer

[0057] 33: First groove structure

[0058] 331: Gate Oxide

[0059] 332: Low-doped polysilicon layer

[0060] 34: Second groove structure

[0061] 341: Gate Oxide

[0062] 342: Low-doped polysilicon layer

[0063] 35: Third groove structure

[0064] 351: Gate Oxide

[0065] 352: Low-doped polysilicon layer

[0066] 4: Interlayer dielectric layer

[0067] 41: Tetraethyl orthosilicate film

[0068] 42: Borophosphosilicate glass film

[0069] 5: First metal layer

[0070] 51: Nickel-platinum alloy layer

[0071] 52: Titanium metal layer

[0072] 53: Titanium tungsten alloy layer

[0073] 54: Aluminum metal layer

[0074] 6: Passivation layer

[0075] 7: Second metal layer

[0076] 71: Titanium metal layer

[0077] 72: Nickel metal layer

[0078] 73: Silver metal layer

[0079] w1: first width

[0080] w2: second width

[0081] w3: third width

[0082] C1, C2, C3, C4: Curve DETAILED DESCRIPTION

[0083] See also Figure 2 , Figure 21 is a cross-sectional schematic diagram showing a multi-trench Schottky diode provided by a preferred embodiment of the present invention. As shown in the figure, a multi-trench Schottky diode 100 includes a semiconductor base layer 1, a back metal layer 2, an epitaxial layer 3, an interlayer dielectric (ILD) layer 4, a first metal layer 5, a passivation layer 6 and a second metal layer 7.

[0084] The semiconductor substrate 1 has a back surface 11 and a front surface 12 arranged opposite to each other, and the semiconductor substrate 1 is an N-type heavily doped silicon crystal layer. The back metal layer 2 is formed on the back surface 11 of the semiconductor substrate 1. The epitaxial layer 3 is formed on the front surface 12 of the semiconductor substrate 1, and has a cell region 3a and a terminal region 3b, and the epitaxial layer 3 is an N-type lightly doped silicon crystal layer, wherein the light doping of the epitaxial layer 3 is relative to the heavy doping of the semiconductor substrate 1; in addition, the epitaxial layer 3 includes a plurality of cell trench structures 31 (only one is marked in the figure), a termination trench structure 32, a first trench structure 33, a second trench structure 34 and a third trench structure 35.

[0085] A plurality of cell trench structures 31 are spaced apart from each other and are located in the cell region 3a, and each cell trench structure 31 includes a gate oxide layer 311 and a low-doped polysilicon layer 312, and the low-doped polysilicon layer 312 fills the trench of the gate oxide layer 311. The terminal trench structure 32 is located at the junction of the cell region 3a and the terminal region 3b, that is, the terminal trench structure 32 spans the cell region 3a and the terminal region 3b. In the present embodiment, the terminal trench structure 32 further includes a gate oxide layer 321 and two low-doped polysilicon layers 322 (only one is marked in the figure), the gate oxide layer 321 is formed in the cell region 3a and the terminal region 3b, and the two low-doped polysilicon layers 322 are respectively formed on both sides of the gate oxide layer 321; wherein, the gate oxide layer 321 and the low-doped polysilicon layer 322 are formed in practice mainly by first opening a trench on the surface of the epitaxial layer 3, then oxidizing the inner wall of the trench to form the gate oxide layer 321, and then filling polysilicon into the two side walls of the trench, thereby forming two low-doped polysilicon layers 322 respectively on both sides of the gate oxide layer 321.

[0086] The first trench structure 33 is spaced apart from the terminal trench structure 32 in the terminal region 3b and has a first width w1; wherein the first trench structure 33 further comprises a gate oxide layer 331 and two low-doped polysilicon layers 332 (only one is marked in the figure), the gate oxide layer 331 is formed in the terminal region 3b, and the two low-doped polysilicon layers 332 are respectively formed on both sides of the gate oxide layer 331. The second trench structure 34 is spaced apart from the first trench structure 33 in the terminal region 3b and has a second width w2 less than the first width w1; wherein the second trench structure 34 further comprises a gate oxide layer 341 and two low-doped polysilicon layers 342 (only one is marked in the figure), the gate oxide layer 341 is formed in the terminal region 3b, and the two low-doped polysilicon layers 342 are respectively formed on both sides of the gate oxide layer 341. The third trench structure 35 is spaced apart from the second trench structure 34 in the terminal region 3b and has a third width w3 that is smaller than the second width w2; wherein the third trench structure 35 further includes a gate oxide layer 351 and two low-doped polysilicon layers 352 (only one is marked in the figure), the gate oxide layer 351 is formed in the terminal region 3b, and the two low-doped polysilicon layers 352 are respectively formed on both sides of the gate oxide layer 351.

[0087] As mentioned above, the ratio of the first width w1, the second width w2 and the third width w3 is 7:5:3, and in the present embodiment, the first width w1 is, for example, 14 μm, the second width w2 is, for example, 10 μm, the third width w3 is, for example, 6 μm, and the distance between the first trench structure 33 and the second trench structure 34 is 2.8 μm, and the distance between the second trench structure 34 and the third trench structure 35 is also 2.8 μm.

[0088] The interlayer dielectric layer 4 includes a tetraethyl orthosilicate (TEOS) film 41 and a borophosphosilicate glass (BPSG) film 42. The TEOS film 41 covers the terminal trench structure 32, the first trench structure 33, the second trench structure 34 and the third trench structure 35 of the epitaxial layer 3 in the terminal region 3b, and the TEOS film 41 further forms a first TEOS trench (not shown), a second TEOS trench (not shown) and a third TEOS trench (not shown) at the first trench structure 33, the second trench structure 34 and the third trench structure 35, respectively. The borophosphosilicate glass film 42 covers the first tetraethyl orthosilicate groove, the second tetraethyl orthosilicate groove and the third tetraethyl orthosilicate groove of the tetraethyl orthosilicate film 41 in the terminal area 3b, and forms a first interlayer dielectric layer groove (not shown), a second interlayer dielectric layer groove (not shown) and a third interlayer dielectric layer groove (not shown) at the first groove structure 33, the second groove structure 34 and the third groove structure 35 respectively.

[0089] The first metal layer 5 includes a nickel-platinum alloy layer 51, a titanium metal layer 52, a titanium-tungsten alloy layer 53, and an aluminum metal layer 54. The nickel-platinum alloy layer 51 is stacked on the epitaxial layer 3 in the cell region 3a and electrically contacts the low-doped polysilicon layer 322. The titanium metal layer 52 is stacked on the nickel-platinum alloy layer 51 and the borophosphosilicate glass film 42 of the interlayer dielectric layer 4, and extends from the cell region 3a to between the second trench structure 34 and the third trench structure 35 of the terminal region 3b, and the titanium metal layer 52 further forms a first titanium metal layer trench (not shown) and a second titanium metal layer trench (not shown) at the first interlayer dielectric layer trench and the second interlayer dielectric layer trench, respectively. The titanium-tungsten alloy layer 53 is stacked on the titanium metal layer 52 and extends from the unit cell region 3a to between the second groove structure 34 and the third groove structure 35 of the terminal region 3b, and the titanium-tungsten alloy layer 53 further forms a first titanium-tungsten alloy layer groove (not shown) and a second titanium-tungsten alloy layer groove (not shown) at the first titanium metal layer groove and the second titanium metal layer groove, respectively. The aluminum metal layer 54 is stacked on the titanium-tungsten alloy layer 53 and extends from the unit cell region 3a to between the second groove structure 34 and the third groove structure 35 of the terminal region 3b, and the aluminum metal layer 54 further forms a first metal layer groove (not shown) and a second metal layer groove (not shown) at the first titanium-tungsten alloy layer groove and the second titanium-tungsten alloy layer groove, respectively.

[0090] The passivation layer 6 is partially stacked on the aluminum metal layer 54 of the first metal layer 5 in the cell region 3a, and extends from the cell region 3a to the terminal region 3b and is stacked on the first metal layer 5 and the third interlayer dielectric layer trench, and the passivation layer 6 further forms a first passivation layer trench (not shown), a second passivation layer trench (not shown) and a third passivation layer trench (not shown) at the first metal layer trench, the second metal layer trench and the third interlayer dielectric layer trench respectively. In the present embodiment, the passivation layer 6 is a silicon nitride layer.

[0091] The second metal layer 7 includes a titanium metal layer 71, a nickel metal layer 72 and a silver metal layer 73. The titanium metal layer 71 is stacked on the aluminum metal layer 54 and the passivation layer 6 of the first metal layer 5 in the cell region 3a, and extends from the cell region 3a to the terminal region 3b and is partially stacked on the first passivation layer groove. The nickel metal layer 72 is stacked on the titanium metal layer 71 in the cell region 3a, and is stacked on the titanium metal layer 71 at the first passivation layer groove extending from the cell region 3a to the terminal region 3b. The silver metal layer 73 is stacked on the nickel metal layer 72 in the cell region 3a, and is stacked on the nickel metal layer 72 at the first passivation layer groove extending from the cell region 3a to the terminal region 3b.

[0092] Please continue reading Figure 3 and Figure 4 , Figure 3 is a schematic diagram showing an electromagnetic field distribution curve of a multi-trench Schottky diode provided in a preferred embodiment of the present invention; Figure 4 It is a schematic diagram showing a potential curve of a multi-trench Schottky diode provided in a preferred embodiment of the present invention.

[0093] like Figures 1 to 3 As shown, Figure 3 The curve C1 corresponds to Figure 1 The electric field distribution of the existing trench Schottky diode PA100, and Figure 3 The curve C2 corresponds to Figure 2 The electric field distribution of the multi-trench Schottky diode 100 provided in the preferred embodiment of the present invention. Among them, the electric field of curve C1 at 0-10μm is higher because it corresponds to the cell structure PA31 of the cell area PA3a. However, since the first metal layer PA5 extends to the terminal area PA3b, there will be charges concentrated on the edge of the first metal layer PA5, causing the electric field of curve C1 at about 25μm of the measurement position to rise again; in comparison, although the multi-trench Schottky diode 100 of the present embodiment extends the first metal layer 5 to between the second trench structure 34 and the third trench structure 35 of the terminal area 3b, since the first metal layer 5 has the first metal layer trench and the second metal layer trench formed at the first trench structure 33 and the second trench structure 34 respectively, the electric field of the multi-trench Schottky diode 100 of the present embodiment can be effectively reduced at 10μm to 14μm corresponding to the first metal layer trench and at 26μm to 30μm corresponding to the second metal layer trench, thereby dispersing the electric field of the entire terminal area 3b without excessive concentration. In addition, since the electric field in the terminal region 3b is dispersed because the first metal layer 5 extends to between the second trench structure 34 and the third trench structure 35 in the terminal region 3b, the strong electric field can be effectively kept away from the cell trench structure 31 in the cell region 3a, thereby effectively preventing the Schottky contact of the cell trench structure 31 from being disturbed by the strong electric field.

[0094] On the other hand, Figure 4 As shown, Figure 4 The curve C3 corresponds to Figure 1 The potential change of the existing trench Schottky diode PA100, Figure 4The curve C4 corresponds to the potential change of the multi-trench Schottky diode 100 of the present invention; wherein, since the guard ring structure PA33 of the trench Schottky diode PA100 corresponds to the measurement position 10μm~20μm, the potential of the curve C1 is maintained below 50V, but after passing the guard ring structure PA33, the potential will change drastically to close to 250V, resulting in the breakdown voltage occurring prematurely in practice; however, since the multi-trench Schottky diode 100 of the present invention utilizes the first width w1 of the first trench structure 33, the second width w2 of the second trench structure 34 and the third width w3 of the third trench structure 35 to gradually decrease, and the first metal layer 5 extends between the second trench structure 34 and the third trench structure 35, the potential of the multi-trench Schottky diode 100 can be gradually increased, thereby effectively avoiding the breakdown voltage from occurring prematurely.

[0095] In summary, compared to the trench Schottky diode in the prior art, which extends the first metal layer and the second metal layer to the terminal region in order to increase the reverse bias, thereby causing the surface of the epitaxial layer to easily accumulate surface charges, the multi-trench Schottky diode of the present invention can effectively disperse the electric field in the terminal region by opening the first trench structure, the second trench structure and the third trench structure in the terminal region, and extending the first metal layer to between the second trench structure and the third trench structure, thereby avoiding excessive concentration of the electric field on the surface of the terminal region; in addition, by gradually reducing the width of the first trench structure, the second trench structure and the third trench structure, the potential of the terminal region can also be effectively increased gradually, thereby effectively avoiding premature breakdown voltage.

[0096] The above preferred embodiments are described in detail to more clearly describe the features and spirit of the present invention, but are not intended to limit the scope of the present invention by the preferred embodiments disclosed above. On the contrary, the purpose is to cover various changes and arrangements with equivalents within the scope of the claims to be applied for by the present invention.

Claims

1. A multi-trench Schottky diode, comprising: a semiconductor substrate; A back metal layer is formed on one side of the semiconductor substrate; An epitaxial layer is formed on the other side of the semiconductor base layer relative to the back metal layer and has a cell region and a terminal region, and the epitaxial layer includes: A terminal trench structure is located at the junction of the unit cell region and the terminal region; a first trench structure, which is spaced apart from the terminal trench structure in the terminal region and has a first width; a second trench structure, spaced apart from the first trench structure in the terminal region and having a second width smaller than the first width; as well as A third trench structure is disposed in the terminal region at a distance from the second trench structure and has a third width smaller than the second width: An interlayer dielectric layer is stacked on the terminal trench structure, the first trench structure, the second trench structure and the third trench structure in the terminal region, and a first interlayer dielectric layer trench, a second interlayer dielectric layer trench and a third interlayer dielectric layer trench are formed at the first trench structure, the second trench structure and the third trench structure respectively; A first metal layer is stacked on the terminal trench structure in the cell region and extends from the cell region to between the second trench structure and the third trench structure in the terminal region, and the first metal layer further forms a first metal layer trench and a second metal layer trench at the first interlayer dielectric layer trench and the second interlayer dielectric layer trench, respectively: A passivation layer is partially stacked on the first metal layer in the cell region, and extends from the cell region to the terminal region and is stacked on the first metal layer and the third interlayer dielectric layer trench, and the passivation layer further forms a first passivation layer trench, a second passivation layer trench, and a third passivation layer trench at the first metal layer, the second metal layer trench, and the third interlayer dielectric layer trench, respectively; as well as A second metal layer covers the first metal layer and the passivation layer in the cell region, extends from the cell region to the terminal region and is partially stacked in the first passivation layer trench.

2. The multi-trench Schottky diode according to claim 1, wherein: The ratio of the first width, the second width and the third width is 7:5:

3.

3. The multi-trench Schottky diode according to claim 1, wherein: The interlayer dielectric layer includes a tetraethyl orthosilicate film and a borophosphosilicate glass film. The tetraethyl orthosilicate film covers the epitaxial layer in the terminal region, and the borophosphosilicate glass film covers the tetraethyl orthosilicate film in the terminal region.

4. The multi-trench Schottky diode according to claim 1, wherein: The epitaxial layer further comprises a plurality of unit cell trench structures, each of the unit cell trench structures comprising: a gate oxide layer formed in the cell region; and A low-doped polysilicon layer is formed in the gate oxide layer.

5. The multi-trench Schottky diode according to claim 1, wherein: The terminal groove structure also includes: a gate oxide layer formed in the cell region and the terminal region; and A low-doped polysilicon layer is formed in the gate oxide layer.

6. The multi-trench Schottky diode according to claim 5, wherein: The first metal layer includes a nickel-platinum alloy layer, which is stacked on the epitaxial layer and electrically contacts the low-doped polysilicon layer.

7. The multi-trench Schottky diode according to claim 6, wherein: The first metal layer includes a titanium metal layer, a titanium-tungsten alloy layer and an aluminum metal layer. The titanium metal layer is stacked on the nickel-platinum alloy layer and the interlayer dielectric layer, and extends from the unit cell region to between the second trench structure and the third trench structure in the terminal region. The titanium-tungsten alloy layer is stacked on the titanium metal layer, and the aluminum metal layer is stacked on the titanium-tungsten alloy layer.

8. The multi-trench Schottky diode according to claim 1, wherein: The second metal layer includes a titanium metal layer, a nickel metal layer and a silver metal layer. The titanium metal layer is stacked on the first metal layer and the passivation layer, and extends from the unit cell area to the terminal area and is partially stacked on the first passivation layer groove. The nickel metal layer is stacked on the titanium metal layer, and the silver metal layer is stacked on the nickel metal layer.

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