Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a substrate, a plurality of parallel dummy gates on the substrate, and side structures on both sides of the dummy gates, wherein the substrate comprises an isolation region, the extension direction of the isolation region intersects with the plurality of parallel dummy gates; removing the dummy gates intersecting within the isolation region to form an initial cross-cut isolation trench that crosses the plurality of parallel dummy gates; removing the side structures within the isolation region to form a target cross-cut isolation trench; and forming a cross-cut isolation structure that fills the target cross-cut isolation trench. The method improves the performance of the device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shorten. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short channel effect (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as Fin Field-Effect Transistor (FinFET). In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFET, the gate structure has a stronger control ability over the channel, can effectively suppress the short channel effect, and has better compatibility with existing integrated circuit manufacturing.

[0004] However, devices formed by existing semiconductor processes have poor performance. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate comprising a substrate, a plurality of parallel dummy gates located on the substrate, and side structures located on both sides of the dummy gates, wherein the substrate comprises an isolation region, and an extension direction of the isolation region intersects with the plurality of parallel dummy gates;

[0008] Removing the dummy gates intersecting the isolation region to form an initial cross-cutting isolation trench that crosses the plurality of parallel dummy gates;

[0009] removing the side structures in the isolation region to form a target cross-cutting isolation trench;

[0010] A cross-cut isolation structure is formed to fill the target cross-cut isolation trench.

[0011] Accordingly, an embodiment of the present invention further provides a semiconductor structure, including:

[0012] A substrate, the substrate comprising a substrate, a plurality of parallel dummy gates located on the substrate, and side structures located on both sides of the dummy gates, wherein the substrate comprises an isolation region, and an extension direction of the isolation region intersects with the plurality of parallel dummy gates;

[0013] A cross-cutting isolation structure is located in the isolation region, and the cross-cutting isolation structure isolates the plurality of parallel dummy gates and side structures between the plurality of parallel dummy gates.

[0014] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0015] In an embodiment of the present invention, when forming a target cross-cutting isolation trench, while removing the dummy gate intersecting within the isolation region, the side structure within the isolation region is also removed to remove protrusions that may be located on the side of the dummy gate, thereby avoiding damage to the metal gate caused by the protrusions in subsequent processes, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1 to 8 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0017] Figures 9 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0018] Figure 22 to Figure 24 It is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] As can be seen from the background art, devices formed by existing processes still have the problem of poor performance. The reasons for the poor performance of the device are now analyzed in conjunction with a method for forming a semiconductor structure.

[0020] refer to Figures 1 to 8 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0021] like Figure 1 to Figure 2As shown, a substrate 100 is provided, the substrate comprising a substrate 101 and a plurality of parallel dummy gates 120 located on the substrate, wherein the substrate 100 comprises an isolation region 10A, and the extension direction of the isolation region 10A intersects with the plurality of parallel dummy gates 120. Figure 2 for Figure 1 Cross-sectional view along the AA' direction.

[0022] like Figure 3 As shown, an anisotropic etching process is used to etch away the dummy gates intersecting the isolation region 10A, so as to form a transverse isolation trench 121 that transversely cuts through the plurality of parallel dummy gates.

[0023] like Figure 4 As shown, a cross-cutting isolation structure 140 is deposited in the cross-cutting isolation trench 121 .

[0024] like Figure 5 As shown, a metal gate 150 is formed at the remaining dummy gate locations.

[0025] like Figures 5 to 7 As shown, the isolation gate 151 in the metal gate 150 is removed by wet etching to form a truncated isolation trench 161. Figure 7 for Figure 6 Cross-sectional view along BB' direction.

[0026] like Figure 8 As shown, a truncation isolation structure 160 is formed to fill the truncation isolation trench 161 .

[0027] The inventors have found that the device formed by the above method has poor performance. This is because during the formation of the dummy gate structure or in the process after the formation, the dummy gate structure may form a protrusion due to environmental influences (such as temperature, pressure, etc.). Figures 2 to 4 The black shadow area shown in, for example, when the pseudo gate is polycrystalline silicon, it is easy to crystallize in a high temperature environment (such as the high temperature environment during the sidewall deposition process), thereby protruding from the original process space and invading the side structures on both sides of the pseudo gate; further, in the process of forming the cross-cut isolation groove, the anisotropic etching process only etches in the direction perpendicular to the substrate surface, and does not etch in other directions to avoid damaging other parts of the pseudo gate, which results in the protrusion protruding from the original process space. If this part of the protrusion that cannot be removed is connected to the remaining pseudo gate, the metal gate subsequently formed in the pseudo gate process space will extend to the protrusion position at the same time, so that in the step of wet etching to remove the isolation gate in the metal gate, the etching solution can easily etch the material at the protrusion position, and through the protrusion position (such as Figure 7 ), immersed in the metal gate that does not need to be etched (as shown in Figure 6The gate structure of the device is damaged.

[0028] Based on this, in an embodiment of the present invention, when forming a target cross-cutting isolation trench, while removing the dummy gate intersecting within the isolation region, the side structure within the isolation region is also removed to remove protrusions that may be located on the side of the dummy gate, thereby avoiding damage to the metal gate caused by the protrusions in subsequent processes, thereby improving device performance.

[0029] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figures 9 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0031] refer to Figure 9-10 , providing a substrate 200, the substrate comprising a substrate 201, a plurality of parallel dummy gates 220 located on the substrate, and side structures located on both sides of the dummy gates.

[0032] in, Fig.10 is along Fig. 9 Cross-sectional view along CC' direction.

[0033] The substrate includes an isolation region 20A, the extension direction of which intersects with the plurality of parallel dummy gates, and optionally, the extension direction of the isolation region is perpendicular to the extension direction of the plurality of parallel dummy gates. The isolation region 20A is a region of the substrate 200 for forming a target cross-cutting isolation trench, which covers a portion of the structure of the plurality of parallel dummy gates and a portion of the side structure between the plurality of parallel dummy gates, so as to form a target cross-cutting isolation trench by subsequently etching the isolation region.

[0034] The width of the isolation region should not be too large or too small. If the isolation region is too large, the width of the target cross-cutting isolation trench formed subsequently will also be too large, which will occupy too much space and will not be conducive to reducing the size of the semiconductor structure; if the width of the isolation region is too small, the width of the target cross-cutting isolation trench formed subsequently will also be too small, which will not be conducive to playing the role of isolating the device. Accordingly, the width of the isolation region can be 10 nanometers to 30 nanometers.

[0035] The substrate 201 is used to provide support for other structures. In an embodiment of the present invention, the material of the substrate 201 may be silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate. An interface layer may also be formed on the surface of the substrate 201, and the material of the interface layer may be silicon oxide, silicon nitride or silicon oxynitride, etc.

[0036] The dummy gate 220 is a metal gate structure formed in a subsequent process to occupy a space position. The dummy gate 220 can be polysilicon. In other embodiments, the material of the dummy gate 220 can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, carbon nitride silicon oxynitride or amorphous carbon.

[0037] In the process of forming the device structure, in order to facilitate the simultaneous formation of multiple device structures, multiple parallel dummy gates are usually formed on the substrate at the same time, so as to facilitate the corresponding processing in the device formation process, thereby simplifying the process flow.

[0038] In an embodiment of the present invention, the base further comprises a discrete fin protruding from the substrate, and the plurality of dummy gates span the fin. The material of the fin may be the same as or different from the material of the substrate. The dummy gate spans over the discrete fin, so that the fin is used as a channel structure to control the device.

[0039] Side structures are formed on both sides of the dummy gate 220 , and the side structures are used to provide isolation, support, and process space definition for the dummy gate 220 to form a corresponding device structure.

[0040] In the embodiment of the present invention, the side structure may include sidewalls 230 located on both sides of the dummy gate, and the sidewalls 230 may define the formation area of ​​the source and drain doping layers. Furthermore, in the embodiment of the present invention, the side structure may further include an interlayer dielectric layer 240 located between adjacent sidewalls, and the interlayer dielectric layer is used to isolate different device structures and further define a process space for the device.

[0041] The material of the sidewall spacer may be silicon nitride. In other embodiments of the present invention, the sidewall spacer may also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.

[0042] The material of the interlayer dielectric layer 240 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 240 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer 240 may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0043] In the embodiment of the present invention, a hard mask layer 250 may be formed on the dummy gate 220, and the side structure (including the sidewall 230 and the interlayer dielectric layer 240) is flush with the hard mask layer 250. The hard mask layer 250 is used to protect the dummy gate, and the material of the hard mask layer 250 may be silicon nitride. In other embodiments, the material of the hard mask layer may also be silicon oxynitride.

[0044] In the embodiment of the present invention, in order to remove the dummy gate intersecting the isolation region, refer to Figure 11 to Figure 12 In the embodiment of the present invention, the hard mask layer and a part of the thickness of the interlayer dielectric layer in the isolation region 20A are first removed to expose the dummy gate.

[0045] Specifically, the hard mask layer and the side structure of a part of the thickness in the isolation region can be removed by a series of semiconductor processes such as photolithography and etching. For example, a patterned first mask layer (such as Fig.11 The first mask layer has an opening that exposes the isolation region, and the first mask layer 260 is further used as a mask to remove the hard mask layer 250 and a portion of the side structure (such as Fig.12 As shown), thereby exposing the dummy gate.

[0046] Next, the dummy gates intersecting the isolation region are removed to form an initial cross-cutting isolation trench that crosses the plurality of parallel dummy gates.

[0047] Specifically, an initial cross-cutting isolation trench that crosses the multiple parallel dummy gates can be formed by a series of semiconductor processes such as photolithography and etching. For example, a patterned second mask layer can be formed, the second mask layer has an opening that exposes the isolation region, and the corresponding portion of the dummy gate is further removed using the second mask layer as a mask, thereby forming an initial cross-cutting isolation trench that crosses the multiple parallel dummy gates.

[0048] It can be understood that in the process of removing the dummy gate, based on the fact that the material of the dummy gate is different from that of other parts, an etching process with a relatively high selectivity for the dummy gate material can be selected according to the characteristics of the material to etch the initial cross-cutting isolation groove, thereby reducing damage to other parts of the device structure.

[0049] Next, the side structures in the isolation region are removed to form a target cross-cutting isolation trench.

[0050] The target cross-cutting isolation trench is used to cut off the dummy gate in the extension direction of the dummy gate to isolate multiple corresponding device structures in the extension direction of the dummy gate. It should be noted that, in order to facilitate the semiconductor integration process, the target cross-cutting isolation trench simultaneously cuts off multiple parallel dummy gates in a direction perpendicular to the extension direction of the dummy gate to isolate multiple device structures at the same time. Correspondingly, the extension direction of the isolation region is perpendicular to the extension direction of the multiple parallel dummy gates and intersects with the dummy gate.

[0051] In an embodiment of the present invention, by removing the side structure in the isolation region, the protrusions in the side structure that may be located between the dummy gates can be removed at the same time, thereby avoiding damage to the metal gate caused by the protrusions in subsequent processes, thereby improving device performance.

[0052] It should be noted that when the side structure only includes the sidewall formed on the side of the pseudo gate, the target cross-cutting isolation trench can be formed by only deleting the sidewall in the isolation region. In a further embodiment, the side structure can also be defined to further include an interlayer dielectric layer located between the sidewalls for isolating the device structure, so that the device structure located on the side of the pseudo gate can be completely removed, so that the target cross-cutting structure formed in the isolation region is a through-groove, further completely removing the structure that may have protrusions, and facilitating the complete filling of the subsequent cross-cutting isolation structure.

[0053] Among them, in order to further thoroughly remove the protrusion located on the side of the pseudo gate, the embodiment of the present invention further sets the isolation region to also cover the side wall of the pseudo gate located at the edge of the isolation region close to the edge of the isolation region, so that in this step, the side structure that may have protrusions is further completely removed.

[0054] In the embodiment of the present invention, the removal of the dummy gate intersecting the isolation region and the removal of the side structure in the isolation region can be performed simultaneously, thereby simplifying the process flow and reducing the process cost.

[0055] Specifically, simultaneously performing the removing of the dummy gate intersecting the isolation region and the removing of the side structure in the isolation region may include:

[0056] refer to Fig.12 , forming a patterned isolation mask layer on the substrate, wherein the isolation mask layer exposes the isolation area.

[0057] The isolation mask layer may be a hard mask layer or a photoresist mask layer, and may be formed by photolithography plus etching, or a photolithography process. The isolation region is exposed through the isolation mask layer to facilitate the corresponding process flow for the structure in the isolation region.

[0058] In an embodiment of the present invention, the isolation mask layer may be a first mask layer 260, and the corresponding isolation mask layer formation step may be performed in the step of removing the hard mask layer and a partial thickness of the interlayer dielectric layer in the isolation area to expose the pseudo gate, thereby simplifying the process flow in this embodiment.

[0059] refer to Fig.13 Using the isolation mask layer 260 as a mask, the pseudo gate 220 intersecting the isolation region 20A and the side structure in the isolation region are etched away.

[0060] The process flow is simplified by simultaneously removing the dummy gate 220 intersecting the isolation region 20A and the side structure in the isolation region.

[0061] Specifically, in an embodiment of the present invention, a dry etching process can be used to etch and remove the pseudo gate 220 intersecting in the isolation region 20A and the side structure in the isolation region. Based on the different materials of the pseudo gate 220 and the side structure, different process gases are used in the dry etching process. Specifically, in the dry etching process, the process gas used to etch and remove the pseudo gate is a chlorine-containing gas with a pressure of 50mt to 100mt; the process gas used to etch and remove the side structure is a fluorine-containing gas with a pressure of 0mt to 20mt. Among them, the chlorine-containing gas includes chlorine gas, and the flow rate of the chlorine gas is 0sccm to 300sccm; the fluorine-containing gas includes CH2F2 and CF4, the flow rate of CH2F2 is 0sccm to 50sccm, and the flow rate of CF4 is 60sccm to 100sccm.

[0062] It should be noted that, in order to ensure that the etching process has good anisotropic characteristics and thus avoid damage to other structures in the substrate, the gas pressure in the embodiments of the present invention is generally relatively small so that the corresponding etching ions have higher verticality.

[0063] After removing the dummy gate 220 in the isolation region 20A and the side structure in the isolation region, the isolation mask layer is further removed to provide a process space for subsequent forming processes.

[0064] Next, refer to Figure 14-15 , forming a cross-cutting isolation structure 270 filling the target cross-cutting isolation trench. 15 is Fig.14 Cross-sectional view along CC' direction.

[0065] The device structures are isolated by forming a cross-cut isolation structure 270 filling the target cross-cut isolation trench, wherein the cross-cut isolation structure 270 may be made of an insulating material to electrically isolate the device structures.

[0066] The material of the cross-cutting isolation structure 270 may be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In an embodiment of the present invention, the material of the cross-cutting isolation structure 270 may be silicon nitride.

[0067] In an embodiment of the present invention, the process of forming a cross-cut isolation structure that fills the target cross-cut isolation trench may include: forming a cross-cut isolation material that completely covers the substrate having one side of the cross-cut isolation trench; grinding and removing the cross-cut isolation material on the surface of the substrate, and retaining the cross-cut isolation material in the target cross-cut isolation trench as the cross-cut isolation structure 270.

[0068] The process for forming the cross-cut isolation material may be a flowable chemical vapor deposition (FCVD) process. The grinding process may be chemical mechanical grinding, so that the cross-cut isolation structure forms good morphological features.

[0069] In the embodiment of the present invention, after forming the cross-cutting isolation structure filling the target cross-cutting isolation trench, the following process may also be included:

[0070] refer to Fig.16 , wet etching is used to remove the remaining dummy gate on the substrate to form a gate trench 281.

[0071] The dummy gate is removed to form a gate trench 281 to provide a process space for the subsequent formation of a metal gate.

[0072] In order to completely remove the remaining dummy gate and isolation mask layer on the substrate, this step adopts a wet etching process to remove the dummy gate and isolation mask layer. Specifically, an acidic oxidizing etching solution such as a mixed solution of nitric acid (HN) and hydrofluoric acid (HF) can be used to etch the dummy gate.

[0073] It should be noted that, during the process of removing the dummy gate, a hard mask layer is also formed on the dummy gate. Accordingly, in this step, the hard mask layer is first removed to expose the dummy gate, and then the dummy gate is removed.

[0074] In particular, based on the fact that the side structure that may have protrusions has been removed in the embodiment of the present invention, the process of forming the gate trench in this step will not form a gap corresponding to the protrusion part based on the protrusion in the side structure.

[0075] refer to Figure 16-18 , a metal gate 280 is formed in the gate trench 281; wherein, Fig.18 Bit Fig.17Cross-sectional view along DD' direction.

[0076] Specifically, after the gate trench 281 is formed, a deposition, electroplating or other process may be used to form a metal material in the gate trench 281 , and the metal material outside the gate trench may be further removed by a grinding process to form a metal gate 280 in the gate trench 281 .

[0077] It should be noted that in the formation process of the embodiment of the present invention, the metal gate 280 formed includes not only a metal conductive gate used as a gate structure in the device structure, but also an isolation gate 282 used as an isolation gate. The isolation gate 282 is used to be etched and removed in subsequent steps, and a truncated isolation structure is formed at a corresponding spatial position, so as to achieve isolation between device structures.

[0078] Among them, based on the fact that the side structure that may form a protrusion has been removed in the embodiment of the present invention, the corresponding process of forming the gate groove will not form a gap corresponding to the protrusion part based on the protrusion in the side structure, and thus no metal material will be formed in the gap in this step.

[0079] For further reference, Figure 18-Figure 20 , the isolation gate 282 in the metal gate 280 is removed by wet etching to form a truncated isolation trench 291. Fig. 20 is along Fig.19 Cross-sectional view obtained by cutting along the DD' direction.

[0080] Correspondingly, in this step, the isolation gate may be removed by wet etching or a combination of wet etching and dry etching, which will not be elaborated in detail in the present invention.

[0081] Among them, based on the fact that the side structure that may form a protrusion has been removed in the embodiment of the present invention, the process of forming the corresponding gate groove will not form a gap corresponding to the protrusion part based on the protrusion in the side structure, and further, no metal material will be formed in the gap during the formation of the metal gate, so that in this step, the etching solution will not penetrate into the metal gate that does not need to be etched through the corresponding gap, or the etching solution will further penetrate into the metal gate that does not need to be etched after etching and removing the metal material in the gap, thereby avoiding damage to the gate structure of the device.

[0082] For further reference, Fig.21 , forming a truncation isolation structure 290 filling the truncation isolation trench.

[0083] The device structures are isolated by forming a truncation isolation structure 290 filling the truncation isolation trench, wherein the material of the truncation isolation structure 290 may be an insulating material to electrically isolate the device structures.

[0084] The truncated isolation structure 290 may be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In an embodiment of the present invention, the truncated isolation structure 290 may be silicon nitride.

[0085] In an embodiment of the present invention, the process of forming a truncated isolation structure 290 filling the truncated isolation trench may include: forming a truncated isolation material that completely covers the substrate on one side of the truncated isolation trench; grinding and removing the truncated isolation material on the surface of the substrate, and retaining the truncated isolation material in the truncated isolation trench as the truncated isolation structure 290.

[0086] The process of forming the truncated isolation material may be a flowable chemical vapor deposition process (FCVD). The polishing process may be a chemical mechanical polishing process, so that the truncated isolation structure forms a good morphology feature.

[0087] The present invention also provides a semiconductor structure. Figure 22-Figure 24 ,in, Fig.23 for Fig. 22 The cross-section along the EE' direction, Fig.24 for Fig. 22 The cross-section in the FF' direction includes:

[0088] The substrate 300 includes a substrate 301, a plurality of parallel dummy gates 320 on the substrate, and a side structure 330 on both sides of the dummy gates, wherein the substrate 300 includes an isolation region 30A, and an extension direction of the isolation region 30A intersects with the plurality of parallel dummy gates 320.

[0089] The isolation region 30A is a region of the substrate 300 where a target cross-cutting isolation trench is set, and the region cross-cuts a portion of the structure of the plurality of parallel dummy gates 320 and a portion of the side structure between the plurality of parallel dummy gates.

[0090] It should be noted that the target cross-cutting isolation trench 370 is used to cut off the dummy gate in the extension direction of the dummy gate to isolate multiple corresponding device structures in the extension direction of the dummy gate. It should be noted that, in order to facilitate the semiconductor integration process, the target cross-cutting isolation trench simultaneously cuts off multiple parallel dummy gates in a direction perpendicular to the extension direction of the dummy gate to isolate multiple device structures at the same time. Correspondingly, the extension direction of the isolation region is perpendicular to the extension direction of the multiple parallel dummy gates and intersects with the dummy gate.

[0091] The width of the isolation region 30A should not be too large or too small. If the isolation region 30A is too large, the width of the target cross-cutting isolation trench formed subsequently will also be too large, which will occupy too much space and will not be conducive to reducing the size of the semiconductor structure; if the width of the isolation region 30A is too small, the width of the corresponding target cross-cutting isolation trench will also be too small, which will not be conducive to playing the role of isolating the device. Accordingly, the width of the isolation region can be 10 nanometers to 30 nanometers.

[0092] The substrate 301 is used to provide support for other structures. In an embodiment of the present invention, the material of the substrate 301 may be silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate. An interface layer may also be formed on the surface of the substrate 301, and the material of the interface layer may be silicon oxide, silicon nitride or silicon oxynitride, etc.

[0093] The dummy gate 320 is a metal gate structure formed in a subsequent process to occupy a space position. The dummy gate 320 can be polysilicon. In other embodiments, the material of the dummy gate 320 can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, carbon nitride silicon oxynitride or amorphous carbon.

[0094] In the process of forming the device structure, in order to facilitate the simultaneous formation of multiple device structures, multiple parallel dummy gates are usually formed on the substrate at the same time, so as to facilitate the corresponding processing in the device formation process, thereby simplifying the process flow.

[0095] In an embodiment of the present invention, the base further comprises a discrete fin protruding from the substrate, and the plurality of dummy gates span the fin. The material of the fin may be the same as or different from the material of the substrate. The dummy gate spans over the discrete fin, so that the fin is used as a channel structure to control the device.

[0096] Side structures are formed on both sides of the dummy gate 320 , and the side structures are used to provide isolation, support, and process space definition for the dummy gate 320 .

[0097] In the embodiment of the present invention, the side structure may include sidewalls 330 located on both sides of the dummy gate, and the sidewalls 330 may define the formation area of ​​the source and drain doping layers. Further, in the embodiment of the present invention, the side structure may further include an interlayer dielectric layer 340 located between adjacent sidewalls 330, and the interlayer dielectric layer 340 is used to isolate different device structures and further define a process space for the device.

[0098] The material of the sidewall spacer 330 may be silicon nitride. In other embodiments of the present invention, the sidewall spacer may also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.

[0099] The material of the interlayer dielectric layer 340 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 340 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer 340 may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0100] In the embodiment of the present invention, a hard mask layer 350 may be formed on the dummy gate 320, and the side structure (including the sidewall 330 and the interlayer dielectric layer 340) is flush with the hard mask layer 350. The hard mask layer 350 is used to protect the dummy gate, and the material of the hard mask layer 350 may be silicon nitride. In other embodiments, the material of the hard mask layer 350 may also be silicon oxynitride.

[0101] Furthermore, the semiconductor structure further includes: a cross-cutting isolation structure 370 located in the isolation region 30A, wherein the cross-cutting isolation structure 370 isolates the plurality of parallel dummy gates 320 and side structures between the plurality of parallel dummy gates 320 .

[0102] Optionally, the cross-cut isolation structure 370 is used to isolate the device structure. The cross-cut isolation structure 370 may be made of an insulating material to electrically isolate the device structures.

[0103] The material of the cross-cutting isolation structure 370 may be one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In an embodiment of the present invention, the material of the cross-cutting isolation structure 370 may be silicon nitride.

[0104] Based on the fact that the side structure that may form a protrusion has been removed in the embodiment of the present invention, the corresponding process of forming the gate groove will not form a gap corresponding to the protrusion part based on the protrusion in the side structure, and further, no metal material will be formed in the gap during the formation of the metal gate. In this step, the etching solution will not penetrate into the metal gate that does not need to be etched through the corresponding gap, or the etching solution will further penetrate into the metal gate that does not need to be etched after removing the metal material in the gap through etching, thereby avoiding damage to the gate structure of the device.

[0105] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0106] Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate, a plurality of parallel dummy gates located on the substrate, and side structures located on both sides of the dummy gates, wherein the substrate comprises an isolation region, and an extension direction of the isolation region intersects with the plurality of parallel dummy gates; removing the dummy gates intersecting the isolation region to form an initial cross-cutting isolation trench that crosses the plurality of parallel dummy gates; Removing the side structure in the isolation region to form a target cross-cutting isolation trench; while removing the side structure in the isolation region, simultaneously removing the protrusion of the pseudo gate in the side structure; forming a cross-cut isolation structure filling the target cross-cut isolation trench; After forming the cross-cut isolation structure that fills the target cross-cut isolation trench, the method also includes: using wet etching to remove the remaining dummy gate on the substrate to form a gate trench; forming a metal gate in the gate trench; using wet etching to remove the isolation gate in the metal gate to form a truncated isolation trench, wherein the truncated isolation trench exposes the side wall of the cross-cut isolation structure; and forming a truncated isolation structure that fills the truncated isolation trench.

2. The method for forming a semiconductor structure according to claim 1, wherein: The side structure at least includes a spacer formed on a side of the dummy gate.

3. The method for forming a semiconductor structure according to claim 2, wherein: The side structure further includes an interlayer dielectric layer located between the sidewalls.

4. The method for forming a semiconductor structure according to claim 1, wherein: The isolation region covers a portion of the structure of the plurality of parallel dummy gates and a portion of the side structure between the plurality of parallel dummy gates.

5. The method for forming a semiconductor structure according to claim 4, wherein: The isolation region also covers a sidewall of a dummy gate located at an edge of the isolation region and close to the edge of the isolation region.

6. The method for forming a semiconductor structure according to claim 1, wherein: The removing of the dummy gate intersecting the isolation region and the removing of the side structure in the isolation region are performed simultaneously.

7. The method for forming a semiconductor structure according to claim 6, wherein: Simultaneously performing the removing of the dummy gate intersecting the isolation region and the removing of the side structure in the isolation region, comprises: forming a patterned isolation mask layer on the substrate, wherein the isolation mask layer exposes the isolation area; The isolation mask layer is used as a mask to etch and remove the dummy gate intersecting in the isolation region and the side structure in the isolation region.

8. The method for forming a semiconductor structure according to claim 7, wherein: A dry etching process is adopted to etch and remove the dummy gate intersecting the isolation region and the side structure in the isolation region.

9. The method for forming a semiconductor structure according to claim 8, wherein: In the dry etching process, the process gas used to etch and remove the dummy gate is a chlorine-containing gas with a pressure of 50mt to 100mt; The process gas used for etching and removing the side structure is fluorine-containing gas, and the pressure is 0mt to 20mt.

10. The method for forming a semiconductor structure according to claim 9, wherein: The chlorine-containing gas includes chlorine gas, and the flow rate of the chlorine gas is 0 sccm to 300 sccm; the fluorine-containing gas includes CH2F2 and CF4, and the flow rate of CH2F2 is 0 sccm to 50 sccm, and the flow rate of CF4 is 60 sccm to 100 sccm.

11. The method for forming a semiconductor structure according to claim 1, wherein: A hard mask layer is also formed on the dummy gate, and the side structure is flush with the hard mask layer; after the step of providing the substrate and before the step of removing the dummy gate intersecting the isolation region, the method further includes: The hard mask layer and a portion of the thickness of the side structure in the isolation region are removed to expose the dummy gate.

12. The method for forming a semiconductor structure according to claim 1, wherein: The forming of the cross-cutting isolation structure filling the target cross-cutting isolation trench comprises: forming a cross-cutting isolation material completely covering a side of the substrate having the cross-cutting isolation trench; The isolation material on the surface of the substrate is removed by grinding, and the cross-cutting isolation material in the target cross-cutting isolation trench is retained as the cross-cutting isolation structure.

13. The method for forming a semiconductor structure according to claim 1, wherein: The base also includes a discrete fin protruding from the substrate, and the plurality of parallel dummy gates span across the fin; After removing the isolation gate in the metal gate and before forming the truncated isolation structure filling the truncated isolation trench, the method further includes: The fin portion located below the isolation gate is removed so that the truncated isolation trench extends to the substrate.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the cross-cut isolation structure includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

15. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure as claimed in any one of claims 1 to 14.

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