Trench filling method for trench sidewall gate structure

Abstract

The present invention relates to a trench filling method of a trench sidewall gate structure, comprising: obtaining a wafer formed with a trench sidewall gate structure; bombarding the top opening of the trench by plasma to partially remove the insulating material at the opening, thereby expanding the top opening to form a first opening that is larger at the top and smaller at the bottom; sealing the trench by an HDPCVD process, so that the trench forms a cavity below the sealing structure; and filling the first opening with an insulating material. After the filling of the present invention, a cavity is formed in the trench, and the cavity can be used as a part of the contact hole formed subsequently, which can save the etching time of the contact hole and reduce the etching difficulty of the contact hole. In addition, the present invention can control the height of the cavity below the STI, and can avoid the phenomenon that the acid or corrosive liquid in the subsequent process etches through the insulating material above the cavity and flows back into the cavity. Therefore, the above method is compatible with the CMOS process.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing, and in particular to a trench filling method for a trench sidewall gate structure. Background Art

[0002] A new type of trench DMOS (Double-diffused MOSFET, double diffused metal oxide semiconductor) device needs to form a gate on the bottom sidewall of the trench. For integrated processes, such as the BCD process (the BCD process is an integrated process technology that can make BJT, CMOS and DMOS devices on the same chip), the new trench sidewall gate structure needs to be compatible with the traditional CMOS process and cannot affect the insulation isolation performance of the shallow trench isolation structure (STI) of the device. To achieve the above purpose, it is necessary to fill the trench after the trench sidewall gate structure is formed to achieve the effect of not affecting the normal CMOS structure manufacturing. After filling, the conventional manufacturing process is carried out to form an interlayer dielectric (ILD), and then etched to the bottom of the trench to form a contact hole and lead out. According to the design size requirements, the depth-to-width ratio of the trench is large (an exemplary depth-to-width ratio>9.0), and traditional filling technology is difficult to meet the requirements. Summary of the invention

[0003] Based on this, it is necessary to provide a trench filling method for a trench sidewall gate structure that can meet the trench filling requirements.

[0004] A trench filling method for a trench sidewall gate structure comprises: obtaining a wafer formed with a trench sidewall gate structure, wherein a trench is formed on the wafer, a gate is formed at the bottom of the sidewall of the trench, and an insulating material covering the gate is formed on the sidewall of the trench; bombarding the top opening of the trench by plasma to partially remove the insulating material at the opening, thereby expanding the top opening to form a first opening that is larger at the top and smaller at the bottom, wherein the bottom of the first opening is higher than the bottom of a shallow trench isolation structure of the device; sealing the trench by a high-density plasma chemical vapor deposition process, wherein the bottom of the sealing structure is lower than the bottom of the first opening and not higher than the bottom of the shallow trench isolation structure, and the trench forms a cavity below the sealing structure; and filling the first opening with the insulating material.

[0005] In one of the embodiments, in the step of obtaining a wafer having a trench sidewall gate structure, the top opening of the trench is a structure that is larger at the top and smaller at the bottom; in the step of expanding the top opening to form a first opening that is larger at the top and smaller at the bottom, the bottom of the top opening moves downward in the process of becoming the first opening, so that the bottom of the first opening is lower than the bottom of the top opening.

[0006] In one embodiment, the step of filling the first opening with the insulating material includes: forming an interlayer dielectric; performing contact hole etching on the interlayer dielectric to form a first contact hole, wherein the first contact hole is formed by etching through the interlayer dielectric and the insulating material in the first opening and then connecting to the cavity.

[0007] In one of the embodiments, the step of etching the contact hole of the interlayer dielectric continues to etch downward to the bottom of the groove after etching to the cavity; after the step of etching the contact hole of the interlayer dielectric, it also includes the step of filling the first contact hole with a conductive material to form a gate lead-out structure electrically connected to the gate.

[0008] In one embodiment, the step of bombarding the top opening of the trench with plasma is performed using a high-density plasma chemical vapor deposition machine, and the deposition recipe does not contain silicon source gas so that only the bombardment capability is retained.

[0009] In one embodiment, the reaction gas in the deposition recipe includes oxygen and hydrogen.

[0010] In one of the embodiments, the step of sealing the trench by high-density plasma chemical vapor deposition process is performed using an STI menu, and the STI menu is a menu for depositing silicon oxide in a shallow trench isolation structure with a sputtering / deposition ratio of 0.3±0.03.

[0011] In one embodiment, the step of bombarding the top opening of the trench with plasma is performed using the STI recipe in which the SiH4 flow rate is reduced to zero.

[0012] In one embodiment, the step of filling the first opening with the insulating material includes depositing silicon oxide by a high-density plasma chemical vapor deposition process, and the deposition rate is greater than the deposition rate of the step of sealing the trench by a high-density plasma chemical vapor deposition process.

[0013] In one of the embodiments, in the step of obtaining a wafer having a trench sidewall gate structure formed thereon, the wafer also has the shallow trench isolation structure formed thereon.

[0014] In one embodiment, the step of filling the first opening with the insulating material further includes a step of chemical mechanical polishing the filled insulating material.

[0015] In one embodiment, the trench sidewall gate structure is a structure in a VDMOS (vertical double diffused metal oxide semiconductor field effect transistor).

[0016] In one of the embodiments, in the step of obtaining a wafer having a trench sidewall gate structure formed thereon, the aspect ratio of the trench is greater than 9:1.

[0017] The trench filling method of the trench sidewall gate structure above forms a cavity in the trench after filling, and the cavity can be used as a part of the contact hole formed subsequently, which can save the etching time of the contact hole and reduce the etching difficulty of the contact hole. In addition, the method can control the height of the cavity below the shallow trench isolation structure, and can avoid the phenomenon that the acid or corrosive liquid in the subsequent process will etch through the insulating material above the cavity and flow back into the cavity. Therefore, the trench filling method of the trench sidewall gate structure above is compatible with the CMOS process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0019] Figure 1 is a flow chart of a trench filling method of a trench sidewall gate structure in one embodiment;

[0020] Figure 2 is a cross-sectional schematic diagram of a trench sidewall gate structure in a wafer in one embodiment;

[0021] Figure 3 is a schematic cross-sectional view of a wafer after step S120 is completed in one embodiment;

[0022] Figure 4a is a schematic diagram of re-depositing at a position slightly below the bottom of the first opening in step S130 in one embodiment, Figure 4b is a schematic cross-sectional view of a wafer after step S130 is completed in one embodiment;

[0023] Figure 5 is a schematic cross-sectional view of a wafer after step S140 is completed in one embodiment;

[0024] Figure 6 is a cross-sectional schematic diagram of a wafer after the insulating material filled in step S140 is subjected to CMP processing in one embodiment;

[0025] Figure 7 It is a cross-sectional schematic diagram of the device after the first contact hole is filled with a conductive material in one embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0028] It should be noted that when an element is referred to as "fixed on" another element, it can be directly on another element or there can also be a centered element. When an element is considered to be "connected" to another element, it can be directly connected to another element or there may be a centered element at the same time. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for the purpose of illustration. When an element or layer is referred to as "on...", "adjacent to...", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be an intermediate element or layer. On the contrary, when an element is referred to as "directly on...", "directly adjacent to...", "directly connected to" or "directly coupled to" other elements or layers, there is no intermediate element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0029] When the terms "comprise" and / or "include" are used in this specification, they indicate the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof. The singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0031] Exemplary deep trench filling methods mainly include SACVD (sub-atmospheric pressure chemical vapor deposition), atomic layer deposition, etc., but they can usually only fill trenches with an aspect ratio of no more than 6: 1. However, the trench sidewall gate structure involved in this application needs to fill trenches with an aspect ratio greater than 9: 1, so the above exemplary filling technology cannot meet the requirements.

[0032] Figure 1 1 is a flow chart of a trench filling method for a trench sidewall gate structure in an embodiment, comprising the following steps:

[0033] S110, obtaining a wafer having a trench sidewall gate structure formed thereon.

[0034] Figure 2 1 is a cross-sectional schematic diagram of a trench sidewall gate structure in a wafer in an embodiment, comprising a substrate 10, a trench 11, a gate 20 and an insulating layer 22. The gate 20 is formed at the bottom of the sidewall of the trench 11, and the insulating layer 22 covers the gate 20 and the sidewall of the trench 11.

[0035] The substrate includes a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). The substrate may also be formed with other structures commonly used in integrated circuit manufacturing, such as a shallow trench isolation (STI) structure.

[0036] In one embodiment, the gate 20 is made of polysilicon. In other embodiments, the gate 20 may be made of metal, metal nitride, metal silicide or similar compounds.

[0037] In one embodiment, the insulating material of the insulating layer 22 is silicon oxide, such as silicon dioxide.

[0038] Reference Figure 2 In this embodiment, the top opening of the groove 11 is a structure that is larger at the top and smaller at the bottom, similar to a trumpet shape.

[0039] In one embodiment, a shallow trench isolation structure ( Figure 2 (not shown), the shallow trench isolation structure can be the STI of CMOS.

[0040] S120, bombarding the top opening of the trench with plasma to expand the top opening to form a first opening that is larger at the top and smaller at the bottom.

[0041] The top opening of the trench 11 is bombarded by plasma to remove part of the insulating material at the opening, thereby expanding the top opening to form a first opening that is larger at the top and smaller at the bottom, and the bottom of the first opening is higher than the bottom of the shallow trench isolation structure of the device (the STI of CMOS in this embodiment). Since the subsequent formation of the seal will be slightly below the bottom of the first opening, in order to control the height of the seal, the bottom of the first opening needs to be controlled to be slightly higher than the bottom of the shallow trench isolation structure of the device. The expansion of the top opening can reduce the difficulty of filling in the subsequent step (step S140).

[0042] exist Figure 2 and Figure 3 In the illustrated embodiment, after the plasma bombardment treatment in step S120 , the trumpet-shaped top opening will expand outward as a whole and the bottom will move downward. Figure 3 Arrows are used to indicate plasma bombardment. In one embodiment, a portion of the insulating material removed by plasma bombardment will be re-deposited (Re-Dep) on the inner surface of the groove below the first opening, especially at the lower part of the bell mouth. This re-deposition process can prepare for subsequent sealing. Figure 3 This inverted trapezoidal flare is conducive to forming a seal in the subsequent steps.

[0043] S130, HDPCVD (high density plasma chemical vapor deposition) is used to seal the trench, and the bottom of the sealing structure is lower than the bottom of the first opening and not higher than the bottom of the STI.

[0044] The trench 11 below the first opening is sealed by depositing an insulating material through a high-density plasma chemical vapor deposition process. The deposited insulating material may be silicon oxide, such as silicon dioxide. The high-density plasma chemical vapor deposition process also involves plasma bombardment during the deposition process. Figure 4aFIG. 1 is a schematic diagram of re-deposition (Re-Dep) at a position slightly below the bottom of the first opening in step S130 in one embodiment, wherein the solid arrow indicates plasma bombardment, and the dotted arrow indicates the moving direction of the insulating material after being removed from the original position, that is, the insulating material moves to a position 23 slightly below the bottom of the first opening and is re-deposited. After the deposition is completed in step S130, a sealing structure 24 is formed, see FIG. Figure 4b The bottom of the sealing structure 24 ( Figure 4b The position indicated by the arrow in the middle (indicated by the arrow in the middle) is lower than the bottom of the first opening and not higher than the bottom of the shallow trench isolation structure (STI of CMOS in this embodiment). After sealing, the trench forms a cavity 13 below the sealing structure 24. Controlling the height of the cavity 13 below the shallow trench isolation structure can prevent the acid or etching solution in the subsequent process from corroding the insulating material above the cavity 13 and flowing back into the cavity 13. In one embodiment, the bottom of the sealing structure 24 is flush with the bottom of the shallow trench isolation structure.

[0045] S140, filling the first opening with an insulating material.

[0046] The first opening may be filled by depositing an insulating material, such as Figure 5 As shown. In one embodiment, step S140 is to fill the first opening with a high-density plasma chemical vapor deposition process, so that the same machine can be used as in the previous steps, saving the time / cost of changing the machine. In order to save time for filling the first opening, high-density plasma chemical vapor deposition can adopt a higher deposition rate, that is, the value of the sputtering / deposition ratio (S / D ratio) is smaller. In one embodiment, the sputtering / deposition ratio of step S140 is less than the sputtering / deposition ratio of step S130, and specifically the sputtering / deposition ratio of step S140 can be 0.06. In other embodiments, a menu with a faster deposition rate can be selected according to actual conditions to improve filling efficiency. In one embodiment, the deposited insulating material is silicon oxide, such as silicon dioxide. In one embodiment, after filling, the step of performing chemical mechanical polishing (CMP) on the filled insulating material is also included.

[0047] The trench filling method of the trench sidewall gate structure forms a cavity 13 in the trench after filling. The cavity 13 can be used as a part of the contact hole formed subsequently, which can save the etching time of the contact hole and reduce the etching difficulty of the contact hole. In addition, the method can control the height of the cavity 13 below the shallow trench isolation structure of the CMOS, and can avoid the phenomenon that the acid or corrosive liquid in the subsequent process will etch through the insulating material above the cavity 13 and flow back into the cavity. Therefore, the trench filling method of the trench sidewall gate structure is compatible with the CMOS process.

[0048] In some embodiments, a shallow trench isolation structure is also formed on the wafer obtained in step S110 , and the shallow trench isolation structure may be a STI of CMOS. Figure 6 1 is a cross-sectional view of a wafer after CMP treatment of the insulating material filled in step S140 in one embodiment. When forming the shallow trench isolation structure 32, silicon nitride 34 ( Figure 6 In the embodiment shown, the silicon nitride 34 of the active region is formed between the trench sidewall gate structure and the adjacent shallow trench isolation structure 32. The silicon nitride 34 is used as a grinding stop layer when performing CMP treatment after filling with insulating material in step S140.

[0049] In one embodiment, it is necessary to avoid the plasma bombardment in step S120 (and S130 ) from damaging the silicon nitride 34 , and therefore it is necessary to reasonably control the thickness of the insulating material removed by the plasma bombardment in step S120 .

[0050] In one embodiment, the trench of the trench sidewall gate structure is formed by etching downward in the STI region. Specifically, the STI structure can be formed by the following process: first, a layer of silicon nitride is deposited on the surface of the substrate, and then, the silicon nitride is photolithographically etched to form a shallow groove in the STI region, and then silicon dioxide is filled in the shallow groove. The CMP of the STI can be performed together with the CMP treatment of the insulating material in the aforementioned step S140.

[0051] In one embodiment, the trench sidewall gate structure is a structure in a VDMOS (vertical double diffused metal oxide semiconductor field effect transistor), that is, the gate 20 is a gate of a VDMOS.

[0052] In one embodiment, after step S140 is completed, device manufacturing can continue according to a conventional CMOS process until an interlayer dielectric (ILD) is formed on the wafer surface (above the trench of the trench sidewall gate structure), and the interlayer dielectric is etched for contact holes to form a first contact hole. The first contact hole is formed by etching through the interlayer dielectric and the insulating material in the first opening and then connected to the cavity 13. After etching through the cavity 13, a small amount of etching is continued to the bottom of the trench, so that a contact hole compatible with the CMOS process can be formed.

[0053] Figure 7 FIG. 1 is a schematic cross-sectional view of a device after the first contact hole is filled with a conductive material in an embodiment. Figure 7, the first contact hole 50 extends downward through the interlayer dielectric 50 and the insulating material in the trench to the bottom of the trench, and the gate 20 can be led out by filling the first contact hole 50 with a conductive material. In one embodiment, the conductive material filled in the first contact hole 50 is metal tungsten. In other embodiments, the conductive material can also be any suitable conductive material well known to those skilled in the art, including but not limited to metal materials; wherein the metal material can include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al.

[0054] In one embodiment, step S120 is performed using a high-density plasma chemical vapor deposition machine, and the deposition recipe does not contain a silicon source gas so that only the bombardment capability is retained. In one embodiment, the reaction gases in the deposition recipe include oxygen and hydrogen. Since the machines used in steps S130 and S140 can both be high-density plasma chemical vapor deposition machines, step S120 also uses a high-density plasma chemical vapor deposition machine. The time / cost of replacing the machine can be saved.

[0055] In one embodiment, step S130 is performed using an STI menu, specifically a menu for depositing silicon oxide in a CMOS STI with a sputtering / deposition ratio of 0.3±0.03. For embodiments in which the position of the sealing structure 24 needs to be precisely controlled at the bottom of the STI (i.e., an embodiment in which the bottom of the sealing structure 24 is flush with the bottom of the shallow trench isolation structure), this is mainly achieved by controlling the sputtering / deposition ratio at 0.3±0.03. This menu also has a strong plasma bombardment capability during the deposition process. And the use of this sputtering / deposition ratio can form a seal more quickly, which is beneficial to saving process time. In one embodiment, the adjustment of the sputtering / deposition ratio is mainly achieved by adjusting the high-frequency radio frequency power (HFpower) of the high-density plasma chemical vapor deposition machine.

[0056] In one embodiment, step S120 is performed using the aforementioned STI menu with SiH4 flow rate reduced to 0, and the specific gas flow rates are: oxygen 72±6sccm; hydrogen 400±20sccm. In one embodiment, the low frequency radio frequency power (LF power) of the aforementioned STI menu is 2000±100W; the medium frequency radio frequency power (MF power) is 2000±100W; and the high frequency radio frequency power (HF power) is 3100±200W.

[0057] In one embodiment, the trench filling method of the trench sidewall gate structure is applied to the manufacturing process of a device integrating VDMOS and CMOS, such as the manufacturing process of a BCD device.

[0058] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A trench filling method for a trench sidewall gate structure, comprising: Obtaining a wafer having a trench sidewall gate structure, wherein the wafer has a trench, a gate is formed at the bottom of the sidewall of the trench, and an insulating material covering the gate is formed on the sidewall of the trench; Bombarding the top opening of the trench by plasma to remove the insulating material at the opening, thereby expanding the top opening to form a first opening that is larger at the top and smaller at the bottom, wherein the bottom of the first opening is higher than the bottom of the shallow trench isolation structure of the device; The trench is sealed by a high-density plasma chemical vapor deposition process, wherein the bottom of the sealing structure is lower than the bottom of the first opening and not higher than the bottom of the shallow trench isolation structure, and the trench forms a cavity below the sealing structure; The first opening is filled with the insulating material.

2. The trench filling method of the trench sidewall gate structure according to claim 1, characterized in that: In the step of obtaining a wafer having a groove sidewall gate structure, the top opening of the groove is a structure that is larger at the top and smaller at the bottom; in the step of expanding the top opening to form a first opening that is larger at the top and smaller at the bottom, the bottom of the top opening moves downward in the process of becoming the first opening, so that the bottom of the first opening is lower than the bottom of the top opening.

3. The trench filling method of the trench sidewall gate structure according to claim 1, characterized in that: The step of filling the first opening with the insulating material comprises: forming an interlayer dielectric; The interlayer dielectric is etched to form a first contact hole, wherein the first contact hole is formed by etching through the interlayer dielectric and the insulating material in the first opening and then connected to the cavity.

4. The trench filling method of the trench sidewall gate structure according to claim 3, characterized in that: The step of etching the contact hole of the interlayer dielectric includes, after etching to the cavity, continuing to etch downward to the bottom of the groove; after the step of etching the contact hole of the interlayer dielectric, the step also includes filling the first contact hole with a conductive material to form a gate lead-out structure electrically connected to the gate.

5. The trench filling method of the trench sidewall gate structure according to claim 1, characterized in that: The step of bombarding the top opening of the groove by plasma is performed using a high-density plasma chemical vapor deposition machine, and the deposition menu does not contain silicon source gas so that only the bombardment capability is retained.

6. The trench filling method of the trench sidewall gate structure according to claim 5, characterized in that: The reactive gases in the deposition recipe include oxygen and hydrogen.

7. The trench filling method of the trench sidewall gate structure according to claim 5 or 6, characterized in that: The step of sealing the trench by high-density plasma chemical vapor deposition process is performed using an STI menu, which is a menu for depositing silicon oxide in a shallow trench isolation structure with a sputtering / deposition ratio of 0.3±0.

03.

8. The trench filling method of the trench sidewall gate structure according to claim 7, characterized in that: The step of bombarding the top opening of the trench with plasma is performed by using the STI recipe in which the SiH4 flow rate is reduced to 0.

9. The trench filling method of the trench sidewall gate structure according to claim 1, characterized in that: The step of filling the first opening with the insulating material includes depositing silicon oxide by a high-density plasma chemical vapor deposition process, and the deposition rate is greater than the deposition rate of the step of sealing the trench by a high-density plasma chemical vapor deposition process.

10. The trench filling method of the trench sidewall gate structure according to claim 1, characterized in that: In the step of obtaining a wafer having a trench sidewall gate structure formed thereon, the wafer also has the shallow trench isolation structure formed thereon.

11. The trench filling method of the trench sidewall gate structure according to claim 1, characterized in that: The trench sidewall gate structure is a structure in VDMOS.

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