Magnetic tunnel junction memory cell with buffer layer and method for forming the same

Abstract

A memory cell structure includes a dielectric cap layer disposed on a substrate and a first dielectric layer disposed on the dielectric cap layer. The memory cell structure may further include a buffer layer disposed on the first dielectric layer, and a connecting via structure embedded in the buffer layer, the first dielectric layer, and the dielectric cap layer. The memory cell structure may further include a bottom electrode and a magnetic tunnel junction (MTJ) memory cell, wherein the bottom electrode is disposed on the connecting via structure and the buffer layer, and the magnetic tunnel junction (MTJ) memory cell includes one or more magnetic tunnel junction layers disposed on the bottom electrode.

Description

Technical Field

[0001] Embodiments of the present invention relate to a magnetic tunnel junction memory cell with a buffer layer and a method for forming the same. Background Art

[0002] Semiconductor manufacturing may implement ion beam etching to form various layers with various patterns throughout a semiconductor stack. Ion beam etching may selectively etch portions of the same layer(s) at different rates due to a loading effect, in which certain portions of the topmost layer are exposed to the ion beam at a higher rate than other portions of the same layer. Thus, one region of a material layer may be etched at a higher rate than another region of the same material layer. As a result of such selective etching, the logic portion of the semiconductor device may be exposed for all of the various layers, thereby contaminating the logic portion. Summary of the invention

[0003] An embodiment of the present invention provides a memory cell structure, comprising: a first dielectric layer; a buffer layer, arranged on the first dielectric layer; a connecting via structure, embedded in the buffer layer and the first dielectric layer; a bottom electrode, arranged on the connecting via structure and the buffer layer, wherein the buffer layer has an etching rate of 0.8 to 1.3 relative to the etching rate of the bottom electrode; and a magnetic tunnel junction (MTJ) memory cell, comprising one or more magnetic tunnel junction layers arranged on the bottom electrode.

[0004] An embodiment of the present invention provides a magnetic tunnel junction (MTJ) memory device, comprising: an array of magnetic tunnel junction memory cells, located on a substrate, wherein each of the magnetic tunnel junction memory cells comprises: a bottom electrode; one or more magnetic tunnel junction layers; and a top electrode; an array of connecting via structures, wherein each connecting via structure of the array of connecting via structures contacts the bottom surface of a corresponding bottom electrode of a corresponding one of the magnetic tunnel junction memory cells; and a buffer layer surrounding the sidewalls of the connecting via structure, wherein the top surface of the buffer layer contacts the bottom surface of each bottom electrode of each of the magnetic tunnel junction memory cells of the array of magnetic tunnel junction memory cells.

[0005] An embodiment of the present invention provides a method for forming a magnetic tunnel junction (MTJ) memory device, comprising: forming a first dielectric layer; forming a buffer layer on the first dielectric layer; patterning the buffer layer and the first dielectric layer to form a cavity passing through the buffer layer and the first dielectric layer; depositing a filling material into the cavity to form a connecting via structure; forming a bottom electrode layer on the top surface of the connecting via structure and the top surface of the buffer layer; forming one or more magnetic tunnel junction layers for forming a magnetic tunnel junction memory unit; forming a mask on the one or more magnetic tunnel junction layers; and performing an ion beam etching process to pattern the one or more magnetic tunnel junction layers to form the magnetic tunnel junction memory unit and pattern the bottom electrode layer into a bottom electrode, wherein the buffer layer prevents the ion beam etching process from exposing the underlying metal interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of a magnetic tunnel junction (MTJ) memory cell structure after forming an array of memory cells and an array of metal etch stop portions.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a complementary metal-oxide-semiconductor (CMOS) transistor, a metal interconnect structure formed in a dielectric material layer, and ion beam etching a buffer layer according to an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming an array of connected via structures according to an embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a bottom electrode material layer, a nonmagnetic metal buffer layer, a synthetic antiferromagnetic layer, a nonmagnetic tunnel barrier layer, a free magnetization layer, a top electrode material layer and a metal etch mask material layer according to an embodiment of the present disclosure.

[0011] Figure 5 is a vertical cross-sectional view of an exemplary structure after patterning a metal etch mask material layer into a metal etch mask portion according to an embodiment of the present disclosure.

[0012] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming an array of memory cells and an array of metal etch stop portions according to an embodiment of the present disclosure.

[0013] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming an array of inter-dielectric spacer portions according to an embodiment of the present disclosure.

[0014] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming an array of outer dielectric spacer portions according to an embodiment of the present disclosure.

[0015] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a memory level dielectric layer according to an embodiment of the present disclosure.

[0016] Fig.10 is a vertical cross-sectional view of an exemplary structure after array contact structures are formed in the memory array region 100 and the logic region 200 according to an embodiment of the present disclosure.

[0017] Fig.11 is a flow chart showing the general processing steps of the disclosed method. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and structures are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature(s) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] In general, the structures and methods of the disclosed embodiments may be used to form memory cells and / or arrays of memory cells. Specifically, the structures and methods of the disclosed embodiments may be used to form magnetic tunnel junction memory cells and / or arrays of magnetic tunnel junction memory cells. Although the disclosed embodiments are described using an exemplary structure including a magnetic tunnel junction memory cell, the methods of the disclosed embodiments may be used to form any memory cell or any array of memory cells that includes a vertical stack of patterned material portions that constitute the memory cell and includes a top electrode.

[0021] It should be understood that a memory device according to embodiments of the present disclosure may include a single discrete memory cell, a one-dimensional array of memory cells, or a two-dimensional array of memory cells. It should also be understood that the one-dimensional array of memory cells of embodiments of the present disclosure may be implemented as a periodic one-dimensional array of memory cells, and the two-dimensional array of memory cells of the present disclosure may be implemented as a periodic two-dimensional array of memory cells. In addition, while embodiments of the present disclosure are described using embodiments in which a two-dimensional array of memory cells is formed within a particular metal interconnect level, embodiments in which a two-dimensional array of memory cells is formed within different metal interconnect levels are expressly contemplated herein.

[0022] Figure 1 is a vertical cross-sectional view of an MTJ memory cell structure after forming an array of memory cells and an array of metal etch stop portions. Figure 1 FIG. 1 shows the loading effect that occurs during the formation of the MTJ memory cell structure. Figure 1 , ion beam etching (IBE) may be performed to transfer the pattern of the metal etch mask portion 159 through the layer stack including the bottom electrode material layer 126 and the MTJ layer 140. The layer stack formed by the metal etch mask material portion 159, the MTJ layer 140, and the bottom electrode material layer 126 may be patterned into an array of memory cells (126, 140) based on the metal etch mask portion 159.

[0023] As a result of the angular orientation of the IBE process, as shown by ion beams A and B (shown as dashed lines), the memory array region 100 and the logic region 200 may be etched at different rates due to a loading effect. The loading effect is a result of having various layer densities at the IBE stage such that different topological pattern changes will cause different etching rates throughout the stack. For example, due to the density of the array formed by the memory cells (126, 140) and the array formed by the metal etch mask portion 159, the memory array region 100 may be subject to a shadowing effect. The shadowing effect reduces the exposure of the connecting via level dielectric layer 110 in the ion beam A, so that the topmost portion of the memory array region 100 (e.g., the metal etch mask portion 159) may limit the amount of the ion beam that can reach the connecting via level dielectric layer 110. In contrast, the logic region 200 may have a lower component density and may not be subject to the shadowing effect caused by the dense MTJ portion, so that the connecting via level dielectric layer 110 increases exposure in the ion beam B. Therefore, the connecting via level dielectric layer 110 in the logic area 200 may be etched at a higher etch rate than in the memory array area 100. For example, as a result of the ion beam etching process, a portion of the connecting via level dielectric layer 110 in the memory array area 100 may be recessed by approximately The portion of the logic region 200 connected to the via-level dielectric layer 110 may be recessed by about

[0024] In some cases, depending on the thickness and material composition of the connection via level dielectric layer 110, the connection via level dielectric layer 110 may be completely etched away in the logic region 200. In such cases, the dielectric cap layer 108 may be completely exposed to the ion beam etching process. This may cause some of the dielectric cap layer 108 to be etched away. In some cases, all of the dielectric cap layer 108 may be etched away, thereby exposing and contaminating the metal interconnect structure 648.

[0025] The increased recess of the connection via level dielectric layer 110 in the logic region 200 due to the loading effect compared to the memory array region 100 is a result of the intrinsic ion beam etching rate of the connection via level dielectric layer 110. The bottom electrode material layer 126 may be formed of a material such as titanium nitride (TiN), which has a relative etching rate of 1. For example, the connection via level dielectric layer 110 may be formed of an oxide-based material having a relative etching rate of about 2.8 (i.e., a relative etching rate of 1 relative to TiN). The oxide (connection via level dielectric layer 110) has a poor selectivity to TiN (bottom electrode material layer 126), so that the connection via level dielectric layer 110 has an overall etching rate of 2.2 to 2.9 in the logic region 200 relative to the etching rate of the bottom electrode material layer 126. For example, the ion beam etching rate of the connecting via-level dielectric layer 110 composed of oxide may be 1.2 times that of the bottom electrode material layer 126L composed of TiN (eg, Figure 4 The ion beam etching rate is 2.2 to 2.9 times that of the conventional ion beam etching method (as shown).

[0026] The increased recess of the connecting via level dielectric layer 110 in the logic region 200 due to the loading effect compared to the memory array region 100 may lead to further complications in subsequent etching processes. After the IBE etching process has been performed, additional etching processes may be performed during the subsequent formation of structures. For example, additional etching processes may be performed when dielectric spacers (not shown) are formed around the array formed by the memory cells (126, 140). Additional anisotropic etching processes performed to form structures such as arrays formed by internal dielectric spacer portions may also be applied to any remaining portions of the connecting via level dielectric layer 110 and the dielectric cap layer 108 in the logic region 200. The thickness of the remaining portions of the connecting via level dielectric layer 110 and the dielectric cap layer 108 that have increased recess in the logic region 200 due to the loading effect may not be thick enough to persist in any subsequent etching process. Therefore, performing a subsequent etching process after the ion beam etching may completely remove the connecting via-level dielectric layer 110 and the dielectric cap layer 108 in the logic region 200. Exposing the metal interconnect structure 648 in the logic region 200 to the subsequent etching process may cause the metal interconnect structure 648 to be contaminated, thereby causing a reduction in conductivity or other complications in the manufacturing process, thereby rendering the device ineffective.

[0027] Various embodiments of the present disclosure can mitigate loading effects and reduce contamination of metal layers. Various embodiments include devices and methods for buffer layers for mitigating bottom loading effects in magnetoresistive random-access memory (MRAM) designs.

[0028] Figure 2is a vertical cross-sectional view of an exemplary structure after forming a complementary metal oxide semiconductor (CMOS) transistor, a metal interconnect structure formed in a dielectric material layer, and ion beam etching a buffer layer according to an embodiment of the present disclosure. Figure 2 , showing an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 9, which may be a semiconductor substrate, such as a commercially available silicon substrate. A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed in an upper portion of the substrate 9. Suitable doped semiconductor wells, such as a p-type well and an n-type well, may be formed in each region laterally enclosed by a portion of the shallow trench isolation structure 720. Field effect transistors may be formed above the top surface of the substrate 9. For example, each field effect transistor may include a source region 732, a drain region 738, a semiconductor channel 735, and a gate structure 750, the semiconductor channel 735 including a surface portion of the substrate 9 extending between the source region 732 and the drain region 738. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source region 732 , and a drain-side metal-semiconductor alloy region 748 may be formed on each drain region 738 .

[0029] The exemplary structure may include a memory array region 100 and a logic region 200, wherein a memory element array is subsequently formed in the memory array region 100, and logic devices supporting the operation of the memory element array are formed in the logic region 200. In one embodiment, the devices (e.g., field effect transistors) in the memory array region 100 may include a bottom electrode access transistor, which provides access to the bottom electrode of the memory cell to be formed later. A top electrode access transistor may be formed in the logic region 200 in this processing step, wherein the top electrode access transistor provides access to the top electrode of the memory cell to be formed later. The devices (e.g., field effect transistors) in the logic region 200 may provide the functions required to operate the memory cell array to be formed later. Specifically, the devices in the logic region 200 may be configured to control the programming operation, the erasing operation, and the sensing (reading) operation of the memory cell array. For example, the devices in the logic region 200 may include sensing circuitry and / or top electrode bias circuitry. Devices formed on the top surface of substrate 9 may include complementary metal oxide semiconductor (CMOS) transistors and, if desired, additional semiconductor devices such as resistors, diodes, capacitors, etc., and are collectively referred to as CMOS circuitry 700 .

[0030] Various metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) formed in the dielectric material layers (601, 610, 620, 630 and 640) may then be formed over the substrate 9 and devices (e.g., field effect transistors). The dielectric material layers may, for example, include a contact-level dielectric material layer 601, a first metal line-level dielectric material layer 610, a second line-and-via-level dielectric material layer 620, a third line-and-via-level dielectric material layer 630, and a fourth line-and-via-level dielectric material layer 640. The metal interconnect structure may include a device contact via structure 612 formed in the contact-level dielectric material layer 601 and contacting corresponding components of the CMOS circuit system 700, a first metal line structure 618 formed in the first metal line-level dielectric material layer 610, a first metal via structure 622 formed in a lower portion of a second line-and-via-level dielectric material layer 620, a second metal line structure 628 formed in an upper portion of the second line-and-via-level dielectric material layer 620, a second metal via structure 632 formed in a lower portion of a third line-and-via-level dielectric material layer 630, a third metal line structure 638 formed in an upper portion of the third line-and-via-level dielectric material layer 630, a third metal via structure 642 formed in a lower portion of a fourth line-and-via-level dielectric material layer 640, and a fourth metal line structure 648 formed in an upper portion of the fourth line-and-via-level dielectric material layer 640 (i.e., copper metal contacts / copper substrates for conveying logic signals throughout the logic region 200). In one embodiment, the second metal line structure 628 may include a source line connected to a source side power supply of the memory element array. The voltage provided by the source line may be applied to the bottom electrode through an access transistor disposed in the memory array region 100.

[0031] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, copper (Cu), Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used. In one embodiment, the first metal via structure 622 and the second metal line structure 628 may be formed as an integrated line and via structure by a dual damascene process, the second metal via structure 632 and the third metal line structure 638 may be formed as an integrated line and via structure, and / or the third metal via structure 642 and the fourth metal line structure 648 may be formed as an integrated line and via structure. Although the present disclosure is described using an embodiment in which a memory cell array is formed on the fourth line and via level dielectric material layer 640, embodiments in which a memory cell array may be formed at a different metal interconnect level are expressly contemplated herein.

[0032] A dielectric cap layer 108 and a connecting via-level dielectric layer 110 may be sequentially formed over the metal interconnect structure and the dielectric material layer. For example, the dielectric cap layer 108 may be formed on the top surface of the fourth metal line structure 648 and on the top surface of the fourth line and via-level dielectric material layer 640. The dielectric cap layer 108 includes a dielectric cap material that can protect the underlying metal interconnect structure (e.g., the fourth metal line structure 648). In one embodiment, the dielectric cap layer 108 may include a material (i.e., a dielectric material) that can provide high etching resistance and may also be used as an etch stop material during a subsequent anisotropic etching process for etching the connecting via-level dielectric layer 110. For example, the dielectric cap layer 108 may include silicon carbide or silicon nitride and may have a thickness in the range of 5 nm to 30 nm, although smaller and larger thicknesses may also be used.

[0033] The connection via level dielectric layer 110 may include any material that may be used for the dielectric material layers (601, 610, 620, 630, 640). For example, the connection via level dielectric layer 110 may include undoped silicate glass or doped silicate glass deposited by decomposition of tetraethylorthosilicate (TEOS). The thickness of the connection via level dielectric layer 110 may be in the range of 50 nm to 200 nm, although lesser and greater thicknesses may also be used. The dielectric cap layer 108 and the connection via level dielectric layer 110 may be formed as flat blanket (unpatterned) layers having respective flat top surfaces and respective flat bottom surfaces extending throughout the memory array region 100 and the logic region 200.

[0034] A buffer layer 112 may be sequentially formed on the connecting via-level dielectric layer 110. The buffer layer 112 may include a material that is resistant to ion beam etching, which may protect the dielectric cap layer 108, the connecting via-level dielectric layer 110, and the metal interconnect structure (e.g., the fourth metal line structure 648) below. For example, the buffer layer 112 may be composed of a material that mitigates the loading effect applied during the ion beam etching process, so that the buffer layer 112 may be etched at a reduced (slower) rate compared to an implementation using only the dielectric cap layer 108 and the connecting via-level dielectric layer 110, thereby preventing the fourth metal line structure 648 from being exposed and thus contaminated during a subsequent etching process. In one embodiment, the buffer layer 112 may include a material that can provide high etching resistance, such as aluminum oxide (Al2O3), which may have a relative to the bottom electrode material layer 126L (e.g., Figure 4 The etch rate of the buffer layer 112 (as shown) is a relative ion beam etch rate of 0.8 to 1.3. For example, the ion beam etch rate of the buffer layer 112 composed of Al2O3 may be 0.8 to 1.3 times the ion beam etch rate of the bottom electrode material layer 126L composed of TiN. In one embodiment, the buffer layer 112 may include materials such as tantalum pentoxide (Ta2O5). The buffer layer 112 may have a thickness in the range of 5nm to 80nm, for example 10nm to 70nm, but smaller and larger thicknesses may also be used. The buffer layer 112 may be formed as a flat blanket (unpatterned) layer having a corresponding flat top surface and a corresponding flat bottom surface extending throughout the memory array area 100 and the logic area 200. In one embodiment, the buffer layer 112 may have a thickness ratio of 0.7 to 1 relative to the thickness of the bottom electrode layer 126L.

[0035] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming an array of connected through-hole structures according to an embodiment of the present disclosure. Figure 3, a through hole cavity may be formed through the buffer layer 112, the connecting via-level dielectric layer 110, and the dielectric cap layer 108. For example, a photoresist layer (not shown) may be applied over the buffer layer 112, and the photoresist layer may be patterned to form an opening in a region of the memory array region 100 overlying a corresponding one of the fourth metal line structures 648. Anisotropic etching may be performed to transfer the pattern in the photoresist layer through the buffer layer 112, the connecting via-level dielectric layer 110, and the dielectric cap layer 108. The lower electrode contact through hole cavity may have a tapered sidewall having a taper angle (relative to the vertical direction) in the range of 1 degree to 10 degrees. The top surface of the fourth metal line structure 648 may be physically exposed at the bottom of each lower electrode contact through hole cavity. The photoresist layer may then be removed, for example, by ashing.

[0036] The metal barrier layer 122 may be formed as a material layer. The metal barrier layer may cover the physically exposed top surface of the fourth metal line structure 648, the tapered sidewalls of the lower electrode contact via cavity, and the top surface of the buffer layer 112 without any holes passing therethrough. The metal barrier layer 122 may include a conductive metal nitride, such as TiN, TaN, and / or WN. Other suitable materials within the contemplated scope of the present disclosure may also be used. The thickness of the metal barrier layer 122 may be in the range of 3 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0037] A metal fill material 124, such as tungsten or copper, may be deposited in the remaining volume of the lower electrode contact via cavity. The metal fill material 124 and the portion of the metal barrier layer 122 overlying the horizontal plane including the topmost surface of the buffer layer 112 may be removed by a planarization process, such as chemical mechanical planarization. Each remaining portion of the metal fill material 124 located in a corresponding via cavity constitutes a metal via fill material portion 124. Each remaining portion of the metal barrier layer 122 located in a corresponding via cavity constitutes a metal barrier layer 122. Each combination of the metal barrier layer 122 and the metal fill material portion 124 that fills the via cavity constitutes a connecting via structure (122, 124). An array of connecting via structures (122, 124) may be formed on the buffer layer 112 and the metal interconnect structure below in the connecting via-level dielectric layer 110.

[0038] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a bottom electrode material layer, a nonmagnetic metal buffer layer, a synthetic antiferromagnetic layer, a nonmagnetic tunnel barrier layer, a free magnetization layer, a top electrode material layer, and a metal etching mask material layer according to an embodiment of the present disclosure. Figure 4, a layer stack including a bottom electrode material layer 126L, a non-magnetic metal buffer material layer 130L, a synthetic antiferromagnetic layer 140L, a non-magnetic tunnel barrier material layer 146L, a free magnetization material layer 148L, a top electrode material layer 158L, and a metal etch mask material layer 159L can be formed on the metal barrier layer and the metal via filling material portion 124. The layers in the layer stack can be deposited by a corresponding chemical vapor deposition process or a corresponding physical vapor deposition process. Each layer in the layer stack can be deposited as a flat blanket material layer with a corresponding uniform thickness throughout. The non-magnetic metal buffer material layer 130L, the synthetic antiferromagnetic layer 140L, the non-magnetic tunnel barrier material layer 146L, and the free magnetization material layer 148L are collectively referred to as a memory material layer. In other words, the memory material layer is formed between the bottom electrode material layer 126L and the top electrode material layer 158L.

[0039] Although the disclosed embodiments are described using an embodiment in which the memory material layer includes a nonmagnetic metal buffer material layer 130L, a synthetic antiferromagnetic layer 140L, a nonmagnetic tunnel barrier material layer 146L, and a free magnetization material layer 148L, the disclosed methods and structures may be applied to any structure in which the memory material layer includes a stack of different layers disposed between the bottom electrode material layer 126L and the top electrode material layer 158L and includes a material layer that can store information in any manner. Modifications to the disclosed embodiments are expressly contemplated herein in which the memory material layer includes a phase change memory (PCM) material, a ferroelectric (Fe) memory material, or a vacancy-modulated conductive oxide material.

[0040] The bottom electrode material layer 126L includes at least one non-magnetic metal material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, alloys thereof, and / or combinations thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used. For example, the bottom electrode material layer 126L may include elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt, and / or may be substantially composed of elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt. The thickness of the bottom electrode material layer 126L may be in the range of 10 nm to 100 nm, although lesser and greater thicknesses may also be used.

[0041] The non-magnetic metal buffer material layer 130L includes a non-magnetic material that can be used as a seed layer. Specifically, the non-magnetic metal buffer material layer 130L can provide a template crystal structure that aligns the polycrystalline grains of the material of the synthetic antiferromagnetic layer 140L along a direction that maximizes the magnetization of the reference layer within the synthetic antiferromagnetic layer 140L. The non-magnetic metal buffer material layer 130L can include Ti, CoFeB alloy, NiFe alloy, ruthenium, or a combination thereof. The thickness of the non-magnetic metal buffer material layer 130L can be in the range of 3nm to 30nm, but smaller and larger thicknesses can also be used.

[0042] The synthetic antiferromagnet (SAF) layer 140L may include a layer stack of a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference magnetic layer 143. Each of the ferromagnetic hard layer 141 and the reference magnetic layer 143 may have a corresponding fixed magnetization direction. The antiferromagnetic coupling layer 142 provides an antiferromagnetic coupling between the magnetization of the ferromagnetic hard layer 141 and the magnetization of the reference magnetic layer 143, so that the magnetization direction of the ferromagnetic hard layer 141 and the magnetization direction of the reference magnetic layer 143 remain fixed during the operation of the memory cell to be formed later. The ferromagnetic hard layer 141 may include a hard ferromagnetic material, such as PtMn, IrMn, RhMn, FeMn, OsMn, etc. The reference magnetic layer 143 may include a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the contemplated scope of the present disclosure may also be used. The antiferromagnetic coupling layer 142 may include ruthenium or iridium. The thickness of the antiferromagnetic coupling layer 142 may be selected so that the exchange interaction induced by the antiferromagnetic coupling layer 142 stabilizes the relative magnetization directions of the ferromagnetic hard layer 141 and the reference magnetization layer 143 in opposite directions, i.e., antiparallel alignment. In one embodiment, the net magnetization of the SAF layer 140L is achieved by matching the magnetization magnitude of the ferromagnetic hard layer 141L with the magnetization magnitude of the reference magnetization layer 143. The thickness of the SAF layer 140L may be in the range of 5 nm to 30 nm, although lesser and greater thicknesses may also be used.

[0043] The nonmagnetic tunnel barrier material layer 146L may include a tunnel barrier material, which may be an electrically insulating material having a thickness that allows electrons to tunnel. For example, the nonmagnetic tunnel barrier material layer 146L may include magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), or zirconium oxide (ZrO2). Other suitable materials within the contemplated scope of the present disclosure may also be used. The thickness of the nonmagnetic tunnel barrier material layer 146L may be 0.7 nm to 1.3 nm, but lesser and greater thicknesses may also be used.

[0044] The free magnetic material layer 148L includes a ferromagnetic material having two stable magnetization directions that are parallel or antiparallel to the magnetization direction of the reference magnetic layer 143. The free magnetic material layer 148L includes a hard ferromagnetic material, such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the scope of the present disclosure may also be used. The thickness of the free magnetic material layer 148L may be in the range of 1 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0045] The top electrode material layer 158L includes a top electrode material, which may include any non-magnetic material that may be used for the bottom electrode material layer 126L. Exemplary metal materials that may be used for the top electrode material layer 158L include, but are not limited to, TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, alloys thereof, and / or combinations thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used. For example, the bottom electrode material layer 126L may include elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt, and / or may be substantially composed of elemental metals such as W, Cu, Ti, Ta, Ru, Co, Mo, or Pt. The thickness of the top electrode material layer 158L may be in the range of 10 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0046] The metal etch mask material layer 159L includes a metal etch stop material that provides high resistance to an anisotropic etching process that will be used to etch a dielectric material (which may, for example, include undoped silicate glass, doped silicate glass, or organic silicate glass). In one embodiment, the metal etch mask material layer 159L may include a conductive metal nitride material (e.g., TiN, TaN, or WN) or a conductive metal carbide material (e.g., TiC, TaC, or WC). In one embodiment, the metal etch mask material layer 159L includes TiN and / or is essentially composed of TiN. The metal etch mask material layer 159L may be deposited by chemical vapor deposition or physical vapor deposition. The thickness of the metal etch mask material layer 159L may be in the range of 2 nm to 20 nm, for example, 3 nm to 10 nm, but lesser and greater thicknesses may also be used.

[0047] Figure 5 is a vertical cross-sectional view of an exemplary structure after the metal etch mask material layer is patterned into a metal etch mask portion according to an embodiment of the present disclosure. Figure 5 , a photoresist layer 177 may be applied over the metal etch mask material layer 159L, and the photoresist layer 177 may be photolithographically patterned to form an array of discrete photoresist material portions. Each discrete photoresist material portion in the array of discrete photoresist material portions may overlie a corresponding one of the connecting via structures (122, 124). In one embodiment, the connecting via structures (122, 124) may be arranged as a two-dimensional periodic array having a first pitch along a first horizontal direction and a second pitch along a second horizontal direction. The discrete photoresist material portions may be arranged as a two-dimensional periodic array having the same periodicity as the two-dimensional periodic array of the connecting via structures (122, 124).

[0048] A first anisotropic etching process may be performed to etch unmasked areas of the metal etch mask material layer 159L. The first anisotropic etching process uses the photoresist layer 177 as an etching mask, and the patterned portion of the metal etch mask material layer 159L constitutes the metal etch mask portion 159. The first anisotropic etching process patterns the metal etch mask material layer 159L into a two-dimensional array formed by the metal etch mask portion 159. The two-dimensional array formed by the metal etch mask portion 159 may replicate the pattern of the photoresist layer 177. The photoresist layer 177 may be removed after the first anisotropic etching process, or may remain on the two-dimensional array formed by the metal etch mask portion 159 during a subsequent second anisotropic etching process.

[0049] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming an array of memory cells and an array of metal etch stop portions according to an embodiment of the present disclosure. Figure 6, a second anisotropic etching process (e.g., ion beam etching) may be performed to transfer the pattern of the two-dimensional array formed by the metal etching mask portion 159 through the layer stack including the top electrode material layer 158L, the free magnetization material layer 148L, the nonmagnetic tunnel barrier material layer 146L, the synthetic antiferromagnetic layer 140L, the nonmagnetic metal buffer material layer 130L, and the bottom electrode material layer 126L. During the second anisotropic etching process, portions of the layer stack (158L, 148L, 146L, 140L, 130L, 126L) not masked by the metal etching mask portion 159 may be etched. In embodiments where the photoresist layer 177 is present at the beginning of the second anisotropic etching process, the photoresist layer 177 may be consumed incidentally during the second anisotropic etching process, and the metal etching mask portion 159 may be used as an etching mask at least during the patterning of the bottom electrode material layer 126L. Alternatively, in embodiments where the photoresist layer 177 is removed before the second anisotropic etching process, the metal etching mask portion 159 may be used as an etching mask throughout the second anisotropic etching process.

[0050] The second anisotropic etching process may include a series of anisotropic etching steps that sequentially etches various material layers of the underlying layer stack. In one embodiment, the patterned portion of the layer stack may include sidewalls having a non-zero taper angle (i.e., having a non-vertical surface). The taper angle may vary from layer to layer and may typically be in the range of 3 degrees to 30 degrees, such as 6 degrees to 20 degrees, although smaller and larger taper angles may also be used.

[0051] The unmasked portion of the buffer layer 112 may be vertically recessed by the second anisotropic etching process. For example, as a result of the loading effect caused during the ion beam etching, the exposed surface of the buffer layer 112 may be recessed to a greater extent in the logic area 200 than in the memory array area 100. In other words, portions of the buffer layer 112 are thicker in the memory array area 100 than in the logic area 200. However, due to the etching rate of the buffer layer 112 material (Al2O3, Ta2O5, etc.), the buffer layer 112 may persist during the ion beam etching process, thereby enabling the underlying layers (connecting via-level dielectric layer 110, dielectric cap layer 108) to not be exposed, thereby enabling the metal line structure 648 to be protected during subsequent etching processes. For example, the selectivity of Al2O3 (buffer layer 112) to TiN (bottom electrode material layer 126L) enables the loading effect to be minimized, so that the etching rate of the buffer layer 112 relative to the bottom electrode material layer 126L has a relative etching rate of 0.8 to 1.3 in the logic region 200. For example, the ion beam etching rate of the buffer layer 112 composed of Al2O3 may be 0.8 to 1.3 times the ion beam etching rate of the bottom electrode material layer 126L composed of TiN.

[0052] The layer stack (159L, 158L, 148L, 146L, 140L, 130L, 126L) formed by the metal etch mask material layer 159L, the top electrode material layer 158L, the free magnetization material layer 148L, the nonmagnetic tunnel barrier material layer 146L, the synthetic antiferromagnetic layer 140L, the nonmagnetic metal buffer material layer 130L and the bottom electrode material layer 126L can be patterned into an array of memory cells (126, 130, 140, 146, 148, 158) and an array of metal etch mask portions 159. Each of the memory cells (126, 130, 140, 146, 148, 158) includes a bottom electrode 126, a memory material stack (130, 140, 146, 148) and a top electrode 158. Each of the metal etch mask portions 159 is a patterned portion of the metal etch mask material layer 159L that overlies a respective one of the memory cells (126, 130, 140, 146, 148, 158).

[0053] In one embodiment, each memory cell (126, 130, 140, 146, 148, 158) may be a magnetic tunnel junction (MTJ) memory cell. Each MTJ memory cell (126, 130, 140, 146, 148, 158) may include a bottom electrode 126, a magnetic tunnel junction structure (140, 146, 148), and a top electrode 158. Each magnetic tunnel junction (140, 146, 148) may include a synthetic antiferromagnet (SAF) structure 140, a nonmagnetic tunnel barrier layer 146, and a free magnetization layer 148. A nonmagnetic metal buffer layer 130 may be disposed between the bottom electrode 126 and the magnetic tunnel junction (140, 146, 148). Each bottom electrode 126 is a patterned portion of a bottom electrode material layer 126L. Each SAF structure 140 is a patterned portion of a SAF layer 140L. Each nonmagnetic tunnel barrier 146 is a patterned portion of a nonmagnetic tunnel barrier material layer 146L. Each free magnetic layer 148 is a patterned portion of a free magnetic material layer 148L. Each top electrode 158 is a patterned portion of a metal etch mask material layer 159L. In one embodiment, the metal etch mask portion 159 includes and / or consists essentially of a conductive metal nitride material (e.g., TiN, TaN, or WN), and each of the memory cells (126, 130, 140, 146, 148, 158) includes a vertical stack including a synthetic antiferromagnetic structure 140, a nonmagnetic tunnel barrier layer 146, and a free magnetic layer 148.

[0054] Figure 7is a vertical cross-sectional view of an exemplary structure after forming an array of inner dielectric spacer portions according to an embodiment of the present disclosure. Figure 7 A first dielectric material, such as silicon nitride, may be conformally deposited over the array of memory cells (126, 130, 140, 146, 148, 158) and the array of metal etch mask portions 159. For example, the first dielectric material may be deposited by a chemical vapor deposition process. The thickness of the first dielectric material above the horizontal surface may be in the range of 2 nm to 20 nm, such as 4 nm to 10 nm, although lesser and greater thicknesses may also be used. An anisotropic etching process may be performed to remove horizontal portions of the first dielectric material. The remaining portions of the first dielectric material constitute an array of inner dielectric spacer portions 162 that laterally surrounds the array of memory cells (126, 130, 140, 146, 148, 158). In one embodiment, the duration of the anisotropic etching process may be selected such that the sidewalls of the array of metal etch mask portions 159 are partially or completely physically exposed. The maximum thickness of each inner dielectric spacer portion 162 can be in the range of 2 nm to 20 nm, such as 4 nm to 10 nm, although lesser and greater thicknesses can also be employed.

[0055] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming an array of outer dielectric spacer portions according to an embodiment of the present disclosure. Figure 8 , a second dielectric material, such as a dielectric metal oxide, may be conformally deposited over the array formed by the inner dielectric spacer portions 162. For example, the second dielectric material may include aluminum oxide, hafnium oxide, lanthanum oxide, or yttrium oxide, and may be deposited by a chemical vapor deposition process. The thickness of the second dielectric material above the horizontal surface may be in the range of 2nm to 20nm, such as 4nm to 10nm, but lesser and greater thicknesses may also be used. An anisotropic etching process may be performed to remove horizontal portions of the second dielectric material. The remaining portions of the second dielectric material constitute an array of outer dielectric spacer portions 164 that laterally surrounds the array formed by the inner dielectric spacer portions 162. In one embodiment, the outer dielectric spacer portions 164 may be deposited directly on the sidewalls of the metal etch mask portions 159. In one embodiment, the entirety of each sidewall of the metal etch mask portion 159 may contact the corresponding outer dielectric spacer portion 164. The maximum thickness of each outer dielectric spacer portion 164 can be in the range of 2 nm to 20 nm, such as 4 nm to 10 nm, although lesser and greater thicknesses can also be employed.

[0056] Each successive combination of the inner dielectric spacer portion 162 and the outer dielectric spacer portion 164 constitutes a dielectric spacer (162, 164). The array of dielectric spacers (162, 164) laterally surrounds the array of memory cells (126, 130, 140, 146, 148, 158) and the array of metal etch mask portions 159. Although the present disclosure is described using embodiments in which the dielectric spacers (162, 164) include inner dielectric spacer portions 162 and outer dielectric spacer portions 164, embodiments in which the dielectric spacers consist of either inner dielectric spacer portions 162 or outer dielectric spacer portions 164 are expressly contemplated herein. In general, the dielectric spacers (162, 164) may be formed around each metal etch mask portion 159 within the array of metal etch mask portions 159. Each dielectric spacer ( 162 , 164 ) may be formed directly on and around the sidewalls of the corresponding metal etch mask portion 159 .

[0057] exist Figure 7 and Figure 8 The etching process performed in the embodiment can further recess the buffer layer 112 while still maintaining the layers (108, 110) to protect the metal line structure 648 in the logic area 200 from exposure and contamination. Figure 8 After the dielectric spacers (162, 164) are formed and etched as shown, a subsequent etching process may be performed to completely remove the buffer layer 112 in the logic region 200, thereby exposing the connecting via-level dielectric layer 110. Before removing the buffer layer 112 in the logic region 200, the connecting via-level dielectric layer 110 is protected by first forming the dielectric spacers (162, 164) so ​​that the connecting via-level dielectric layer 110 is not over-etched during the formation of the MTJ structure. The buffer layer 112 may be removed by a wet etching process to prepare for the deposition of additional layers to complete the MTJ structure. For example, a wet etching process using hydrofluoric acid (HF) may be performed. The buffer layer 112 may include Al2O3, which has a wet etching rate in HF acid of about 100 %. to (For example, ). Performing a wet etching process to remove the buffer layer 112 in the logic area 200 may also partially remove the exposed portion of the buffer layer 112 in the memory array area 100 (e.g., between the dielectric spacers (162, 164)). However, due to the loading effect during the previously performed IBE process, the exposed portion of the buffer layer 112 in the memory array area 100 may be thicker than the portion of the buffer layer 112 in the logic area 200. Therefore, the wet etching process may be controlled to remove the buffer layer 112 in the logic area 200 while retaining the buffer layer 112 in the memory array area 100. Controlling the wet etching process to retain a portion of the buffer layer 112 within the memory array area 100 may prevent gaps or voids from forming around or under the dielectric spacers (162, 164).

[0058] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a memory level dielectric layer according to an embodiment of the present disclosure. Fig. 9 , a memory-level dielectric layer 170 may be formed to surround the array of dielectric spacers (162, 164). The memory-level dielectric layer 170 includes a planarizable dielectric material, such as undoped silicate glass or doped silicate glass. The dielectric material of the memory-level dielectric layer 170 may be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarizing deposition process (e.g., spin coating). A chemical mechanical planarization process may be performed to remove a portion of the deposited dielectric material from above a horizontal plane including the top surface of the metal etch mask portion 159. Various planarization assist structures (not shown) (e.g., electrically isolated patterned portions of the metal etch mask material layer 159L and the underlying material layer) may be employed in the logic region 200 to assist in planarizing the deposited dielectric material. The remaining portion of the deposited dielectric material after the planarization process constitutes the memory-level dielectric layer 170. The top surface of the memory-level dielectric layer 170 may be in the same horizontal plane as the top surface of the metal etch mask portion 159. In an embodiment, the top surfaces of the dielectric spacers ( 162 , 164 ), such as the top surface of the outer dielectric spacer portion 164 , can be in the same horizontal plane as the top surface of the memory level dielectric layer 170 .

[0059] Fig.10 FIG. 1 is a vertical cross-sectional view of an exemplary structure after forming array contact structures in the memory array region 100 and the logic region 200 according to an embodiment of the present disclosure. Fig.10 , combined with the buffer layer 112, various methods can be used to complete Figures 2 to 10The manufacturing process of the MTJ structure shown. For example, any further processes for completing the MTJ structure may involve etching the remaining portion of the buffer layer 112 (if any) in the logic area 200 to deposit a metal layer or contact layer on the metal line structure 648. Providing the buffer layer 112 on the connecting via level dielectric layer 110 can prevent over-etching of the connecting via level dielectric layer 110 during the second anisotropic etching process used to form individual memory cells in the memory array area 100. In this way, the metal line structure 648 in the logic area 200 can be protected from exposure and contamination. By having a buffer layer 112 with a relative ion beam etching rate of 0.8 to 1.3 on the connecting via level dielectric layer 110, the etching amount due to the loading effect of the second anisotropic etching process can be reduced by up to 67%.

[0060] An array of contact via structures 180 may be formed in the memory array region 100, and an array of connection via structures 280 may be formed in the logic region 200. Each contact via structure 180 includes a corresponding metal barrier layer 182 and a corresponding metal filling material portion 184. Each connection via structure 280 includes a corresponding metal barrier layer 282 and a corresponding metal filling material portion 284. The top surfaces of the contact via structures 180 and the connection via structures 280 may be in the same horizontal plane as the top surface of the via-level dielectric layer 176 (i.e., after a Chemical Mechanical Polishing (CMP) process is performed).

[0061] In general, the contact via structure 180 may be formed by depositing at least one conductive material in a via cavity (not shown) in the memory array region 100, and the connecting via structure 280 may be formed by depositing the at least one conductive material in a via cavity (not shown) in the logic region 200. The via cavity for the connecting via structure 280 may be formed by removing portions of various layers including the via-level dielectric layer 176, the memory-level dielectric layer 170, the buffer layer 112 (if any remain in the logic region 200), the connecting via-level dielectric layer 110, and the dielectric cap layer 108 (e.g., by an etching process). Each contact via structure 180 may be formed directly on the top surface of the corresponding metal etch mask portion 159 exposed in the corresponding via cavity. An array of contact via structures 180 may be formed on the top surface of the metal etch mask portion 159 in the array of via cavities. In embodiments where the upper portion of each via cavity in the memory array region 100 has a greater lateral extent than the downwardly protruding portion of the corresponding via cavity, the horizontal bottom surface of each contact via structure 180 may contact the horizontal surface of the dielectric spacers (162, 164) and / or the horizontal surface of the memory level dielectric layer 170. In one embodiment, the horizontal surface of the contact via structure 180 that contacts the dielectric spacers (162, 164) and / or the memory level dielectric layer 170 may include an annular bottom surface of the upper portion of the contact via structure 180.

[0062] Each connecting via structure 280 may be formed directly on the top surface of the corresponding metal interconnect structure 648. For example, after performing the IBE etching process and any subsequent etching processes, the connecting via level dielectric layer 110 and the dielectric cap layer 108 may remain. Therefore, additional deposition (forming a mask) and etching processes may be performed to etch any remaining portions of the buffer layer 112 (if any remain in the logic region 200), selected portions of the connecting via level dielectric layer 110, and selected portions of the dielectric cap layer 108 to expose the top surface of the corresponding metal interconnect structure 648. Such etching processes may also etch the memory level dielectric layer 170, the first dielectric etch stop layer 172, the second dielectric etch stop layer 174, and the via level dielectric layer 176 to form a via level cavity in which the connecting via structure 280 may be formed.

[0063] A line-level dielectric layer 190 may be deposited over the via-level dielectric layer 176. The line-level dielectric layer 190 may include any inter-layer dielectric (ILD) material. The thickness of the line-level dielectric layer 190 may be in the range of 100 nm to 600 nm, such as 150 nm to 300 nm, although lesser and greater thicknesses may also be used. Line trenches may be formed through the line-level dielectric layer 190, for example, by applying and patterning a photoresist layer over the line-level dielectric layer 190, and transferring the pattern in the photoresist layer through the line-level dielectric layer 190 by performing an anisotropic etching process. The photoresist layer may then be removed, for example, by ashing. At least one contact via structure 180 and / or at least one connection via structure 280 may be physically exposed at the bottom of each line trench. At least one conductive material (e.g., a combination of a metal barrier material and a metal filling material) may be deposited in the line trench, and excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the line-level dielectric layer 190 by a planarization process (e.g., a CMP process). The remaining portions of the at least one conductive material filling the line trench constitute metal line structures (192, 198). The metal line structures (192, 198) may include array connection metal lines 192 that contact at least one of the contact via structures 180 and logic area metal lines 198 that do not directly contact the contact via structures 180. In one embodiment, the array connection metal lines 192 may include word lines or bit lines for a two-dimensional array formed by memory cells (126, 130, 140, 146, 148, 158).

[0064] Reference Fig.11 , a flowchart showing the general processing steps of the disclosed method for forming a single MTJ memory device. An MTJ memory device can be formed by this method. Referring to steps 1110 and Figure 2 , a dielectric cap layer (108) may be formed on the substrate (9). Referring to steps 1120 and Figure 2 , a first dielectric layer (110) may be formed on the dielectric cap layer (108). Referring to steps 1130 and Figure 2 , a buffer layer (112) may be formed on the first dielectric layer (110). Referring to steps 1140 and Figure 3 The buffer layer (112), the first dielectric layer (110), and the dielectric cap layer (108) may be patterned to form a cavity through the buffer layer (112), the first dielectric layer (110), and the dielectric cap layer (108). Referring to steps 1150 and Figure 3 , a filling material (124) may be deposited into the cavity to form a connecting via structure (122, 124). Referring to steps 1160 and Figure 4, a bottom electrode layer (126L) may be formed on the surface of the connecting via structures (122, 124) and the surface of the buffer layer (112). Referring to steps 1170 and Figure 4 , one or more MTJ layers for forming MTJ memory cells (126, 130, 140, 146, 148, 158) may be formed. Referring to steps 1180 and Figure 5 , a mask (eg, a photoresist layer 177) may be formed over the one or more MTJ layers. Referring to steps 1190 and Figure 6 An ion beam etching process may be performed to pattern the one or more MTJ layers to form MTJ memory cells (126, 130, 140, 146, 148, 158), and pattern the bottom electrode layer (126L) into a bottom electrode (126), so that the buffer layer (112) prevents the ion beam etching process from exposing the underlying metal interconnect structure 648.

[0065] With reference to all the drawings and according to various embodiments of the present disclosure, a memory cell structure is provided. The memory cell structure may include a first dielectric layer (110). The memory cell structure may also include a buffer layer (112) disposed on the first dielectric layer (110) and a connecting via structure (122, 124) embedded in the buffer layer (112) and the first dielectric layer (110). The memory cell structure may also include a bottom electrode (126) disposed on the connecting via structure (122, 124) and the buffer layer (112), wherein the buffer layer has an etching rate of 0.8 to 1.3 relative to the bottom electrode etching rate. The memory cell structure may also include an MTJ memory cell (126, 130, 140, 146, 148, 158), wherein the MTJ memory cell includes one or more MTJ layers disposed on the bottom electrode (126).

[0066] In one embodiment, the buffer layer (112) may be composed of aluminum oxide (Al2O3). In other embodiments, the buffer layer (112) may be composed of tantalum pentoxide (Ta2O5). In one embodiment, the buffer layer (112) may have a vertical thickness of 10 nanometers to 70 nanometers. In one embodiment, the buffer layer (112) may have a vertical thickness ratio of 0.7 to 1 relative to the vertical thickness of the bottom electrode (126). In one embodiment, the buffer layer (112) has a relative ion beam etching rate of 0.8 to 1.3 relative to the ion beam etching rate of the bottom electrode (126). In one embodiment, the exposed portion of the buffer layer (112) may be removed by a wet etching process. In one embodiment, the buffer layer (112) may have wet etch rate.

[0067] With reference to all figures and according to various embodiments of the present disclosure, an MTJ memory device is provided. The MTJ memory device may include an array of MTJ memory cells located above a substrate (9), wherein each of the MTJ memory cells (126, 130, 140, 146, 148, 158) includes a bottom electrode (126), one or more MTJ layers (130, 140, 146, 148) and a top electrode (158). The MTJ memory device may also include an array of connecting via structures, such that each connecting via structure (122, 124) of the array of connecting via structures may contact a bottom surface of a corresponding bottom electrode (126) of a corresponding one of the MTJ memory cells (126, 130, 140, 146, 148, 158). The MTJ memory device may further include a buffer layer (112), the buffer layer (112) may surround the sidewalls of the connecting via structures (122, 124), so that the top surface of the buffer layer (112) may contact the bottom surface of each bottom electrode (126) of each of the MTJ memory cells (126, 130, 140, 146, 148, 158) of the array of MTJ memory cells. In one embodiment, the array of MTJ memory cells (126, 130, 140, 146, 148, 158) may be disposed in a memory array region (100). In one embodiment, the buffer layer (112) may be disposed in the memory array region (100) and a logic region (200) having a lower element density than the memory array region (100) (i.e., the logic region has fewer structural elements than the memory array region on a horizontal plane of the MTJ memory device).

[0068] In some embodiments, a memory cell structure includes: a first dielectric layer; a buffer layer disposed on the first dielectric layer; a connecting via structure embedded in the buffer layer and the first dielectric layer; a bottom electrode disposed on the connecting via structure and the buffer layer, wherein the buffer layer has an etching rate of 0.8 to 1.3 relative to the bottom electrode etching rate; and a magnetic tunnel junction (MTJ) memory cell, including one or more magnetic tunnel junction layers disposed on the bottom electrode. In some embodiments, the buffer layer includes aluminum oxide (Al2O3). In some embodiments, the buffer layer includes tantalum pentoxide (Ta2O5). In some embodiments, the buffer layer has a vertical thickness of 10 nanometers to 70 nanometers. In some embodiments, the buffer layer has a vertical thickness ratio of 0.7 to 1 relative to the vertical thickness of the bottom electrode. In some embodiments, the bottom electrode is composed of titanium nitride (TiN). In some embodiments, the exposed portion of the buffer layer is removed by a wet etching process, and wherein the buffer layer has wet etch rate.

[0069] In some embodiments, a magnetic tunnel junction (MTJ) memory device includes: an array of magnetic tunnel junction memory cells located on a substrate, wherein each of the magnetic tunnel junction memory cells includes: a bottom electrode; one or more magnetic tunnel junction layers; and a top electrode; an array of connecting via structures, wherein each connecting via structure of the array of connecting via structures contacts a bottom surface of a corresponding one of the bottom electrodes of the magnetic tunnel junction memory cells; and a buffer layer surrounding a sidewall of the connecting via structure, wherein a top surface of the buffer layer contacts a bottom surface of each bottom electrode of each of the magnetic tunnel junction memory cells of the array of magnetic tunnel junction memory cells. In some embodiments, the array of magnetic tunnel junction memory cells is disposed in a memory array region, and wherein the buffer layer is disposed in the memory array region and a logic region having a lower element density than the memory array region. In some embodiments, the buffer layer has an ion beam etching rate of 0.8 to 1.3 relative to the bottom electrode ion beam etching rate.

[0070] In some embodiments, a method of forming a magnetic tunnel junction (MTJ) memory device includes: forming a first dielectric layer; forming a buffer layer over the first dielectric layer; patterning the buffer layer and the first dielectric layer to form a cavity through the buffer layer and the first dielectric layer; depositing a fill material into the cavity to form a connecting via structure; forming a bottom electrode layer over a top surface of the connecting via structure and a top surface of the buffer layer; forming one or more magnetic tunnel junction layers for forming a magnetic tunnel junction memory cell; forming a mask over the one or more magnetic tunnel junction layers; and performing an ion beam etching process to pattern the one or more magnetic tunnel junction layers to form the magnetic tunnel junction memory cell and patterning the bottom electrode layer into a bottom electrode, wherein the buffer layer prevents the ion beam etching process from exposing an underlying metal interconnect structure. In some embodiments, the buffer layer is composed of aluminum oxide (Al2O3). In some embodiments, the buffer layer is composed of tantalum pentoxide (Ta2O5). In some embodiments, the buffer layer has a vertical thickness of 10 nanometers to 70 nanometers. In some embodiments, the buffer layer has a vertical thickness ratio of 0.7 to 1 relative to the vertical thickness of the bottom electrode layer. In some embodiments, the buffer layer has an ion beam etching rate of 0.8 to 1.3 relative to the bottom electrode ion beam etching rate. In some embodiments, the bottom electrode layer is composed of titanium nitride (TiN). In some embodiments, the method further includes: forming a second dielectric layer over the exposed portion of the magnetic tunnel junction memory cell, the exposed portion of the bottom electrode, and the exposed portion of the buffer layer; and performing an etching process to form a dielectric spacer portion surrounding the magnetic tunnel junction memory cell and the bottom electrode, wherein performing the etching process removes a portion of the buffer layer so that the first dielectric layer is exposed. In some embodiments, the method further includes: performing a wet etching process to remove the exposed portion of the buffer layer. In some embodiments, the buffer layer has wet etch rate.

[0071] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications to this article without departing from the spirit and scope of the present invention.

Claims

1. A memory cell structure, comprising: a metal line structure embedded in a dielectric material layer overlying a substrate, wherein a top surface of the metal line structure is located within a horizontal plane including a top surface of the dielectric material layer; A dielectric layer stack, covering the metal line structure and the dielectric material layer, and including from bottom to top: a dielectric cap layer, a connecting via-level dielectric layer, and a buffer layer; a connecting via structure contacting the top surface of the metal line structure and extending vertically through the dielectric layer stack, the top surface of the connecting via structure being coplanar with a first horizontal surface segment of the top surface of the buffer layer; A bottom electrode, disposed on the connecting through-hole structure and the buffer layer; a magnetic tunnel junction memory cell including one or more magnetic tunnel junction layers disposed on the bottom electrode and located in a memory array region; a dielectric spacer laterally surrounding the magnetic tunnel junction memory cell; and A memory-level dielectric layer comprising a dielectric material that is laterally spaced apart from the magnetic tunnel junction memory cell by the dielectric spacer, wherein the dielectric material of the memory-level dielectric layer laterally surrounds the magnetic tunnel junction memory cell, directly contacts a second horizontal surface segment of the top surface of the buffer layer that is vertically recessed relative to the first horizontal surface segment, and directly contacts a horizontal surface of the connecting via-level dielectric layer in a logic region that is laterally spaced apart from the memory array region.

2. The memory cell structure of claim 1, wherein the buffer layer comprises aluminum oxide (Al2O3).

3. The memory cell structure of claim 1, wherein the buffer layer comprises tantalum pentoxide (Ta2O5). 4 . The memory cell structure of claim 1 , wherein the buffer layer has a vertical thickness of 10 nanometers to 70 nanometers. 5 . The memory cell structure of claim 1 , wherein the buffer layer has a vertical thickness ratio of 0.7 to 1 relative to a vertical thickness of the bottom electrode.

6. The memory cell structure of claim 1, wherein the bottom electrode is composed of titanium nitride (TiN).

7. The memory cell structure according to claim 1, wherein the exposed portion of the buffer layer is removed by a wet etching process, and wherein the buffer layer has wet etch rate.

8. A magnetic tunnel junction memory device, comprising: a plurality of metal line structures embedded in a dielectric material layer overlying a substrate, wherein top surfaces of the plurality of metal line structures are located within a horizontal plane including a top surface of the dielectric material layer; A dielectric layer stack, covering the plurality of metal line structures and the dielectric material layer, and comprising from bottom to top: a dielectric cap layer, a connecting via-level dielectric layer, and a buffer layer; an array of connected via structures contacting a top surface of a corresponding one of the plurality of metal line structures, extending vertically through the dielectric layer stack, and wherein the top surface of the array of connected via structures is coplanar with a corresponding first horizontal surface segment of the top surface of the buffer layer; and an array of magnetic tunnel junction memory cells located in the memory array region and above the dielectric layer stack and the array of connecting via structures; an array of dielectric spacers laterally surrounding corresponding magnetic tunnel junction memory cells within the array of magnetic tunnel junction memory cells; and a memory-level dielectric layer comprising a dielectric material laterally spaced from corresponding magnetic tunnel junction memory cells in the array of magnetic tunnel junction memory cells by corresponding dielectric spacers in the array of dielectric spacers, wherein the dielectric material of the memory-level dielectric layer laterally surrounds the magnetic tunnel junction memory cells, directly contacts a second horizontal surface segment of the top surface of the buffer layer that is vertically recessed relative to the first horizontal surface segment, and directly contacts a horizontal surface of the connecting via-level dielectric layer in a logic region that is laterally spaced from the memory array region, wherein each of the magnetic tunnel junction memory cells comprises: a bottom electrode having a bottom surface in contact with a corresponding one of the connecting via structures; one or more magnetic tunnel junction layers; and Top electrode. 9 . The magnetic tunnel junction memory device according to claim 8 , wherein the buffer layer is disposed in the memory array region and the logic region having a lower device density than the memory array region. 10 . The magnetic tunnel junction memory device of claim 8 , wherein the buffer layer has an ion beam etching rate of 0.8 to 1.3 relative to an ion beam etching rate of a bottom electrode.

11. A method of forming a magnetic tunnel junction memory device, comprising: forming a metal line structure in the dielectric material layer, wherein a top surface of the metal line structure is located in a horizontal plane including a top surface of the dielectric material layer; Forming a dielectric layer stack on the metal line structure and the dielectric material layer, wherein the dielectric layer stack comprises from bottom to top: a dielectric cap layer, a connecting via-level dielectric layer, and a buffer layer; forming a connecting via structure to contact the top surface of the metal line structure and to extend vertically through the dielectric layer stack, wherein the top surface of the connecting via structure is coplanar with a first horizontal surface segment of the top surface of the buffer layer; forming a bottom electrode on a top surface of the connecting via structure and a top surface of the buffer layer; forming a magnetic tunnel junction memory cell in a memory array region; forming a dielectric spacer to laterally surround the magnetic tunnel junction memory cell; and A memory-level dielectric layer including a dielectric material is formed, the memory-level dielectric layer being laterally spaced apart from the magnetic tunnel junction memory cell by the dielectric spacer, wherein the dielectric material of the memory-level dielectric layer laterally surrounds the magnetic tunnel junction memory cell, directly contacts a second horizontal surface segment of the top surface of the buffer layer that is vertically recessed relative to the first horizontal surface segment, and directly contacts a horizontal surface of the connecting via-level dielectric layer in a logic region that is laterally spaced apart from the memory array region.

12. The method of claim 11, wherein the buffer layer is composed of aluminum oxide (Al2O3).

13. The method of claim 11, wherein the buffer layer is composed of tantalum pentoxide (Ta2O5). The method of claim 11 , wherein the buffer layer has a vertical thickness of 10 nm to 70 nm. 15 . The method of claim 14 , wherein the buffer layer has a vertical thickness ratio of 0.7 to 1 with respect to a vertical thickness of the bottom electrode layer. 16 . The method of claim 11 , wherein the buffer layer has an ion beam etching rate of 0.8 to 1.3 relative to an ion beam etching rate of a bottom electrode.

17. The method of claim 16, wherein the bottom electrode layer is composed of titanium nitride (TiN).

18. The method of claim 11, wherein said forming said magnetic tunnel junction memory cell comprises: forming one or more magnetic tunnel junction layers; forming a mask over the one or more magnetic tunnel junction layers; as well as An ion beam etching process is performed to pattern the one or more magnetic tunnel junction layers to form the magnetic tunnel junction memory cell, wherein the buffer layer prevents the ion beam etching process from exposing underlying metal interconnect structures.

19. The method according to claim 18, further comprising: A wet etching process is performed to remove the exposed portion of the buffer layer.

20. The method according to claim 19, wherein the buffer layer has wet etch rate.

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