Capacitor substrate and method for forming the same

Abstract

The present invention relates to a capacitor substrate and a method for forming the same. The capacitor substrate comprises: a substrate having a metal core layer, a first electrode, comprising a first through-hole passing through the metal core layer and a first through-hole connected to the metal core layer; a second electrode, comprising a second through-hole passing through the substrate and a second through-hole connected to the metal core layer; wherein the metal core layer is exposed at the first through-hole but not at the second through-hole, the interface between the metal core layer and the first through-hole has a first metal layer, and the interface between the metal core layer and the first through-hole and the second through-hole has a second metal layer. The above technical solution of the present invention can at least reduce the steps of the capacitor substrate manufacturing process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a capacitor substrate and a method for forming the same. Background Art

[0002] FIG1 is a schematic diagram of various stages of a conventional method for manufacturing a capacitor substrate. In the conventional method for manufacturing a capacitor substrate (such as an aluminum capacitor substrate), Figure 1A As shown in FIG. 1 , a through hole (Through Via) 12 is first formed in the substrate 10. Then, as shown in FIG. Figure 1B As shown, a first electroplating process is performed to electroplate a conductive material (such as copper) 20 in the through hole 12 and on the surface of the substrate 10. Figure 1C As shown, the remaining space in the through hole 12 is filled with ink material 22 and a conductive material 20 covering the ink material 22 is formed. Figure 1D As shown, a blind via 14 is formed, and another electroplating process is performed to fill the blind via 14 with a conductive material 20. Figure 1E The conductive material 20 is patterned to complete the electrode production of the anode region 18 and the cathode region 19 of the capacitor, such as Figure 1F However, the existing manufacturing process is relatively complicated.

[0003] In addition, the capacitor metal layer material in the prior art capacitor substrate is Al (aluminum), and Al is an amphoteric metal, so Al is easily corroded when it comes into contact with acid or alkaline, which will affect the efficiency of the entire capacitor. If the process steps can be reduced to avoid or reduce the possibility of Al being corroded, the efficiency of the capacitor can be ensured. Summary of the invention

[0004] In view of the problem that the number of steps in the capacitor substrate manufacturing process in the related art is too large, the present invention provides a capacitor substrate and a method for forming the same, which can at least reduce the number of steps in the capacitor substrate manufacturing process.

[0005] According to one aspect of an embodiment of the present invention, a capacitor substrate is provided, comprising: a substrate having a metal core layer, a first through-hole, which passes through the substrate and serves as a first electrode of the capacitor; a first through-hole, which extends to the metal core layer and is electrically connected to the first through-hole; a second through-hole, which passes through the substrate and serves as a second electrode of the capacitor; and a second through-hole, which extends to the metal core layer and is electrically connected to the second through-hole. The metal core layer is exposed at the first through-hole but not at the second through-hole, the interface between the metal core layer and the first through-hole has a first metal layer, and the interface between the metal core layer and the first through-hole and the second through-hole has a second metal layer.

[0006] In some embodiments, each of the first through via and the second through via includes an ink material passing through the metal core layer and a conductive material surrounding the ink material, and upper and lower end surfaces of the ink material are exposed by the conductive material.

[0007] In some embodiments, each of the first through-hole and the second through-hole has a pit on a surface away from the metal core layer.

[0008] In some embodiments, the first through hole and the second through hole are located on opposite sides of the metal core layer.

[0009] In some embodiments, the metal core of the metal core layer includes an aluminum material.

[0010] In some embodiments, the metal core layer further includes a dielectric layer covering the aluminum material and a capacitor metal layer covering the dielectric layer.

[0011] In some embodiments, the second metal layer contacts the capacitor metal layer.

[0012] In some embodiments, each of the first through via and the second through via has an opening away from the metal core layer, wherein a lattice size of the metal material of each of the first through via and the second through via is greater near the opening than away from the opening.

[0013] In some embodiments, each of the first via and the second via has an opening away from the metal core layer, wherein a lattice size of each of the first via and the second via near the opening is greater than a lattice size away from the opening.

[0014] In some embodiments, the material of each of the first metal layer and the second metal layer includes zinc and nickel.

[0015] In some embodiments, the first electrode is an anode of the capacitor substrate and the second electrode is a cathode of the capacitor substrate.

[0016] According to another aspect of an embodiment of the present invention, a method for forming a capacitor substrate is provided, comprising: providing a substrate having a metal core layer; forming a first through-hole and a second through-hole passing through the substrate and a first blind hole and a second blind hole connected to the metal core layer, wherein the metal core layer is exposed to the first through-hole but not to the second through-hole; plating a first metal layer on the surface of the metal core layer exposed in the first through-hole, and plating a second metal layer on the surface of the metal core layer exposed at the bottom of the first blind hole and the second blind hole; forming a metal material in the first through-hole, the first blind hole, the second through-hole, and the second blind hole to form a first electrode and a second electrode of the capacitor.

[0017] In some embodiments, performing the electroplating process includes: first performing low-current electroplating, and then performing high-current electroplating.

[0018] In some embodiments, during the electroplating process, the lattice size of the metal material formed first is smaller than the lattice size of the metal material formed later.

[0019] In some embodiments, after performing the electroplating process, the method further includes: filling ink material into the metal material in the first through-hole and the second through-hole.

[0020] In some embodiments, after performing the electroplating process, the method further includes: patterning the metal material to separate the first electrode and the second electrode.

[0021] In some embodiments, plating the first metal layer and the second metal layer includes forming the first metal layer and the second metal layer using zinc and nickel materials.

[0022] In some embodiments, after performing an electroplating process on the metal material, pits are formed on the surface of the metal material at the first blind hole and the second blind hole.

[0023] In some embodiments, forming the first blind via and the second blind via includes forming the first through via and the second through via on opposite sides of the metal core layer.

[0024] In some embodiments, the first electrode is used as an anode of the capacitor substrate and the second electrode is used as a cathode of the capacitor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0026] Figures 1A to 1F It is a schematic diagram of various stages of a conventional method for manufacturing a capacitor substrate.

[0027] Figure 2-Figure 5 and Figure 7-Figure 8 is a schematic diagram of various stages of forming a capacitor substrate according to an embodiment of the present invention.

[0028] Fig. 6A A schematic diagram of the structure of the metal core layer is shown.

[0029] Figure 6B A schematic structural diagram of forming a metal layer on a metal core layer is shown.

[0030] Fig. 9 A flow chart of forming a capacitor substrate according to an embodiment of the present invention is shown.

[0031] Fig.10is a schematic diagram of a capacitor substrate according to another embodiment of the present invention.

[0032] Fig.11 yes Fig.10 Schematic diagram of the structure of the third through hole. Specific embodiments

[0033] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0034] According to an embodiment of the present invention, a method for forming a capacitor substrate is provided. First, Figure 2 As shown, a substrate 210 is provided. The substrate 210 has a first side 211 and a second side 212 opposite to the first side 211. The substrate 210 has a metal core layer (Core) 220 inside. In some embodiments, the metal core of the metal core layer 220 may include an aluminum material. The metal core layer 220 may also include a dielectric layer covering the aluminum material and a capacitor metal layer covering the dielectric layer (hereinafter referred to as Fig. 6A and Figure 6B details).

[0035] like Figure 3 As shown, a first through hole 222 and a second through hole 224 are formed through the substrate 210. Both the first through hole 222 and the second through hole 224 extend from the first side 211 to the second side 212 of the substrate 210. The metal core layer 220 is exposed to the first through hole 222. That is, the first through hole 222 passes through the metal core layer 220, so that the metal core layer 220 is exposed at the side wall of the first through hole 222. The metal core layer 220 is not provided at the position where the second through hole 224 is formed, and the metal core layer 220 is not exposed to the second through hole 224.

[0036] like Figure 4 As shown, a first blind hole 232 and a second blind hole 234 are formed to reach the metal core layer 220. In some embodiments, the first through hole 222 and the second through hole 224 are formed by a mechanical drilling process. In some embodiments, the first blind hole 232 and the second blind hole 234 are formed by a laser process.

[0037] In some embodiments, the first blind hole 232 and the second blind hole 234 are formed from the first side 211 and the second side 212 of the substrate 210, respectively, so that the first blind hole 232 and the second blind hole 234 are formed on opposite sides of the metal core layer 220. The first blind hole 232 extends upward from the first side 211 of the substrate 210 to the metal core layer 220. The second blind hole 234 extends downward from the second side 212 of the substrate 210 to the metal core layer 220.

[0038] like Figure 5 As shown, a first metal layer 242 is plated on the surface of the metal core layer 220 exposed in the first through-hole 222. A second metal layer 244 is plated on the surface of the metal core layer 220 exposed at the bottom of the first blind hole 232 and the second blind hole 234. The second metal layer 244 is in contact with the capacitor metal layer. In some embodiments, the first metal layer 242 and the second metal layer 244 are formed using zinc and nickel materials. The materials of the first metal layer 242 and the second metal layer 244 both include zinc and nickel.

[0039] Specifically, Fig. 6A shows a schematic diagram of the structure of the metal core layer, Figure 6B FIG. 2 shows a schematic diagram of a structure in which a metal layer is formed on a metal core layer. Fig. 6A As shown, the metal core layer 220 includes a metal core 281. The metal core 281 may include an aluminum material. The metal core layer 220 may further include a dielectric layer 282 covering the metal core 281 and a capacitor metal layer 283 covering the dielectric layer 282.

[0040] Combination Figure 5 and Figure 6B As shown, in some embodiments, Zn / Ni (zinc / nickel) chemical plating is performed on the exposed area of ​​the metal core layer 220 of the aluminum material in the first through-hole 222, thereby forming a first metal layer 242 on the surface of the exposed metal core layer 220 in the first through-hole 222. By forming the first metal layer 242 on the surface of the metal core layer 220 in the first through-hole 222, the first metal layer 242 can protect the metal core layer 220 during the subsequent electroplating of the metal material. In addition, the first metal layer 242 can also be used as a seed layer for electroplating during the subsequent electroplating of the metal material.

[0041] like Figure 5As shown, during the Zn / Ni chemical plating of the metal core layer 220 exposed in the first through-hole 222, a second metal layer 244 of Zn / Ni is also formed on the metal core layer 220 exposed at the bottom surfaces of the first blind hole 232 and the second blind hole 234. Since the present invention co-electroplates metal materials in the second through-hole 224 and the second blind hole 234 in the subsequent process, the second metal layer 244 is also formed on the metal core layer 220 in the second blind hole 234.

[0042] Continue to refer Figure 5 As shown, a metal material electroplating process is performed to form a metal material 250 (also referred to as a conductive material) in the first through-hole 222, the second through-hole 224, the first blind hole 232, and the second blind hole 234. The metal material 250 does not completely fill the space in the first through-hole 222 and the second through-hole 224, the metal material 250 completely fills the first blind hole 232 and the second blind hole 234, and the metal material 250 may cover the first side 211 and the second side 212 of the substrate 210. In some embodiments, the metal material 250 may be copper.

[0043] In some embodiments, during the electroplating process of the metal material 250, since the first through-hole 222, the second through-hole 224 and the first blind hole 232, the second blind hole 234 are electroplated together, a two-stage electroplating can be used. In the two-stage electroplating, a small current electroplating is performed first, and then a large current electroplating is performed. Among them, the small current is more suitable for electroplating in the first blind hole 232 and the second blind hole 234, and the large current is more suitable for electroplating in the first through-hole 222 and the second through-hole 224. Since during the co-electroplating, electroplating is performed first with a small current and then with a large current, this can take into account the electroplating effect of both the through-holes (222, 224) and the blind holes (232, 234).

[0044] In some embodiments, plus reverse current electroplating is used during the first 2 / 3 electroplating process to fill the first blind hole 232 and the second blind hole 234, and direct current (DC) current electroplating is used during the last 1 / 3 electroplating process to fill the first blind hole 232 and the second blind hole 234. In other embodiments, other appropriate configurations can also be made for the two-stage electroplating. Due to the two-stage electroplating, there are two different lattice sizes in the metal material 250 formed by electroplating. Among them, the lattice size of the metal material 250 formed first is smaller than the lattice size of the metal material 250 formed later. At the openings of the first through-hole 222 and the second through-hole 224 away from the metal core layer 220, the lattice size of the metal material 250 near the opening is larger than the lattice size away from the opening. At the openings of the first blind hole 232 and the second blind hole 234 away from the metal core layer 220, the lattice size of the metal material 250 near the opening is larger than the lattice size away from the opening.

[0045] After the electroplating process of the metal material 250 is performed, since the present invention adopts co-plating in the first through hole 222, the second through hole 224, the first blind hole 232 and the second blind hole 234, and since the electroplating process first performs low-current electroplating and then performs high-current electroplating, dimples 290 are generated on the surface of the metal material 250 formed at the first blind hole 232 and the second blind hole 234. In some embodiments, the depth of the dimples 290 is in the range of 2 μm-5 μm.

[0046] like Figure 7 As shown, the ink material 262 is filled in the metal material 250 in the first through hole 222 and the second through hole 224. Since the metal material 250 does not completely fill the space in the first through hole 222 and the second through hole 224, the ink material 262 is filled in the remaining space of the first through hole 222 and the second through hole 224. The metal material 250 surrounds the ink material 262. The upper end surface and the lower end surface of the ink material 262 are exposed through the metal material 250.

[0047] like Figure 8 As shown, the metal material 250 is patterned to form the capacitor substrate 200. The metal material 250 on the first side 211 and the second side 212 of the substrate 210 is patterned to remove the metal material 250 in the first through-hole 222 and the first blind hole 232, so as to separate the metal material 250 in the second through-hole 224 and the second blind hole 234. The metal material 250 and the ink material 262 in the first through-hole 222 may be collectively referred to as a first through-via 272, which serves as a first electrode of the capacitor substrate 200. The metal material 250 in the first blind hole 232 may be referred to as a first through-via 278. The metal material 250 and the ink material 262 in the second through-hole 224 may be collectively referred to as a second through-via 274, which serves as a second electrode of the capacitor substrate 200. The metal material 250 in the second blind hole 234 may be referred to as a second through-via 279.

[0048] Fig. 9 FIG. 1 is a flow chart of forming a capacitor substrate according to an embodiment of the present invention. Figure 2 As shown, a substrate 210 having a metal core layer 220 is provided.

[0049] At step S904, refer to Figure 3 and Figure 4 As shown, first and second through-holes 222 and 224 are formed through the substrate 210 and first and second blind holes 232 and 234 are connected to the metal core layer 220 , wherein the metal core layer 220 is exposed to the first through-hole 222 but not to the second through-hole 224 .

[0050] At step S906, refer to Figure 5 As shown, a first metal layer 242 is plated on the surface of the metal core layer 220 exposed in the first through hole 222 , and a second metal layer 244 is plated on the surface of the metal core layer 220 exposed at the bottom of the first blind hole 232 and the second blind hole 234 .

[0051] At step S908, refer to Figure 5 As shown, metal material 250 is formed in the first through hole 222, the first blind hole 232, the second through hole 224 and the second blind hole 234 to facilitate subsequent processes (such as Figure 7 and Figure 8 As shown in the figure, a first electrode and a second electrode of a capacitor are formed.

[0052] refer to Figure 8 The structure of the capacitor substrate of the present invention is described. Figure 8 As shown, the capacitor substrate 200 provided by the present invention includes a substrate 210 having a metal core layer 220, a first through-hole 272, a second through-hole 274, a first through-hole 278, and a second through-hole 278. The first through-hole 272 passes through the substrate 210 and the metal core layer 220 and serves as a first electrode of the capacitor. The second through-hole 274 passes through the substrate 210 and serves as a second electrode of the capacitor. Each of the first through-hole 272 and the second through-hole 274 includes an ink material 262 passing through the substrate 210 and a conductive material 250 surrounding the ink material 262, and the upper end surface and the lower end surface of the ink material 262 are exposed by the conductive material 250. In some embodiments, the first through-hole 272 is used as an anode of the capacitor substrate 210, and the second through-hole 274 is used as a cathode of the capacitor substrate 210.

[0053] The metal core layer 220 is exposed at the first through-via 272, and the side of the metal core layer 220 adjacent to the first through-via 272 is not covered by the dielectric material. The first metal layer 242 is provided at the interface between the metal core layer 220 and the first through-via 272. The metal core layer 220 is not exposed at the second through-via, and the side of the metal core layer 220 adjacent to the second through-via 274 may be covered by the dielectric material in the substrate 210.

[0054] The first through hole 278 and the second through hole 279 are located on opposite sides of the metal core layer 220. The first through hole 278 extends to the metal core layer 220 and is electrically connected to the first through hole 272. The second through hole 279 extends to the metal core layer 220 and is electrically connected to the second through hole 274. The second metal layer 244 is provided at the interface between the metal core layer 220 and the first through hole 278 and the second through hole 279. The first through hole 278 and the second through hole 279 have pits 290 on their surfaces away from the metal core layer 220.

[0055] The metal material 250 extending on the first side 211 of the substrate 210 between the first through-via 272 and the first through-via 278 is formed as a first trace 288, and the metal material 250 extending on the second side 212 of the substrate 210 between the second through-via 274 and the second through-via 279 is formed as a second trace 289. The first through-via 278 is connected to the first through-via 274 used as a first electrode through the first trace 288. The first trace 288 and the first through-via 278 can be used to electrically connect the first electrode to other components. The second through-via 279 is connected to the second through-via 274 used as a second electrode through the second trace 289. The second trace 289 and the second through-via 279 can be used to electrically connect the second electrode to other elements.

[0056] In summary, in order to solve the problem of too many steps in the existing capacitor substrate manufacturing process, the present invention reduces the process steps by first forming the holes to be electroplated (for example, through holes 222, 224 and blind holes 232, 234) and then performing the electroplating process together.

[0057] Fig.10 FIG. 2 is a schematic diagram of a capacitor substrate 200 ′ according to another embodiment of the present invention. Fig.10 As shown, a third through hole 291 connected to the first through hole 278 and a third trace 292 connected to the third through hole 291 are formed. A fourth through hole 293 connected to the second through hole 279 and a fourth trace 294 connected to the fourth through hole 293 are also formed. The first through hole 278 and the first trace 288, the second through hole 279 and the second trace 289, the third through hole 291 and the third trace 292, and the fourth through hole 293 and the fourth trace 294 can be RDLs (redistribution lines) on different levels in the capacitor substrate 200'. The RDL can be used to electrically connect the corresponding first electrode (first through-via 272) and the second electrode (second through-via 274) to other components. In some embodiments, the lattice size of the material of the third through hole 291 and the fourth through hole 293 is also different. As Fig.11 As shown, taking the third through hole 291 as an example, the lattice size of the first formed inner layer 2912 of the third through hole 291 is smaller than the lattice size of the later formed outer layer 2914. In some embodiments, the thickness of the inner layer 2912 is not greater than 8 μm.

[0058] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also be aware that these equivalent structures do not deviate from the spirit and scope of the present invention, and can be subjected to various changes, substitutions and changes without departing from the spirit and scope of the present invention.

Claims

1. A capacitor substrate, characterized in that: include: A substrate having a metal core layer, a first through via penetrating the substrate and serving as a first electrode of the capacitor; a first through hole extending to the metal core layer and electrically connected to the first through via; a second through via penetrating the substrate and serving as a second electrode of the capacitor; a second through hole extending to the metal core layer and electrically connected to the second through via; The metal core layer is exposed at the first through-hole but not at the second through-hole, the metal core layer has a first metal layer at the interface with the first through-hole, and the metal core layer has a second metal layer at the interface with the first through-hole and the second through-hole.

2. The capacitor substrate according to claim 1, wherein: Each of the first through-via and the second through-via includes an ink material passing through the metal core layer and a conductive material surrounding the ink material, and an upper end surface and a lower end surface of the ink material are exposed by the conductive material.

3. The capacitor substrate according to claim 1, wherein: Each of the first through-hole and the second through-hole has a pit on a surface away from the metal core layer.

4. The capacitor substrate according to claim 1, wherein: The first through hole and the second through hole are located at two opposite sides of the metal core layer.

5. The capacitor substrate according to claim 1, wherein: The metal core of the metal core layer includes aluminum material.

6. The capacitor substrate according to claim 5, characterized in that The metal core layer further includes a dielectric layer covering the aluminum material and a capacitor metal layer covering the dielectric layer.

7. The capacitor substrate according to claim 6, characterized in that The second metal layer contacts the capacitor metal layer.

8. The capacitor substrate according to claim 1, wherein: Each of the first through via and the second through via has an opening away from the metal core layer, wherein a lattice size of a metal material of each of the first through via and the second through via is larger near the opening than at a distance from the opening.

9. The capacitor substrate according to claim 1, wherein: Each of the first through-hole and the second through-hole has an opening away from the metal core layer, wherein a lattice size of each of the first through-hole and the second through-hole near the opening is larger than a lattice size away from the opening.

10. The capacitor substrate according to claim 1, wherein: A material of each of the first metal layer and the second metal layer includes zinc and nickel.

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