Imaging device

Abstract

The imaging device according to the embodiment includes a first substrate, a second substrate, wirings, and trenches. The first substrate includes pixels each having a photodiode and a floating diffusion portion that holds the charge converted by the photodiode. The second substrate includes a pixel circuit for reading a pixel signal according to the charge held by the floating diffusion portion in the pixel, and the second substrate is stacked on the first substrate. The wirings penetrate the first substrate and the second substrate in the stacking direction and establish an electrical connection between the floating diffusion portion in the first substrate and an amplifying transistor in the pixel circuit of the second substrate. The trenches are formed at least in the second substrate and extend in parallel with the wirings, and the depth of the trenches is equal to or greater than the thickness of the semiconductor layer in the second substrate.

Description

Technical Field

[0001] The present invention relates to an imaging device. Background Art

[0002] In related art, by introducing fine processing and increasing the mounting density, miniaturization of the area per pixel of an imaging device having a two-dimensional structure has been achieved. In recent years, in order to further miniaturize the imaging device and increase the pixel density, an imaging device having a three-dimensional structure has been developed. In an imaging device having a three-dimensional structure, for example, a semiconductor substrate having a plurality of sensor pixels and a semiconductor substrate having a signal processing circuit for processing signals obtained by each sensor pixel are stacked on each other.

[0003] Citation List

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Laid-Open No. 2010-245506 Summary of the Invention

[0006] Technical Problem to be Solved by the Invention

[0007] Incidentally, in an imaging device having a three-dimensional structure, in the case of stacking three semiconductor chips, it is impossible to bond all the semiconductor substrates between the surfaces on the front surface side. In the case of arbitrarily stacking three semiconductor substrates, due to the structure in which the semiconductor substrates are electrically connected to each other, there is a possibility that the chip size increases or miniaturization of the area per pixel is hindered. Therefore, it is desired to provide a three-layer-structured imaging device having the same chip size as before and not hindering miniaturization of the area per pixel.

[0008] In addition, in the case not limited to a three-layer structure, the imaging device uses a connection via as an FD wiring to connect a floating diffusion portion in a pixel and a gate of an amplifying transistor in a pixel circuit. In fine pixels, the area of the connection via of the FD wiring is about 45%. Therefore, since the effective area of the pixel circuit is reduced, it is impossible to expand the layout area of the amplifying transistor.

[0009] Solution to the Technical Problem

[0010] To solve the above problems, a camera device according to an embodiment includes a first substrate, a second substrate, wirings, and trenches. The first substrate includes pixels each having a photodiode and a floating diffusion portion that holds charges converted by the photodiode. The second substrate includes pixel circuits that read pixel signals according to the charges held in the floating diffusion portions of the pixels, and is stacked on the first substrate. The wirings penetrate the first substrate and the second substrate in a stacking direction, and electrically connect the floating diffusion portions in the first substrate to amplification transistors in the pixel circuits of the second substrate. The trenches are formed at least in the second substrate, extend parallel to the wirings, and have a depth equal to or greater than the thickness of a semiconductor layer in the second substrate.

[0011] Advantages of the Invention

[0012] By reducing the parasitic capacitance of the wirings, the charge-voltage conversion efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram showing an example of a functional configuration of a camera device according to an embodiment of the present invention.

[0014] Figure 2 shows Figure 1 a schematic plan view of a schematic configuration of the camera device shown.

[0015] Figure 3 shows along Figure 2 a schematic diagram of a cross-sectional configuration taken along line III-III' shown.

[0016] Figure 4 is Figure 1 an equivalent circuit diagram of the pixel sharing unit shown.

[0017] Figure 5 is a diagram showing an example of a connection state between a plurality of pixel sharing units and a plurality of vertical signal lines.

[0018] Figure 6 shows Figure 3 a schematic cross-sectional view showing an example of a specific configuration of the camera device shown.

[0019] Figure 7A shows Figure 6 a schematic diagram showing an example of a planar configuration of a main part of the first substrate shown.

[0020] Figure 7B shows a pad portion together with Figure 7A a schematic diagram of a planar configuration of a main part of the first substrate shown.

[0021] Figure 8 is a schematic diagram showing an example of the planar structure of the second substrate (semiconductor layer) shown in Figure 6

[0022] Figure 9 is a schematic diagram showing an example of the planar structure of the pixel circuit and the main part of the first substrate together with Figure 6 the first wiring layer shown in

[0023] Figure 10 is a schematic diagram showing Figure 6 an example of the planar structure of the first wiring layer and the second wiring layer shown in

[0024] Figure 11 is a schematic diagram showing Figure 6 an example of the planar structure of the second wiring layer and the third wiring layer shown in

[0025] Figure 12 is a schematic diagram showing Figure 6 an example of the planar structure of the third wiring layer and the fourth wiring layer shown in

[0026] Figure 13 is a schematic diagram for explaining the path of the input signal to the imaging device shown in Figure 3

[0027] Figure 14 is a schematic diagram for explaining Figure 3 the signal path of the pixel signal of the imaging device shown in

[0028] Figure 15 is a schematic diagram showing Figure 8 a modified example of the planar structure of the second substrate (semiconductor layer) shown in

[0029] Figure 16 is a schematic diagram showing the planar structure of the first wiring layer and the main part of the first substrate together with Figure 15 the pixel circuit shown in

[0030] Figure 17 is a schematic diagram showing an example of the planar structure of the second wiring layer together with Figure 16 the first wiring layer shown in

[0031] Figure 18 is a schematic diagram showing an example of the planar structure of the third wiring layer together with Figure 17 the second wiring layer shown in

[0032] Figure 19 is a schematic diagram showing an example of the planar structure of the fourth wiring layer together with Figure 18 the third wiring layer shown in ​​

[0033] Figure 20 is a schematic diagram showing a modified example of the planar structure of the first substrate shown in Figure 7A

[0034] Figure 21 is a schematic diagram showing an example of the planar structure of the second substrate (semiconductor layer) stacked on the first substrate shown in Figure 20

[0035] Figure 22 is a schematic diagram showing an example of the planar structure of the first wiring layer together with the pixel circuit shown in Figure 21

[0036] Figure 23 is a schematic diagram showing an example of the planar structure of the second wiring layer together with the first wiring layer shown in Figure 22

[0037] Figure 24 is a schematic diagram showing an example of the planar structure of the third wiring layer together with the second wiring layer shown in Figure 23

[0038] Figure 25 is a schematic diagram showing an example of the planar structure of the fourth wiring layer together with the third wiring layer shown in Figure 24

[0039] Figure 26 is a schematic diagram showing Figure 20 another example of the planar structure of the first substrate shown in

[0040] Figure 27 is a schematic diagram showing an example of the planar structure of the second substrate (semiconductor layer) stacked on the first substrate shown in Figure 26

[0041] Figure 28 is a schematic diagram showing an example of the planar structure of the first wiring layer together with the pixel circuit shown in Figure 27

[0042] Figure 29 is a schematic diagram showing an example of the planar structure of the second wiring layer together with the first wiring layer shown in Figure 28

[0043] Figure 30 is a schematic diagram showing an example of the planar structure of the third wiring layer together with the second wiring layer shown in Figure 29

[0044] Figure 31 is a schematic diagram showing an example of the planar structure of the fourth wiring layer together with the third wiring layer shown in Figure 30 ​​​​​​​​​​Schematic diagram of an example of a planar structure together with the third wiring layer shown.

[0045] Figure 32 Shows Figure 3 Schematic cross-sectional view of another example of the imaging device shown.

[0046] Figure 33 For explaining Figure 32 Schematic diagram of the path of the input signal of the imaging device shown.

[0047] Figure 34 For explaining Figure 32 Schematic diagram of the signal path of the pixel signal of the imaging device shown.

[0048] Figure 35 Shows Figure 6 Schematic cross-sectional view of another example of the imaging device shown.

[0049] Figure 36 Shows Figure 4 Another example of the equivalent circuit shown.

[0050] Figure 37 Shows Figure 7A Schematic plan view of another example of the pixel isolation portion shown, etc.

[0051] Figure 38 Equivalent circuit diagram showing an example of the structure of the pixel sharing unit in the imaging device of the 2-1 embodiment.

[0052] Figure 39 Schematic cross-sectional view showing an example of the stacked structure of the first substrate and the second substrate in the imaging device of the 2-1 embodiment.

[0053] Figure 40 Schematic diagram showing an example of the stacked structure of the first substrate and the second substrate.

[0054] Figure 41 Schematic diagram showing an example of the arrangement of the trenches T1 on the surface of the second substrate.

[0055] Figure 42 Schematic diagram showing an example of the arrangement of the trenches T2 on the surface of the second substrate.

[0056] Figure 43 Schematic diagram showing an example of the arrangement of the trenches T3 on the surface of the second substrate.

[0057] Figure 44 Schematic diagram showing an example of the arrangement of the trenches T4 on the surface of the second substrate.

[0058] Figure 45 It is a schematic cross-sectional view showing an example of the stacked structure of the first substrate and the second substrate of the 2-2 embodiment.

[0059] Figure 46A It is a schematic diagram showing an example of the arrangement constitution of the trenches T5 on the surface of the second substrate.

[0060] Figure 46B It is a schematic diagram showing an example of the arrangement constitution of the trenches T10 on the surface of the second substrate.

[0061] Figure 46C It is a schematic diagram showing an example of the arrangement constitution of the trenches T11 on the surface of the second substrate.

[0062] Figure 46D It is a schematic diagram showing an example of the arrangement constitution of the trenches T12 on the surface of the second substrate.

[0063] Figure 46E It is a schematic diagram showing an example of the arrangement constitution of the trenches T13 on the surface of the second substrate.

[0064] Figure 46F It is a schematic diagram showing an example of the arrangement constitution of the trenches T14 on the surface of the second substrate.

[0065] Figure 46G It is a schematic diagram showing an example of the arrangement constitution of the trenches T15 on the surface of the second substrate.

[0066] Figure 46H It is a schematic diagram showing an example of the arrangement constitution of the trenches T16 on the surface of the second substrate.

[0067] Figure 47 It is a schematic diagram showing an example of the schematic cross-sectional shape of the trench T5.

[0068] Figure 48A It is an equivalent circuit diagram showing an example of the structure of the pixel sharing unit of the imaging device of the 2-3 embodiment.

[0069] Figure 48B It is an equivalent circuit diagram showing another example of the structure of the pixel sharing unit of the imaging device of the 2-3 embodiment.

[0070] Figure 49 It is a schematic cross-sectional view showing an example of the stacked structure of the first substrate and the second substrate of the 2-3 embodiment.

[0071] Figure 50A It is an equivalent circuit diagram showing an example of the structure of a plurality of pixel circuits of the second substrate of the 3-1 embodiment.

[0072] Figure 50B It is a schematic structural block diagram of a column signal processing unit of the first aspect.

[0073] Figure 50C It is a schematic structural block diagram of a column signal processing unit of the second aspect.

[0074] Figure 50D It is an explanatory diagram of a first structural example of a comparator.

[0075] Figure 50E It is an explanatory diagram of a second structural example of a comparator.

[0076] Figure 50F It is an explanatory diagram of a third structural example of a comparator.

[0077] Figure 50G It is a schematic structural block diagram of a column signal processing unit of the third aspect.

[0078] Figure 50H It is an explanatory diagram of a structural example of a comparator of the third aspect.

[0079] Figure 50I It is a schematic structural block diagram of a column signal processing unit of the fourth aspect.

[0080] Figure 50J It is an explanatory diagram of a structural example of a pre-circuit.

[0081] Figure 51 It is a schematic cross-sectional view showing an example of a stacked structure of a first substrate and a second substrate of the 3-1 embodiment.

[0082] Figure 52 It is a schematic diagram showing an example of a planar structure of a pixel circuit.

[0083] Figure 53 It shows the FD wiring FDL and the shielding wiring SL2 and Figure 52 a schematic diagram of an example of a planar structure overlapping the front surface of the pixel circuit shown.

[0084] Figure 54 It is a schematic cross-sectional view showing an example of a stacked structure of a first substrate and a second substrate of the 3-2 embodiment.

[0085] Figure 55 It is an equivalent circuit diagram showing an example of the structure of a plurality of pixel circuits on a second substrate of the 3-3 embodiment.

[0086] Figure 56 It is an equivalent circuit diagram showing an example of the structure of a pixel sharing unit of a global shutter mode imaging device of the 3-4 embodiment.

[0087] Figure 57 It is an equivalent circuit diagram showing a structural example of a pixel sharing unit of a storage - holding type global shutter mode imaging device according to the 3rd - 5th embodiments.

[0088] Figure 58 It is a diagram showing an example of a schematic configuration of an imaging system including an imaging device according to the above - mentioned embodiments and their modifications.

[0089] Figure 59 It shows Figure 58 a diagram showing an example of an imaging process of the imaging system shown.

[0090] Figure 60 It is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0091] Figure 61 It is an explanatory diagram showing an example of installation positions of an out - of - vehicle information detection unit and an imaging unit.

[0092] Figure 62 It is a diagram showing a schematic configuration of an endoscopic surgery system.

[0093] Figure 63 It is a block diagram showing an example of a functional configuration of a camera head and a CCU. Specific embodiments

[0094] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that in the following embodiments, the same parts are denoted by the same reference numerals, and redundant explanations will be omitted.

[0095] Hereinafter, a scheme for implementing the present invention will be described in detail with reference to the accompanying drawings. Note that the description will be given in the following order.

[0096] 1. The 1st embodiment (imaging device having a three - substrate stacked structure)

[0097] 2. The 1st modification (first example of a planar structure)

[0098] 3. The 2nd modification (second example of a planar structure)

[0099] 4. The 3rd modification (third example of a planar structure)

[0100] 5. The 4th modification (example in which the contact portion between substrates is provided at the central portion of the pixel array portion)

[0101] 6. The 5th modification (example including a planar transfer transistor)

[0102] 7. The 6th modification (example in which one pixel is connected to one pixel circuit)

[0103] 8. Seventh Modification Example (Structural Example of Pixel Isolation Portion)

[0104] 9. Second Embodiment

[0105] 9.1 Problems to be Solved by the Second Embodiment

[0106] 9.2 Overview of the Second Embodiment

[0107] 9.3 Specific Example of the Second-1 Embodiment

[0108] 9.3.1 Structure of the Second-1 Embodiment

[0109] 9.3.2 Operations and Effects of the Second-1 Embodiment

[0110] 9.3.3 Modification Example of the Second-1 Embodiment

[0111] 9.4 Specific Example of the Second-2 Embodiment

[0112] 9.4.1 Structure of the Second-2 Embodiment

[0113] 9.4.2 Operations and Effects of the Second-2 Embodiment

[0114] 9.5 Specific Example of the Second-3 Embodiment

[0115] 9.5.1 Structure of the Second-3 Embodiment

[0116] 9.5.2 Operations and Effects of the Second-3 Embodiment

[0117] 10. Third Embodiment

[0118] 10.1 Problems to be Solved by the Third Embodiment

[0119] 10.2 Overview of the Third Embodiment

[0120] 10.3 Specific Example of the Third-1 Embodiment

[0121] 10.3.1 Structure of the Third-1 Embodiment

[0122] 10.3.2 Operations and Effects of the Third-1 Embodiment

[0123] 10.4 Specific Example of the Third-2 Embodiment

[0124] 10.4.1 Structure of the Third-2 Embodiment

[0125] 10.4.2 Operations and Effects of the Third-2 Embodiment

[0126] 10.5 Specific Example of the 3-3 Embodiment

[0127] 10.5.1 Structure of the 3-3 Embodiment

[0128] 10.5.2 Operation and Effect of the 3-3 Embodiment

[0129] 10.6 Specific Example of the 3-4 Embodiment

[0130] 10.6.1 Structure of the 3-4 Embodiment

[0131] 10.6.2 Operation and Effect of the 3-4 Embodiment

[0132] 10.7 Specific Example of the 3-5 Embodiment

[0133] 10.7.1 Structure of the 3-5 Embodiment

[0134] 10.7.2 Operation and Effect of the 3-5 Embodiment

[0135] 11. Application Example (Imaging System)

[0136] 12. Application Example

[0137] <1. First Embodiment>

[0138] [Functional Configuration of Imaging Device 1]

[0139] Figure 1 is a block diagram showing an example of the functional configuration of an imaging device (imaging device 1) according to an embodiment of the present invention.

[0140] For example, Figure 1 the imaging device 1 includes an input unit 510A, a line driving unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0141] In the pixel array unit 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 including a plurality of pixels is a repeating unit, and the pixel sharing unit 539 is repeatedly arranged in an array composed of a row direction and a column direction. In this specification, for convenience, the row direction may be referred to as the H direction, and the column direction perpendicular to the row direction may be referred to as the V direction. In Figure 1 the example, one pixel sharing unit 539 includes four pixels (pixel 541A, pixel 541B, pixel 541C, and pixel 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (to be described later Figure 6as shown in etc.). The pixel sharing unit 539 is a unit that shares one pixel circuit (the pixel circuit 210 to be described later). In other words, for every 4 pixels (pixel 541A, pixel 541B, pixel 541C, pixel 541D), one pixel circuit (the pixel circuit 210 to be described later) is provided. The pixel circuit operates in a time-division manner to sequentially read the pixel signals of each of the pixels 541A, 541B, 541C, and 541D. For example, the pixels 541A, 541B, 541C, and 541D are arranged in 2 rows × 2 columns. In the pixel array unit 540, a plurality of row driving signal lines 542 and a plurality of vertical signal lines (column read lines) 543 are provided together with the pixels 541A, 541B, 541C, and 541D. The row driving signal lines 542 drive the pixels 541 arranged side by side in the row direction in the pixel array unit 540 and included in each of the plurality of pixel sharing units 539. In the pixel sharing unit 539, each of the pixels arranged side by side in the row direction is driven. As will be described in detail later with reference to Figure 4 the pixel sharing unit 539 is provided with a plurality of transistors. To drive each of the plurality of transistors, a plurality of row driving signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column read line) 543. The pixel signal is read from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 through the vertical signal line (column read line) 543. Figure 4

[0142] The row driving unit 520 includes, for example, a row address control unit (in other words, a row decoder unit) that determines the position of the row for driving the pixels and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0143] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit with the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539). The column signal processing unit 550 may have an amplification circuit unit that amplifies the signal read from the pixel sharing unit 539 through the vertical signal line 543. The column signal processing unit 550 may have a noise processing unit. In the noise processing unit, for example, the system noise level is removed from the signal obtained as a result of photoelectric conversion read by the pixel sharing unit 539.

[0144] ​The column signal processing unit 550 has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel common unit 539 or the analog signal after noise processing is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared. In the counter unit, the time is measured until the comparison result of the comparator unit is inverted. The column signal processing unit 550 may include a horizontal scan circuit unit that executes control to scan the read columns.

[0145] Based on the reference clock signal or the timing control signal input to the device, the timing control unit 530 supplies signals for controlling timing to the row driving unit 520 and the column signal processing unit 550.

[0146] The image signal processing unit 560 is a circuit that performs various signal processes on the data obtained as a result of photoelectric conversion (in other words, the data obtained as a result of the imaging operation of the imaging device 1). The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may include a processor unit.

[0147] An example of the signal process executed in the image signal processing unit 560 is a tone curve correction process that gives a lot of gray levels when the AD-converted imaging data is data obtained by imaging a dark subject, and reduces gray levels when the AD-converted imaging data is data obtained by imaging a bright subject. In this case, it is desirable to pre-store the characteristic data of the tone curve in the data holding unit of the image signal processing unit 560 based on the tone curve by which the gray level of the imaging data is corrected.

[0148] The input unit 510A is used, for example, to input a reference clock signal, a timing control signal, characteristic data, etc. from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, etc. The characteristic data is, for example, to be stored in the data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude change unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0149] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is used to input the signal input to the input terminal 511 into the imaging device 1. In the input amplitude change unit 513, the amplitude of the signal obtained by the input circuit unit 512 is changed to an amplitude that can be easily used in the imaging device 1. In the input data conversion circuit unit 514, the arrangement of the data string of the input data is changed. The input data conversion circuit unit 514 includes, for example, a serial-to-parallel conversion circuit. In the serial-to-parallel conversion circuit, the serial signal received as the input data is converted into a parallel signal. In the input unit 510A, the input amplitude change unit 513 and the input data conversion circuit unit 514 may not be provided. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on the power supplied to the imaging device 1 from the outside.

[0150] When the imaging device 1 is connected to an external storage device, the input unit 510A may be provided with a storage interface circuit for receiving data from the external storage device. Examples of the external storage device include a flash memory, SRAM, and DRAM.

[0151] The output unit 510B outputs the image data to the outside of the device. The image data is, for example, the image data captured by the imaging device 1, the image data that has been signal-processed by the image signal processing unit 560, and the like. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0152] The output data conversion circuit unit 515 includes, for example, a parallel-to-serial conversion circuit, and in the output data conversion circuit unit 515, the parallel signal used inside the imaging device 1 is converted into a serial signal. The output amplitude change unit 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude can be easily used in an external device connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the wiring outside the imaging device 1 connected to the output terminal 518 is driven by the output circuit unit 517. At the output terminal 518, data is output from the imaging device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude change unit 516 may not be provided.

[0153] When the imaging device 1 is connected to an external storage device, the output unit 510B may be provided with a storage interface circuit for outputting data to the external storage device. Examples of the external storage device include a flash memory, SRAM, and DRAM, etc.

[0154] [Schematic structure of the imaging device 1]

[0155] Figure 2 andFigure 3 An example of the schematic configuration of the imaging device 1 is shown. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Figure 2 The planar configurations of the first substrate 100, the second substrate 200, and the third substrate 300 are schematically shown, and Figure 3 the cross-sectional configurations of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on one another are schematically shown. Figure 3 Corresponding to the cross-sectional configuration taken along Figure 2 the line III-III' shown. The imaging device 1 is an imaging device having a three-dimensional structure formed by bonding three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film surrounding the wiring is referred to as the wiring layer (100T, 200T, 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in sequence, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in sequence along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. Figure 3 The arrow shown indicates the incident direction of the light L on the imaging device 1. In this specification, for convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be referred to as "lower", "lower side", "below", and the side opposite to the light incident side may be referred to as "upper", "upper side", and "above". In addition, in this specification, for convenience, in a substrate including a semiconductor layer and a wiring layer, the side of the substrate closer to the wiring layer may be referred to as the front, and the side of the substrate closer to the semiconductor layer may be referred to as the back. The description in the specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated type imaging device in which light enters from the back side of the first substrate 100 having a photodiode.

[0156] Both the first substrate 100 and the second substrate 200 are used to form the pixel array section 540 and the pixel common unit 539 included in the pixel array section 540. In the first substrate 100, a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel common unit 539 are provided. Each of these pixels 541 has a photodiode (a photodiode PD described later) and a transfer transistor (a transfer transistor TR described later). In the second substrate 200, a pixel circuit (a pixel circuit 210 described later) included in the pixel common unit 539 is provided. The pixel circuit reads the pixel signals transferred from the photodiodes of each of the pixels 541A, 541B, 541C, and 541D through the transfer transistor, or resets the photodiodes. In addition to this pixel circuit, the second substrate 200 also has a plurality of row driving signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also has a power supply line 544 extending in the row direction. The third substrate 300 has, for example, an input unit 510A, a row driving unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The row driving unit 520 is provided, for example, in a region where a part of the row driving unit 520 overlaps with the pixel array section 540 in the stacking direction (hereinafter, simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driving unit 520 is provided in a region where the row driving unit 520 overlaps with a part near the end in the H direction of the pixel array section 540 in the stacking direction ( Figure 2 ). For example, the column signal processing unit 550 is provided in a region where a part of the column signal processing unit 550 overlaps with the pixel array section 540 in the stacking direction. More specifically, the column signal processing unit 550 is provided in a region where the column signal processing unit 550 overlaps with a part near the end in the V direction of the pixel array section 540 in the stacking direction ( Figure 2 ). Although not shown, the input unit 510A and the output unit 510B may be provided in a part other than the third substrate 300 and may be provided on the second substrate 200. Alternatively, the input unit 510A and the output unit 510B may be provided on the back (light incident surface) side of the first substrate 100. Note that, as another name, the pixel circuit provided on the second substrate 200 may also be referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel reading circuit, or a reading circuit. In this specification, the term "pixel circuit" is used.

[0157] The first substrate 100 and the second substrate 200 are, for example, connected by through electrodes (through electrodes described laterFigure 6 are electrically connected to the through electrodes 120E and 121E). For example, the second substrate 200 and the third substrate 300 are electrically connected through the contact portions 201, 202, 301, and 302. The contact portions 201 and 202 are provided on the second substrate 200, and the contact portions 301 and 302 are provided on the third substrate 300. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided and a contact region 202R in which a plurality of contact portions 202 are provided. The third substrate 300 has a contact region 301R in which a plurality of contact portions 301 are provided and a contact region 302R in which a plurality of contact portions 302 are provided. The contact region 201R and the contact region 301R are arranged in the stacking direction ( Figure 3 ). That is, for example, the contact region 201R and the contact region 301R are provided in a region where the row driving unit 520 (the third substrate 300) and the pixel array unit 540 (the second substrate 200) overlap each other in the stacking direction or in a region near the overlapping region. For example, the contact region 201R and the contact region 301R are arranged at the end portions in the H direction of such a region ( Figure 2 ). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping a part of the row driving unit 520 (specifically, the end portion of the row driving unit 520 in the H direction) ( Figure 2 and Figure 3 ). For example, the contact portions 201 and 301 connect the row driving unit 520 provided on the third substrate 300 to the row driving signal line 542 provided on the second substrate 200. For example, the contact portions 201 and 301 may connect the input unit 510A provided on the third substrate 300 to the power supply line 544 and the reference potential line (the reference potential line VSS described later). The contact region 202R and the contact region 302R are arranged in the stacking direction between the pixel array unit 540 and the column signal processing unit 550 ( Figure 3 ). That is, for example, the contact region 202R and the contact region 302R are provided in a region where the column signal processing unit 550 (the third substrate 300) and the pixel array unit 540 (the second substrate 200) overlap each other in the stacking direction or in a region near the overlapping region. For example, the contact region 202R and the contact region 302R are arranged at the end portions in the V direction of such a region ( Figure 2)。In the third substrate 300, for example, the contact region 301R is provided at a position overlapping with a part of the column signal processing unit 550 (specifically, the end portion of the column signal processing unit 550 in the V direction). Figure 2 and Figure 3 )。For example, the contact portion 202 and the contact portion 302 are used to connect the pixel signals (signals corresponding to the amount of electric charge generated as a result of the photoelectric conversion of the photodiode) output from each of the plurality of pixel common units 539 included in the pixel array unit 540 to the column signal processing unit 550 provided on the third substrate 300. The pixel signals are transmitted from the second substrate 200 to the third substrate 300.

[0158] Figure 3 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected through the wiring layer 100T, the wiring layer 200T, and the wiring layer 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 to the third substrate 300. Specifically, the contact portion 201, the contact portion 202, the contact portion 301, and the contact portion 302 are formed of electrodes formed of a conductive material. For example, the conductive material is formed of a metal material such as copper (Cu), aluminum (Al), or gold (Au). For example, the contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate to the third substrate through wirings formed as electrodes, and enable input and / or output of signals between the second substrate 200 and the third substrate 300.

[0159] The electrical connection portion that can electrically connect the second substrate 200 to the third substrate 300 can be provided at a desired position. For example, as Figure 3 the contact regions 201R, 202R, 301R, and 302R described above, the electrical connection portion can be provided in a region overlapping with the pixel array unit 540 in the stacking direction. In addition, the electrical connection portion can be provided in a region that does not overlap with the pixel array unit 540 in the stacking direction. Specifically, the electrical connection portion can be provided in a region overlapping with the peripheral portion arranged outside the pixel array unit 540 in the stacking direction.

[0160] The first substrate 100 and the second substrate 200 are provided with a connection hole portion Hl and a connection hole portion H2, for example. The connection hole portion H1 and the connection hole portion H2 penetrate the first substrate 100 and the second substrate 200. Figure 3 )。The connection hole portion H1 and the connection hole portion H2 are provided outside the pixel array unit 540 (or a portion overlapping with the pixel array unit 540). Figure 2)。For example, the connection hole portion H1 is disposed outside the pixel array portion 540 in the H direction, and the connection hole portion H2 is disposed outside the pixel array portion 540 in the V direction. For example, the connection hole portion H1 reaches the input unit 510A provided in the third substrate 300, and the connection hole portion H2 reaches the output unit 510B provided in the third substrate 300. The connection hole portions H1 and H2 may be hollow or at least partially contain a conductive material. For example, bonding wires are connected to the electrodes formed as the input unit 510A and / or the output unit 510B. Alternatively, the electrodes formed as the input unit 510A and / or the output unit 510B are connected to the conductive material provided in the connection hole portions H1 and H2. The conductive material provided in the connection hole portions H1 and H2 may be embedded in a part or all of the connection hole portions H1 and H2, and the conductive material may be formed on the sidewalls of the connection hole portions H1 and H2.

[0161] In Figure 3 , the input unit 510A and the output unit 510B are provided in the third substrate 300, but the present invention is not limited thereto. For example, by transmitting the signals of the third substrate 300 through the wiring layer 200T and the wiring layer 300T to the second substrate 200, the input unit 510A and / or the output unit 510B may be provided in the second substrate 200. Similarly, by transmitting the signals of the second substrate 200 through the wiring layer 100T and the wiring layer 200T to the first substrate 1000, the input unit 510A and / or the output unit 510B may be provided in the first substrate 100.

[0162] Figure 4 is an equivalent circuit diagram showing a structural example of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 ( Figure 4 shows four pixels 541 of the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplifying transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD. As described above, by operating one pixel circuit 210 in a time-division manner, the pixel sharing unit 539 sequentially outputs the pixel signals of the four pixels 541 (the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D) included in the pixel sharing unit 539 to the vertical signal line 543. The state where one pixel circuit 210 is connected to a plurality of pixels 541 and the pixel signals of the plurality of pixels 541 are output by one pixel circuit 210 in a time-division manner is referred to as "a plurality of pixels 541 sharing one pixel circuit 210".

[0163] Pixels 541A, 541B, 541C, and 541D have the same components. Hereinafter, in order to distinguish the components of pixels 541A, 541B, 541C, and 541D from each other, identification number 1 is assigned to the end of the reference numeral of the component of pixel 541A, identification number 2 is assigned to the end of the reference numeral of the component of pixel 541B, identification number 3 is assigned to the end of the reference numeral of the component of pixel 541C, and identification number 4 is assigned to the end of the reference numeral of the component of pixel 541D. In cases where it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the ends of the reference numerals of the components of pixels 541A, 541B, 541C, and 541C are omitted.

[0164] Pixels 541A, 541B, 541C, and 541D, for example, have a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion section FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1, PD2, PD3, PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (such as ground). The photodiode PD performs photoelectric conversion on incident light and generates charges according to the amount of received light. The transfer transistor TR (transfer transistors TR1, TR2, TR3, and TR4) is, for example, an n-type complementary metal oxide semiconductor (CMOS) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion section FD, and the gate is electrically connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel common unit 539 (refer to Figure 1 ). The transfer transistor TR transfers the charges generated in the photodiode PD to the floating diffusion section FD. The floating diffusion section FD (floating diffusion sections FD1, FD2, FD3, and FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion section FD is a charge holding device for temporarily holding the charges transferred from the photodiode PD, and is a charge-voltage conversion device for generating a voltage according to the amount of charge.

[0165] The four floating diffusions FD (floating diffusion FD1, floating diffusion FD2, floating diffusion FD3, and floating diffusion FD4) included in one pixel common unit 539 are electrically connected to each other and are electrically connected to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. The drive signal line is a part of the plurality of row drive signal lines 542 connected to one pixel common unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is a part of the plurality of row drive signal lines 542 connected to one pixel common unit 539. The gate of the amplifying transistor AMP is connected to the floating diffusion FD, the drain of the amplifying transistor AMP is connected to the power supply line VDD, and the source of the amplifying transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. The drive signal line is a part of the plurality of row drive signal lines 542 connected to one pixel common unit 539.

[0166] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate of the transfer transistor TR (transfer gate TG) includes, for example, a so-called vertical electrode and is provided to extend from the front surface of the semiconductor layer (the semiconductor layer 100S described later) to reach the depth of the PD shown later. Figure 6 of the semiconductor layer 100S) to reach the depth of the PD shown later. Figure 6 The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifying transistor AMP generates a voltage signal as the pixel signal according to the level of the charge held in the floating diffusion FD. The amplifying transistor AMP is connected to the vertical signal line 543 through the selection transistor SEL. The amplifying transistor AMP and the load circuit unit (refer to Figure 1 ) of the column signal processing unit 550 connected to the vertical signal line 543 form a source follower. When the selection transistor is turned on, the amplifying transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 through the vertical signal line 543. For example, the reset transistor RST, the amplifying transistor AMP, and the selection transistor SEL are N-type MOS transistors.

[0167] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion of the floating diffusion section FD. Generally, when imaging in the dark, the pixel signal is small. When performing charge-voltage conversion based on Q = CV, if the capacitance of the floating diffusion section FD (FD capacitance C) is large, the voltage V when converted to voltage by the amplification transistor AMP becomes small. On the other hand, since the pixel signal in the bright area becomes large, unless the FD capacitance C is large, the floating diffusion section FD cannot receive the charge of the photodiode PD. In addition, the FD capacitance C needs to be large so that the voltage V when converted to voltage by the amplification transistor AMP does not become too large (in other words, V becomes small). In view of this, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, thereby increasing the entire FD capacitance C. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the entire FD capacitance C decreases. In this way, by turning on and off the FD conversion gain switching transistor FDG, the FD capacitance C can be made variable, and the conversion efficiency can be switched. For example, the FD conversion gain switching transistor FDG is an N-type MOS transistor.

[0168] Note that a configuration without setting the FD conversion gain switching transistor FDG is also feasible. In this case, for example, the pixel circuit 210 includes three transistors, such as the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST. The pixel circuit 210 has at least one of the pixel transistors such as the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0169] The selection transistor SEL can be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (refer to Figure 1 ). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Note that although not shown, the number of pixels 541 sharing one pixel circuit 210 may not be four. For example, two or eight pixels 541 can share one pixel circuit 210.

[0170] Figure 5 An example of the connection state between the multiple pixel sharing units 539 and the vertical signal line 543 is shown. For example, the four pixel sharing units 539 arranged in the column direction are divided into four groups, and the vertical signal line 543 is respectively connected to the four groups. For the sake of simplicity of explanation, Figure 5An example is shown in which each of the four groups has one pixel sharing unit 539, but each of the four groups may include a plurality of pixel sharing units 539. As described above, in the imaging device 1, a plurality of pixel sharing units 539 arranged in the column direction can be divided into a plurality of groups, and each group includes one or more pixel sharing units 539. For example, the vertical signal lines 543 and the column signal processing unit 550 are connected to each group, and pixel signals can be read from each group simultaneously. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged in the column direction. In this case, pixel signals are sequentially read from the plurality of pixel sharing units 539 connected to one vertical signal line 543 in a time-division manner.

[0171] [Specific Structure of Imaging Device 1]

[0172] Figure 6 An example of a cross-sectional structure in a direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1 is shown. For ease of understanding, Figure 6 The positional relationship of the components is schematically shown and may be different from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 also has a light receiving lens 401 on the rear side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. For example, the light receiving lens 401 is provided in each of the pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 includes a pixel array portion 540 arranged in the central portion and a peripheral portion 540B arranged outside the pixel array portion 540.

[0173] The first substrate 100 sequentially has an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T starting from the light receiving lens 401 side. The semiconductor layer 100S is formed of, for example, a silicon substrate. The semiconductor layer 100S has a p-well layer 115 in a part of the front surface (the surface on the wiring layer 100T side) and its vicinity, and an n-type semiconductor region 114 in other regions (regions deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0174] Figure 7A An example of the planar structure of the first substrate 100 is shown. Figure 7A The planar structures of the pixel isolation portion 117, the photodiode PD, the floating diffusion portion FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100 are mainly shown. Reference will be made toFigure 7A Together with Figure 6 the structure of the first substrate 100 will be described.

[0175] The floating diffusion portion FD and the VSS contact region 118 are provided near the front surface of the semiconductor layer 100S. The floating diffusion portion FD includes an n-type semiconductor region provided in the p-well layer 115. The floating diffusion portions FD (the floating diffusion portion FD1, the floating diffusion portion FD2, the floating diffusion portion FD3, and the floating diffusion portion FD4) of each of the pixels 541A, 541B, 541C, and 541D are provided, for example, to be close to each other in the central portion of the pixel common unit 539 ( Figure 7A ). Although details will be described later, the four floating diffusion portions (the floating diffusion portion FD1, the floating diffusion portion FD2, the floating diffusion portion FD3, and the floating diffusion portion FD4) included in the pixel common unit 539 are electrically connected to each other by electrical connection means (the pad portion 120 described later) in the first substrate 100 (more specifically, in the wiring layer 100T). In addition, the floating diffusion portion FD is connected from the first substrate 100 to the second substrate 200 by electrical means (the through electrode 120E described later) (more specifically, from the wiring layer 100T to the wiring layer 200T). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion portion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means.

[0176] The VSS contact region 118 is a region electrically connected to the reference potential line VSS and is arranged away from the floating diffusion portion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion portion FD is arranged at one end in the V direction of each pixel, and the VSS contact region 118 is arranged at the other end in the V direction of each pixel ( Figure 7A ). The VSS contact region 118 includes, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, the ground potential or a fixed potential. Therefore, the reference potential is supplied to the semiconductor layer 100S.

[0177] The transfer transistor TR is provided in the first substrate 100 together with the photodiode PD, the floating diffusion portion FD, and the VSS contact region 118. The photodiode PD, the floating diffusion portion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side of the semiconductor layer 100S (the side opposite to the light incident surface side, the second substrate 200 side). The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end of the vertical portion TGa is provided in the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, almost no transmission failure of the pixel signal occurs, and the efficiency of reading the pixel signal can be improved.

[0178] The horizontal portion TGb of the transfer gate TG extends in the H direction from the position facing the vertical portion TGa toward the central portion of the pixel common unit 539, for example. Figure 7A ) Therefore, the position of the via electrode (the via electrode TGV described later) reaching the transfer gate TG in the H direction can be made close to the position of the via electrodes (the via electrode 120E and the via electrode 121E described later) connected to the floating diffusion portion FD and the VSS contact region 118 in the H direction. For example, the plurality of pixel common units 539 provided in the first substrate 100 have the same structure. Figure 7A )

[0179] In the semiconductor layer 100S, a pixel isolation portion 117 for isolating the pixels 541A, 541B, 541C, and 541D from each other is provided. The pixel isolation portion 117 is formed to extend in the normal direction of the semiconductor layer 100S (the direction perpendicular to the front surface of the semiconductor layer 100S). The pixel isolation portion 117 is provided for separating the pixels 541A, 541B, 541C, and 541D from each other, and the pixel isolation portion 117 has, for example, a grid-like planar shape. Figure 7A and Figure 7B)。For example, the pixel isolation portion 117 electrically and optically isolates the pixel 541A, the pixel 541B, the pixel 541C, and the pixel 541D from each other. The pixel isolation portion 117 includes, for example, a light-shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light-shielding film 117A. The insulating film 117B is disposed between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is formed of silicon oxide (SiO), for example. The pixel isolation portion 117 has a full trench isolation (FTI) structure, for example, and penetrates the semiconductor layer 100S. Although not shown, the pixel isolation portion 117 is not limited to the FTI structure that penetrates the semiconductor layer 100S. For example, a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S can be used. The pixel isolation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0180] For example, in the semiconductor layer 100S, a first pinning region 113 and a second pinning region 116 are provided. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on the side surface of the pixel isolation portion 117, specifically, between the pixel isolation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of a p-type semiconductor region, for example.

[0181] The fixed charge film 112 having negative fixed charges is disposed between the semiconductor layer 100S and the insulating film 111. The first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (rear surface) side of the semiconductor layer 100S by the electric field induced by the fixed charge film 112. Therefore, the dark current generated due to the interface state on the light-receiving surface side of the semiconductor layer 100S is suppressed. The fixed charge film 112 is formed of an insulating film having negative fixed charges, for example. Examples of the material of the insulating film having negative fixed charges include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0182] The light-shielding film 117A is disposed between the fixed charge film 112 and the insulating film 111. The light-shielding film 117A can be provided continuously with the light-shielding film 117A constituting the pixel isolation portion 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 can be selectively provided at a position facing the pixel isolation portion 117 in the semiconductor layer 100S, for example. The insulating film 111 is provided to cover the light-shielding film 117A. The insulating film 111 is formed of silicon oxide, for example.

[0183] The wiring layer 100T disposed between the semiconductor layer 100S and the second substrate 200 has, in order from the semiconductor layer 100S side, an interlayer insulating film 119, a pad portion 120 and a pad portion 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124. For example, a horizontal portion TGB of the transfer gate TG is disposed in the wiring layer 100T. The interlayer insulating film 119 is disposed on the entire front surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is formed of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above description and may be a configuration including wirings and insulating films.

[0184] Figure 7B The pad portion 120 and the pad portion 121 are shown together with Figure 7A the planar configuration shown. The pad portion 120 and the pad portion 121 are disposed in a selected region on the interlayer insulating film 119. The pad portion 120 is for connecting the floating diffusion portions FD (floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4) of the respective pixels 541A, pixel 541B, pixel 541C, and pixel 541D. For example, for each pixel common unit 539 ( Figure 7B ), the pad portion 120 is arranged in the central portion of the pixel common unit 539 in the plan view. The pad portion 120 is provided so as to straddle the pixel isolation portion 117 and is arranged to overlap at least a part of each of the floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4 ( Figure 6 and 7B ). Specifically, the pad portion 120 is formed in a region that overlaps at least a part of each of the plurality of floating diffusion portions FD (floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4) of the common pixel circuit 210 and at least a part of the pixel isolation portion 117 formed between the plurality of photodiodes PD (photodiode PD1, photodiode PD2, photodiode PD3, and photodiode PD4) formed in the common pixel circuit 210 in a direction perpendicular to the front surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with connection vias 120C for electrically connecting the pad portion 120 to the floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4. The connection vias 120C are provided in each of the pixels 541A, pixel 541B, pixel 541C, and pixel 541D. For example, by embedding a part of the pad portion 120 in the connection vias 120C, the pad portion 120 is electrically connected to the floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4.

[0185] The pad portion 121 is used to connect multiple VSS contact regions 118 to each other. For example, the VSS contact regions 118 in pixels 541C and 541D of one pixel common unit 539 and the VSS contact regions 118 in pixels 541A and 541B of another pixel common unit 539 are electrically connected through the pad portion 121, and the above-mentioned one pixel common unit 539 and the above-mentioned another pixel common unit 539 are adjacent in the V direction. For example, the pad portion 121 is arranged to straddle the pixel isolation portion 117 and is arranged to overlap at least a part of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a part of each of the multiple VSS contact regions 118 and at least a part of the pixel isolation portion 117 formed between the multiple VSS contact regions 118 in a direction perpendicular to the front surface of the semiconductor layer 100s. The interlayer insulating film 119 is provided with connection vias 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection vias 121C are provided in each of the pixels 541A, pixel 541B, pixel 541C, and pixel 541D. For example, the pad portion 121 and the VSS contact region 118 are electrically connected by embedding a part of the pad portion 121 in the connection via 121C. For example, the pad portions 120 and 121 of each of the multiple pixel common units 539 arranged in the V direction are arranged at substantially the same position in the H direction ( Figure 7B ).

[0186] By providing the pad portion 120, the wiring for connecting from each floating diffusion portion FD to the pixel circuit 210 (for example, the gate electrode of the amplifying transistor AMP) in the entire chip can be reduced. Similarly, by providing the pad portion 121, the wiring for supplying potential to each VSS contact region 118 in the entire chip can be reduced. Therefore, the area of the entire chip can be reduced, the electrical interference between the wirings of the miniaturized pixels can be suppressed, and / or the cost can be reduced by reducing the number of components.

[0187] The pad portions 120 and 121 can be disposed at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120 and 121 can be disposed in the insulating region 212 of the wiring layer 100T or the semiconductor layer 200s. When the pad portions 120 and 121 are disposed in the wiring layer 100T, the pad portions 120 and 121 can be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120 and 121 can be directly connected to at least a part of each of the floating diffusion portion FD and / or the VSS contact region 118. In addition, connection vias 120C and 121C can be respectively provided from the floating diffusion portion FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 can be disposed at positions required for the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0188] Particularly, when the pad portions 120 and 121 are disposed in the wiring layer 100T, the wiring for connecting to the floating diffusion portion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200s can be reduced. Therefore, in the second substrate 200 in which the pixel circuit 210 is formed, the area of the insulating region 212 for forming the through-wiring connecting the floating diffusion portion FD to the pixel circuit 210 can be reduced. Thus, a large area of the second substrate 200 in which the pixel circuit 210 is formed can be ensured. By ensuring the area of the pixel circuit 210, large pixel transistors can be formed, and it helps to improve the image quality by noise reduction and the like.

[0189] Particularly, when the pixel isolation portion 117 employs an FTI structure, since the floating diffusion portion FD and / or the VSS contact region 118 are preferably provided in each pixel 541, by using the structure of the pad portions 120 and 121, the wiring for connecting the first substrate 100 to the second substrate 200 can be greatly reduced.

[0190] In addition, as Figure 7B shown, for example, the pad portion 120 connecting a plurality of floating diffusion portions FD and the pad portion 121 connecting a plurality of VSS contact regions 118 are alternately arranged linearly in the V direction. In addition, the pad portions 120 and 121 are formed at positions surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusion portions FD. Therefore, in the first substrate 100 on which a plurality of elements are formed, elements other than the floating diffusion portion FD and the VSS contact region 118 can be freely arranged, and the layout efficiency of the entire chip can be improved. In addition, the symmetry of the layout of the elements formed in each pixel common unit 539 is ensured, and the difference in the characteristics of each pixel 541 can be suppressed.

[0191] The pad portions 120 and 121 are formed of, for example, polysilicon (Poly Si), and more specifically, doped polysilicon doped with impurities. The pad portions 120 and 121 are preferably formed of a conductive material having high heat resistance such as polysilicon, tungsten (W), titanium (Ti), or titanium nitride (TiN). Therefore, the pixel circuit 210 can be formed after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. The reason will be described below. Note that, in the following description, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 and the second substrate 200 is referred to as the first manufacturing method.

[0192] Here, it is also conceivable to form the pixel circuit 210 on the second substrate 200 and then bond the second substrate 200 to the first substrate 100 (hereinafter referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are formed in advance on each of the front surface of the first substrate 100 (the front surface of the wiring layer 100T) and the front surface of the second substrate 200 (the front surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded to each other, at the same time, the electrodes for electrical connection formed on the front surface of the first substrate 100 and the front surface of the second substrate 200 come into contact with each other. Therefore, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by adopting the configuration of the imaging device 1 using the second manufacturing method, for example, it is possible to manufacture using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, and an imaging device with high quality and high performance can be manufactured.

[0193] In such a second manufacturing method, when the first substrate 100 and the second substrate 200 are joined to each other, alignment errors may occur due to the manufacturing equipment used for joining. In addition, the sizes of the first substrate 100 and the second substrate 200 are, for example, on the order of several tens of centimeters in diameter, but when the first substrate 100 and the second substrate 200 are joined to each other, there is a possibility that expansion and contraction of the substrates occur in the microscopic regions of the corresponding portions of the first substrate 100 and the second substrate 200. Such expansion and contraction of the substrates are caused by slight offsets when the substrates come into contact with each other. Due to such expansion and contraction of the first substrate 100 and the second substrate 200, errors may occur in the positions of the electrodes for electrical connection formed on the front surfaces of the first substrate 100 and the second substrate 200, respectively. In the second manufacturing method, even if such errors occur, it is preferable to take measures such that the electrodes of the first substrate 100 and the second substrate 200 come into contact with each other. Specifically, in consideration of the above-described errors, at least one of the electrodes of the first substrate 100 and the second substrate 200, preferably both, are enlarged. Therefore, when the second manufacturing method is used, for example, the size of the electrode formed on the front surface of the first substrate 100 or the second substrate 200 (the size in the substrate plane direction) is larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 200 to the front surface in the thickness direction.

[0194] On the other hand, the pad portion 120 and the pad portion 121 are formed of a heat-resistant conductive material so that the first manufacturing method can be used. In the first manufacturing method, after the first substrate 100 including the photodiode PD, the transfer transistor TR, etc. is formed, the first substrate 100 and the second substrate 200 (the semiconductor layer 2000S) are joined to each other. In this case, the second substrate 200 is in a state where patterns such as active elements and wiring layers constituting the pixel circuit 210 are not formed. Since the second substrate 200 is in a state before pattern formation, even if an alignment error occurs at the joining position when the first substrate 100 and the second substrate 200 are joined together, this joining error does not cause an alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are joined. For example, when forming a pattern on the second substrate, in an exposure apparatus for forming the pattern, the pattern formed on the first substrate is set as an alignment target and the pattern is formed. For the above reasons, during the manufacturing of the imaging device 1 by the first manufacturing method, an error in the joining position between the first substrate 100 and the second substrate 200 does not cause a problem. For the same reason, during the manufacturing of the imaging device 1 by the first manufacturing method, an error caused by expansion and contraction of the substrates, which occurs in the second manufacturing method, does not cause a problem.

[0195] In the first manufacturing method, after joining the first substrate 100 and the second substrate 200 (semiconductor layer 200S) in this manner, active elements are formed on the second substrate 200. Then, through electrodes 120E, through electrodes 121E, and through electrodes TGV ( Figure 6 ) are formed. In the formation of the through electrodes 120E, the through electrodes 121E, and the through electrodes TGV, for example, a pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure performed by an exposure apparatus. Due to the use of reduced exposure projection, even if an alignment error occurs between the second substrate 200 and the exposure apparatus, the magnitude of the error in the second substrate 200 is only a fraction (the reciprocal of the magnification of the reduced exposure projection) of the error in the second manufacturing method. Therefore, by adopting the configuration of the imaging device 1 using the first manufacturing method, it is easy to align the elements formed on each of the first substrate 100 and the second substrate 200, and an imaging device with high quality and high performance can be manufactured.

[0196] The imaging device 1 manufactured using the first manufacturing method has characteristics different from those of the imaging device manufactured by the second manufacturing method. Specifically, in the imaging device 1 manufactured by the first manufacturing method, for example, the through electrodes 120E, the through electrodes 121E, and the through electrodes TGV have a substantially constant thickness (dimension in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, the through electrodes 121E, and the through electrodes TGV have a tapered shape, the through electrodes 120E, the through electrodes 121E, and the through electrodes TGV have a tapered shape with a constant inclination. In the imaging device 1 including such through electrodes 120E, through electrodes 121E, and through electrodes TGV, it is easy to miniaturize the pixel 541.

[0197] Here, when manufacturing the imaging device 1 by the first manufacturing method, since active elements are formed on the second substrate 200 after joining the first substrate 100 and the second substrate 200 (semiconductor layer 200S) to each other, the first substrate 100 is also affected by the heat treatment required for forming the active elements. Therefore, as described above, a conductive material with high heat resistance is preferably used for the pad portions 120 and 121 provided on the first substrate 100. For example, the pad portions 120 and 121 are preferably formed of a material having a higher melting point (i.e., higher heat resistance) than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad portions 120 and 121. Therefore, the imaging device 1 can be manufactured using the first manufacturing method.

[0198] For example, a passivation film 122 is provided over the entire front surface of the semiconductor layer 100S to cover the pad portions 120 and 121( Figure 6 ). The passivation film 122 is formed of, for example, a silicon nitride (SiN) film. An interlayer insulating film 123 covers the pad portions 120 and 121, and the passivation film 122 is sandwiched between the interlayer insulating film 123 and the pad portions 120 and 121. For example, the interlayer insulating film 123 is provided above the entire front surface of the semiconductor layer 100S. The interlayer insulating film 123 is formed of, for example, a silicon oxide (SiO) film. A bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is provided on the entire main surface of the first substrate 100. The bonding film 124 is formed of, for example, a silicon nitride film.

[0199] The light receiving lens 401 faces the semiconductor layer 100S, and for example, the fixed charge film 112 and the insulating film 111 are sandwiched therebetween( Figure 6 ). The light receiving lens 401 is provided, for example, at positions facing the photodiodes PD of each of the pixels 541A, 541B, 541C, and 541D.

[0200] The second substrate 200 sequentially has a semiconductor layer 200S and a wiring layer 200T starting from the first substrate 100 side. The semiconductor layer 200S is formed of a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 20 is provided with pixel circuits 210 arranged for each pixel common unit 539. The pixel circuits 210 are provided, for example, on the front surface side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the rear surface side (semiconductor layer 200S side) of the second substrate 200 faces the front surface side (wiring layer 100T side) of the first substrate. That is, the second substrate 200 is bonded to the first substrate 100 in a face-to-back manner.

[0201] Figures 8 to 12 An example of the planar structure of the second substrate 200 is schematically shown. Figure 8 The structure of the pixel circuit 210 provided near the front surface of the semiconductor layer 200S is shown. Figure 9 The structures of the wiring layer 200T (specifically, the first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and the respective portions of the first substrate 100 are schematically shown. Figures 10 to 12 An example of the planar structure of the wiring layer 200T is shown. Hereinafter, reference will be made to Figures 8 to 12 together with Figure 6The structure of the second substrate 200 will be described together. In Figure 8 and Figure 9 , the outer shape of the photodiode PD (the boundary between the pixel isolation portion 117 and the photodiode PD) is shown by a dashed line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 214 in the portion overlapping with the gate electrodes of the respective transistors constituting the pixel circuit 210 is shown by a dotted line. In the portion overlapping with the gate electrode of the amplification transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213 and the boundary between the element isolation region 213 and the insulating region 212 are both provided on one side in the trench width direction.

[0202] The second substrate 200 is provided with an insulating region 212 that separates the semiconductor layer 200S and an element isolation region 213 provided in a part in the thickness direction of the semiconductor layer 200S ( Figure 6 ). For example, the through electrodes 120E and 121E of the two pixel common units 539 connected to two adjacent pixel circuits 210 in the H direction and the through electrodes TGV (through electrode TGV1, through electrode TGV2, through electrode TGV3, and through electrode TGV4) are arranged in the insulating region 212 provided between the two pixel circuits 210 ( Figure 9 ).

[0203] The insulating region 212 has a thickness substantially the same as the thickness of the semiconductor layer 200S ( Figure 6 ). The semiconductor layer 200S is divided by the insulating region 212. The through electrodes 120E and 121E and the through electrodes TGV are arranged in the insulating region 212. The insulating region 212 is formed of, for example, silicon oxide.

[0204] The through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wirings of the wiring layer 200T (the first wiring W1, the second wiring W2, the third wiring W3, and the fourth wiring W4 described later). The through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends of the through electrodes 120E and 121E are connected to the pad portions 120 and 121 ( Figure 6)。The via electrode 120E is used to electrically connect the pad portion 120 and the pixel circuit 210. That is, the floating diffusion portion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 through the via electrode 120E. The via electrode 121E is used to electrically connect the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the VSS contact region 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200 through the via electrode 121E.

[0205] The via electrode TGV is arranged to penetrate the insulating region 212 in the thickness direction. The upper end of the via electrode TGV is connected to the wiring of the wiring layer 200T. The via electrode TGV is arranged to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and the lower end of the via electrode TGV is connected to the transfer gate TG( Figure 6 )。Such a via electrode TGV is used to electrically connect the transfer gates TG (transfer gates TG1, transfer gates TG2, transfer gates TG3, and transfer gates TG4) of each of the pixels 541A, pixels 541B, pixels 541C, and pixels 541D to the wiring of the wiring layer 200T (a part of the row drive signal line 542, specifically, the wirings TRG1, TRG2, TRG3, and TRG4 described later). That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the via electrode TGV, and the drive signal is transmitted to each transfer transistor TR (transfer transistors TR1, transfer transistors TR2, transfer transistors TR3, and transfer transistors TR4).

[0206] The insulating region 212 is a region for insulating the via electrode 120E, the via electrode 121E, and the via electrode TGV (which are used to electrically connect the first substrate 100 to the second substrate 200) from the semiconductor layer 200S. For example, the via electrode 120E, the via electrode 121, and the via electrode TGV (via electrodes TGV1, via electrodes TGV2, via electrodes TGV3, and via electrodes TGV4) connected to two adjacent pixel circuits 210 in the H direction are arranged in the insulating region 212 provided between the two pixel circuits 210 (pixel common unit 539). For example, the insulating region 212 is arranged to extend in the V direction ( Figure 8 and Figure 9 )。Here, by designing the arrangement of the horizontal portion TGb of the transfer gate TG, the via electrode TGV is arranged such that the position of the via electrode TGV in the H direction is closer to the positions of the via electrode 120E and the via electrode 121E in the H direction than the position of the vertical portion TGa ( Figure 7A and 9)。For example, the through electrode TGV is disposed at substantially the same position as the through electrodes 120E and 121E in the H direction. Thus, the through electrodes 120E, 121E, and the through electrode TGV can be commonly provided in the insulating region 212 extending in the V direction. As another arrangement example, it is also conceivable to provide only the horizontal portion TGb in the region overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed substantially directly above the vertical portion TGa, and for example, the through electrode TGV is disposed at substantially the center portions of each pixel 541 in the H and V directions. In this case, the position of the through electrode TGV in the H direction is greatly deviated from the positions of the through electrodes 120E and 121E in the H direction. For example, an insulating region 212 is provided around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate the through electrode TGV and the through electrodes 120E and 121E from the adjacent semiconductor layer 200S. When the positions of the through electrode TGV and the through electrodes 120E and 121E in the H direction are greatly separated from each other, it is necessary to independently provide the insulating region 212 around each of the through electrodes 120E, 121E, and the through electrode TGV. Thus, the semiconductor layer 200S is finely divided. In contrast, the layout in which the through electrodes 120E, 121E, and the through electrode TGV are commonly disposed in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. Thus, a large area of the semiconductor element formation region of the semiconductor layer 200S can be ensured. Thus, for example, the size of the amplification transistor AMP can be increased, and noise can be suppressed.

[0207] As described with reference to Figure 4 above, the pixel sharing unit 539 has the following structure: Among them, the floating diffusion portions FD provided in a plurality of pixels 541 are electrically connected, and a plurality of pixels 541 share one pixel circuit 210. The floating diffusion portions FD are electrically connected through the pad portions 120 provided on the first substrate 100 ( Figure 6 and Figure 7B)。The electrical connection portion (pad portion 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected by a through electrode 120E. As another structural example, it is also conceivable to provide an electrical connection portion between the floating diffusion portions FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes respectively connected to the floating diffusion portion FD1, the floating diffusion portion FD2, the floating diffusion portion FD3, and the floating diffusion portion FD4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S is increased, and the insulation region 212 for insulating the peripheries of these through electrodes is increased. In contrast, in the structure in which the pad portion 120 is provided on the first substrate 100 ( Figure 6 and Figure 7B ), the number of through electrodes can be reduced, and the insulation region 212 can be reduced. Therefore, a large area of the semiconductor element formation region of the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplification transistor AMP can be increased, and noise can be suppressed.

[0208] The element isolation region 213 is provided on the front surface side of the semiconductor layer 200S. The element isolation region 213 has a shallow trench isolation (STI) structure. In the element isolation region 213, the semiconductor layer 200S is excavated in the thickness direction (the direction perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the excavation portion. This insulating film is formed of, for example, silicon oxide. The element isolation region 213 isolates the plurality of transistors constituting the pixel circuit 210 from each other according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (the deep portion of the semiconductor layer 200S).

[0209] Here, with reference to Figure 7A 、 Figure 7B and Figure 8 , the difference between the outer shape (the outer shape in the substrate plane direction) of the pixel sharing unit 539 on the first substrate 100 and the outer shape of the pixel sharing unit 539 on the second substrate 200 will be described.

[0210] In the imaging device 1, the pixel sharing unit 539 is provided on both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided on the first substrate 100 is different from the outer shape of the pixel sharing unit 539 provided on the second substrate 200.

[0211] In Figure 7A and Figure 7BAmong them, the outlines of pixels 541A, 541B, 541C, and 541D are shown by single-dot dash lines, and the outer shape of pixel sharing unit 539 is shown by thick lines. For example, pixel sharing unit 539 of first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541A and 541C) arranged adjacent to each other in the V direction. That is, pixel sharing unit 539 of first substrate 100 includes four pixels 541 of adjacent 2 rows × 2 columns, and pixel sharing unit 539 of first substrate 100 has a substantially square outer shape. In pixel array section 540, these pixel sharing units 539 are arranged adjacent to each other with a two-pixel pitch (pitch corresponding to two pixels 541) in the H direction and a two-pixel pitch (pitch corresponding to two pixels 541) in the V direction.

[0212] In Figure 8 and Figure 9 Among them, the outlines of pixels 541A, 541B, 541C, and 541D are shown by single-dot dash lines, and the outer shape of pixel sharing unit 539 is shown by thick lines. For example, the outer shape of pixel sharing unit 539 of second substrate 200 is smaller than that of pixel sharing unit 539 of first substrate 100 in the H direction and larger than that of pixel sharing unit 539 of first substrate 100 in the V direction. For example, pixel sharing unit 539 of second substrate 200 is formed to have a size (area) corresponding to one pixel in the H direction and a size corresponding to four pixels in the V direction. That is, pixel sharing unit 539 of second substrate 200 is formed to have a size corresponding to pixels arranged in adjacent 1 row × 4 columns, and pixel sharing unit 539 of second substrate 200 has a substantially rectangular outer shape.

[0213] For example, in each pixel circuit 210, selection transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG are arranged in this order in the V direction ( Figure 8 ). By setting the outer shape of each pixel circuit 210 in the substantially rectangular shape as described above, four transistors (selection transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) can be arranged side by side in one direction ( Figure 8 the V direction). Therefore, the drains of amplification transistor AMP and reset transistor RST can be shared in one diffusion region (diffusion region connected to power supply line VDD). For example, it can be in a substantially square shape (refer to Figure 21)Set the formation region of each pixel circuit 210. In this case, two transistors are arranged along one direction, and it is difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by setting the formation region of the pixel circuit 210 in a substantially rectangular shape, four transistors can be easily arranged close to each other, and the formation region of the pixel circuit 210 can be reduced. That is, the pixel can be miniaturized. In addition, when it is not necessary to reduce the formation region of the pixel circuit 210, the formation region of the amplification transistor AMP can be increased, and noise can be suppressed.

[0214] In addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided near the front surface of the semiconductor layer 200S, for example. The VSS contact region 218 includes a p-type semiconductor region, for example. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) through the wiring of the wiring layer 200T and the via electrode 121E. For example, the VSS contact region 218 is provided at a position adjacent to the source of the FD conversion gain switching transistor FDG, and the element isolation region 213 is interposed between the VSS contact region 218 and the source ( Figure 8 ).

[0215] Next, with reference to Figure 7B and Figure 8 the positional relationship between the pixel common unit 539 provided on the first substrate 100 and the pixel common unit 539 provided on the second substrate 200 will be described. For example, one of the two pixel common units 539 arranged in the V direction of the first substrate 100 (for example, Figure 7B the upper side of the paper surface) is connected to one of the two pixel common units 539 arranged in the H direction of the second substrate 200 (for example, Figure 8 the left side of the paper surface). For example, the other pixel common unit 539 of the two pixel common units 539 arranged in the V direction of the first substrate 100 (for example, Figure 7B the lower side of the paper surface) is connected to the other pixel common unit 539 of the two pixel common units 539 arranged in the H direction of the second substrate 200 (for example, Figure 8 the right side of the paper surface).

[0216] For example, among the two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to the layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V direction and the H direction. Hereinafter, the effects obtained by this layout will be described.

[0217] Among the two pixel sharing units 539 arranged in the V direction on the first substrate 100, each pad portion 120 is provided at the central portion of the outer shape of the pixel sharing unit 539, that is, at the central portion of the pixel sharing unit 539 in the V direction and the H direction ( Figure 7B ). On the other hand, since the pixel sharing unit 539 of the second substrate 200 has an outer shape that is substantially rectangular in the V direction as described above, for example, the amplification transistor AMP connected to the pad portion 120 is arranged at a position shifted upward in the paper surface from the center of the pixel sharing unit 539 in the V direction. For example, when the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are the same, the distance between the amplification transistor AMP of one pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 120 of the pixel sharing unit 539 on the upper side of the paper surface in FIG. 7) becomes relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 120 of the pixel sharing unit 539 on the lower side of the paper surface in FIG. 7) becomes long. Therefore, the wiring area required for connecting the amplification transistor AMP and the pad portion 120 is increased, and the wiring layout of the pixel sharing unit 539 may become complicated. This may affect the miniaturization of the imaging device 1.

[0218] On the other hand, the internal layouts of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 are inverted at least in the V direction, so that the distances between the amplification transistors AMP of both of the two pixel sharing units 539 and the pad portion 120 can be shortened. Therefore, compared with the configuration in which the internal layouts of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 are the same, the imaging device 1 can be easily miniaturized. Note that the planar layouts of the multiple pixel sharing units 539 of the second substrate 200 are symmetric about the left and right within the Figure 8 range shown, but are asymmetric about the left and right when including the layout of the first wiring layer W1 shown later Figure 9 .

[0219] In addition, preferably, the internal layouts of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 are also inverted in the H direction. Hereinafter, the reason will be described. As Figure 9As shown, each of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 is connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are arranged at the central portions in the H direction (between the two pixel sharing units 539 arranged in the H direction) of the two pixel sharing units 539, and the two pixel sharing units 539 are arranged in the H direction on the second substrate 200. Therefore, the internal layouts of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 are also inverted in the H direction, so that the distance between each of the multiple pixel sharing units 539 of the second substrate 200 and the pad portions 120 and 121 can be reduced. That is, it is easier to miniaturize the imaging device 1.

[0220] In addition, the positions of the outlines of the pixel sharing units 539 of the second substrate 200 may not be aligned with the positions of any outlines of the pixel sharing units 539 of the first substrate 100. For example, in one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, Figure 9 the left side of the paper surface), the outline on one side in the V direction (for example, Figure 9 the upper side of the paper surface) is arranged outside the outline on one side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, Figure 7B the upper side of the paper surface). In addition, in the other pixel sharing unit 539 of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, Figure 9 the right side of the paper surface), the outline on the other side in the V direction (for example, Figure 9 the lower side of the paper surface) is arranged outside the outline on the other side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, Figure 9 the lower side of the paper surface). As described above, by arranging the pixel sharing units 539 of the second substrate 200 and the pixel sharing units 539 of the first substrate 100 with respect to each other, the distance between the amplification transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the imaging device 1.

[0221] In addition, the positions of the outlines of the multiple pixel sharing units 539 of the second substrate 200 may not be aligned. For example, the two pixel sharing units 539 arranged in the H direction on the second substrate 200 are arranged such that the positions of the outlines in the V direction are offset. Therefore, the distance between the amplification transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the imaging device 1.

[0222] Reference will be made to Figure 7B and Figure 9Describe the repeated arrangement of the pixel sharing unit 539 in the pixel array unit 540. The pixel sharing unit 539 of the first substrate 100 has the size of two pixels 541 in the H direction and the size of two pixels 541 in the V direction ( Figure 7B ). For example, in the pixel array unit 540 of the first substrate 100, the pixel sharing unit 539 having the size corresponding to four pixels 541 is repeatedly arranged adjacent to each other with two pixel pitches in the H direction (corresponding to the pitch of two pixels 541) and two pixel pitches in the V direction (corresponding to the pitch of two pixels 541). Alternatively, in the pixel array unit 540 of the first substrate 100, a pair of pixel sharing units 539 in which two pixel sharing units 539 are arranged adjacent to each other in the V direction can be provided. In the pixel array unit 540 of the first substrate 100, the pair of pixel sharing units 539 are repeatedly arranged adjacent to each other with two pixel pitches in the H direction (corresponding to the pitch of two pixels 541) and four pixel pitches in the V direction (corresponding to the pitch of four pixels 541). The pixel sharing unit 539 of the second substrate 200 has the size of one pixel 541 in the H direction and the size of four pixels 541 in the V direction ( Figure 9 ). For example, in the pixel array unit 540 of the second substrate 200, a pair of pixel sharing units 539 are provided, and each pair of pixel sharing units 539 includes two pixel sharing units 539 having the size corresponding to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and are arranged offset in the V direction. In the pixel array unit 540 of the second substrate 200, multiple pairs of pixel sharing units 539 are repeatedly arranged adjacent to each other without a gap with two pixel pitches in the H direction (corresponding to the pitch of two pixels 541) and four pixel pitches in the V direction (corresponding to the pitch of four pixels 541). This arrangement of the pixel sharing unit 539 enables the pixel sharing unit 539 to be arranged without a gap. Therefore, it is easy to miniaturize the imaging device 1.

[0223] Preferably, the amplifying transistor AMP has a three-dimensional structure such as a Fin type ( Figure 6 ), etc. Therefore, the size of the effective gate width is increased, and noise can be suppressed. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have a planar structure, for example. The amplifying transistor AMP can have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG can have a three-dimensional structure.

[0224] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is in contact with, for example, the front surface of the semiconductor layer 200S and covers the entire front surface of the semiconductor layer 200S. The passivation film 221 covers the gate electrodes of each of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. The plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4) are isolated by the interlayer insulating film 222. The interlayer insulating film 222 is formed of, for example, silicon oxide.

[0225] In the wiring layer 200T, for example, the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, the fourth wiring layer W4, and the contact portions 201 and 202 are sequentially provided from the semiconductor layer 200S side, and they are insulated from each other by the interlayer insulating film 222. In the interlayer insulating film 222, a plurality of connection portions that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 and its underlying layer are provided. The connection portion is a portion where a conductive material is embedded in a connection hole provided in the interlayer insulating film 222. For example, in the interlayer insulating film 222, a connection portion 218V that connects the first wiring layer W1 and the VSS contact region 218 is provided. For example, the aperture diameter of the connection portion that connects the elements of the second substrate 200 is different from the aperture diameters of the through electrodes 120E, the through electrode 121E, and the through electrode TGV. Specifically, preferably, the aperture diameter of the connection hole that connects the elements of the second substrate 200 is smaller than the aperture diameters of the through electrodes 120E, the through electrode 121E, and the through electrode TGV. The reason will be described below. The depth of the connection portion (such as the connection portion 218V) provided in the wiring layer 200T is smaller than the depths of the through electrodes 120E, the through electrode 121E, and the through electrode TGV. Therefore, in the connection portion, the connection hole can be more easily filled with a conductive material compared to the through electrodes 120E, the through electrode 121E, and the through electrode TGV. By making the aperture diameter of the connection portion smaller than the aperture diameters of the through electrodes 120E, the through electrode 121E, and the through electrode TGV, the imaging device 1 can be easily miniaturized.

[0226] For example, the through electrode 120E is connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG through the first wiring layer W1 (specifically, the connection hole reaches the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects the through electrode 121E to the connection portion 218V, for example, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S.

[0227] Next, with reference to Figures 10 to 12 the planar structure of the wiring layer 200T will be described. Figure 10 An example of the planar structure of the first wiring layer W1 and the second wiring layer W2 is shown. Figure 11 An example of the planar structure of the second wiring layer W2 and the third wiring layer W3 is shown. Figure 12 An example of the planar structure of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0228] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL that extend in the H direction (row direction) ( Figure 11 ). These wirings correspond to the multiple row driving signal lines 542 described with reference to Figure 4 . Wirings TRG1, TRG2, TRG3, and TRG4 are respectively used to transmit driving signals to transfer gates TG1, TG2, TG3, and TG4. Wirings TRG1, TRG2, TRG3, and TRG4 are connected to transfer gates TG1, TG2, TG3, and TG4 through the second wiring layer W2, the first wiring layer W1, and the through electrode 120E, respectively. Wiring SELL is used to transmit a driving signal to the gate of the selection transistor SEL, wiring RSTL is used to transmit a driving signal to the gate of the reset transistor RST, and wiring FDGL is used to transmit a driving signal to the gate of the FD conversion gain switching transistor FDG. Wirings SELL, RSTL, and FDGL are connected to the gates of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG through the second wiring layer W2, the first wiring layer W1, and the connection part, respectively.

[0229] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 that extend in the V direction (column direction) ( Figure 12 ). The power supply line VDD is connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection part. The reference potential line VSS is connected to the VSS contact area 218 through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection part 218V. In addition, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad part 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL through the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection part.

[0230] The contact portions 201 and 202 may be provided at positions overlapping with the pixel array portion 540 in a plan view (e.g., Figure 3 ), or may be provided in the peripheral portion 540B outside the pixel array portion 540 (e.g., Figure 6 ). The contact portions 201 and 202 are provided on the front surface of the second substrate 200 (the surface on the side of the wiring layer 200T). The contact portions 201 and 202 are formed of a metal such as copper (Cu) and aluminum (Al), for example. The contact portions 201 and 202 are exposed on the front surface of the wiring layer 200T (the surface on the side of the third substrate 300). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding between the second substrate 200 and the third substrate 300.

[0231] Figure 6 An example of a peripheral circuit provided in the peripheral portion 540B of the second substrate 200 is shown. The peripheral circuit may include a part of the row driving unit 520, a part of the column signal processing unit 550, etc. In addition, as Figure 3 shown, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200, and the connection hole portions H1 and H2 may be arranged near the pixel array portion 540.

[0232] The third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the side of the second substrate 200. For example, the front surface of the semiconductor layer 300S is disposed on the side of the second substrate 200. The semiconductor layer 300S is formed of a silicon substrate. A circuit is provided in a portion on the front surface side of the semiconductor layer 300S. Specifically, for example, at least a part of the input unit 510A, the row driver unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B is provided in the portion on the front surface side of the semiconductor layer 300S. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers isolated by the interlayer insulating film, and contact portions 301 and 302. The contact portions 301 and 302 are exposed on the front surface (the surface on the side of the second substrate 200) of the wiring layer 300T. The contact portion 301 is in contact with the contact portion 201 of the second substrate 200, and the contact portion 302 is in contact with the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to a circuit (for example, at least one of the input unit 510A, the row driver unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B) formed in the semiconductor layer 300S. For example, the contact portions 301 and 302 are formed of a metal such as copper (Cu) and aluminum (Al). For example, the external terminal TA is connected to the input unit 510A through the connection hole portion H1, and the external terminal TB is connected to the output unit 510B through the connection hole portion H2.

[0233] Here, the features of the imaging device 1 will be described.

[0234] Generally, an imaging device mainly includes a photodiode and a pixel circuit. Here, when the area of the photodiode increases, the charge generated by photoelectric conversion increases, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal, and the imaging device can output better image data (image information). On the other hand, when the size of the transistor included in the pixel circuit (particularly, the size of the amplification transistor) increases, the noise generated in the pixel circuit decreases, thereby improving the S / N ratio of the imaging signal, and the imaging device can output better image data (image information).

[0235] However, in an imaging device in which the photodiode and the pixel circuit are provided on the same semiconductor substrate, if the area of the photodiode is increased in a limited area of the semiconductor substrate, the size of the transistor included in the pixel circuit will be reduced. In addition, if the size of the transistor included in the pixel circuit is increased, the area of the photodiode will be reduced.

[0236] To solve these problems, for example, the imaging device 1 of the present embodiment adopts a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD. Therefore, within a limited area of the semiconductor substrate, it is possible to make the area of the photodiode PD as large as possible and make the size of the transistors included in the pixel circuit 210 as large as possible. As a result, the S / N ratio of the pixel signal can be improved, and the imaging device 1 can output better image data (image information).

[0237] When a structure is implemented in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD, a plurality of wirings connected to one pixel circuit 210 extend from the floating diffusion portions FD of each of the plurality of pixels 541. To ensure a large area of the semiconductor substrate 200 on which the pixel circuit 210 is formed, for example, a connection wiring can be formed that connects the plurality of extended wirings to each other and integrates the plurality of extended wirings into one. Similarly, for a plurality of wirings extending from the VSS contact region 118, a connection wiring can be formed that connects the plurality of extended wirings to each other and integrates the plurality of extended wirings into one.

[0238] For example, when a connection wiring that connects a plurality of wirings extending from the floating diffusion portions FD of each of the plurality of pixels 541 to each other is formed in the semiconductor substrate 200 on which the pixel circuit 210 is formed, the area for forming the transistors included in the pixel circuit 210 can be reduced. Similarly, when a connection wiring that connects and integrates a plurality of wirings extending from the VSS contact regions 118 of each of the plurality of pixels 541 is formed in the semiconductor substrate 200 on which the pixel circuit 210 is formed, the area for forming the transistors included in the pixel circuit 210 can be reduced.

[0239] To solve these problems, for example, the imaging device 1 of the present embodiment can have the following structure: a plurality of pixels 541 share one pixel circuit 210, the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD, and the first substrate 100 is provided with a connection wiring that connects the floating diffusion portions FD of the plurality of pixels 541 to each other and integrates them into one, and a connection wiring that connects the VSS contact regions 118 included in the plurality of pixels 541 to each other and integrates them into one.

[0240] Here, for example, when using the above-described second manufacturing method for providing connection wirings that connect the floating diffusion portions FD of the plurality of pixels 541 to each other and integrate them into one, and connection wirings that connect the VSS contact regions 118 included in the plurality of pixels 541 to each other and integrate them into one on the first substrate 100, the first substrate 100 and the second substrate 200 can be manufactured using appropriate processes according to the structures of the first substrate 100 and the second substrate 200, respectively, and an imaging device having high quality and high performance can be manufactured. Further, the connection wirings of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, in the case of using the second manufacturing method, electrodes connected to the floating diffusion portion FD and electrodes connected to the VSS contact region 118 are provided on the front surfaces of the first substrate 100 and the second substrate 200, respectively, which are the bonding interface surfaces of the first substrate 100 and the second substrate 200. Further, even when a positional deviation occurs between the electrodes provided on the front surfaces of the two substrates when the first substrate 100 and the second substrate 200 are bonded together, it is preferable to enlarge the electrodes formed on the front surfaces of the two substrates so that the electrodes formed on the front surfaces of the two substrates come into contact with each other. In this case, it can be considered that it becomes difficult to arrange the electrodes in the limited regions of the respective pixels included in the imaging device 1.

[0241] To solve the problem of the need for large electrodes at the bonding interface surface between the first substrate 100 and the second substrate 200, for example, in the imaging device 1 of the present embodiment, the above-described first manufacturing method can be used as a manufacturing method in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD. Therefore, it is easy to align the elements formed on the first substrate 100 and the second substrate 200, and an imaging device having high quality and high performance can be manufactured. Further, a unique structure generated by using this manufacturing method (that is, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in sequence) can be provided. In other words, a structure in which the first substrate 100 and the second substrate 200 are stacked in a back-to-back manner can be provided, and through electrodes 120E and 121E that penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front surface side of the semiconductor layer 200S of the second substrate 200 and reach the front surface of the semiconductor layer 100S of the first substrate 100 can be provided.

[0242] In a structure in which a connection wiring that connects floating diffusion parts FD of a plurality of pixels 541 to each other and integrates the floating diffusion parts FD into one, and a connection wiring that connects VSS contact regions 118 of the plurality of pixels 541 to each other and integrates the VSS contact regions 118 into one are provided on a first substrate 100, when the structure is stacked with a second substrate 200 using a first manufacturing method and a pixel circuit 210 is formed on the second substrate 200, the heat treatment required for forming active elements included in the pixel circuit 210 may affect the connection wiring formed on the first substrate 100.

[0243] Therefore, in order to solve the problem of the influence of the heat treatment during the formation of active elements on the connection wiring, in the imaging device 1 of the present embodiment, it is desirable to use a conductive material having high heat resistance for the connection wiring that connects floating diffusion parts FD of a plurality of pixels 541 to each other and integrates the floating diffusion parts FD into one, and the connection wiring that connects VSS contact regions 118 of the plurality of pixels 541 to each other and integrates the VSS contact regions 118 into one. Specifically, as the conductive material having high heat resistance, a material having a melting point higher than at least a part of the melting point of the wiring material included in the wiring layer 200T of the second substrate 200 can be used.

[0244] As described above, for example, the imaging device 1 according to the embodiment includes: (1) a structure in which a first substrate 100 and a second substrate 200 are stacked in a face-to-back manner (specifically, a structure in which a semiconductor layer 100S and a wiring layer 100T of the first substrate 100, and a semiconductor layer 200S and a wiring layer 200T of the second substrate 200 are stacked in sequence); (2) a structure in which through electrodes 120E and 121E are provided that penetrate the semiconductor layer 200S of the second substrate 200 from the front surface side, the semiconductor layer 200S, and the wiring layer 100T of the first substrate 100 and reach the semiconductor layer 100S of the first substrate 100; and (3) a structure in which a connection wiring that connects floating diffusion parts FD included in a plurality of pixels 541 to each other and integrates the floating diffusion parts FD into one, and a connection wiring that connects VSS contact regions 118 included in the plurality of pixels 541 to each other and integrates the VSS contact regions 118 into one are formed of a conductive material having high heat resistance, so that without providing a large electrode at the interface between the first substrate 100 and the second substrate 200, the first substrate 100 can be provided with a connection wiring that connects floating diffusion parts FD included in a plurality of pixels 541 to each other and integrates the floating diffusion parts FD into one, and a connection wiring that connects VSS contact regions 118 included in the plurality of pixels 541 to each other and integrates the VSS contact regions 118 into one.

[0245] [Operation of Imaging Device 1]

[0246] Next, with reference toFigure 13 and Figure 14 explain the operation of the imaging device 1. Figure 13 and 14 are obtained by adding arrows respectively indicating the paths of the respective signals to Figure 3 . In Figure 13 , the paths of the input signals input to the imaging device 1 from the outside, the power supply potential, and the reference potential are shown by arrows. In Figure 14 , the signal paths of the pixel signals output from the imaging device 1 to the outside are shown by arrows. For example, the input signals (e.g., pixel clock and synchronization signal) input to the imaging device 1 through the input unit 510A are transmitted to the row driving unit 520 of the third substrate 300, and the row driving unit 520 generates a row driving signal. The row driving signal is transmitted to the second substrate 200 through the contact portion 301 and the contact portion 201. In addition, the row driving signal reaches each pixel common unit 539 of the pixel array portion 540 through the row driving signal line 542 of the wiring layer 200T. Among the row driving signals reaching the pixel common unit 539 of the second substrate 200, the driving signals other than the transfer gate TG are input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 through the through electrode TGV, and drives the pixels 541A, 541B, 541C, and 541D ( Figure 13 ). In addition, the power supply potential and the reference potential supplied from the outside of the imaging device 1 to the input unit 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 through the contact portion 301 and the contact portion 201, and are supplied to the pixel circuit 210 of each pixel common unit 539 via the wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 through the through electrode 121E. On the other hand, the pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of each pixel common unit 539 of the second substrate 200 through the through electrode 120E. The pixel signals based on the above pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 through the vertical signal line 543 and the contact portions 202 and 302. The pixel signals are processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside through the output unit 510B.

[0247] [Effect]

[0248] In the present embodiment, the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). Therefore, compared with the case where the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed on the same substrate, the areas of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 can be enlarged. As a result, the amount of pixel signals obtained by photoelectric conversion can be increased, and the transistor noise of the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signals is improved, and the imaging device 1 can output better pixel data (image information). In addition, the imaging device 1 can be miniaturized (in other words, the pixel size can be reduced and the size of the imaging device 1 can be reduced). The imaging device 1 can increase the number of pixels per unit area by reducing the pixel size and can output high-quality images.

[0249] In addition, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other through the through electrodes 120E and 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other or a method of connecting the first substrate 100 and the second substrate 200 through a through wiring (e.g., through-silicon via (TSV)) penetrating the semiconductor layer can be considered. Compared with these methods, by providing the through electrodes 120E and 121E in the insulating region 212, the area required for connecting between the first substrate 100 and the second substrate 200 can be reduced. As a result, the pixel size can be reduced, and the imaging device 1 can be further miniaturized. In addition, by further reducing the area of each pixel, the resolution can be further improved. When there is no need to reduce the chip size, the formation regions of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 can be enlarged. Thus, the amount of pixel signals obtained by photoelectric conversion can be increased, and the noise of the transistors included in the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signals is improved, and the imaging device 1 can output better pixel data (image information).

[0250] In addition, in the imaging device 1, the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are provided on different substrates (the second substrate 200 and the third substrate 300). Therefore, compared with the case where the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are formed on the same substrate, the area of the pixel circuit 210 and the areas of the column signal processing unit 550 and the image signal processing unit 560 can be enlarged. As a result, the noise generated by the column signal processing unit 550 can be reduced, and an advanced image processing circuit can be incorporated in the image signal processing unit 560. Consequently, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0251] In addition, in the imaging device 1, the pixel array unit 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing unit 550 and the image signal processing unit 560 are provided on the third substrate 300. Further, the contact portions 201, 202, 301, and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array unit 540. Therefore, the layout of the contact portions 201, 202, 301, and 302 can be freely set without being disturbed by the layout of various wirings provided in the pixel array. Accordingly, the contact portions 201, 202, 301, and 302 can be used for electrical connection between the second substrate 200 and the third substrate 300. For example, by using the contact portions 201, 202, 301, and 302, the column signal processing unit 550 and the image signal processing unit 560 have a higher degree of freedom in layout. As a result, the noise generated by the column signal processing unit 550 can be reduced, and an advanced image processing circuit can be incorporated in the image signal processing unit 560. Consequently, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0252] In addition, in the imaging device 1, the pixel isolation portion 117 penetrates the semiconductor layer 100S. Therefore, even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is shortened due to the miniaturization of each pixel area, color mixing between the pixels 541A, 541B, 541C, and 541D can be suppressed. As a result, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0253] In addition, in the imaging device 1, the pixel circuit 210 is provided for each pixel common unit 539. Therefore, compared with the case where the pixel circuit 210 is provided in each of the pixels 541A, 541B, 541C, and 541D, the formation area of the transistors (amplification transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switching transistor FDG) constituting the pixel circuit 210 can be enlarged. For example, by increasing the formation area of the amplification transistor AMP, noise can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0254] In addition, in the imaging device 1, a pad portion 120 for electrically connecting four pixels (pixels 541A, 541B, 541C, and 541D) to the floating diffusion portion FD (floating diffusion portions FD1, FD2, FD3, and FD4) is provided on the first substrate 100. Therefore, compared with the case where the pad portion 120 is provided on the second substrate 200, the number of through electrodes (through electrode 120E) connecting the first substrate 100 and the second substrate 200 can be reduced. Therefore, by reducing the insulating region 212, the formation area of the transistors (semiconductor layer 200S) constituting the pixel circuit 210 can be ensured with a sufficient size. Therefore, the noise of the transistors included in the pixel circuit 210 can be reduced, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0255] Hereinafter, a modification example of the imaging device 1 according to the above-described embodiment will be described. In the following modification examples, the same reference numerals are given to the same configurations as those in the above-described embodiment.

[0256] <2. First Modification Example>

[0257] Figures 15 to 19 A modification example of the planar configuration of the imaging device 1 according to the above-described embodiment is shown. Figure 15 The planar configuration near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown and corresponds to that described in the above-described embodiment Figure 8 corresponds. Figure 16 The configurations of each part of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100 are schematically shown and correspond to those described in the above-described embodiment Figure 9 corresponds. Figure 17 An example of the planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown and corresponds to that described in the above-described embodiment Figure 10 corresponds. Figure 18An example of the planar structure of the second wiring layer W2 and the third wiring layer W3 is shown, and it corresponds to that described in the above embodiment Figure 11 corresponds. Figure 19 An example of the planar structure of the third wiring layer W3 and the fourth wiring layer W4 is shown, and it corresponds to that described in the above embodiment Figure 12 corresponds.

[0258] In this modified example, as Figure 16 shown, in the two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout of one pixel sharing unit 539 (e.g., the right side of the paper surface) is obtained by only inverting the internal layout of the other pixel sharing unit 539 (e.g., the left side of the paper surface) in the H direction. In addition, the deviation in the V direction between the contour of one pixel sharing unit 539 and the contour of the other pixel sharing unit 539 is greater than the deviation described in the above embodiment ( Figure 9 ). In this way, by increasing the deviation in the V direction, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad portion 120 connected thereto (the pad portion 120 of the other pixel sharing unit 539 (the lower side of the paper surface) among the two pixel sharing units 539 arranged in the V direction shown in FIG. 7) can be reduced. Using this layout, Figures 15 to 19 the first modified example of the imaging device 1 shown can make the areas of the two pixel sharing units 539 arranged in the H direction the same as the area of the pixel sharing unit 539 of the second substrate 200 described in the above embodiment, without inverting the planar layout of the two pixel sharing units 539 in the V direction. Note that the planar layout of the pixel sharing unit 539 of the first substrate 100 is the same as the planar layout described in the above embodiment ( Figure 7A and Figure 7B ). Therefore, the imaging device 1 of this modified example can obtain the same effect as the imaging device 1 described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangements described in the above embodiment and this modified example.

[0259] <3. Second Modified Example>

[0260] Figures 20 to 25 A modified example of the planar structure of the imaging device 1 according to the above embodiment is shown. Figure 20 The planar structure of the first substrate 100 is schematically shown and corresponds to that described in the above embodiment Figure 7A corresponds. Figure 21 The planar structure near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown and corresponds to that described in the above embodiment Figure 8 corresponds. Figure 22Schematically shows the configuration of each part of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100, and is the same as that described in the above embodiment Figure 9 corresponding. Figure 23 Shows an example of the planar structure of the first wiring layer W1 and the second wiring layer W2, and is the same as that described in the above embodiment Figure 10 corresponding. Figure 24 Shows an example of the planar structure of the second wiring layer W2 and the third wiring layer W3, and is the same as that described in the above embodiment Figure 11 corresponding. Figure 25 Shows an example of the planar structure of the third wiring layer W3 and the fourth wiring layer W4, and is the same as that described in the above embodiment Figure 12 corresponding.

[0261] In this modified example, the outer shape of each pixel circuit 210 has a substantially square planar shape ( Figure 21 etc.). In this regard, the planar structure of the imaging device 1 in this modified example is different from the planar structure of the imaging device 1 described in the above embodiment.

[0262] For example, as described in the above embodiment, the pixel sharing unit 539 of the first substrate 100 is formed on a pixel region of 2 rows × 2 columns and has a substantially square planar shape ( Figure 20 ). For example, in each pixel sharing unit 539, the horizontal portions TGb of the transfer gates TG1 and TG3 of the pixels 541A and 541C in one pixel column extend in a direction from the position overlapping with the vertical portion TGa toward the central portion of the pixel sharing unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541A and 541C and in a direction toward the central portion of the pixel sharing unit 539), and the horizontal portions TGb of the transfer gates TG2 and TG4 of the pixels 541B and 541D in the other pixel column extend in a direction from the position overlapping with the vertical portion TGa toward the outer edge of the pixel sharing unit 539 in the H direction (more specifically, in a direction toward the outer edges of the pixels 541B and 541D and in a direction toward the outside of the pixel sharing unit 539). The pad portion 120 connected to the floating diffusion portion FD is provided at the central portion of the pixel sharing unit 539 (the central portion of the pixel sharing unit 539 in the H direction and the V direction), and the pad portion 121 connected to the VSS contact region 118 is provided at the end of the pixel sharing unit 539 at least in the H direction (in Figure 20 , in the H direction and the V direction).

[0263] As another example of the arrangement, it is also conceivable to provide the horizontal portions TGb of the transfer gates TGl, TG2, TG3, and TG4 only in the region facing the vertical portion TGa. At this time, as described in the above embodiment, the semiconductor layer 200S is likely to be subdivided. Therefore, it is difficult to form large transistors of the pixel circuit 210. On the other hand, when the horizontal portions TGb of the transfer gates TG1, TG2, TG3, and TG4 extend in the H direction from the position overlapping the vertical portion TGa as in the above modification, the width of the semiconductor layer 200S can be increased as described in the above embodiment. Specifically, the positions of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 in the H direction can be arranged at positions close to the through electrode 120E in the H direction, and the positions of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 in the H direction can be arranged at positions close to the through electrode 121E in the H direction. Therefore, as described in the above embodiment, the width (dimension in the H direction) of the semiconductor layer 200S extending along the V direction can be increased. Therefore, the size of the transistors of the pixel circuit 210, particularly the size of the amplifying transistor AMP, can be increased. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0264] The pixel common unit 539 of the second substrate 200 has, for example, substantially the same dimensions as the pixel common unit 539 of the first substrate 100 in the H direction and the V direction, and is provided, for example, in a region corresponding to a pixel region of approximately 2 rows × 2 columns. For example, in each pixel circuit 210, the selection transistor SEL and the amplifying transistor AMP are arranged side by side in the V direction in a semiconductor layer 200S extending in the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the V direction in a semiconductor layer 200S extending in the V direction. Via the insulating region 212, a semiconductor layer 200S provided with the selection transistor SEL and the amplifying transistor AMP and a semiconductor layer 200S provided with the FD conversion gain switching transistor FDG and the reset transistor RST are arranged in the H direction. The insulating region 212 extends in the V direction ( Figure 21 ).

[0265] Here, reference will be made to Figure 21 and Figure 22 to describe the outer shape of the pixel common unit 539 of the second substrate 200. For example, Figure 20[[END the pixel common unit 539 of the first substrate 100 shown is connected to one side in the H direction of the pad portion 120 provided ( ​The amplifying transistor AMP and the selection transistor SEL on the left side of the paper surface), and the FD conversion gain switching transistor FDG and the reset transistor RST on the other side in the H direction of the pad portion 120 ( ​ on the right side of the paper surface). The outer shape of the pixel common unit 539 of the second substrate 200 including the amplifying transistor AMP, the selection transistor SEL, the FD conversion gain switching transistor FDG, and the reset transistor RST is determined by the following four outer edges.

[0266] The first outer edge is one end in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP ( ​ the upper end of the paper surface). The first outer edge is provided between the amplifying transistor AMP included in the pixel common unit 539 and the selection transistor SEL included in the pixel common unit 539 adjacent to one side of the pixel common unit 539 in the V direction ( ​ the upper side of the paper surface). More specifically, the first outer edge is provided at the central portion in the V direction of the element isolation region 213 between the amplifying transistor AMP and the selection transistor SEL. The second outer edge is the other end in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP ( ​ the lower end of the paper surface). The second outer edge is provided between the selection transistor SEL included in the pixel common unit 539 and the amplifying transistor AMP included in the pixel common unit 539 adjacent to the other side of the pixel common unit 539 ( ​ the lower side of the paper surface). More specifically, the second outer edge is provided at the central portion in the V direction of the element isolation region 213 between the selection transistor SEL and the amplifying transistor AMP. The third outer edge is the other end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG ( ​ the lower end of the paper surface). The third outer edge is provided between the FD conversion gain switching transistor FDG included in the pixel common unit 539 and the reset transistor RST included in the pixel common unit 539 adjacent to the other end of the pixel common unit 539 in the V direction ( ​ the lower side of the paper surface). More specifically, the third outer edge is provided at the central portion in the V direction of the element isolation region 213 between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is one end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG ( ​ the upper end of the paper surface). The fourth outer edge is provided between the reset transistor RST included in the pixel common unit 539 and one side of the pixel common unit 539 in the V direction ( ​between the FD conversion gain switching transistors FDG (not shown) included in the pixel sharing unit 539 adjacent to the upper side of the paper surface. More specifically, the fourth outer edge is provided at the center portion in the V direction of the element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0267] In the outer shape of the pixel sharing unit 539 of the second substrate 200 including such a first outer edge, second outer edge, third outer edge, and fourth outer edge, the third outer edge and the fourth outer edge are arranged to be offset to one side with respect to the first outer edge and the second outer edge in the V direction (in other words, offset to one side in the V direction). By using such a layout, both the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG can be arranged as close as possible to the pad portion 120. Therefore, the area of the wiring connecting the amplifying transistor AMP and the FD conversion gain switching transistor FDG to the pad portion 120 is reduced, and the imaging device 1 can be easily miniaturized. Note that the VSS contact region 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, a plurality of pixel circuits 210 have the same arrangement.

[0268] The imaging device 1 including such a second substrate 200 can also obtain the same effects as those described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangements described in the above embodiment and this modification.

[0269] <4. Third Modification>

[0270] ​ A modification of the planar structure of the imaging device 1 according to the above embodiment is shown. ​ The planar structure of the first substrate 100 is schematically shown and corresponds to that described in the above embodiment ​ corresponds. ​ The planar structure near the front surface of the semiconductor layer 200S of the second substrate 200 is schematically shown and corresponds to that described in the above embodiment ​ corresponds. ​ The structure of each part of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100 is schematically shown and corresponds to that described in the above embodiment ​ corresponds. ​ An example of the planar structure of the first wiring layer W1 and the second wiring layer W2 is shown and corresponds to that described in the above embodiment ​ corresponds. ​An example of the planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown and corresponds to that described in the above embodiment. ​ Corresponding. ​ An example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown and corresponds to that described in the above embodiment. ​ Corresponding.

[0271] In this modified example, the semiconductor layer 200S of the second substrate 200 extends along the H direction ( ​ ). That is, this configuration roughly corresponds to the configuration obtained by rotating the planar configuration of the imaging device 1 shown by, for example, 90 degrees. ​ etc.

[0272] For example, as described in the above embodiment, the pixel sharing unit 539 of the first substrate 100 is formed on a pixel region of 2 rows × 2 columns and has a substantially square planar shape ( ​ ). For example, in each pixel sharing unit 539, the transfer gates TG1 and TG2 of the pixels 541A and 541B in one pixel row extend toward the central portion of the pixel sharing unit 539 in the V direction, and the transfer gates TG3 and TG4 of the pixels 541C and 541D in the other pixel row extend in a direction toward the outside of the pixel sharing unit 539 in the V direction. The pad portion 120 connected to the floating diffusion portion FD is provided at the central portion of the pixel sharing unit 539, and the pad portion 121 connected to the VSS contact region 118 is provided at least at the end portion of the pixel sharing unit 539 in the V direction ( ​ in the V direction and the H direction in the V direction). In this case, the positions in the V direction of the through electrodes TGV1 and TGV2 of the transfer gate TG1 and the transfer gate TG2 are close to the position in the V direction of the through electrode 120E, and the positions in the V direction of the through electrodes TGV3 and TGV4 of the transfer gate TG3 and the transfer gate TG4 are close to the position in the V direction of the through electrode 121E ( ​ ). Therefore, for the same reason as described in the above embodiment, the width (dimension in the V direction) of the semiconductor layer 200S extending along the H direction can be increased. Therefore, the size of the amplification transistor AMP can be increased, and noise can be suppressed.

[0273] In each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged at a position adjacent to the selection transistor SEL in the V direction, and the insulating region 212 is sandwiched between the selection transistor SEL and the reset transistor RST. ​)。The FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the H direction. The VSS contact region 218 is provided in the insulating region 212 in an island shape. For example, the third wiring layer W3 extends in the H direction ( ​ ) and the fourth wiring layer W4 extends in the V direction ( ​ ).

[0274] The imaging device 1 including such a second substrate 200 can also achieve the same effects as those described in the above embodiments. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangements described in the above embodiments and this modification example. For example, the semiconductor layer 200S described in the above embodiments and the first modification example can extend along the H direction.

[0275] <5. Fourth Modification Example>

[0276] ​ A modification example of the cross-sectional structure of the imaging device 1 according to the above embodiment is schematically shown. ​ Corresponding to those described in the above embodiment ​ . In this modification example, in addition to the contact portions 201, 202, 301, and 302, the imaging device 1 further has contact portions 203, 204, 303, and 304 at positions facing the central portion of the pixel array portion 540. The imaging device 1 of this modification example is different from the imaging device 1 described in the above embodiment in this regard.

[0277] The contact portions 203 and 204 are provided on the second substrate 200 and are exposed on the bonding surface with the third substrate 300. The contact portions 303 and 304 are provided on the third substrate 300 and are exposed on the bonding surface with the second substrate 200. The contact portion 203 is in contact with the contact portion 303, and the contact portion 204 is in contact with the contact portion 304. That is, in the imaging device 1, in addition to the contact portions 201, 202, 301, and 302, the second substrate 200 and the third substrate 300 are also connected through the contact portions 203, 204, 303, and 304.

[0278] Next, the operation of the imaging device 1 will be described with reference to ​ and ​ . In ​ , the input signals input to the imaging device 1 from the outside and the paths of the power supply potential and the reference potential are shown by arrows. In ​In this case, the signal path of the pixel signal output from the imaging device 1 to the outside is indicated by an arrow. For example, an input signal input to the imaging device is transmitted to the row driving unit 520 of the third substrate 300 through the input unit 510A, and the row driving unit 520 generates a row driving signal. The row driving signal is transmitted to the second substrate 200 through the contact portion 303 and the contact portion 203. In addition, the row driving signal reaches each pixel common unit 539 of the pixel array portion 540 through the row driving signal line 542 of the wiring layer 200T. Among the row driving signals reaching the pixel common unit 539 of the second substrate 200, driving signals other than the driving signal of the transfer gate TG are input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 through the through electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven. In addition, the power supply potential and the reference potential supplied to the input unit 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are transmitted to the second substrate 200 through the contact portion 303 and the contact portion 203, and are supplied to the pixel circuit 210 of each pixel common unit 539 via the wiring of the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 through the through electrode 121E. On the other hand, for each pixel common unit 539, the pixel signal photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 200. The pixel signal based on this pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 through the vertical signal line 543 and the contact portions 204 and 304. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside through the output unit 510B.

[0279] The imaging device 1 including such contact portions 203, 204, 303, and 304 can also obtain the same effects as those described in the above embodiments. The position, number, etc. of the contact portions can vary according to the design of the circuit of the third substrate 300 to which the wiring is connected through the contact portions 303 and 304.

[0280] <6. Fifth Modified Example>

[0281] ​ A modified example of the cross-sectional structure of the imaging device 1 according to the above embodiment is shown. ​ Corresponding to that described in the above embodiment ​. In this modified example, a transfer transistor TR having a planar structure is provided on the first substrate 100. The imaging device 1 of this modified example is different from the imaging device 1 described in the above-described embodiment in this respect.

[0282] In the transfer transistor TR, the transfer gate TG is composed only of a horizontal portion TGb. In other words, the transfer gate TG does not have a vertical portion TGa and is provided to face the semiconductor layer 100S.

[0283] The imaging device 1 including such a transfer transistor TR having a planar structure can also obtain the same effects as those described in the above-described embodiment. In addition, it can be imagined that, compared with the case where a vertical transfer gate TG is provided on the first substrate, by providing a planar transfer gate TG on the first substrate 100, the photodiode PD can be formed closer to the front surface of the semiconductor layer 100S, thereby increasing the saturation signal amount (Qs). In addition, it can be thought that, compared with the method of forming a vertical transfer gate TG on the first substrate 100, in the method of forming a planar transfer gate TG on the first substrate 100, the number of manufacturing steps is smaller and the photodiode PD is less likely to be adversely affected by the manufacturing steps.

[0284] <7. Sixth Modified Example>

[0285] ​ A modified example of the pixel circuit of the imaging device 1 according to the above-described embodiment is shown. ​ Corresponding to that described in the above-described embodiment ​ . In this modified example, a pixel circuit 210 is provided for each pixel (pixel 541A). That is, the plurality of pixels do not share the pixel circuit 210. The imaging device 1 of this modified example is different from the imaging device 1 described in the above-described embodiment in this respect.

[0286] The imaging device 1 of this modified example is the same as the imaging device 1 described in the above-described embodiment in that the pixel 541A and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). Therefore, the imaging device 1 according to this modified example can also obtain the same effects as those described in the above-described embodiment.

[0287] <8. Seventh Modified Example>

[0288] ​Shows a modified example of the planar structure of the pixel isolation portion 117 described in the above embodiment. A gap is provided in the pixel isolation portion 117 surrounding each of the pixels 541A, 541B, 541C, and 541D. That is, the pixel isolation portion 117 may not surround the entire outer periphery of the pixels 541A, 541B, 541C, and 541D. For example, the gap of the pixel isolation portion 117 is provided near the pad portion 120 and the pad portion 121 (refer to ​ ).

[0289] In the above embodiment, an example of the FTI structure in which the pixel isolation portion 117 penetrates the semiconductor layer 100S (refer to ​ ) has been described, but the pixel isolation portion 117 may have other structures other than the FTI structure. For example, the pixel isolation portion 117 may be provided so as not to completely penetrate the semiconductor layer 100S and may have a so-called deep trench isolation (DTI) structure.

[0290] <9. Second Embodiment>

[0291] <9.1 Problems to be Solved by the Second Embodiment>

[0292] However, the floating diffusion portion FD in the pixel 541 and the gate of the amplifying transistor AMP in the pixel circuit 210 are connected through a connection via hole serving as the FD wiring FDL. In fine pixels, the area of the connection via hole of the FD wiring FDL is about 45%. Therefore, since the effective area of the pixel circuit 210 is reduced, the layout area of the amplifying transistor AMP cannot be enlarged.

[0293] In addition, the capacitance between the FD wiring FDL and the gate of the amplifying transistor AMP and the capacitance between other connection via holes extending in parallel with the connection via hole of the FD wiring FDL (for example, the TG wiring TGL or the VSS wiring VSS) overlap the capacitance of the floating diffusion portion FD. Therefore, the FD capacitance is increased, the charge-voltage conversion efficiency is reduced, and the read noise cannot be reduced.

[0294] <9.2 Overview of the Second Embodiment>

[0295] Therefore, the imaging device has a first substrate, a second substrate, wirings, and trenches. The first substrate has pixels including photodiodes and floating diffusion portions that hold charges converted by the photodiodes. The second substrate includes pixel circuits that read pixel signals based on the charges held in the floating diffusion portions of the pixels, and is stacked on the first substrate. The wirings penetrate the first substrate and the second substrate in the stacking direction, and electrically connect the floating diffusion portions of the first substrate to the amplifier transistors in the pixel circuits of the second substrate. Trenches are formed at least in the second substrate, extend parallel to the wirings, and have a depth equal to or greater than the thickness of the semiconductor layer in the second substrate.

[0296] In the imaging device, trenches are formed at a depth equal to or greater than the thickness of the semiconductor layer in the second substrate and extend parallel to the wirings that electrically connect the floating diffusion portions in the first substrate to the amplifier transistors in the pixel circuits of the second substrate. As a result, the parasitic capacitance of the wirings is reduced, and the charge-voltage conversion efficiency is improved.

[0297] <9.3 Specific Example of the Second-1 Embodiment>

[0298] <9.3.1 Structure of the Second-1 Embodiment>

[0299] ​ is an equivalent circuit diagram showing a structural example of a pixel sharing unit 539 of the imaging device 1 of the second-1 embodiment. The imaging device 1 has a structure in which a first substrate 100, a second substrate 200, and a third substrate 300 are stacked. The first substrate 100 has pixels 541 that perform photoelectric conversion. The second substrate 200 has pixel circuits 210A that read pixel signals based on the charges output from the pixels 541. The third substrate 300 has a processing circuit that detects pixel signals. The pixel sharing unit 539 has pixels 541 and pixel circuits 210A. The pixels 541 have four photodiodes PD, four transfer transistors TR that transfer the charges converted by the respective photodiodes PD, and floating diffusion portions FD that hold the charges transferred by the transfer transistors TR.

[0300] The pixel circuit 210A includes, for example, a reset transistor RST, an amplifier transistor AMP, a selection transistor SEL, a power supply line VDD, and a vertical signal line (VSL) 543. The reset transistor RST resets the voltage of the floating diffusion portion FD to a predetermined potential. The amplifier transistor AMP generates a voltage signal as a pixel signal according to the level of the charge held in the floating diffusion portion FD. The selection transistor SEL controls the connection between the drain of the amplifier transistor AMP and the vertical signal line 543. The floating diffusion portion FD of the first substrate 100 is electrically connected to the gate of the amplifier transistor AMP of the pixel circuit 210A of the second substrate 200 through an FD wiring FDL.

[0301] The vertical signal line 543 electrically connects each pixel circuit 210A to the column signal processing unit 550 of the processing circuit arranged on the third substrate 300. Then, the column signal processing unit 550 detects the pixel signals appearing in the vertical signal line 543 from each pixel circuit 210A.

[0302] The imaging device 1 has an FD wiring FDL that connects the floating diffusion portion FD of the pixel 541 on the first substrate 100 to the gate of the amplification transistor AMP of the pixel circuit 210A on the second substrate 200. The FD wiring FDL is formed as a connection through hole between the first substrate 100 and the second substrate 200. The imaging device 1 has a trench T formed closer to the first substrate 100 side in the second substrate 200 and extending in parallel with the FD wiring FDL. The trench T is in a state where, for example, a conductive material is embedded therein.

[0303] The source of the amplification transistor AMP in the pixel circuit 210A of the second substrate 200 is connected to the shielding wiring SL made of a conductive material embedded in the trench T to have the same potential. By reducing the parasitic capacitance between the FD wiring FDL and the shielding wiring SL to (1-(SF gain)) times, the capacitance of the FD wiring FDL can be reduced to improve the charge-voltage conversion efficiency.

[0304] ​ is a schematic cross-sectional view showing an example of the stacked structure of the first substrate 100 and the second substrate 200 of the 2-1 embodiment. The wiring layer 100T between the semiconductor layer 100S in the first substrate 100 and the second substrate 200 is made of, for example, SiO 2 etc., and has a through wiring penetrating the wiring layer 100T in the stacking direction. The first substrate 100 and the second substrate 200 are electrically connected to each other through the through wiring.

[0305] The through wiring includes a TG wiring TGL electrically connected to the gate (transfer gate TG) of the transfer transistor TR connected to the pixel 541, and an FD wiring FDL connecting the gate of the amplification transistor AMP of the pixel circuit 210A to the connection pad of the floating diffusion portion FD. The trench T is formed between the TG wiring TGL and the FD wiring FDL in the wiring layer 100T. Note that the depth of the trench T is equal to or greater than the thickness of the Si substrate of the second substrate 200 and is within a range that does not affect the floating diffusion portion FD formed in the first substrate 100. The shielding wiring SL is formed of a conductive material such as doped polysilicon or metal embedded in the trench T.

[0306] ​It is a schematic diagram showing an example of the stacked structure of the first substrate 100 and the second substrate 200. When observing the shield wiring SL (groove T) from the front surface (stacking surface) of the wiring layer 100T, as shown in the figure, on the stacking surface of the wiring layer 100T, the shield wiring SL is formed in a circular shape centered on the FD wiring FDL. That is, on the stacking surface of the wiring layer 100T, a groove T extending parallel to the FD wiring FDL is formed, so that in a state where the FD wiring FDL and the TG wiring TGL extending parallel to the FD wiring FDL are electrically separated from each other, the FD wiring FDL is surrounded in a circular shape on the stacking surface.

[0307] <9.3.2 Operation and effects of the 2-1st embodiment>

[0308] In the imaging device 1 of the 2-1st embodiment, the shield wiring SL extends parallel to the FD wiring FDL that penetrates and connects the first substrate 100 and the second substrate 200. In addition, in the imaging device 1, the source of the amplification transistor AMP of the pixel circuit 210A of the second substrate 200 is electrically connected to the shield wiring SL to have the same potential. Therefore, since the parasitic capacitance between the FD wiring FDL and the shield wiring SL is reduced to (1-(SF gain)) times, the capacitance of the FD wiring FDL can be reduced to improve the charge-voltage conversion efficiency. In addition, even when one FD wiring FDL extends parallel to two TG wirings TGL, the shield wiring SL is arranged between each FD wiring FDL and the TG wiring TGL and between the FD wiring FDL and another FD wiring FDL. Therefore, by reducing the parasitic capacitance of the FD wiring FDL, the charge-voltage conversion efficiency can be improved.

[0309] <9.3.3 Variation of the 2-1st embodiment>

[0310] In addition, it has been exemplified that when observing the shield wiring SL from the front surface (stacking surface) of the wiring layer 100T, the shield wiring SL is formed in a circular shape centered on the FD wiring FDL, but the present invention is not limited thereto and can be appropriately deformed. ​ It is a schematic diagram showing an example of the arrangement structure of the grooves T1 on the surface of the second substrate 200. ​ It is a schematic diagram showing an example of the arrangement structure of the grooves T2 on the surface of the second substrate 200. For example, when observing the shield wiring SL from the front surface (stacking surface) of the wiring layer, ​ the parallel plate-shaped groove T1 shown can be used, or ​ the rectangular groove T2 shown can be used, and this can be appropriately deformed.

[0311] ​It is a schematic diagram showing an example of the arrangement of the trenches T3 on the surface of the second substrate 200. In addition, the trench T can be arranged at a position where the FD wiring FDL and the TG wiring TGL are electrically separated from each other. For example, with respect to ​ the shown FD wiring FDL, a trench T3 having a width length greater than that of the FD wiring FDL can be arranged. ​ It is a schematic diagram showing an example of the arrangement of the trenches T4 on the surface of the second substrate 200. When ​ the TG wiring TGL is arranged on the diagonal line of the shown FD wiring FDL, the trench T4 can be arranged on the diagonal line of the FD wiring FDL between the FD wiring FDL and the TG wiring TGL and can be appropriately deformed.

[0312] In the imaging device 1 of the 2-1st embodiment, an example has been described where the shielding wiring SL having the trench T in which the conductive material is embedded is formed in the wiring layer 100T. However, a hollow trench T can be formed as the shielding wiring SL in the wiring layer 100T without embedding the conductive material in the trench T, and it can be appropriately deformed.

[0313] Note that, as the selected pixel 541, for example, an example has been described of the pixel 541 selected based on row selection among one or more pixels 541 arranged in the row direction. However, the unselected pixel 541 can be any pixel 541 other than the selected pixel 541, and it can be appropriately deformed.

[0314] As the selected pixel 541, an example of the pixel 541 selected based on row selection has been described. However, for example, it can be the pixel 541 selected based on column selection among one to more pixels 541 arranged in the column direction, and it can be appropriately deformed.

[0315] The pixel 541 includes, for example, a total of four photodiodes PD of 2×2, but it can be appropriately deformed as long as the pixel 541 includes one or more photodiodes PD, and is not limited to four photodiodes PD.

[0316] <9.4 Specific Example of the 2-2nd Embodiment>

[0317] <9.4.1 Structure of the 2-2nd Embodiment>

[0318] In the imaging device 1 of the 2-1st embodiment, an example has been described where the trench T is arranged between one FD wiring FDL and the TG wiring TGL. However, the trench T can be arranged between four FD wirings FDL and the TG wiring TGL, and its embodiment will be described below as the 2-2nd embodiment. The same components as those in the 2-1st embodiment are denoted by the same reference numerals, and redundant descriptions of the components and operations will be omitted.

[0319] ​ It is a schematic cross-sectional view showing an example of the stacked structure of the first substrate 100 and the second substrate 200 of the second - 2 embodiment. The wiring layer 100T has a first FD wiring FDL1, a second FD wiring FDL2, a first TG wiring TGL1, and a second TG wiring TGL2.

[0320] The wiring layer 100T includes a first trench T51, a second trench T52, and a third trench T53. The first trench T51 is formed between the first TG wiring TGL1 and the first FD wiring FDL1 and electrically isolates the first FD wiring FDL1 from the first TG wiring TGL1. The second trench T52 is formed between the second TG wiring TGL2 and the second FD wiring FDL2 and electrically separates the second TG wiring TGL2 from the second FD wiring FDL2. The third trench T53 is formed between the first FD wiring FDL1 and the second FD wiring FDL2 and electrically separates the first FD wiring FDL1 from the second FD wiring FDL2.

[0321] ​ It is a schematic diagram showing an example of the arrangement structure of the trenches T5 on the surface of the second substrate 200. When observing the trenches T5 from the front surface (stacking surface) of the wiring layer 100T, as ​ shown, the trenches T5 include a first trench T51, a second trench T52, a third trench T53, a fourth trench T54, and a fifth trench T55. The first trench T51 electrically separates the first FD wiring FDL1 from the first TG wiring TGL1 and electrically separates the third FD wiring FDL3 from the third TG wiring TGL3. The third trench T53 electrically separates the first FD wiring FDL1 from the second FD wiring FDL2 and electrically separates the third FD wiring FDL3 from the fourth FD wiring FDL4. The second trench T52 electrically separates the second FD wiring FDL2 from the second TG wiring TGL2 and electrically separates the fourth FD wiring FDL4 from the fourth TG wiring TGL4. ​ It is a schematic diagram showing an example of the schematic cross-sectional shape of the trench T5. In the trench T5, as ​ shown, the hole size on the front surface (second substrate 200) side can be larger than the hole size on the rear surface (first substrate 100) side and can be appropriately deformed.

[0322] The arrangement structure of the trench T can be appropriately deformed and can be as ​ shown. ​ It is a schematic diagram showing an example of the arrangement structure of the trenches T10 on the surface of the second substrate 200. The L-shaped trenches T10 can be arranged at ​On each diagonal of the first FD wiring FDL1 shown with respect to the TG wirings TGL1 to TGL4. In this case, the trench T10 electrically separates the first FD wiring FDL1 from the first TG wiring TGL1, the first FD wiring FDL1 from the second TG wiring TGL2, the first FD wiring FDL1 from the third TG wiring TGL3, and the first FD wiring FDL1 from the fourth TG wiring TGL4.

[0323] ​ FIG. is a schematic diagram showing an example of the arrangement configuration of the trenches T11 on the surface of the second substrate 200. As ​ shown, each of the FD wirings FDL1 to FDL4 can be surrounded by grid-shaped trenches T11. The trenches electrically separate the FD wiring FDL from the adjacent FD wiring FDL and the FD wiring FDL from the adjacent TG wiring TGL. Figure 46D FIG. is a schematic diagram showing an example of the arrangement configuration of the trenches T12 on the surface of the second substrate 200. As Figure 46D shown, each of the FD wirings FDL1 to FDL4 can be surrounded by grid-shaped trenches T12. At the same time, the shielding of the cross-shaped intersection T12A of the trench T12 is omitted. Therefore, needless to say, the FD wiring FDL is electrically separated from the adjacent FD wiring FDL and the FD wiring FDL is electrically separated from the adjacent TG wiring TGL, and the situation where the processing depth of the intersection becomes deeper during trench processing can be avoided.

[0324] Figure 46E FIG. is a schematic diagram showing an example of the arrangement configuration of the trenches T13 on the surface of the second substrate 200. Figure 46E The trench T13 shown has a cross trench T131 and a diagonal trench T132. The cross trench T131 electrically separates adjacent FD wirings FDL from each other. The diagonal trench T132 electrically separates the FD wiring FDL from the TG wiring TGL on its diagonal. Figure 46F FIG. is a schematic diagram showing an example of the arrangement configuration of the trenches T14 on the surface of the second substrate 200. Figure 46F The trench T14 shown has a cross trench T141 and a diagonal trench T142. The cross trench T141 electrically separates adjacent FD wirings FDL from each other. The diagonal trench T142 electrically separates the FD wiring FDL from the TG wiring TGL on its diagonal.

[0325] Figure 46G FIG. is a schematic diagram showing an example of the arrangement configuration of the trenches T15 on the surface of the second substrate 200. Figure 46GThe shown trench T15 has a cross trench T151 and a diagonal trench T152. The cross trench T151 electrically separates adjacent FD wirings FDL from each other. The diagonal trench T152 electrically separates the FD wiring FDL from the TG wiring TGL on its diagonal line. At the same time, the shielding of the cross-shaped intersection T151A of the cross trench T151 is omitted. Therefore, needless to say, the FD wiring FDL is electrically separated from the adjacent FD wiring FDL and the FD wiring FDL is electrically separated from the adjacent TG wiring TGL, and the situation where the processing depth of the intersection T151A becomes deeper during trench processing can be avoided.

[0326] Figure 46H It is a schematic diagram showing an example of the arrangement structure of the trench T16 on the surface of the second substrate 200. Figure 46H The shown trench T16 has a cross trench T161 and a diagonal trench T162. The cross trench T161 electrically separates adjacent FD wirings FDL from each other. The diagonal trench T162 electrically separates the FD wiring FDL from the TG wiring TGL on its diagonal line. At the same time, the shielding of the cross-shaped intersection T161A of the cross trench T161 is omitted. Therefore, needless to say, the FD wiring FDL is electrically separated from the adjacent FD wiring FDL and the FD wiring FDL is electrically separated from the adjacent TG wiring TGL, and the situation where the processing depth of the intersection T161A becomes deeper during trench processing can be avoided.

[0327] <9.4.2 Operation and effects of the second - 2 embodiment>

[0328] Even when the four FD wirings FDL1 to FDL4 and the four TG wirings TGL1 to TGL4 extend in parallel, there are trenches T5 arranged to electrically isolate each FD wiring FDL from the TG wiring TGL and to electrically separate the FD wiring FDL from other FD wirings FDL. Therefore, by reducing the capacitance of the FD wiring FDL, the charge - voltage conversion efficiency can be improved.

[0329] In the imaging device 1 of the 2 - 1 embodiment, an example has been given of the case where a shield wiring SL composed of a trench T in which a conductive material is embedded is arranged in the wiring layer 100T. However, the material embedded in the trench T is not limited to a conductive material and can be, for example, a gas, and its embodiment will be described below as the 2 - 3 embodiment.

[0330] <9.5 Specific example of the 2 - 3 embodiment>

[0331] <9.5.1 Structure of the 2 - 3 embodiment>

[0332] Figure 48A It is an equivalent circuit diagram showing an example of the structure of the pixel sharing unit 539 in the imaging device 1 of the 2 - 3 embodiment, andFigure 49 FIG. 1 is a schematic cross-sectional view showing an example of a stacked structure of a first substrate 100 and a second substrate 200 according to the second and third embodiments. The imaging device 1 includes an FD wiring FDL that penetrates and connects a semiconductor layer 100S in the first substrate 100 and a wiring layer 100T between the second substrates 200, and a trench T6 that extends in parallel with the FD wiring FDL formed on the side of the second substrate 200 closer to the first substrate 100.

[0333] The trench T6 is filled and sealed with a gas having a low relative dielectric constant (εs) such as air (1.00054), N2 (1.00057), He (1.00052), or Ar (1.00007) to form a shield wiring SL1. By using an air gap having a relative dielectric constant lower than that of SiO 2 with a relative dielectric constant of 3.9, the FD capacitance can be reduced to improve the charge-voltage conversion efficiency.

[0334] In the imaging device 1 according to the second and third embodiments, since the trench T6 filled with a gas having a low relative dielectric constant is disposed between the FD wiring FDL and the TG wiring TGL, the parasitic capacitance of the FD wiring FDL is reduced, thereby improving the charge-voltage conversion efficiency.

[0335] Note that the case where the trench T6 is sealed with a gas having a low dielectric constant has been exemplified, but the trench T6 may be filled with an insulating film material having a low dielectric constant (Low-k) and may be appropriately deformed.

[0336] In addition, the case where the depth of the trench T6 is set to be deeper than SiO in the second substrate 200 and within a range that does not affect the floating diffusion portion FD of the first substrate 100 has been exemplified. However, the depth is not limited thereto, and compared with the shield wiring SL, it may be set to 2 the depth of the trench T6 of the shield wiring SL1 shown, and may be appropriately deformed. In addition, for the wiring layer 100T, for example, SiO has been exemplified Figure 49 for the wiring layer 100T. However, for example, an insulating film material having a dielectric constant (Low-k) lower than that of SiO 2 may be used, and may be appropriately deformed. 2

[0337] <9.5.2 Operations and Effects of the Second and Third Embodiments>

[0338] In the imaging device 1 of the second to third embodiments, even when one FD wiring FDL and two TG wirings TGL extend in parallel, a shielding wiring SL1 is arranged to electrically isolate each FD wiring FDL from the TG wiring TGL and to electrically isolate the FD wiring FDL from other FD wirings FDL. Therefore, by reducing the parasitic capacitance of the FD wiring FDL, the charge-voltage conversion efficiency can be improved.

[0339] Figure 48B is an equivalent circuit diagram showing another example of the structure of the pixel sharing unit of the imaging device of the second to third embodiments.

[0340] Figure 48B The pixel sharing unit of Figure 48A differs from the pixel sharing unit of

[0341] in that the back gate of the amplifying transistor AMP is connected to the source of the amplifying transistor AMP.

[0342] Consequently, since the gate-source voltage Vgs of the amplifying transistor AMP is reduced, the potential of the reset level appearing in the vertical signal line (column read line) 543 is increased.

[0343] <10. Third Embodiment>

[0344] <10.1 Problem to be Solved by the Third Embodiment>

[0345] For example, let the charge obtained by photoelectric conversion of the photodiode PD be Qp, the FD capacitance of the floating diffusion section FD be Cfd, and the gain of the source follower circuit be Gsf. In this case, the source follower output voltage Vsf is calculated by the formula Vsf = Gsf * Qp / Cfd. Therefore, when a large output voltage is obtained using the same amount of light, the signal-to-noise ratio (S / N) is improved. However, as the FD capacitance (Cfd) increases, the source follower output voltage (Vsf) decreases. Therefore, the source follower output voltage (Vsf) can be increased by increasing the gain (Gsf) of the source follower circuit. However, the influence of the parasitic capacitance of the FD capacitance (Cfd) is large, and it is necessary to reduce the parasitic capacitance.

[0346] <10.2 Outline of the Third Embodiment>

[0347] Therefore, the imaging device has a first substrate, a second substrate, wirings, and shielding wirings. The first substrate has pixels including photodiodes and floating diffusion parts that hold charges converted by the photodiodes. The second substrate has pixel circuits that read pixel signals based on the charges held in the floating diffusion parts of the pixels, and is stacked on the first substrate. The wirings electrically connect the floating diffusion parts in the first substrate to amplification transistors in the pixel circuits of the second substrate, and are formed on the first substrate and the second substrate. In a state where the well layers of the pixel circuits and the well layers of the amplification transistors of the pixel circuits are electrically isolated from each other, the shielding wirings electrically connect the gates and the sources of the amplification transistors, and the shielding wirings shield the wirings while extending in parallel with the wirings.

[0348] In the imaging device, in a state where the well layer of the pixel circuit and the well layer of the amplification transistor are electrically isolated from each other, the shielding wiring extends in parallel with the wiring and shields the wiring, and the shielding wiring electrically connects the gate and the source of the amplification transistor. That is, the source of the amplification transistor and the well layer of the amplification transistor are connected to have the same potential, thereby eliminating the substrate bias effect, and the gains of the floating diffusion part amplitude and the amplification transistor source amplitude are set to 1. In addition, the shielding wiring that extracts the source potential of the amplification transistor is arranged around the wiring, and the wiring connected to the floating diffusion part moves with the same amplitude as the floating diffusion part. Therefore, since the wiring connection capacitance is reduced, the capacitance of the floating diffusion part is reduced, thereby improving the charge-voltage conversion efficiency.

[0349] That is, in the imaging device, the capacitance of the floating diffusion part caused by the parasitic resistance of the wiring is reduced, thereby improving the charge-voltage conversion efficiency. In addition, crosstalk with adjacent wirings can be suppressed by the shielding wiring.

[0350] <10.3 Specific Example of the 3-1 Embodiment>

[0351] <10.3.1 Structure of the 3-1 Embodiment>

[0352] Figure 50A is an equivalent circuit diagram showing a structural example of a plurality of pixel circuits 210B of the second substrate 200 of the 3-1 embodiment. The second substrate 200 includes a common p-well layer 250 shared by all pixels and an independent p-well layer 251 for the amplification transistor AMP of each pixel 541, and the common p-well layer 250 and the independent p-well layer 251 are electrically isolated by a full trench (FTI) T7.

[0353] In the common p-well layer 250, a reset transistor RST and a selection transistor SEL of each pixel circuit 210B are formed. Since the common p-well layer 250 is connected to the GND potential, the back gates of the reset transistor RST and the selection transistor SEL are fixed to the GND potential.

[0354] On the other hand, in the independent p-well layer 251, an amplifying transistor AMP of the pixel circuit 210B is formed. Since the independent p-well layer 251 is connected to the source of the amplifying transistor AMP, the potential of the independent p-well layer 251 changes with the source potential of the amplifying transistor AMP. That is, since the back gate and the source potential of the amplifying transistor AMP have the same potential, the gain of the source follower circuit becomes 1.

[0355] For example, when the back gate of the amplifying transistor AMP is fixed at the GND potential, a substrate bias effect appears according to the fluctuation of the source potential of the amplifying transistor AMP, and the gain of the source follower circuit becomes a value of about 0.85. Therefore, since the independent p-well layer 251 follows the source potential of the amplifying transistor AMP, the gain of the source follower circuit increases by 17%, which causes the source follower output voltage (Vsf) to increase by 17%.

[0356] At the same time, the column signal processing unit 550 is respectively connected to the vertical signal lines (column read lines) 543, and reads pixel signals through the vertical signal lines (column read lines) 543.

[0357] Here, the structure of the column signal processing unit 550 will be described.

[0358] Figure 50B It is a schematic structural block diagram of the column signal processing unit of the first aspect.

[0359] The column signal processing unit 550 includes, for example, a reference signal generation unit 551 configured as a constant voltage source, an AD converter 552 that performs AD conversion based on the reference signal input from the reference signal generation unit 551, and a load circuit LD configured as a current source, and outputs an AD conversion output ADCOUT as pixel data according to the voltage of the vertical signal line (column read line) 543.

[0360] According to the above structure, the read pixel signal can be converted into digital data and output.

[0361] Figure 50C It is a schematic structural block diagram of the column signal processing unit of the second aspect.

[0362] The column signal processing unit 550 of the second aspect uses a single-slope ADC structure.

[0363] The column signal processing unit 550 includes, for example, a RAMP generation circuit 553 that generates and outputs a RAMP waveform, a comparator 554 that compares the voltage of the pixel signal read through the vertical signal line (column read line) 543 with the voltage of the RAMP waveform and outputs a comparison result signal, a counter 555 that performs an up-count when the level of the comparison result signal of the comparator 554 is, for example, "H" level, and a latch 556 that receives the count value of the counter 555 at a predetermined time interval and outputs an AD conversion output ADCOUT as pixel data based on the voltage of the vertical signal line (column read line) 543.

[0364] Similarly, through the above configuration, the read pixel signal can be converted into digital data and output.

[0365] Here, an example of the circuit configuration of the comparator 554 will be described.

[0366] Figure 50D is an explanatory diagram of a first configuration example of the comparator.

[0367] As Figure 50D shown, the comparator 554 includes a P-type MOS (PMOS) transistor PT11 and a P-type MOS (PMOS) transistor PT12, an N-type MOS (NMOS) transistor NT11 and an N-type MOS (NMOS) transistor NT12, capacitors C11 and C12, and switches SW11 and SW12.

[0368] In the above configuration, the source of the PMOS transistor PT11 and the source of the PMOS transistor PT12 are connected to the high-potential side power supply VDD.

[0369] The drain of the PMOS transistor PT11 is connected to the drain of the NMOS transistor NT11.

[0370] In addition, the drain and the gate of the PMOS transistor PT11 are connected, and the connection point is connected to the gate of the PMOS transistor 12.

[0371] The drain of the PMOS transistor PT12 is connected to the drain of the NMOS transistor NT12, and the connection point is the output terminal OUT1.

[0372] The source of the NMOS transistor NT11 and the source of the NMOS transistor NT12 are connected to each other, and the connection point is connected to the drain of the NMOS transistor NT13.

[0373] In addition, the drain of the NMOS transistor NT13 is connected to the low-potential side power supply GND.

[0374] The gate of NMOS transistor NT11 is connected to one terminal of capacitor C11, and the other terminal of capacitor C11 is the input terminal for the input RAMP signal.

[0375] In addition, the gate of NMOS transistor NT12 is connected to one terminal of capacitor C12, and the other terminal of capacitor C12 is the input terminal for the input pixel signal VSL.

[0376] Therefore, in comparator 554, PMOS transistors PT11 and PT12 form a current mirror circuit, and NMOS transistors NT11 and NT12 are used as a differential comparison circuit using NMOS transistor NT13 as a current source.

[0377] Figure 50E It is an explanatory diagram of the second structural example of the comparator.

[0378] As Figure 50E shown, comparator 554 includes PMOS transistors PT21 to PT23, NMOS transistors NT21 and NT22, capacitors C21 to C23, and switches SW21 and SW22.

[0379] In the above structure, the sources of NMOS transistor NT21 and NMOS transistor NT22 are connected to the low-potential side power supply GND.

[0380] The drain of NMOS transistor NT21 is connected to the gate of NMOS transistor NT22 and the drain of PMOS transistor PT22.

[0381] The drain of NMOS transistor NT22 is connected to the drain of PMOS transistor PT23 and the output terminal OUTl.

[0382] The source of PMOS transistor PT22 is connected to the sources of PMOS transistor PT23 and the drain of PMOS transistor PT21. The source of PMOS transistor PT21 is connected to the high-potential side power supply VDD.

[0383] NMOS transistors NT21 and NT22 form a current mirror circuit.

[0384] In addition, the gate of PMOS transistor PT22 is connected to one terminal of capacitor C21, and the other terminal of capacitor C21 is the input terminal for the input pixel signal VSL.

[0385] The gate of PMOS transistor PT22 is connected to one terminal of capacitor C22, and the other terminal of capacitor C22 is the input terminal for the input RAMP signal.

[0386] The capacitors C21 and C22 are used as input capacitors.

[0387] Therefore, the PMOS transistors PT21 to PT23 form a differential comparison circuit, and the entire circuit functions as a comparator.

[0388] Figure 50F It is an explanatory diagram of a third structural example of the comparator.

[0389] As Figure 50F shown, the comparator 554 includes a PMOS transistor PT31, an NMOS transistor NT31, an NMOS transistor NT32, capacitors C31 and C32, and a switch SW31.

[0390] In the above structure, the drain of the NMOS transistor NT31 is connected to the high-potential side power supply VDD, and the source of the NMOS transistor NT31 is connected to the source of the PMOS transistor PT31.

[0391] The drain of the PMOS transistor PT31 is connected to the drain of the NMOS transistor NT32 and the output terminal OUT1.

[0392] The source of the NMOS transistor NT32 is connected to the low-potential side power supply GND.

[0393] In addition, the switch SW31 is connected between the gate terminal and the drain terminal of the PMOS transistor PT31.

[0394] The gate of the PMOS transistor PT31 is connected to one terminal of the capacitor C31, and the other terminal of the capacitor C31 is the input terminal of the input pixel signal VSL.

[0395] The gate of the PMOS transistor PT31 is connected to one terminal of the capacitor C32, and the other terminal of the capacitor C32 is the input terminal of the input RAMP signal.

[0396] The capacitors C31 and C32 are used as input capacitors.

[0397] Therefore, a comparison circuit is formed by the voltage division ratio of the PMOS transistor PT31, the NMOS transistor NT31, and the NMOS transistor NT32, and the comparison circuit functions as the comparator of the entire circuit.

[0398] Next, the column signal processing unit of the third aspect will be described.

[0399] Figure 50G It is a schematic structural block diagram of the column signal processing unit of the third aspect.

[0400] The column signal processing unit 550 of the third aspect includes, for example, a RAMP generation circuit 557 that generates and outputs a RAMP waveform, a comparator 558 that compares the voltage of a pixel signal read through a vertical signal line (column read line) with the voltage of the RAMP waveform and outputs a comparison result signal, a counter 559 that performs an up-count when the level of the comparison result signal of the comparator 558 is, for example, an "H" level, and a latch 560 that receives the count value of the counter 559 at a predetermined interval and outputs an AD conversion output ADCOUT as pixel data based on the voltage of the vertical signal line (column read line) 543.

[0401] In the column signal processing unit 550 of the third aspect, the current generated by the load circuit LD is connected to the vertical signal line (column read line) 543 through the comparator 558; by the current flowing through the load circuit LD, a bias current is simultaneously applied to the amplification transistor AMP and the comparator 558 that constitute the pixel, and thus, the current consumption can be reduced.

[0402] Figure 50H It is an explanatory diagram of a structural example of the comparator of the third aspect.

[0403] As Figure 50H shown, the comparator 558 includes a PMOS transistor PT41, a capacitor C41, a switch SW41, and a load circuit LD.

[0404] In the above structure, the source of the PMOS transistor PT41 is an input terminal for inputting the pixel signal VSL, and the drain of the PMOS transistor PT41 is connected to the load circuit LD and the output terminal OUTl.

[0405] In addition, the switch SW41 is connected between the gate terminal and the drain terminal of the PMOS transistor PT41.

[0406] The gate of the PMOS transistor PT41 is connected to one terminal of the capacitor C41, and the other terminal of the capacitor C41 is an input terminal for inputting the RAMP signal.

[0407] The capacitor C41 serves as an input capacitor.

[0408] Therefore, a comparison circuit that outputs an output signal according to the gate-source voltage of the PMOS transistor PT41 is constituted, and the entire circuit serves as a comparator.

[0409] Next, the column signal processing unit of the fourth aspect will be described.

[0410] Figure 50I It is a schematic structural block diagram of the column signal processing unit of the fourth aspect.

[0411] The column signal processing unit 550 of the fourth aspect includes a load circuit LD, a pre-stage circuit 561 that connects the current generated by the load circuit LD to the vertical signal line (column read line) 543, a reference signal generation unit 562 configured as a constant voltage source, for example, and an AD converter 563 that performs AD conversion based on the reference signal input from the reference signal generation unit 562.

[0412] Here, an example of the configuration of the pre-stage circuit 561 will be described.

[0413] Figure 50J It is an explanatory diagram of an example of the configuration of the pre-stage circuit.

[0414] As Figure 50J shown, the pre-stage circuit 561 includes a PMOS transistor PT51, capacitors C51 and C52, and a load circuit LD.

[0415] In the above configuration, the source of the PMOS transistor PT51 is the input terminal for inputting the pixel signal VSL, and the drain of the PMOS transistor PT51 is connected to the load circuit LD and the output terminal OUTl.

[0416] In addition, the capacitor C52 is connected between the gate terminal and the drain terminal of the PMOS transistor PT51. The capacitor C52 serves as a feedback capacitor.

[0417] In addition, the capacitor C51 serves as a reference capacitor. One terminal of the capacitor C51 is connected to the gate of the PMOS transistor PT51, and the other terminal of the capacitor C51 is connected to the low-potential side power supply GND.

[0418] The pre-stage circuit 561 is configured as a current reuse column amplifier (CRCA).

[0419] According to the above configuration, the gate-source voltage of the PMOS transistor PT51 fluctuates according to the pixel signal VSL input to the source of the PMOS transistor PT51, and the drain current of the PMOS transistor PT51 is changed. The output voltage Vout corresponding to the drain current is output from the output terminal OUT1 through the drain of the PMOS transistor PT51.

[0420] As described above, the pre-stage circuit 561 serves as a comparison circuit that effectively outputs an output signal according to the pixel signal VSL, and the entire circuit serves as an amplifier.

[0421] Figure 51It is a schematic cross-sectional view showing an example of the stacked structure of the first substrate 100 and the second substrate 200 of the 3-1 embodiment. The first substrate 100 includes a photodiode PD, a transfer transistor TR, and a floating diffusion portion FD. The pixel circuit 210B on the second substrate 200 includes a reset transistor RST, an amplifying transistor AMP, a selection transistor SEL, and an FD wiring line FDL. The wiring layer 100T including a plurality of layers (M1 to M3) on the first substrate 100 and the wiring layer 200T including a plurality of layers (MP to M1) on the second substrate 200 are connected by a copper-copper junction CC.

[0422] The wiring layer 100T and the wiring layer 200T penetrate from the first substrate 100 to the second substrate 200, and an FD wiring line FDL that connects the floating diffusion portion FD of each pixel 541 on the first substrate 100 to the amplifying transistor AMP in the pixel circuit 210B on the second substrate 200 is arranged.

[0423] The amplifying transistor AMP for each pixel 541 of the independent p-well layer 251 on the second substrate 200 is electrically isolated from the common p-well layer 250 by a full trench T7. The gate of the amplifying transistor AMP is connected to the FD wiring line FDL, the drain of the amplifying transistor AMP is connected to the independent p-well layer 251, and the source of the amplifying transistor AMP is connected to the drain of the selection transistor SEL. In addition, the source of the amplifying transistor AMP is electrically connected to a shielding wiring line SL2 that extends in parallel with the FD wiring line FDL and is connected to each layer in the wiring layer 100T and the wiring layer 200T.

[0424] The shielding wiring line SL2 is a wiring line for the source potential of the amplifying transistor AMP (= the back gate potential of the amplifying transistor AMP). The shielding wiring line SL2 is arranged to cover the FD wiring line FDL. The shielding wiring line SL2 is arranged such that the coupling capacitance between the floating diffusion portion FD and the source of the amplifying transistor AMP is large, and the coupling capacitance between the floating diffusion portion FD and the wiring lines other than the floating diffusion portion FD is as small as possible. The shielding wiring line SL2 extends from the wiring layer 200T to the wiring layer 100T through the junction CC between the wiring layer 100T of the first substrate 100 and the wiring layer 200T of the second substrate 200, and is arranged to cover the FD wiring line FDL.

[0425] Since the independent p-well layer 251 is connected to the source of the amplifying transistor AMP, the potential of the independent p-well layer 251 changes with the source potential of the amplifying transistor AMP. That is, since the back gate and the source potential of the amplifying transistor AMP have the same potential, the gain of the source follower circuit becomes 1. The gate potential amplitude and the source potential amplitude of the amplifying transistor AMP become equal. That is, the potential of the shielding wiring SL2 also changes with the change amount of the potential of the floating diffusion portion FD of the FD wiring FDL. Therefore, no charge transfer occurs between the FD wiring FDL and the shielding wiring SL2, and the capacitance value between the FD wiring FDL and the shielding wiring SL2 is reduced. Therefore, even if the coupling between the FD wiring FDL and the shielding wiring SL2 is large, it can be ignored as the capacitance of the floating diffusion portion FD during the actual read operation. Then, since the above arrangement makes the coupling between the FD wiring FDL and other wirings as small as possible, the capacitance of the floating diffusion portion FD becomes a small value. That is, since the parasitic capacitance of the floating diffusion portion FD capacitance is reduced, the source follower output voltage Vsf can be increased.

[0426] In addition, since the shielding wiring SL2 is arranged between the FD wirings FDL of adjacent pixels 541, each FD wiring FDL can be shielded by the shielding wiring SL2. Therefore, the occurrence of crosstalk between adjacent FD wirings FDL can be suppressed.

[0427] If the periphery of the FD wiring FDL is shielded by the potential of this node, the FD wiring follows with the same amplitude as the potential of the floating diffusion portion FD, making the wiring capacitance appear as zero, and thus the FD capacitance can be reduced.

[0428] In a state where the independent p-well layer 251 of the amplifying transistor AMP for each pixel 541 is isolated by the full trench T7, the source of the amplifying transistor AMP and the independent p-well layer 251 are connected to have the same potential. Therefore, the substrate bias effect is eliminated, and the gain of the potential amplitude of the floating diffusion portion FD and the source potential amplitude of the amplifying transistor AMP is set to 1.

[0429] In order to cover the periphery of the FD wiring FDL with the shielding wiring SL2 that extracts the source potential of the amplifying transistor AMP, the wiring connected to the floating diffusion portion FD moves with the same amplitude as the floating diffusion portion FD. Therefore, since the wiring coupling capacitance appears as zero, the floating diffusion portion FD capacitance can be reduced to improve the charge-voltage conversion efficiency.

[0430] Figure 52It is a schematic diagram showing an example of the planar structure of the pixel circuit 210B. In the pixel circuit 210B, when the common p-well layer 250 and the independent p-well layer 251 are electrically isolated by the full trench T7, a reset transistor RST and a selection transistor SEL are arranged in the common p-well layer 250, and an amplification transistor AMP is arranged in the independent p-well layer 251. Note that the common p-well layer 250 of the reset transistor RST and the selection transistor SEL is fixed to the GND potential.

[0431] Figure 53 is a schematic diagram showing an example of the planar structure in which the FD wiring FDL and the shielding wiring SL2 overlap the front surface of the Figure 52 pixel circuit 210B shown. The FD wiring FDL electrically connects the floating diffusion part FD in the pixel 541 to the gate of the amplification transistor AMP and the source of the reset transistor RST. In addition, the shielding wiring SL2 electrically connects the source of the amplification transistor AMP to the drain of the selection transistor SEL and electrically connects the independent p-well layer 251 to the source of the amplification transistor AMP. The shielding wiring SL2 electrically connected to the source potential of the amplification transistor AMP is arranged to cover the periphery of the FD wiring FDL and is laid out to increase the coupling between them.

[0432] <10.3.2 Operation and Effects of the Third-1 Embodiment>

[0433] In the imaging device 1, the common p-well layer 250 and the independent p-well layer 251 of the amplification transistor AMP are electrically isolated from each other, and the FD wiring FDL is shielded by the shielding wiring SL2 that connects the gate of the amplification transistor AMP to the source of the amplification transistor AMP. That is, by connecting the source of the amplification transistor AMP to the independent p-well layer 251 of the amplification transistor AMP to have the same potential, the substrate bias effect is eliminated, and the gain of the floating diffusion part FD amplitude and the source amplitude of the amplification transistor AMP is set to 1. In addition, by arranging the shielding wiring SL2 that extracts the source potential of the amplification transistor AMP around the FD wiring FDL, the wiring connected to the floating diffusion part FD moves with the same amplitude as the floating diffusion part FD. Therefore, since the wiring coupling capacitance is reduced, the FD capacitance is reduced, thereby improving the charge-voltage conversion efficiency.

[0434] That is, in the imaging device 1, the capacitance of the FD capacitor due to the parasitic resistance of the FD wiring FDL is reduced, thereby improving the charge-voltage conversion efficiency. In addition, crosstalk between adjacent floating diffusion parts FD can be suppressed by the shielding wiring SL2.

[0435] Note that in the 3-1 Embodiment, an example of a structure in which full trench isolation is used as a p-well layer for separately isolating the amplification transistor AMP has been described, but the present invention is not limited thereto, and other methods may be adopted as long as the p-well layer can be separately isolated.

[0436] In the FD wiring FDL that connects the amplification transistor AMP in the second substrate 200 to the floating diffusion portion FD in the first substrate 100, the portion of the FD wiring FDL passing through the second substrate 200 and the first substrate 100 is shielded by the shield wiring SL2. Inside the FD wiring FDL, the portion of the FD wiring FDL passing through the wiring layer 100T of the first substrate 100 and the wiring layer 200T of the second substrate 200 is shielded. However, the shield wiring SL2 can shield the portion of the FD wiring FDL in the FD wiring FDL that passes through the wiring layer 200T of the second substrate 200, and the following describes its embodiment as the 3-2 Embodiment.

[0437] <10.4 Specific Example of the 3-2 Embodiment>

[0438] <10.4.1 Structure of the 3-2 Embodiment>

[0439] Figure 54 FIG. is a schematic cross-sectional view showing an example of the stacked structure of the first substrate 100 and the second substrate 200 of the 3-2 Embodiment. The 3-2 Embodiment is an example of a case where, for example, when reducing the pixel size, the number of arrangements of the joint CC between the wiring layer 100T and the wiring layer 200T is limited. The wiring layer 100T and the wiring layer 200T have the FD wiring FDL penetrating from the first substrate 100 side to the second substrate 200. The FD wiring FDL electrically connects the floating diffusion portion FD of the first substrate 100 to the gate of the amplification transistor AMP of the pixel circuit 210 of the second substrate 200. The shield wiring SL2 shields the portion of the FD wiring FDL that passes through the wiring layer 200T of the second substrate 200 in the FD wiring FDL.

[0440] <10.4.2 Functions and Effects of the 3-2 Embodiment>

[0441] In the case where the number of joints CC is limited due to the reduction in the size of pixel 541, the shielding wiring SL2 is limited to shielding the FD wiring FDL in the FD wiring layer 200T on the second substrate 200 side. For example, in the case where only one joint CC can be arranged in one pixel, the FD wiring FDL can penetrate the wiring layer 100T and the wiring layer 200T to connect the wiring layer 100T to the wiring layer 200T, but the source potential of the amplification transistor AMP cannot extend to the wiring layer 100T on the first substrate 100 side. In this case, the shielding wiring SL2 is arranged to cover only the FD wiring FDL in the wiring layer 200T of the second substrate 200. Therefore, the effect of reducing the floating diffusion portion FD capacitance of the wiring layer 100T on the first substrate side cannot be obtained, and the FD capacitance slightly increases compared to the FD capacitance of the 3-1st embodiment. However, the effect of reducing the FD capacitance of the wiring layer 200T on the second substrate 200 side can be obtained. It is also possible to cope with the reduction in pixels.

[0442] <10.5 Specific Example of the 3-3rd Embodiment>

[0443] <10.5.1 Structure of the 3-3rd Embodiment>

[0444] Figure 55 is an equivalent circuit diagram showing a structural example of a plurality of pixel circuits 210C and 210D of the second substrate 200 of the 3-3rd embodiment. The pixel circuit 210C electrically isolates the independent p-well layer 251A from the common p-well layer 250 through the full trench T8. A group of amplification transistors AMP of a plurality of pixel circuits adjacent in the column direction are arranged in the independent p-well layer 251A, and a group of reset transistors RST and selection transistors SEL adjacent in the column direction are arranged in the common p-well layer 250. In addition, the pixel circuit 210D is located in a different row from the pixel circuit 210C. Then, the pixel circuit 210D electrically isolates the independent p-well layer 251A from the common p-well layer 250 through the full trench T8. A group of amplification transistors AMP of a plurality of pixel circuits adjacent in the column direction are arranged in the independent p-well layer 251A, and a group of reset transistors RST and selection transistors SEL adjacent in the column direction are arranged in the common p-well layer 250.

[0445] The amplifying transistors AMP to be read simultaneously are amplifying transistors AMP adjacent in the row direction. Therefore, when the pixels 541 are read sequentially in a row-by-row manner, when the amplifying transistor AMP reads the pixel signal, the pixel signals of the amplifying transistors AMP adjacent in the column direction are not read simultaneously. Therefore, while the independent p-well layers 251A of the amplifying transistors AMP adjacent in the row direction are isolated, the independent p-well layers 251A of the amplifying transistors AMP adjacent in the column direction are shared. That is, the well layer potentials of the groups of amplifying transistors AMP adjacent in the column direction are shared, and the well layer potentials of the groups of amplifying transistors AMP adjacent in the column direction in the next row are also shared.

[0446] Therefore, when the amplifying transistor AMP of the pixel circuit 210C1 reads the pixel signal, the well layer potentials of the groups of amplifying transistors AMP of the pixel circuits 210C2 and 210C3 in that column have the same potential as the source potential of the amplifying transistor AMP of the pixel circuit 210C1. In addition, the well layer potentials of the amplifying transistors AMP of the pixel circuits 210C2 and 210C3 also have the same potential as the source potential of the amplifying transistor AMP of the pixel circuit 210C1. However, since the amplifying transistors AMP of the other pixel circuits 210C2 and 210C3 adjacent in the column direction are in a non-reading period, the selection transistors SEL are turned off and do not operate as amplifying circuits, so there is no particular impact.

[0447] For example, when the pixels 541 are read sequentially in a row-by-row manner, it can be said that the amplifying transistor AMP of the pixel circuit 210D1 adjacent in the row direction to the amplifying transistor AMP of the pixel circuit 210C1 is read simultaneously. Therefore, the well layer potentials of the amplifying transistor AMP of the pixel circuit 210C1 and the amplifying transistor AMP of the pixel circuit 210D1 adjacent in the row direction have different potentials according to the pixel signal amount. Therefore, it is necessary to isolate the two well layers. That is, it is necessary to isolate the well layers of the pixels 541 to be read simultaneously, but there is no problem even if the well layers of the pixels 541 that are not read simultaneously are shared.

[0448] <10.5.2 Operation and Effects of the 3-3 Embodiment>

[0449] Therefore, even when it is not possible to isolate the p-well layers independently for each pixel due to a reduction in the pixels 541 or the like, the same effects as those of the 3-2 embodiment can be obtained by isolating the p-well layers only in the row direction.

[0450] <10.6 Specific Example of the 3-4 Embodiment>

[0451] <10.6.1 Structure of the 3-4 Embodiment>

[0452] For example, the imaging device of the 3rd - 4th embodiments is a pixel imaging device including a charge holding unit for global shutter. The global shutter mode is generally a mode that performs global exposure in which the exposure of all pixels starts simultaneously and ends simultaneously. Here, all pixels refer to all pixels in the portion that appears in the image and do not include pseudo - pixels, etc. In addition, if the time difference and distortion of the image are small enough not to cause problems, as an alternative to performing global exposure on all pixels simultaneously, the global shutter mode also includes a mode in which the area where global exposure is performed is moved while performing global exposure in units of multiple rows (e.g., dozens of rows). In addition, as an alternative to all pixels in the portion that appears in the image, the global shutter mode also includes a mode in which global exposure is performed on the pixels in a predetermined area.

[0453] Figure 56 It is an equivalent circuit diagram showing a configuration example of the pixel sharing unit 400 of the global shutter mode imaging device of the 3rd - 4th embodiments. The pixel sharing unit 400 of the global shutter mode imaging device has a pixel 410 and a pixel circuit 420. The pixel 410 has a photodiode 411, a charge holding unit 412, a transfer transistor TR413, and an overflow transistor 414. In addition, the pixel circuit 420 has a reset transistor RST42, an amplification transistor AMP42, a selection transistor SEL42, and a floating diffusion portion FD42.

[0454] The reset transistor RST42 has a drain connected to the power supply RST and a source connected to the floating diffusion portion FD42. The reset transistor RST42 initializes (i.e., resets) the floating diffusion portion FD42 according to the drive signal applied to its gate. For example, when the drive signal turns on the reset transistor RST42, the potential of the floating diffusion portion FD42 is reset to the voltage level of the power supply RST. That is, the floating diffusion portion FD42 is initialized.

[0455] The floating diffusion portion FD42 converts the charge transferred from the photodiode PD through the transfer transistor 413 and the charge holding unit 412 into an electrical signal (e.g., a voltage signal) and outputs the electrical signal. The reset transistor RST42 is connected to the floating diffusion portion FD42, and the vertical signal line VSL is connected to the floating diffusion portion FD42 through the amplification transistor AMP42 and the selection transistor SEL42.

[0456] The amplifying transistor AMP42 outputs an electrical signal according to the potential of the floating diffusion section FD42. The amplifying transistor AMP42 forms a source follower circuit together with a constant current source provided in the column signal processing unit, for example. When the pixel is selected, the selection transistor SEL42 is turned on, and the electrical signal from the floating diffusion section FD42 via the amplifying transistor AMP42 is output to the column signal processing unit through the vertical signal line VSL.

[0457] In the pixel common unit 400 of this global shutter mode imaging device, pixels 410 are formed on the first substrate 100, pixel circuits 420 are formed on the second substrate 200, and the pixels 410 and the pixel circuits 420 are connected by the FD wiring FDL.

[0458] The second substrate 200 includes a common p-well layer shared by all pixels and independent p-well layers for respective amplifying transistors AMP42, and the common p-well layer and the independent p-well layers are electrically isolated by full trenches (FTI). In the common p-well layer, a reset transistor RST42 and a selection transistor SEL42 of each pixel circuit 420 are formed. Since the common p-well layer is connected to the GND potential, the back gates of the reset transistor RST42 and the selection transistor SEL42 are fixed to the GND potential.

[0459] On the other hand, in the independent p-well layer, an amplifying transistor AMP42 of the pixel circuit 420 is formed. Since the independent p-well layer is connected to the source of the amplifying transistor AMP42, the potential of the independent p-well layer changes with the source potential of the amplifying transistor AMP42. That is, since the back gate and the source potential of the amplifying transistor AMP42 have the same potential, the gain of the source follower circuit becomes 1.

[0460] That is, the gate potential amplitude of the amplifying transistor AMP42 is equal to the source potential amplitude. That is, the potential of the shielding wiring SL4 also changes with the change amount of the FD potential of the FD wiring FDL. Therefore, no charge transfer occurs between the FD wiring FDL and the shielding wiring SL4, and the capacitance value between the FD wiring FDL and the shielding wiring SL4 is reduced. Therefore, even if the coupling between the FD wiring FDL and the shielding wiring SL4 is large, it can be ignored as the capacitance of the floating diffusion section FD during the actual reading operation. Then, since the above arrangement makes the coupling between the FD wiring FDL and other wirings as small as possible, the FD capacitance becomes a small value. That is, since the parasitic capacitance of the FD capacitance is reduced, the source follower output voltage Vsf can be increased.

[0461] <10.6.2 Operation and Effects of the Third - Fourth Embodiments>

[0462] In the pixel sharing unit 400 of the global shutter mode imaging device according to the third to fourth embodiments, the common p-well layer of the amplification transistor AMP42 is electrically isolated from the independent p-well layer. Further, in the pixel sharing unit 400, the FD wiring FDL is shielded by a shielding wiring SL4 that connects the gate of the amplification transistor AMP42 to the source of the amplification transistor AMP42. That is, by connecting the source of the amplification transistor AMP42 and the independent p-well layer of the amplification transistor AMP42 to have the same potential, the substrate bias effect is eliminated, and the gain of the FD amplitude and the source amplitude of the amplification transistor AMP42 is set to 1. Further, the periphery of the FD wiring FDL is shielded by the shielding wiring SL4 that leads out the source potential of the amplification transistor AMP42, so that the wiring connected to the floating diffusion section FD moves with the same amplitude as the floating diffusion section FD. Therefore, since the wiring coupling capacitance is reduced, the FD capacitance is reduced, thereby improving the charge-voltage conversion efficiency.

[0463] That is, in the pixel sharing unit 400 in the global shutter mode imaging device, by suppressing an increase in the FD capacitance due to the parasitic resistance of the FD wiring FDL and improving the charge-voltage conversion efficiency, the S / N ratio of the pixel signal is improved. Further, crosstalk between adjacent floating diffusion sections FD can be suppressed by the shielding wiring SL4.

[0464] <10.7 Specific Example of the Third to Fifth Embodiments>

[0465] <10.7.1 Structure of the Third to Fifth Embodiments>

[0466] Figure 57 FIG. is an equivalent circuit diagram showing a structural example of a pixel sharing unit 400A of a storage retention type global shutter mode imaging device according to the third to fifth embodiments. The pixel sharing unit 400A includes pixels PX1 and PX4 and a pixel circuit 420A. The pixel PX1 includes a photodiode PD1, first to third transfer transistors TR1A to TR1C, a charge holding unit MEM1, a discharge transistor OFG1, a discharge unit OFD1, and a buffer BUF1. The first transfer transistor TR1A includes a transfer gate TRZ1, the second transfer transistor TR1B includes a transfer gate TRY1 and a transfer gate TRX1, and the third transfer transistor TR1C includes a transfer gate TRG1.

[0467] Similarly, pixel PX4 includes a photodiode PD4, first to third transfer transistors TR4A to TR4C, a charge holding unit MEM4, a discharge transistor OFG4, a discharge unit OFD4, and a buffer BUF4. The first transfer transistor TR4A includes a transfer gate TRZ4, the second transfer transistor TR4B includes a transfer gate TRY4 and a transfer gate TRX4, and the third transfer transistor TR4C includes a transfer gate TRG4.

[0468] In addition, pixel PX1 and pixel PX4 share pixel circuits 420A such as a power supply VDD1 and a power supply VDD2, a floating diffusion portion FD14, a reset transistor RST14, an amplification transistor AMP14, and a selection transistor SEL14.

[0469] In this example, the first to third transfer transistors TR1A to TR1C and the first to third transfer transistors TR4A to TR4C are N-type MOS transistors. In addition, the reset transistor RST14, the amplification transistor AMP14, and the selection transistor SEL14 are also N-type MOS transistors. Based on the drive control of the system control unit, the vertical drive unit and the horizontal drive unit supply drive signals to the gates of the first to third transfer transistors TR1A to TR1C and the first to third transfer transistors TR4A to TR4C. In addition, based on the drive control of the system control unit, the vertical drive unit and the horizontal drive unit supply drive signals to the respective gates of the reset transistor RST14, the amplification transistor AMP14, and the selection transistor SEL14. These drive signals are pulse signals, where the high level state is the active state (conductive state), and the low level state is the non-active state (cut-off state). Note that hereinafter, setting the drive signal to the active state is also referred to as a conductive drive signal, and setting the drive signal to the non-active state is also referred to as a cut-off drive signal.

[0470] The photodiode PD1 and the photodiode PD4 are, for example, photoelectric conversion elements including PN junction photodiodes, and are configured to receive light from a subject, generate charges by photoelectric conversion according to the received light amount, and accumulate the charges.

[0471] The charge holding unit MEMl and the charge holding unit MEM4 are respectively provided between the photodiode PDl and the floating diffusion portion FD14 and between the photodiode PD4 and the floating diffusion portion FD14. In addition, the charge holding unit MEM1 and the charge holding unit MEM4 are regions that temporarily hold the charges generated and accumulated in the photodiode PD1 and the photodiode PD4 until the charges are transferred to the floating diffusion portion FD14 to achieve the global shutter function.

[0472] The first transfer transistor TR1A and the second transfer transistor TR1B are arranged in sequence between the photodiode PD1 and the charge holding unit MEM1. The third transfer transistor TR1C is arranged between the charge holding unit MEM1 and the floating diffusion section FD14. The first transfer transistor TR1A and the second transfer transistor TR1B are configured to transfer the charge accumulated in the photodiode PD1 to the charge holding unit MEM1 according to a drive signal applied to their gates.

[0473] Similarly, the first transfer transistor TR4A and the second transfer transistor TR4B are arranged in sequence between the photodiode PD4 and the charge holding unit MEM4. The third transfer transistor TR4C is arranged between the charge holding unit MEM4 and the floating diffusion section FD14. The first transfer transistor TR4A and the second transfer transistor TR4B are configured to transfer the charge accumulated in the photodiode PD4 to the charge holding unit MEM4 according to a drive signal applied to their gates.

[0474] The third transfer transistor TR1C and the third transfer transistor TR4C transfer the charge temporarily held in the charge holding unit MEMl and the charge holding unit MEM4 to the floating diffusion section FD14 according to a drive signal applied to their gates.

[0475] For example, in the pixels PX1 and PX4, it is assumed that the second transfer transistors TR1B and TR4B are turned off and the third transfer transistors TR1C and TR4C are turned on. In this case, the charges respectively held in the charge holding unit MEM1 and the charge holding unit MEM4 are transferred to the floating diffusion section FD14 through the third transfer transistor TR1C and the third transfer transistor TR4C.

[0476] The buffers BUF1 and BUF4 are charge accumulation regions formed between the first transfer transistor TR1A and the second transfer transistor TR1B respectively. The reset transistor RST14 has a drain connected to the power supply VDD1 and a source connected to the floating diffusion section FD14. The reset transistor RST14 initializes (i.e., resets) the floating diffusion section FD14 according to a drive signal applied to its gate. For example, when the drive signal turns on the reset transistor RST14, the potential of the floating diffusion section FD14 is reset to the voltage level of the power supply VDD1. That is, the floating diffusion section FD14 is initialized.

[0477] The floating diffusion section FD14 converts the charge transferred from the photodiodes PD1 and PD4 through the first to third transfer transistors TR1A to TR1C and TR4A to TR4C and the charge holding units MEM1 and MEM4 into an electrical signal (e.g., a voltage signal) and outputs the electrical signal. The reset transistor RST14 is connected to the floating diffusion section FD14, and the vertical signal line VSL117 is connected to the floating diffusion section FD14 through the amplification transistor AMP14 and the selection transistor SEL14.

[0478] The amplification transistor AMP14 outputs an electrical signal according to the potential of the floating diffusion section FD14. The amplification transistor AMP14 constitutes a source follower circuit together with a constant current source provided in the column signal processing unit, for example. When the pixel PX is selected, the selection transistor SEL14 is turned on, and the electrical signal from the floating diffusion section FD14 via the amplification transistor AMP14 is output to the column signal processing unit through the vertical signal line VSL117.

[0479] In addition to the floating diffusion section FD14 which is respectively the charge transfer destination of the photodiodes PD1 and PD4, the pixels PX1 and PX4 further include a discharge unit OFD1 and a discharge unit OFD4. The discharge transistor OFG1 is arranged between the first transfer transistor TR1A and the second transfer transistor TR1B, and the discharge transistor OFG4 is arranged between the first transfer transistor TR4A and the second transfer transistor TR4B.

[0480] The discharge transistor OFG1 has a drain connected to the discharge unit OFD1 and a source connected to the wiring connecting the first transfer transistor TR1A to the second transfer transistor TR1B. Similarly, the discharge transistor OFG4 has a drain connected to the discharge unit OFD4 and a source connected to the wiring connecting the first transfer transistor TR4A to the second transfer transistor TR4B. The discharge transistors OFG1 and OFG4 initialize (i.e., reset) the photodiodes PD1 and PD4 according to the drive signals applied to their respective gates. Resetting the photodiodes PD1 and PD4 means depleting the photodiodes PD1 and PD4.

[0481] In addition, the discharge transistors OFG1 and OFG4 respectively form overflow channels and discharge the charge overflowing from the photodiodes PD1 and PD4 to the discharge units OFD1 and OFD4, respectively. As described above, in the pixels PX1 and PX4 of the present embodiment, the discharge transistors OFG1 and OFG4 can directly reset the photodiodes PD1 and PD4.

[0482] The pixel PXl, pixel PX4, and floating diffusion portion FD14 are arranged on the first substrate 100, and pixel circuits 420A such as a reset transistor RST14, an amplification transistor AMP14, and a selection transistor SEL14 are arranged on the second substrate 200. In addition, the floating diffusion portion FD of the first substrate 100 and the gate of the amplification transistor AMP14 of the second substrate 200 are connected by an FD wiring FDL.

[0483] The second substrate 200 includes a common p-well layer shared by all pixels and independent p-well layers for the respective amplification transistors AMP14 of the pixels, and the common p-well layer and the independent p-well layers are electrically isolated by full trenches (FTI). In the common p-well layer, a reset transistor RST14 and a selection transistor SEL14 of each pixel circuit 420 are formed. Since the common p-well layer is connected to the GND potential, the back gates of the reset transistor RST14 and the selection transistor SEL14 are fixed to the GND potential.

[0484] On the other hand, in the independent p-well layer, an amplification transistor AMP14 of the pixel circuit 420 is formed. Since the independent p-well layer is connected to the source of the amplification transistor AMP14, the potential of the independent p-well layer changes with the source potential of the amplification transistor AMP14. That is, since the back gate and the source potential of the amplification transistor AMP14 have the same potential, the gain of the source follower circuit becomes 1.

[0485] That is, the amplitude of the gate potential of the amplification transistor AMP14 is equal to the amplitude of the source potential. That is, the potential of the shielding wiring SL5 also changes with the change amount of the FD potential of the FD wiring FDL. Therefore, no charge transfer occurs between the FD wiring FDL and the shielding wiring SL5, and the capacitance value between the FD wiring FDL and the shielding wiring SL5 is reduced. Therefore, even if the coupling between the FD wiring FDL and the shielding wiring SL5 is large, it can be ignored as the capacitance of the floating diffusion portion FD during the actual read operation. Then, since the above arrangement makes the coupling between the FD wiring FDL and other wirings as small as possible, the FD capacitance becomes a small value. That is, since the parasitic capacitance of the FD capacitance is reduced, the source follower output voltage Vsf can be increased.

[0486] <10.7.2 Operations and Effects of the 3rd - 5th Embodiments>

[0487] In the pixel sharing unit 400A of the storage retention type global shutter mode imaging device according to the third to fifth embodiments, the common p-well layer is electrically isolated from the independent p-well layer of the amplification transistor AMP. In the pixel sharing unit 400A, the FD wiring FDL is shielded by the shielding wiring SL5 that connects the gate of the amplification transistor AMP14 to the source of the amplification transistor AMP14. That is, by connecting the source of the amplification transistor AMP14 to the independent p-well layer of the amplification transistor AMP14 to have the same potential, the substrate bias effect is eliminated, and the gain of the FD amplitude and the source amplitude of the amplification transistor AMP14 is set to 1. The periphery of the FD wiring FDL is shielded by the source potential shielding wiring SL5 of the amplification transistor AMP14, so that the wiring connected to the floating diffusion portion FD14 moves with the same amplitude as the floating diffusion portion FD14. Therefore, since the wiring coupling capacitance is reduced, the FD capacitance is reduced, thereby improving the charge-voltage conversion efficiency.

[0488] That is, in the storage retention type global shutter mode imaging device, by suppressing an increase in the FD capacitance due to the parasitic resistance of the FD wiring FDL while improving the charge-voltage conversion efficiency, the S / N of the pixel signal is improved. In addition, crosstalk between adjacent floating diffusion portions FD14 can be suppressed by the shielding wiring SL5.

[0489] In the embodiments and variations of the present invention, examples of methods for forming the above-described layers, films, elements, etc. include physical vapor deposition (PVD) methods, CVD methods, etc. Examples of PVD methods include vacuum vapor deposition using resistance heating or high-frequency heating, electron beam (EB) vapor deposition, various sputtering methods (magnetron sputtering, RF-DC coupled bias sputtering, electron cyclotron resonance (ECR) sputtering, facing target sputtering, high-frequency sputtering, etc.), ion plating methods, laser ablation methods, and molecular beam epitaxy (MBE) methods, laser transfer methods, etc. Examples of CVD methods include plasma CVD methods, thermal CVD methods, MOCVD methods, and optical CVD methods. In addition, other methods include electroplating methods, electroless plating methods, and spin coating methods; immersion methods; casting methods; microcontact printing methods; drop casting methods; various printing methods such as screen printing methods, inkjet printing methods, offset printing methods, gravure printing methods, and flexographic printing methods; stamping methods; spraying methods; and various coating methods such as air coater methods, knife coater methods, bar coater methods, knife-over-roll coater methods, reverse roll coater methods, transfer roll coater methods, gravure coater methods, kiss coater methods, cast coater methods, spray coater methods, slot die coater methods, and calender coater methods. Examples of patterning methods for each layer include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet rays, lasers, etc. In addition, examples of planarization techniques include CMP methods, laser planarization methods, and reflow methods. That is, the imaging device 1 according to the embodiments and variations of the present invention can be easily and inexpensively manufactured using existing semiconductor device manufacturing processes.

[0490] In the above description, an example has been described in which the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST constituting the pixel circuit 210 of the second substrate 211 are formed on the same semiconductor substrate, but the second substrate 211 may be formed of a plurality of semiconductor substrates.

[0491] In this case, if the amplification transistor AMP is arranged at a position far from the floating diffusion portion, a capacitance is formed between the amplification transistor AMP and the floating diffusion portion, which may cause a decrease in conversion efficiency.

[0492] Therefore, preferably, among the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST, at least the amplification transistor AMP and the floating diffusion portion are formed on the same semiconductor substrate, and the remaining transistors are formed on other semiconductor substrates.

[0493] In this case, if the trench width W of the amplification transistor AMP can be increased, the noise can be reduced. Therefore, by adopting the above-described configuration in which the second substrate is formed of a plurality of semiconductors, the area that can be allocated to the amplification transistor AMP can be increased, and the noise can be reduced to improve the performance.

[0494] <11. Application Example>

[0495] Figure 58 An example of a schematic configuration of an imaging system 7 including the imaging device 1 according to the above-described embodiments and their modifications is shown.

[0496] For example, the imaging system 7 is an electronic device such as an imaging device (such as a digital camera or a video camera) or a portable terminal device such as a smart phone or a tablet terminal. The imaging system 7 includes, for example, the imaging device 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 according to the above-described embodiments and their modifications. In the imaging system 7, the imaging device 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via the bus 249.

[0497] The imaging device 1 according to the above-described embodiments and their modifications outputs image data based on incident light. The DSP circuit 243 is a signal processing circuit that processes signals (image data) output from the imaging device 1 according to the above-described embodiments and their modifications. The frame memory 244 temporarily holds the image data processed by the DSP circuit 243 in units of frames. The display unit 245 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, and displays a moving image or a still image captured by the imaging device 1 according to the above-described embodiments and their modifications. The storage unit 246 records the image data of the moving image or the still image captured by the imaging device 1 according to the above-described embodiments and their modifications in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 7 according to user operations. The power supply unit 248 appropriately supplies various power supplies that serve as operation power supplies for the imaging device 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247 to these supply targets.

[0498] Next, the imaging process of the imaging system 7 will be described.

[0499] Figure 59 An example of a flowchart of the imaging operation of the imaging system 7 is shown. The user instructs the start of imaging by operating the operation unit 247 (step S101). Then, the operation unit 247 sends an imaging command to the imaging device 1 (step S102). When the imaging command is received, the imaging device 1 (specifically, the system control circuit) performs imaging by a predetermined imaging method (step S103).

[0500] The imaging device 1 outputs the image data obtained by imaging to the DSP circuit 243. Here, the image data is data for all pixels of the pixel signals generated based on the charges temporarily held in the floating diffusion section FD. The DSP circuit 243 performs predetermined signal processing (for example, noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 causes the frame memory 244 to hold the image data that has undergone the predetermined signal processing, and the frame memory 244 causes the storage unit 246 to store the image data (step S105). In this way, imaging of the imaging system 7 is performed.

[0501] In this application example, the imaging device 1 according to the above-described embodiments and their modified examples is applied to the imaging system 7. Therefore, since the imaging device 1 can be reduced in size or has high definition, a small or high-definition imaging system 7 can be provided.

[0502] <12. Application Example>

[0503] [First Application Example]

[0504] The technology according to the present invention (this technology) can be applied to various products. For example, the technology according to the present invention can be implemented as a device mounted on any type of moving object such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, and a robot.

[0505] Figure 60 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present invention can be applied.

[0506] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In Figure 60 the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, an audio-visual output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0507] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 serves as a control device for devices such as an internal combustion engine, a drive motor, etc. that generate the driving force of the vehicle, a driving force transmission mechanism that transmits the driving force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, a braking device that generates the vehicle's braking force, etc.

[0508] The body system control unit 12020 controls the operation of various devices installed on the vehicle according to various programs. For example, the body system control unit 12020 serves as a control device for a keyless entry system, a smart key system, an electric window device, or various lights such as headlights, reverse lights, brake lights, flashers, and fog lights. In this case, radio waves emitted from a portable device that substitutes for a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the vehicle's door lock device, electric window device, or vehicle lights, etc.

[0509] The out-of-vehicle information detection unit 12030 detects information about the outside of the vehicle on which the vehicle control system 12000 is installed. For example, the out-of-vehicle information detection unit 12030 is connected to the imaging unit 12031. The out-of-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the out-of-vehicle information detection unit 12030 can perform object detection processing such as for a person, a vehicle, an obstacle, a sign, text on the road surface, etc., or distance detection processing.

[0510] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as ranging information. In addition, the light received by the imaging unit 12031 can be visible light, or invisible light such as infrared light.

[0511] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or can determine whether the driver is dozing off.

[0512] The microcomputer 12051 can calculate control target values for a driving force generation device, a steering mechanism, or a braking device based on information about the inside or outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for functions aiming to implement an Advanced Driver Assistance System (ADAS), and the ADAS functions include collision avoidance or impact mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed holding driving, vehicle collision warning, vehicle lane departure warning, etc.

[0513] In addition, the microcomputer 12051 controls a driving force generation device, a steering mechanism, a braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so as to perform cooperative control such as autonomous driving in which the vehicle travels autonomously without relying on the driver's operation.

[0514] In addition, based on information about the outside of the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlamp by according to the positions of the vehicle ahead or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, so as to perform cooperative control such as switching from high beam to low beam for preventing glare.

[0515] The sound image output unit 12052 sends an output signal of at least one of sound or image to an output device capable of providing information notification visually or auditorily to the passengers of the vehicle or the outside of the vehicle. In Figure 60 the example, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown as output devices. The display unit 12062 can include at least one of an in-vehicle display and a head-up display, for example.

[0516] Figure 61 is a diagram showing an example of the installation position of the imaging unit 12031.

[0517] In Figure 61 it, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0518] The imaging units 12101, 12102, 12103, 12104, and 12105 are disposed, for example, at positions such as the front nose, side mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle of the vehicle 12100. The imaging unit 12101 disposed at the front nose and the imaging unit 12105 disposed at the upper part of the windshield inside the vehicle mainly acquire images of the front part of the vehicle 12100. The imaging units 12102 and 12103 disposed at the side mirrors mainly acquire images of the parts on both sides of the vehicle 12100. The imaging unit 12104 disposed on the rear bumper or the rear door mainly acquires images of the rear part of the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used to detect front vehicles, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0519] Figure 61 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 disposed at the front nose, the imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 disposed at the side mirrors, respectively, and the imaging range 12114 represents the imaging range of the imaging unit 12104 disposed on the rear bumper or the rear cover. For example, a bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0520] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0521] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 obtains the distance of each three-dimensional object in the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100), so that three-dimensional objects traveling along a direction substantially the same as that of the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h) can be extracted, and in particular, the closest three-dimensional object on the traveling path of the vehicle 12100 is taken as the preceding vehicle. In addition, the microcomputer 12051 can preset the inter-vehicle distance to be maintained from the preceding vehicle and can perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), and the like. As described above, cooperative control such as autonomous driving in which the vehicle can automatically travel without depending on the driver's operation can be performed.

[0522] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12501 can classify the three-dimensional object data regarding the three-dimensional object into a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, and other three-dimensional objects such as a utility pole, extract the three-dimensional object data, and use the three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 classifies the obstacles around the vehicle 12100 into obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to visually recognize. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 can perform assisted driving to avoid collision by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062 or by the drive system control unit 12010 performing forced deceleration or avoidance steering.

[0523] At least one of imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian exists in the images captured by imaging units 12101 to 12104. For example, such identification of a pedestrian is performed through the following steps: a step of extracting feature points in the images captured by imaging units 12101 to 12104 that are infrared cameras; and a step of performing pattern matching processing on a series of feature points representing an object contour to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by imaging units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 causes the display unit 12062 to superimpose and display a square contour line for emphasis on the identified pedestrian. In addition, the audio-visual output unit 12052 may cause the display unit 12062 to display an icon or the like representing the pedestrian at a required position.

[0524] Examples of a mobile body control system to which the technology according to the present invention can be applied have been described above. The technology according to the present invention can be applied to the imaging unit 12031 in the configuration as described above. Specifically, the imaging device 1 according to the above-described embodiments and their modifications can be applied to the imaging unit 12031. By applying the technology according to the present invention to the imaging unit 12031, an image with high definition and low noise can be obtained, and thus high-precision control can be performed in the mobile body control system by using the captured image.

[0525] [Second Application Example]

[0526] Figure 62 FIG. is an example showing a schematic configuration of an endoscopic surgery system to which the technology (this technology) according to the present invention can be applied.

[0527] Figure 62 FIG. shows a state in which an operator (doctor) 11131 performs surgery on a patient 11132 on a hospital bed 11133 using an endoscopic surgery system 11000. As shown in the drawing, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0528] The endoscope 11100 includes a lens barrel 11101, a region of which at a predetermined length from the distal end is inserted into the body cavity of a patient 11132, and a camera 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100, which is a so-called rigid endoscope configured to have a rigid lens barrel 11101, is shown, but the endoscope 11100 may be configured as a so-called flexible endoscope having a flexible lens barrel.

[0529] An opening portion in which an objective lens is installed is provided at the distal end of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided through an optical fiber extending inside the lens barrel 11101 to the distal end of the lens barrel and irradiated onto an observation target in the body cavity of the patient 11132 through the objective lens. Note that the endoscope 11100 may be a forward-view endoscope, a side-view endoscope, or a lateral-view endoscope.

[0530] An optical system and an imaging element are provided inside the camera 11102, and reflected light (observation light) from the observation target is focused on the imaging element by the optical system. The imaging element performs photoelectric conversion on the observation light and generates an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted as raw data to a camera control unit (CCU) 11201.

[0531] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and centrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives the image signal from the camera 11102 and performs various image processes for displaying an image based on the image signal on the image signal, such as a developing process (demosaicing process).

[0532] The display device 11202 displays an image based on the image signal that has been processed by the CCU 11201 under the control of the CCU 11201.

[0533] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED), etc., and supplies irradiation light for photographing a surgical site or the like to the endoscope 11100.

[0534] The input device 11204 is an input interface for the endoscope surgical system 11000. A user can input various types of information and instructions to the endoscope surgical system 11000 through the input device 11204. For example, the user inputs instructions or the like to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0535] The treatment tool control device 11205 controls the driving of the energy treatment device 11112 for cauterizing and incising tissues, sealing blood vessels, etc. The pneumoperitoneum device 11206 sends gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity, ensuring the visual field of the endoscope 11100 and the working space for the operator. The recorder 11207 is a device capable of recording various types of information related to the operation. The printer 11208 is a device capable of printing various types of information related to the operation in various forms (such as text, images, or graphics, etc.).

[0536] For example, the light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical area may include an LED, a laser light source, or a white light source including a combination thereof. In the case where the white light source includes a combination of RGB laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted in the light source device 11203. In addition, in this case, by irradiating the observation target with the laser from each RGB laser light source in a time-division manner and controlling the driving of the imaging element of the camera 11102 in synchronization with the irradiation timing, it is also possible to capture images corresponding to RGB in a time-division manner. According to this method, even without providing a color filter for the imaging element, a color image can be obtained.

[0537] In addition, the driving of the light source device 11203 can be controlled so that the intensity of the output light changes every predetermined time. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity to acquire pictures and synchronize images in a time-division manner, a high-dynamic-range image without so-called underexposed shadows and overexposed highlights can be generated.

[0538] In addition, the light source device 11203 can be configured to be able to provide light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow-band imaging is performed in which a predetermined tissue (such as blood vessels in the mucosal surface layer, etc.) is imaged with high contrast by using the wavelength dependence of light absorption in human tissues and emitting light in a narrower wavelength band than the irradiation light (i.e., white light) during normal observation. Or, in special light observation, fluorescence observation for obtaining an image from fluorescence generated by irradiation with excitation light can be performed. In fluorescence observation, for example, body tissue can be irradiated with excitation light to observe the fluorescence from the body tissue (autofluorescence observation), or a reagent (such as indocyanine green (ICG)) can be locally injected into the human tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be irradiated onto the human tissue to obtain a fluorescence image. The light source device 11203 can be configured to be able to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0539] Figure 63 shows an example of the functional configuration of the camera 11102 and the CCU 11201 shown Figure 62 in the block diagram.

[0540] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected to each other in a communicable manner via a transmission cable 11400.

[0541] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light taken in from the distal end of the lens barrel 11101 is guided to the camera 11102 and enters the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0542] The imaging unit 11402 includes an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-board type) or a plurality (so-called multi-board type) of imaging elements. For example, when the imaging unit 11402 is configured as a multi-board type, image signals corresponding to RGB can be generated by respective imaging elements, and a color image can be obtained by synthesizing the image signals. Alternatively, the imaging unit 11402 may include a pair of imaging elements for acquiring a right-eye image signal and a left-eye image signal corresponding to three-dimensional (3D) display. By performing 3D display, the surgeon 11131 can more accurately understand the depth of the living tissue at the surgical site. Note that in the case where the imaging unit 11402 is configured as a multi-board type, a plurality of lens units 11401 may be provided corresponding to respective imaging elements.

[0543] In addition, the imaging unit 11402 does not have to be provided on the camera 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 immediately behind the objective lens.

[0544] The driving unit 11403 includes an actuator, and the driving unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 along the optical axis by a predetermined distance under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0545] The communication unit 11404 includes a communication device for sending various types of information to the CCU 11201 and receiving various types of information from the CCU 11201. The communication unit 11404 sends the image signal obtained from the imaging unit 11402 to the CCU 11201 as RAW data through the transmission cable 11400.

[0546] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control information includes, for example, information related to imaging conditions, such as information for specifying the frame rate of the captured image, information for specifying the exposure value when capturing an image, and / or information for specifying the magnification and focus of the captured image.

[0547] Note that imaging conditions such as the frame rate, exposure value, magnification, and focus can be appropriately specified by the user or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the so-called automatic exposure (AE) function, automatic focus (AF) function, and automatic white balance (AWB) function are installed in the endoscope 11100.

[0548] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404.

[0549] The communication unit 11411 includes a communication device for sending various types of information to the camera 11102 and receiving various types of information from the camera 11102. The communication unit 11411 receives the image signal transmitted from the camera 11102 through the transmission cable 11400.

[0550] In addition, the communication unit 11411 sends a control signal to the camera 11102 to control the driving of the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, etc.

[0551] The image processing unit 11412 performs various types of image processing on the RAW data image signal transmitted from the camera 11102.

[0552] The control unit 11413 performs various types of control related to the shooting of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by shooting the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera 11102.

[0553] In addition, the control unit 11413 causes the display device 11202 to display a captured image showing a surgical site or the like based on the image signal that has been subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 can use various image recognition techniques to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, fog when using the energy treatment device 11112, etc. by detecting the shape, color, etc. of the edges of the objects included in the captured image. When the captured image is displayed on the display device 11202, the control unit 11413 can superimpose and display various types of surgical support information on the image of the surgical site by using the recognition result. Since the surgical support information is superimposed and displayed and presented to the operator 11131, the burden on the operator 11131 can be reduced, and the operator 11131 can perform the surgery with confidence.

[0554] The transmission cable 11400 that connects the camera 11102 to the CCU 11201 is an electrical signal cable capable of compatible electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0555] Here, in the example shown in the drawings, communication is performed by a wired method using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 can be performed wirelessly.

[0556] Examples of the endoscopic surgery system to which the technology according to the present invention can be applied have been described above. The technology according to the present invention can be applied to the imaging unit 11402 of the camera 11102 of the endoscope 11100 in the above configuration. When the technology according to the present invention is applied to the imaging unit 11402, the imaging unit 11402 can be reduced in size or have high definition, so that a small-sized or high-definition endoscope 11100 can be provided.

[0557] Although the present invention has been described with reference to the embodiments, modification examples, and application examples thereof, the present invention is not limited to the embodiments as described above, and various modifications can be made. Note that the effects described in this specification are merely examples. The effects of the present invention are not limited to the effects described in this specification. The present invention can have effects other than those described in this specification.

[0558] In addition, for example, the present invention can have the following configuration.

[0559] (1) An imaging device, characterized by comprising:

[0560] A first substrate having pixels, the pixels including a photodiode and a floating diffusion portion that holds the charge converted by the photodiode;

[0561] A second substrate, which includes a pixel circuit and is stacked on the first substrate, and the pixel circuit reads a pixel signal according to the charge held in the floating diffusion portion within the pixel;

[0562] A wiring, which penetrates the first substrate and the second substrate in a stacking direction and electrically connects the floating diffusion portion within the first substrate to an amplifying transistor within the pixel circuit of the second substrate; and

[0563] A trench, which is formed at least in the second substrate, extends parallel to the wiring, and the depth of the trench is equal to or greater than the thickness of the semiconductor layer within the second substrate. (2)

[0565] The imaging device according to (1), further comprising: a shielding wiring, which connects a conductive substance embedded within the trench to a source electrode of the amplifying transistor. (3)

[0567] The imaging device according to (1), wherein a gas having a low dielectric constant is sealed within the trench. (4)

[0569] The imaging device according to (1) or (2),

[0570] characterized in that the first substrate has:

[0571] A semiconductor layer, and

[0572] A wiring layer, which is stacked on the semiconductor layer and is formed of SiO 2 formed. (5)

[0574] The imaging device according to (1) or (2),

[0575] characterized in that the first substrate has:

[0576] A semiconductor layer, and

[0577] A wiring layer, which is stacked on the semiconductor layer and is formed of an insulating material having a dielectric constant lower than that of SiO 2 of. (6)

[0579] The imaging device according to (1),

[0580] characterized in that the trench

[0581] Formed on the semiconductor layer within the second substrate to electrically isolate the wiring from other wirings extending parallel thereto. (7)

[0583] The imaging device according to (6),

[0584] characterized in that, when viewed from the stacking surface of the second substrate,

[0585] the trench is formed on the semiconductor layer in the second substrate and surrounds the wiring in a circular shape. (8)

[0587] The imaging device according to (6),

[0588] characterized in that, when viewed from the stacking surface of the second substrate,

[0589] the trench is formed on the semiconductor layer in the second substrate and surrounds the wiring in a rectangular shape. (9)

[0591] An imaging device, characterized by comprising:

[0592] A first substrate having pixels, the pixels including a photodiode and a floating diffusion portion that holds charges converted by the photodiode;

[0593] A second substrate having pixel circuits and stacked on the first substrate, the pixel circuits reading pixel signals based on the charges held in the floating diffusion portions within the pixels;

[0594] Wirings that electrically connect the floating diffusion portions within the first substrate to amplification transistors within the pixel circuits of the second substrate and are formed in the first substrate and the second substrate, and

[0595] Shielding wirings that electrically connect the gates and sources of the amplification transistors while the well layers of the pixel circuits and the well layers of the amplification transistors within the pixel circuits are electrically isolated from each other, and the shielding wirings extend parallel to the wirings while shielding the wirings. (10)

[0597] The imaging device according to (9),

[0598] characterized in that the shielding wirings

[0599] shield at least the wiring portions of the wirings that connect the amplification transistors within the second substrate to the floating diffusion portions within the first substrate and pass through the second substrate. (11)

[0601] The imaging device according to (9),

[0602] wherein the shielding wiring

[0603] shields the wiring portion passing through the second substrate and the first substrate that connects the amplification transistor in the second substrate to the floating diffusion portion in the first substrate. (12)

[0605] The imaging device according to (9), wherein at least a part of the shielding wiring is closer to the wiring than other wirings. (13)

[0607] The imaging device according to (9), wherein the coupling capacitance between the wiring and the shielding wiring is greater than the coupling capacitance between the wiring and other wirings. (14)

[0609] The imaging device according to (9) further includes:

[0610] a column signal processing unit connected to the plurality of pixel circuits through a plurality of vertical signal lines,

[0611] wherein the column signal processing unit includes an AD converter and a load circuit, and outputs pixel data according to the voltage of the vertical signal line, and the AD converter performs AD conversion based on a reference signal. (15)

[0613] The imaging device according to (9) further includes:

[0614] a column signal processing unit connected to the plurality of pixel circuits through a plurality of vertical signal lines,

[0615] wherein the column signal processing unit includes:

[0616] a RAMP generation circuit that generates and outputs a RAMP waveform,

[0617] a comparator that compares the voltage of the pixel signal read through the vertical signal line with the voltage of the RAMP waveform,

[0618] a counter that counts based on the comparison result signal of the comparator, and

[0619] a latch that outputs pixel data according to the count value of the counter. (16)

[0621] The imaging device according to (15),

[0622] wherein the comparator is configured as a single-slope ADC. (17)

[0624] The imaging device according to (15),

[0625] wherein the comparator includes a transistor having a source terminal and a gate terminal and outputting a comparison result signal according to a gate-source voltage, the source terminal being applied with the pixel signal read through the vertical signal line, and the gate terminal being applied with the RAMP waveform. (18)

[0627] The imaging device according to (9), further comprising:

[0628] a column signal processing unit connected to the plurality of pixel circuits through a plurality of vertical signal lines,

[0629] wherein the column signal processing unit includes:

[0630] a load circuit,

[0631] a pre-stage circuit that connects the current generated by the load circuit to the vertical signal line and is configured as a current reuse circuit, and

[0632] an AD converter that performs AD conversion based on a predetermined reference signal, and

[0633] the column signal processing unit outputs pixel data according to the voltage of the vertical signal line.

[0634] List of reference numerals

[0635] 1 Imaging device

[0636] 100 First substrate

[0637] 100T Wiring layer

[0638] 200 Second substrate

[0639] 200T Wiring layer

[0640] 210A Pixel circuit

[0641] 250 Common p-well layer

[0642] 251 Independent P-well layer

[0643] 541 Pixel

[0644] 554 Comparator

[0645] 558 Comparator

[0646] 561 Pre - circuit

[0647] PD Photo - diode

[0648] FD Floating diffusion section

[0649] FDL FD wiring

[0650] T Trench

[0651] SL Shielding wiring

Claims

1. An imaging device, characterized in that, it includes: a first substrate having pixels, the pixels including a photodiode and a floating diffusion portion that holds the charge converted by the photodiode; a second substrate including a pixel circuit and stacked on the first substrate, the pixel circuit reading a pixel signal based on the charge held in the floating diffusion portion within the pixel; wiring that penetrates the first substrate and the second substrate in a stacking direction and electrically connects the floating diffusion portion within the first substrate to an amplifying transistor within the pixel circuit of the second substrate; a trench formed at least in the second substrate, extending parallel to the wiring, and the depth of the trench being equal to or greater than the thickness of a semiconductor layer within the second substrate; and shielding wiring that connects a conductive material embedded within the trench to the source of the amplifying transistor.

2. The imaging device according to claim 1, characterized in that, a gas having a low dielectric constant is sealed within the trench.

3. The imaging device according to claim 1, characterized in that, the first substrate has: a semiconductor layer, and The wiring layer, which is stacked on the semiconductor layer and is formed of SiO 2 formed.

4. The imaging device according to claim 1, characterized in that, the first substrate has: a semiconductor layer, and A wiring layer, which is stacked on the semiconductor layer and is formed of an insulating material having a dielectric constant lower than that of SiO 2 .

5. The imaging device according to claim 1 or 2, characterized in that, the trench is formed on the semiconductor layer within the second substrate to electrically isolate the wiring from other wiring extending parallel thereto.

6. The imaging device according to claim 5, characterized in that, when viewed from the stacking surface of the second substrate, the trench is formed on the semiconductor layer within the second substrate and surrounds the wiring in a circular shape.

7. The imaging device according to claim 5, characterized in that, when viewed from the stacking surface of the second substrate, the trench is formed on the semiconductor layer within the second substrate and surrounds the wiring in a rectangular shape.

8. An imaging device, characterized in that, it includes: a first substrate having pixels, the pixels including a photodiode and a floating diffusion portion that holds the charge converted by the photodiode; a second substrate having a pixel circuit and stacked on the first substrate, the pixel circuit reading a pixel signal based on the charge held in the floating diffusion portion within the pixel; wiring that electrically connects the floating diffusion portion within the first substrate to an amplifying transistor within the pixel circuit of the second substrate and is formed in the first substrate and the second substrate, and shielding wiring that electrically connects the gate and the source of the amplifying transistor in a state where the well layer of the pixel circuit and the well layer of the amplifying transistor within the pixel circuit are electrically isolated from each other, and the shielding wiring extends parallel to the wiring while shielding the wiring.

9. The imaging device according to claim 8, characterized in that, the shielding wiring Shield at least the wiring portion passing through the second substrate of the wiring that connects the amplification transistor in the second substrate to the floating diffusion portion in the first substrate.

10. The imaging device according to claim 8, wherein, the shielding wiring shields the wiring portion passing through the second substrate and the first substrate of the wiring that connects the amplification transistor in the second substrate to the floating diffusion portion in the first substrate.

11. The imaging device according to any one of claims 8 to 10, wherein, at least a part of the shielding wiring is closer to the wiring than other wirings.

12. The imaging device according to any one of claims 8 to 10, wherein, the coupling capacitance between the wiring and the shielding wiring is greater than the coupling capacitance between the wiring and other wirings.

13. The imaging device according to any one of claims 8 to 10, further comprises: a column signal processing unit connected to a plurality of the pixel circuits through a plurality of vertical signal lines, wherein the column signal processing unit includes an AD converter and a load circuit, and outputs pixel data according to the voltage of the vertical signal lines, and the AD converter performs AD conversion based on a reference signal.

14. The imaging device according to any one of claims 8 to 10, further comprises: a column signal processing unit connected to a plurality of the pixel circuits through a plurality of vertical signal lines, wherein the column signal processing unit includes: a RAMP generation circuit that generates and outputs a RAMP waveform, a comparator that compares the voltage of the pixel signal read through the vertical signal line with the voltage of the RAMP waveform, a counter that counts based on the comparison result signal of the comparator, and a latch that outputs pixel data according to the count value of the counter.

15. The imaging device according to claim 14, wherein the comparator is configured as a single-slope ADC.

16. The imaging device according to claim 14, wherein, the comparator includes a transistor having a source terminal and a gate terminal and outputting a comparison result signal according to the gate-source voltage, the source terminal is applied with the pixel signal read through the vertical signal line, and the gate terminal is applied with the RAMP waveform.

17. The imaging device according to any one of claims 8 to 10, further comprises: a column signal processing unit connected to a plurality of the pixel circuits through a plurality of vertical signal lines, wherein the column signal processing unit includes: a load circuit, a pre-stage circuit that connects the current generated by the load circuit to the vertical signal line and is configured as a current reuse column amplifier, and an AD converter that performs AD conversion based on a predetermined reference signal, and the column signal processing unit outputs pixel data according to the voltage of the vertical signal line.

Images