Die voltage regulation

Abstract

This application relates to die voltage regulation. An apparatus can include a first die and a second die. A component that generates a voltage on the first die can be connected to a capacitor on the second die by a conductive line. The conductive line can allow the capacitor on the second die to regulate the voltage generated by the component on the first die.

Description

[0001] CROSS-REFERENCE

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 044,237, titled “DIE VOLTAGE REGULATION,” filed June 25, 2020, and U.S. Patent Application No. 17 / 338,458, titled “DIE VOLTAGE REGULATION,” filed June 3, 2021, both of which are assigned to the assignee hereof, and each of which is hereby expressly incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The technical field relates to die voltage regulation. BACKGROUND

[0004] Memory devices are widely used in electronic systems to store information. Information is stored by programming memory cells within the memory devices into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, any of which can be stored therein. To access stored information, a component can read or sense at least one storage state in the memory device. To store information, a component can write or program a state into the memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selecting memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can retain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power source. SUMMARY

[0006] An apparatus is described. The apparatus can include a first die comprising a component configured to generate a voltage for use by the first die, a second die comprising a volatile memory comprising a memory cell and a capacitor isolated from the memory cell, wherein the memory cell comprises the capacitor, and a conductive line coupling the capacitor of the second die and the component configured to generate the voltage for use by the first die.

[0007] A method is described. The method can include generating a voltage at a first component disposed on a first die; adjusting the voltage using a capacitor, the capacitor coupled with the first component by a conductive line and disposed on a second die, the second die including a plurality of memory cells including the capacitor, wherein the voltage is adjusted with the capacitor isolated from the plurality of memory cells; and applying the voltage adjusted by the capacitor to one or more components disposed on the first die.

[0008] An apparatus is described. The apparatus can include a substrate in contact with a plurality of conductive pads; an insulating material disposed on the substrate; a first die at least partially surrounded by the insulating material and coupled with a first conductive pad of the plurality of conductive pads by a first conductive line, the first die including a component configured to generate a voltage for the first die; a second die at least partially surrounded by the insulating material and coupled with a second conductive pad of the plurality of conductive pads by a second conductive line, the second die including a volatile memory including a plurality of capacitors configured as memory cells, and the second die including a capacitor isolated from the plurality of capacitors configured as memory cells; and a third conductive line coupled with the component configured to generate a voltage for the capacitor of the second die and the plurality of capacitors configured as memory cells. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system that supports die voltage adjustment is illustrated in accordance with the examples disclosed herein.

[0010] Figure 2 An example of a memory sub-system that supports die voltage adjustment is illustrated in accordance with the examples disclosed herein.

[0011] Figure 3 An example of a die that supports die voltage adjustment is illustrated in accordance with the examples disclosed herein.

[0012] Figure 4 An example of a device that supports die voltage adjustment is illustrated in accordance with the examples disclosed herein.

[0013] Figure 5 An example of a device that supports die voltage adjustment is illustrated in accordance with the examples disclosed herein.

[0014] Figure 6 A block diagram of a device that supports die voltage adjustment is shown in accordance with aspects of the present disclosure.

[0015] Figure 7 A flow diagram illustrating a method that supports die voltage adjustment is shown in accordance with the examples disclosed herein. DETAILED DESCRIPTION

[0016] A device, such as an electronic device, can include multiple dies that provide different functionality. For example, a device can include a first die or non-volatile memory die that is a logic die that provides processing functionality and a non-volatile memory die that serves as a memory for the electronic device. To operate, the first die can use various voltages generated by one or more components on the first die. For example, the first die can include a voltage source, a voltage pump, a low-dropout (LDO) voltage regulator, an input / output (I / O) component, or other component (or any combination thereof) that outputs a voltage for use by the first die. In some cases, the voltage generated by the component on the first die can be regulated by a capacitor so that the voltage does not deviate beyond a threshold of an operating range. However, including a capacitor on the first die to regulate the voltage can be wasteful of space on the first die or cost prohibitive, among other drawbacks. Additionally or alternatively, using a discrete, independent capacitor external to the first die to regulate the voltage can increase the size of a package containing the first die and the external capacitor, which can be undesirable for various applications (e.g., mobile applications).

[0017] According to the techniques described herein, a capacitor on a second die can be used to regulate a voltage generated by one or more components on a first die. The capacitor can be similar to one or more other capacitors of volatile memory cells on the second die, which can be a DRAM die. Among other advantages, using a capacitor on the second die can be more cost effective and space efficient relative to using an internal capacitor on the first die and can be less regulated relative to an independent, discrete external capacitor. To enable voltage regulation by the capacitor on the second die, one or more conductive lines can connect the capacitor to the component that generates the voltage to be regulated. In some examples, the capacitor can be isolated from one or more components on the second die (e.g., memory cells and associated access circuitry), which can increase the reliability of the capacitor (e.g., by limiting the capacitor’s exposure to its rated voltage).

[0018] Features of the disclosure are initially described in the context of systems and subsystems described with reference to Figure 1 and 2 Features of the disclosure are initially described in the context of systems and subsystems described with reference to Figures 3 to 5 and devices described with reference to Figure 6 and Figure 7 These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams and flowcharts relating to die voltage regulation described with reference to

[0019] Figure 1An example of a system 100 that supports die voltage regulation in accordance with examples disclosed herein is illustrated. The system 100 can be included in an electronic device such as a computer or a phone. The system 100 can include a host device 105 and a memory sub-system 110. The host device 105 can be a processor or a system on a chip (SoC) that interfaces with an interface controller 115 and other components of an electronic device that includes the system 100. The memory sub-system 110 can store and provide access to electronic information (e.g., digital information, data) for the host device 105. The memory sub-system 110 can include the interface controller 115, a volatile memory 120, and a non-volatile memory 125. In some examples, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 can be included in the same physical package such as a package 130. However, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 can be arranged on different respective dies (e.g., silicon dies).

[0020] Devices in the system 100 can be coupled through various conductive lines (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring) that can enable communication of information (e.g., commands, addresses, data) between the devices. The conductive lines can constitute channels, data buses, command buses, address buses, etc.

[0021] The memory sub-system 110 can be configured to provide the benefits of the non-volatile memory 125 while maintaining compatibility with the host device 105 that supports protocols for different types of memory (e.g., the volatile memory 120, etc.). For example, the non-volatile memory 125 can provide benefits such as non-volatility, higher capacity, or lower power consumption (e.g., relative to the volatile memory 120), etc. However, the host device 105 can be incompatible or inefficiently configured with various aspects of the non-volatile memory 125. For example, the host device 105 can support voltages, access latencies, protocols, page sizes, etc. that are incompatible with the non-volatile memory 125. To compensate for the incompatibilities between the host device 105 and the non-volatile memory 125, the memory sub-system 110 can be configured with the volatile memory 120 that can be compatible with the host device 105 and serve as a cache for the non-volatile memory 125. Thus, the host device 105 can use protocols supported by the volatile memory 120 while benefiting from the advantages of the non-volatile memory 125.

[0022] In some examples, system 100 can be included in or coupled with a computing device, an electronic device, a mobile computing device, or a wireless device. The device can be a portable electronic device. For example, the device can be a computer, a laptop computer, a tablet computer, a smartphone, a cellular telephone, a wearable device, an internet-connected device, etc. In some examples, the device associated with system 100 can be configured for two-way wireless communication via a base station or an access point. In some examples, the device associated with system 100 can be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some examples, the device associated with system 100 can be referred to as user equipment (UE), a station (STA), a mobile terminal, etc.

[0023] Host device 105 can be configured to interface with memory sub-system 110 using a first protocol supported by interface controller 115 (e.g., low power double data rate (LPDDR)). Thus, in some examples, host device 105 can interface directly with interface controller 115, and indirectly with non-volatile memory 125 and volatile memory 120. In alternative examples, host device 105 can interface directly with non-volatile memory 125 and volatile memory 120. Host device 105 can also interface with other components of an electronic device that includes system 100. Host device 105 can be or include a SoC, a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In some examples, host device 105 can be referred to as a host.

[0024] Interface controller 115 can be configured to interface with volatile memory 120 and non-volatile memory 125 on behalf of host device 105 (e.g., based on one or more commands or requests issued by host device 105). For example, interface controller 115 can facilitate retrieval and storage of data in volatile memory 120 and non-volatile memory 125 on behalf of host device 105. Thus, interface controller 115 can facilitate transfer of data between various subcomponents, such as between host device 105, at least some of volatile memory 120, or non-volatile memory 125. Interface controller 115 can interface with host device 105 and volatile memory 120 using a first protocol, and can interface with non-volatile memory 125 using a second protocol supported by non-volatile memory 125.

[0025] The non-volatile memory 125 can be configured to store digital information (e.g., data) including for an electronic device of the system 100. Thus, the non-volatile memory 125 can include one or more arrays of memory cells and a local memory controller configured to operate the one or more arrays of memory cells. In some examples, the memory cells can be or include FeRAM cells (e.g., the non-volatile memory 125 can be FeRAM). The non-volatile memory 125 can be configured to interface with the interface controller 115 using a second protocol that is different from a first protocol used between the interface controller 115 and the host device 105. In some examples, the non-volatile memory 125 can have a longer access operation latency than the volatile memory 120. For example, retrieving data from the non-volatile memory 125 can take longer than retrieving data from the volatile memory 120. Similarly, writing data to the non-volatile memory 125 can take longer than writing data to the volatile memory 120. In some examples, the non-volatile memory 125 can have a smaller page size than the volatile memory 120, as described herein.

[0026] The volatile memory 120 can be configured to operate as a cache for one or more components such as the non-volatile memory 125. For example, the volatile memory 120 can store information (e.g., data) including for an electronic device of the system 100. Thus, the volatile memory 120 can include one or more arrays of memory cells and a local memory controller configured to operate the one or more arrays of memory cells. In some examples, the memory cells can be or include DRAM cells (e.g., the volatile memory can be DRAM). The non-volatile memory 125 can be configured to interface with the interface controller 115 using a first protocol used between the interface controller 115 and the host device 105.

[0027] In some examples, the volatile memory 120 can have a shorter access operation latency than the non-volatile memory 125. For example, retrieving data from the volatile memory 120 can take less time than retrieving data from the non-volatile memory 125. Similarly, writing data to the volatile memory 120 can take less time than writing data to the non-volatile memory 125. In some examples, the volatile memory 120 can have a larger page size than the non-volatile memory 125. For example, the page size of the volatile memory 120 can be 2 kilobytes (2 kB), and the page size of the non-volatile memory 125 can be 64 bytes (64 B) or 128 bytes (128 B).

[0028] While the non-volatile memory 125 can be a higher density memory than the volatile memory 120, accessing the non-volatile memory 125 can take longer than accessing the volatile memory 120 (e.g., due to different architectures and protocols, etc.). Thus, operating the volatile memory 120 as a cache can reduce latency in the system 100. For example, by retrieving data from the volatile memory 120 rather than from the non-volatile memory 125, access requests for data from the host device 105 can be satisfied relatively quickly. To facilitate operation of the volatile memory 120 as a cache, the interface controller 115 can include a plurality of buffers 135. The buffers 135 can be disposed on the same die as the interface controller 115 and can be configured to temporarily store data for transfer between the volatile memory 120, the non-volatile memory 125, or the host device 105 (or any combination thereof) during one or more access operations (e.g., storage and retrieval operations).

[0029] An access operation can also be referred to as an access process or an access procedure and can involve one or more sub-operations performed by one or more of the components of the memory sub-system 110. Examples of access operations can include storage operations in which data provided by the host device 105 is stored (e.g., written) in the volatile memory 120 or the non-volatile memory 125 (or both), and retrieval operations in which data requested by the host device 105 is obtained (e.g., read) from the volatile memory 120 or the non-volatile memory 125 and returned to the host device 105.

[0030] To store data in the memory sub-system 110, the host device 105 can initiate a storage operation (or “storage process”) by transmitting a storage command (also referred to as a storage request, a write command, or a write request) to the interface controller 115. The storage command can target a set of non-volatile memory cells in the non-volatile memory 125. In some examples, a set of memory cells can also be referred to as a portion of memory. The host device 105 can also provide data to be written to the set of non-volatile memory cells to the interface controller 115. The interface controller 115 can temporarily store the data in the buffer 135-a. After storing the data in the buffer 135-a, the interface controller 115 can transfer the data from the buffer 135-a to the volatile memory 120 or the non-volatile memory 125, or both. In a write-through mode, the interface controller 115 can transfer the data to both the volatile memory 120 and the non-volatile memory 125. In a write-back mode, the interface controller 115 can transfer the data to only the volatile memory 120.

[0031] In either mode, the interface controller 115 can identify an appropriate set of one or more volatile memory cells in the volatile memory 120 for storing data associated with a store command. To do so, the interface controller 115 can implement a bank association mapping in which each bank (e.g., block) of one or more non-volatile memory cells in the non-volatile memory 125 can be mapped to a plurality of banks of volatile memory cells in the volatile memory 120. For example, the interface controller 115 can implement an n-way association mapping that allows data from a bank of non-volatile memory cells to be stored in one of n banks of volatile memory cells in the volatile memory 120. Accordingly, the interface controller 115 can manage the volatile memory 120 as a cache of the non-volatile memory 125 by referencing the n banks of volatile memory cells associated with a target bank of non-volatile memory cells. As used herein, a "bank" of objects can refer to one or more objects, unless otherwise described or indicated. Although described with reference to a bank association mapping, the interface controller 115 can manage the volatile memory 120 as a cache by implementing one or more other types of mappings (e.g., a direct mapping or an associative mapping, etc.).

[0032] After determining which n banks of volatile memory cells are associated with the target bank of non-volatile memory cells, the interface controller 115 can store the data in one or more of the n banks of volatile memory cells. In this way, subsequent retrieval commands for the data from the host device 105 can be efficiently satisfied by retrieving the data from the lower latency volatile memory 120 instead of the higher latency non-volatile memory 125. The interface controller 115 can determine which of the n banks of volatile memory 120 to store the data based on one or more parameters associated with the data stored in the n banks of volatile memory 120, such as a validity, age, or modification status of the data. Accordingly, by storing the data in the volatile memory 120, the store command of the host device 105 can be satisfied completely (e.g., in a write-back mode) or partially (e.g., in a write- through mode). To track the data stored in the volatile memory 120, the interface controller 115 can store a tag address for one or more banks of volatile memory cells (e.g., for each bank of volatile memory cells) that indicates a non-volatile memory cell having data stored in a given bank of volatile memory cells.

[0033] To retrieve data from the memory sub-system 110, the host device 105 can initiate a retrieval operation (also referred to as a retrieval process) by transmitting a retrieval command (also referred to as a retrieval request, a read command, or a read request) to the interface controller 115. The retrieval command can target a set of one or more non-volatile memory cells in the non-volatile memory 125. Upon receiving the retrieval command, the interface controller 115 can check the requested data in the volatile memory 120. For example, the interface controller 115 can check the requested data in the n set of volatile memory cells associated with the target set of non-volatile memory cells. If one of the n set of volatile memory cells stores the requested data (e.g., stores data of the target set of non-volatile memory cells), the interface controller 115 can transfer the data from the volatile memory 120 to the buffer 135-a (e.g., in response to determining that one of the n set of volatile memory cells stores the requested data) so that it can be transmitted to the host device 105. The term “hit” can be used to refer to a situation in which the volatile memory 120 stores the requested data by the host device 105. If the n set of one or more volatile memory cells does not store the requested data (e.g., the n set of volatile memory cells stores data of a different set of non-volatile memory cells than the target set of non-volatile memory cells), the interface controller 115 can transfer the requested data from the non-volatile memory 125 to the buffer 135-a (e.g., in response to determining that the n set of volatile memory cells does not store the requested data) so that it can be transmitted to the host device 105. The term “miss” can be used to refer to a situation in which the volatile memory 120 does not store the requested data by the host device 105.

[0034] In a miss case, after transferring the requested data to buffer 135-a, interface controller 115 can transfer the requested data from buffer 135-a to volatile memory 120, such that volatile memory 120, rather than non-volatile memory 125, can satisfy subsequent read requests for the data. For example, interface controller 115 can store the data in one of n sets of volatile memory cells associated with the target set of non-volatile memory cells. However, the n sets of volatile memory cells can already store data for other sets of non-volatile memory cells. Accordingly, to preserve this other data, interface controller 115 can transfer the other data to buffer 135-b, such that it is transferred to non-volatile memory 125 for storage. This process can be referred to as "eviction," and the data transferred from volatile memory 120 to buffer 135-b can be referred to as "sacrificial" data. In some cases, interface controller 115 can transfer a subset of the sacrificial data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 can transfer one or more subsets of the sacrificial data that have changed since the data was originally stored in non-volatile memory 125. Data that is inconsistent between volatile memory 120 and non-volatile memory 125 (e.g., due to updates in one memory that are not updated in the other memory) can be referred to as "modified" or "dirty" data in some cases. In some examples (e.g., when the interface controller operates in a mode such as write-back mode), dirty data can be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0035] To perform respective operations, each device in system 100 can generate various voltages for internal use. For example, interface controller 115 (or non-volatile memory 125, and other components) can include components or circuitry that generate one or more voltages for use by other components in interface controller 115 (or non-volatile memory 125, and other components). According to the techniques described herein, a capacitor in volatile memory 120 can be used to regulate a voltage generated by interface controller 115 or non-volatile memory 125, or both. To implement this scheme, one or more conductive lines can connect the capacitor in volatile memory 120 to a component that generates the voltage for regulation.

[0036] Figure 2 An example of a memory sub-system 200 that supports die voltage regulation is illustrated in accordance with examples disclosed herein. Memory sub-system 200 can be an example of memory sub-system 110 described with reference to Figure 1 described with reference to Figure 1The host device interactions described. Memory sub-system 200 can include interface controller 202, volatile memory 204, and non-volatile memory 206, which can be as described with reference to Figure 1 The interface controller 115, volatile memory 120, and non-volatile memory 125 examples described. Thus, as described with reference to Figure 1 The interface controller 202 can interface the host device with the volatile memory 204 and the non-volatile memory 206, as described. For example, the interface controller 202 can operate the volatile memory 204 as a cache for the non-volatile memory 206. Operating the volatile memory 204 as a cache can allow the sub-system to provide the benefits of non-volatile memory 206 (e.g., non-volatility, high density storage) while maintaining compatibility with host devices that support a protocol different from the non-volatile memory 206.

[0037] In Figure 2 The dashed lines between components represent a data flow or communication path of data, while the solid lines between components represent a command flow or communication path of commands. In some cases, the memory sub-system 200 is one of a plurality of similar or identical sub-systems that can be included in an electronic device. In some examples, each sub-system can be referred to as a die and can be associated with a respective channel of a host device.

[0038] The non-volatile memory 206 can be configured to operate as a main memory of the host device (e.g., memory for long-term data storage). In some cases, the non-volatile memory 206 can include one or more arrays of FeRAM cells. Each FeRAM cell can include a selection component and a ferroelectric capacitor, and can be accessed by applying an appropriate voltage to one or more access lines, such as word lines, plate lines, and digit lines. In some examples, a subset of FeRAM cells coupled with an active word line can be sensed (e.g., concurrently or simultaneously) without having to sense all FeRAM cells coupled with the active word line. Thus, a page size of a FeRAM array can be different from (e.g., smaller than) a DRAM page size. In the context of a memory device, a page can refer to memory cells in a row (e.g., a group of memory cells having a common row address), and a page size can refer to a number of memory cells in a row or column address, or a number of column addresses accessed during an access operation. Alternatively, a page size can refer to a size of data handled by various interfaces. In some cases, different memory device types can have different page sizes. For example, a DRAM page size (e.g., 2kB) can be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0039] Smaller page sizes of FeRAM arrays can provide various efficiency benefits, as a single FeRAM cell can require more power to read or write than a single DRAM cell. For example, smaller page sizes of FeRAM arrays can facilitate efficient energy usage, as a smaller number of FeRAM cells can be activated when an associated change in information is small. In some examples, the page size of a FeRAM cell array can be dynamically varied (e.g., during operation of the FeRAM cell array), for example, depending on the nature of data and commands operated on with the FeRAM.

[0040] While a single FeRAM cell can require more power to read or write than a single DRAM cell, a FeRAM cell can maintain its stored logic state for a long time without an external power source, as the ferroelectric material in a FeRAM cell can maintain a non-zero electric polarization without an electric field. Thus, inclusion of a FeRAM array in non-volatile memory 206 can provide efficiency benefits over volatile memory cells (e.g., DRAM cells in volatile memory 204), as it can reduce or eliminate the requirement to perform refresh operations.

[0041] Volatile memory 204 can be configured to operate as a cache of non-volatile memory 206. In some cases, volatile memory 204 can include one or more arrays of DRAM cells. Each DRAM cell can include a capacitor that includes a dielectric material to store an electric charge representing a programmable state. The memory cells of volatile memory 204 can be logically grouped or arranged into one or more memory banks (referred to herein as “banks”). For example, volatile memory 204 can include sixteen memory banks. The memory cells of a memory bank can be arranged in a grid or array of intersecting columns and rows, and each memory cell can be accessed or refreshed by applying appropriate voltages to the digit lines (e.g., column lines) and word lines (e.g., row lines) of the memory cells. A row of a memory bank can be referred to as a page, and a page size can refer to the number of columns or memory cells in a row. As described above, the page size of volatile memory 204 can be different from (e.g., greater than) the page size of non-volatile memory 206.

[0042] The interface controller 202 can include various circuitry for interfacing (e.g., communicating) with other devices, such as a host device, volatile memory 204, and non-volatile memory 206. For example, the interface controller 202 can include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces can support communication of information using one or more communication protocols. For example, the data bus interface 208, the C / A bus interface 210, the data bus interface 216, and the C / A bus interface 264 can support communication of information using a first protocol (e.g., LPDDR signaling), while the data bus interface 212 and the C / A bus interface 214 can support communication of information using a second protocol. Thus, the various bus interfaces coupled with the interface controller 202 can support different amounts of data or data rates.

[0043] The data bus interface 208 can be coupled with a data bus 260, a transaction bus 222, and a buffer circuit 224. The data bus interface 208 can be configured to transmit and receive data over the data bus 260 and to transmit and receive control information (e.g., acknowledgement / negative acknowledgement) or metadata over the transaction bus 222. The data bus interface 208 can also be configured to transfer data between the data bus 260 and the buffer circuit 224. The data bus 260 and the transaction bus 222 can be coupled with the interface controller 202 and a host device such that a conductive path is established between the interface controller 202 and the host device. In some examples, the pins of the transaction bus 222 can be referred to as data mask inverted (DMI) pins. While one data bus 260 and one transaction bus 222 are shown, there can be any number of data buses 260 and any number of transaction buses 222 coupled with one or more data bus interfaces 208.

[0044] The C / A bus interface 210 can be coupled with a C / A bus 226 and a decoder 228. The C / A bus interface 210 can be configured to transmit and receive commands and addresses over the C / A bus 226. The commands and addresses received over the C / A bus 226 can be associated with data received or transmitted over the data bus 260. The C / A bus interface 210 can also be configured to transmit the commands and addresses to the decoder 228 such that the decoder 228 can decode the commands and relay the decoded commands and associated addresses to the command circuit 230.

[0045] The data bus interface 212 can be coupled with the data bus 232 and the memory interface circuit 234. The data bus interface 212 can be configured to transmit and receive data over the data bus 232, which can be coupled with the non-volatile memory 206. The data bus interface 212 can also be configured to transfer data between the data bus 232 and the memory interface circuit 234. The C / A bus interface 214 can be coupled with the C / A bus 236 and the memory interface circuit 234. The C / A bus interface 214 can be configured to receive commands and addresses from the memory interface circuit 234 and to relay the commands and addresses to the non-volatile memory 206 (e.g., to a local controller of the non-volatile memory 206) over the C / A bus 236. The commands and addresses transmitted over the C / A bus 236 can be associated with the data received or transmitted over the data bus 232. The data bus 232 and the C / A bus 236 can be coupled with the interface controller 202 and the non-volatile memory 206 such that a conductive path is established between the interface controller 202 and the non-volatile memory 206.

[0046] The data bus interface 216 can be coupled with the data bus 238 and the memory interface circuit 240. The data bus interface 216 can be configured to transmit and receive data over the data bus 238, which can be coupled with the volatile memory 204. The data bus interface 216 can also be configured to transfer data between the data bus 238 and the memory interface circuit 240. The C / A bus interface 264 can be coupled with the C / A bus 242 and the memory interface circuit 240. The C / A bus interface 264 can be configured to receive commands and addresses from the memory interface circuit 240 and to relay the commands and addresses to the volatile memory 204 (e.g., to a local controller of the volatile memory 204) over the C / A bus 242. The commands and addresses transmitted over the C / A bus 242 can be associated with the data received or transmitted over the data bus 238. The data bus 238 and the C / A bus 242 can be coupled with the interface controller 202 and the volatile memory 204 such that a conductive path is established between the interface controller 202 and the volatile memory 204.

[0047] In addition to the buses and bus interfaces for communicating with coupled devices, the interface controller 202 can include circuitry for operating the non-volatile memory 206 as main memory and the volatile memory 204 as a cache. For example, the interface controller 202 can include command circuitry 230, buffer circuitry 224, cache management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0048] Command circuitry 230 can be coupled with buffer circuitry 224, decoder 228, cache management circuitry 244, and scheduler 248, among other components. Command circuitry 230 can be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry 230 can include logic 262 that processes command information (e.g., from a host device) and storage information from other components (e.g., cache management circuitry 244, buffer circuitry 224) and uses the information to generate one or more commands for scheduler 248. Command circuitry 230 can also be configured to transfer address information (e.g., address bits) to cache management circuitry 244. In some examples, logic 262 can be circuitry configured to operate as a finite state machine (FSM).

[0049] Buffer circuitry 224 can be coupled with data bus interface 208, command circuitry 230, memory interface circuitry 234, and memory interface circuitry 234. Buffer circuitry 224 can include a set of one or more buffer circuits for at least some memory banks (if not every memory bank) of volatile memory 204. Buffer circuitry 224 can also include components for accessing the buffer circuitry (e.g., a memory controller). In one example, volatile memory 204 can include sixteen memory banks, and buffer circuitry 224 can include sixteen sets of buffer circuitry. Each set of buffer circuitry can be configured to store data from or for (or both) a respective memory bank of volatile memory 204. For example, the set of buffer circuitry for memory bank 0 (BK0) can be configured to store data from or for (or both) the first memory bank of volatile memory 204, and the set of buffer circuitry for memory bank 15 (BK15) can be configured to store data from or for (or both) the sixteenth memory bank of volatile memory 204.

[0050] Each set of buffer circuits in buffer circuit 224 can include a pair of buffers. The pair of buffers can include one buffer (e.g., an open page data (OPD) buffer) configured to store data targeted by an access command (e.g., a store command or a retrieve command) from a host device and another buffer (e.g., a victim page data (VPD) buffer) configured to store data of an eviction process generated by the access command. For example, the set of buffer circuits for BK0 can include buffer 218 and buffer 220, which can be instances of buffers 135-a and 135-b, respectively. Buffer 218 can be configured to store BK0 data targeted by an access command from a host device. And buffer 220 can be configured to store data transferred from BK0 as part of an eviction process triggered by the access command. Each buffer in the set of buffer circuits can be configured to have a size (e.g., a storage capacity) corresponding to a page size of volatile memory 204. For example, if the page size of volatile memory 204 is 2 kB, then the size of each buffer can be 2 kB. Thus, in some examples, the size of a buffer can be equal to the page size of volatile memory 204.

[0051] Cache management circuit 244 can be coupled with command circuit 230, engine 246, and scheduler 248, among other components. Cache management circuit 244 can include a set of cache management circuits for one or more memory banks (e.g., for each memory bank) of volatile memory. For example, cache management circuit 244 can include sixteen sets of cache management circuits for BK0-BK15. Each set of cache management circuits can include two memory arrays that can be configured to store storage information for volatile memory 204. For example, the set of cache management circuits for BK0 can include memory array 252 (e.g., a CDRAM tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM valid (CDT-V) array) that can be configured to store storage information for BK0. In some examples, a memory array can also be referred to as an array or a buffer. In some cases, a memory array can be or include volatile memory cells, such as SRAM cells.

[0052] The stored information can include content information, validity information, or dirtiness information (or any combination thereof) associated with the volatile memory 204. The content information (which can also be referred to as tag information or address information) can indicate which data is stored in a set of volatile memory cells. For example, the content information (e.g., tag address) for a set of one or more volatile memory cells can indicate which set of one or more non-volatile memory cells currently has the data stored in the set of one or more volatile memory cells. The validity information can indicate whether the data stored in a set of volatile memory cells is actual data (e.g., data having an expected order or form) or placeholder data (e.g., random or dummy data, not having an expected or important order). The dirtiness information can indicate whether the data stored in a set of one or more volatile memory cells of the volatile memory 204 is different from the corresponding data stored in a set of one or more non-volatile memory cells of the non-volatile memory 206. For example, the dirtiness information can indicate whether the data stored in a set of volatile memory cells has been updated with respect to the data stored in the non-volatile memory 206.

[0053] The memory array 252 can include memory cells that store the stored information (e.g., content and validity information) for the associated memory bank (e.g., BK0) of the volatile memory 204. The stored information can be stored on a per page basis (e.g., there can be respective stored information for each page of the associated non-volatile memory bank). The interface controller 202 can check for requested data in the volatile memory 204 by referencing the stored information in the memory array 252. For example, the interface controller 202 can receive a retrieval command from the host device for data in a set of non-volatile memory cells in the non-volatile memory 206. The interface controller 202 can reference the stored information in the memory array 252 using a set of one or more address bits (e.g., a set of row address bits) targeted by the access request. For example, using the set association mapping, the interface controller 202 can reference the content information in the memory array 252 to determine which set of volatile memory cells (if any) stores the requested data.

[0054] In addition to storing content information for volatile memory cells, memory array 252 can also store validity information indicating whether data in a set of volatile memory cells is actual data (also referred to as valid data) or random data (also referred to as invalid data). For example, a volatile memory cell in volatile memory 204 can initially store random data and continue to do so until the volatile memory cell is written with data from a host device or non-volatile memory 206. To keep track of which data is valid, memory array 252 can be configured to set a bit for each set of volatile memory cells when actual data is stored in the set of volatile memory cells. The bit can be referred to as a validity bit or a validity flag. Like content information, validity information stored in memory array 252 can be stored on a page basis. Thus, in some examples, each validity bit can indicate the validity of data stored in an associated page.

[0055] Memory array 254 can be similar to memory array 252 and can also include memory cells that store validity information for a memory bank (e.g., BK0) of volatile memory 204 associated with memory array 252. However, the validity information stored in memory array 254 can be stored on a sub-block basis, rather than on a per-page basis for memory array 252. For example, the validity information stored in the memory cells of memory array 254 can indicate the validity of data for a subset of volatile memory cells in a set (e.g., a page) of volatile memory cells. For example, the validity information in memory array 254 can indicate the validity of each subset (e.g., 64B) of data in a page of data stored in BK0 of volatile memory 204. Storing content information and validity information on a per-page basis in memory array 252 can allow interface controller 202 to quickly and efficiently determine whether there is a data hit or miss in volatile memory 204. Storing validity information on a sub-block basis can allow interface controller 202 to determine which subsets of data to save in non-volatile memory 206 during the eviction process.

[0056] Each cache management circuit set can also include a respective pair of registers coupled with components such as command circuit 230, engine 246, memory interface circuit 234, memory interface circuit 240, and a memory array for that cache management circuit set. For example, a cache management circuit set can include a first register (e.g., register 256, which can be an open page tag (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirtiness information) from memory array 252 or scheduler 248-b, or both. The cache management circuit set can also include a second register (e.g., register 258, which can be a victim page tag (VPT) register) configured to receive storage information from memory array 254 and scheduler 248-a, or both. The information in register 256 and register 258 can be communicated to command circuit 230 and engine 246 to enable these components to make decisions. For example, command circuit 230 can issue a command to read non-volatile memory 206 or volatile memory 204 based on content information from register 256.

[0057] Engine 246-a can be coupled with register 256, register 258, and scheduler 248. Engine 246-a can be configured to receive storage information from various components and issue commands to scheduler 248 based on the storage information. For example, when interface controller 202 is in a first mode such as a write-through mode, engine 246-a can issue a command to scheduler 248-b and, in response, scheduler 248-b can initiate or facilitate a transfer of data from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, when interface controller 202 is in a second mode such as a write-back mode, engine 246-a can issue a command to scheduler 248-b and, in response, scheduler 248-b can initiate or facilitate a transfer of data from buffer 218 to volatile memory 204. In the case of a write-back operation, data stored in volatile memory 204 can eventually be transferred to non-volatile memory 206 during a subsequent eviction process.

[0058] Engine 246-b can be coupled with register 258 and scheduler 248-a. Engine 246-b can be configured to receive storage information from register 258 and issue commands to scheduler 248-a based on the storage information. For example, engine 246-b can issue a command to scheduler 248-a to initiate or facilitate a transfer of dirty data from buffer 220 to non-volatile memory 206 (e.g., as part of an eviction process). If buffer 220 holds a set of data transferred from volatile memory 204 (e.g., victim data), engine 246-b can indicate which subset(s) (e.g., which 64B) of the set of data in buffer 220 should be transferred to non-volatile memory 206.

[0059] The scheduler 248-a can be coupled with various components of the interface controller 202 and can facilitate access to the non-volatile memory 206 by issuing commands to the memory interface circuit 234. The commands issued by the scheduler 248-a can be based on commands from the command circuit 230, the engine 246-a, the engine 246-b, or a combination of these components. Similarly, the scheduler 248-b can be coupled with various components of the interface controller 202 and can facilitate access to the volatile memory 204 by issuing commands to the memory interface circuit 240. The commands issued by the scheduler 248-b can be based on commands from the command circuit 230 or the engine 246-a, or both.

[0060] The memory interface circuit 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuit 234 can prompt the C / A bus interface 214 to relay commands issued by the memory interface circuit 234 over the C / A bus 236 to a local controller in the non-volatile memory 206. And the memory interface circuit 234 can transmit data to or receive data from the non-volatile memory 206 over the data bus 232. In some instances, the commands issued by the memory interface circuit 234 can be supported by the non-volatile memory 206 but not by the volatile memory 204 (e.g., the commands issued by the memory interface circuit 234 can be different from the commands issued by the memory interface circuit 240).

[0061] The memory interface circuit 240 can communicate with the volatile memory 204 via one or more of the data bus interface 216 and the C / A bus interface 264. For example, the memory interface circuit 240 can prompt the C / A bus interface 264 to relay commands issued by the memory interface circuit 240 over the C / A bus 242 to a local controller of the volatile memory 204. And the memory interface circuit 240 can transmit data to or receive data from the volatile memory 204 over one or more data buses 238. In some instances, the commands issued by the memory interface circuit 240 can be supported by the volatile memory 204 but not by the non-volatile memory 206 (e.g., the commands issued by the memory interface circuit 240 can be different from the commands issued by the memory interface circuit 234).

[0062] The components of the interface controller 202 can operate together as the non-volatile memory 206 as a main memory and the volatile memory 204 as a cache. This operation can be prompted by one or more access commands (e.g., read / retrieve commands / requests and write / store commands / requests) received from a host device.

[0063] In some examples, the interface controller 202 can receive a store command from a host device. The store command can be received over the C / A bus 226 and transferred to the command circuitry 230 via one or more of the C / A bus interface 210 and the decoder 228. The store command can include or be accompanied by address bits that target a memory address of the non-volatile memory 206. Data to be stored can be received over the data bus 260 and transferred to the buffer 218 via the data bus interface 208. In a write-through mode, the interface controller 202 can transfer the data to both the non-volatile memory 206 and the volatile memory 204. In a write-back mode, the interface controller 202 can transfer the data to only the volatile memory 204. In either mode, the interface controller 202 can first check to see if the volatile memory 204 has memory cells available to store the data. To do so, the command circuitry 230 can reference the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n sets of volatile memory cells (e.g., pages) associated with the memory address are empty (e.g., storing random or invalid data). In some cases, a set of volatile memory cells in the volatile memory 204 can be referred to as a line or cache line.

[0064] If one of the n sets of associated volatile memory cells is available to store information, the interface controller 202 can transfer the data from the buffer 218 to the volatile memory 204 for storage in the set of volatile memory cells. But if none of the associated sets of volatile memory cells are empty, the interface controller 202 can initiate an eviction process to make room for data in the volatile memory 204. The eviction process can involve transferring old data (e.g., existing data) in one of the n sets of associated volatile memory cells to the buffer 220. Dirty information for the old data can also be transferred to the memory array 254 or the registers 258 to identify a dirty subset of the old data. After storing the old data in the buffer 220, the new data can be transferred from the buffer 218 to the volatile memory 204 and the old data can be transferred from the buffer 220 to the non-volatile memory 206. In some cases, the dirty subset of the old data is transferred to the non-volatile memory 206 and the clean subset (e.g., the subset that was not modified) is discarded. The dirty subset can be identified by the engine 246-b based on the dirty information transferred (e.g., from the volatile memory 204) to the memory array 254 or the registers 258 during the eviction process.

[0065] In another example, the interface controller 202 can receive a retrieve command from the host device. The retrieve command can be received over the C / A bus 226 and transferred to the command circuitry 230 via one or more of the C / A bus interface 210 and the decoder 228. The retrieve command can include address bits that target a memory address of the non-volatile memory 206. Before attempting to access the target memory address of the non-volatile memory 206, the interface controller 202 can check to see if the volatile memory 204 stores the data. To do so, the command circuitry 230 can reference the memory array 252 (e.g., using a set of memory address bits) to determine if one or more of the n sets of volatile memory cells associated with the memory address store the requested data. If the requested data is stored in the volatile memory 204, the interface controller 202 can transfer the requested data to the buffer 218 for transmission to the host device over the data bus 260.

[0066] If the requested data is not stored in the volatile memory 204, the interface controller 202 can retrieve the data from the non-volatile memory 206 and transfer the data to the buffer 218 for transmission to the host device over the data bus 260. Additionally, the interface controller 202 can transfer the requested data from the buffer 218 to the volatile memory 204 so that the data can be accessed with lower latency during subsequent retrieve operations. However, before transferring the requested data, the interface controller 202 can first determine if one or more of the n sets of associated volatile memory cells are available for storing the requested data. The interface controller 202 can determine the availability of the n sets of associated volatile memory cells by communicating with the associated cache management circuitry set. If an associated set of volatile memory cells is available, the interface controller 202 can transfer the data in the buffer 218 to the volatile memory 204 without performing an eviction process. Otherwise, the interface controller 202 can transfer the data from the buffer 218 to the volatile memory 204 after performing an eviction process.

[0067] The memory sub-system 200 can be implemented in one or more configurations, including single chip versions and multi-chip versions. Multi-chip versions can include one or more components of the memory sub-system 200 on a chip separate from a chip that includes one or more other components of the memory sub-system 200, including the interface controller 202, the volatile memory 204, and the non-volatile memory 206 (as well as other components or combinations of components). For example, in one multi-chip version, individual separate chips can include each of the interface controller 202, the volatile memory 204, and the non-volatile memory 206. In contrast, a single chip version can include the interface controller 202, the volatile memory 204, and the non-volatile memory 206 on a single chip. Chips can also be referred to herein as dies.

[0068] In some examples, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 can be disposed on separate dies, and each die can include one or more components that generate voltages for use by one or more other components on that die. Capacitors can be used to regulate the voltages generated by the components to reduce deviation from thresholds of operating ranges. But for cost and space reasons, it can be impractical to use internal capacitors (relative to the die) to regulate voltages. And due to the size of capacitors, using discrete, standalone external capacitors can negatively impact package size.

[0069] According to the techniques described herein, voltages generated by components on a first die (e.g., a die that includes the interface controller 115 or the non-volatile memory 125) can be regulated by a capacitor on a second die (e.g., a die that includes the volatile memory 120). In some examples, the capacitor on the second die can be formed using the same process as the capacitors used as memory cells on the second die, and thus can be cost effective and space efficient relative to alternatives, such as capacitors internal to the first die or discrete, standalone external capacitors. To enable voltage regulation, one or more components that generate one or more voltages to be regulated can be coupled with the capacitor on the second die via one or more conductive lines.

[0070] Figure 3 An example of a die 300 that supports die voltage regulation is illustrated in accordance with examples disclosed herein. The die 300 can include a first die 305 and a second die 310. The first die 305 can be an example of a logic die that includes an interface controller 115 as described with reference to Figure 1 or a memory die that includes a non-volatile memory 125. Alternatively, the first die 305 can be an example of a logic die that includes an interface controller 202 as described with reference to Figure 2 or a memory die that includes a non-volatile memory 206. The second die 310 can be an example of a memory die that includes a volatile memory 120 as described with reference to Figure 1 or a memory die that includes a volatile memory 204. In some examples, the second memory die is a DRAM die (e.g., a die that includes DRAM cells). Figure 2

[0071] ​The first die 305 can include at least one component 315 that outputs a voltage. In some cases, the component 315 can be a component that generates a voltage for use or operation by the first die 305. For example, the component 315 can be a voltage source, a voltage pump, a low-dropout (LDO) voltage regulator, an input / output (I / O) component, or other component that outputs a voltage for use by one or more other components of the first die 305, etc. Additionally or alternatively, the component 315 can supply power to the second die 310 (e.g., the second die 310 can use the voltage output by the component 315 for one or more operations). In some instances, the voltage output by the component 315 can experience destructive or fluctuation that renders the voltage unsuitable for use by other components. For example, the voltage generated by the component 315 can peak and drop in a ragged manner, rather than remaining at a constant level (or a level within an operating range). This potential variation in voltage can negatively impact the operation of the component to which the voltage is applied.

[0072] In some instances, the voltage generated by the component 315 can be regulated (e.g., smoothed, kept within a threshold range) by coupling the component 315 with a capacitive load. For example, the output of the component 315 can be coupled with a “storage” or “smoothing” capacitor that attenuates the voltage when it rises above a threshold, and that boosts the voltage when it falls below the threshold. In one instance, a storage capacitor 320 can be placed in parallel with the output of the component 315, such that the capacitor 1) charges when the voltage of the output rises above the voltage of the capacitor, and 2) discharges when the voltage of the output falls below the voltage of the capacitor, etc. Thus, the storage capacitor 320 can provide current to the output of the component 315 when the voltage of the component 315 is below a threshold voltage, and can sink current when the voltage of the component 315 rises above the threshold voltage. Thus, the capacitor can keep the voltage output of the component 315 within a threshold range.

[0073] However, including such a capacitor on the first die 305 can require space on the first die 305, and be cost prohibitive, among other drawbacks. And using a discrete, external capacitor can increase the size of a package that houses the first die 305 and the second die 310, among other potential drawbacks. For example, the height of the package can be much higher than it otherwise would be to accommodate the capacitor. Since the height of the storage capacitor can be a function of the amplitude (e.g., magnitude) of the voltage to be regulated, increasing the voltage generated by the component 315 can result in a higher storage capacitor, which in turn can increase the size of the physical package that contains the storage capacitor and / or the first die 305.

[0074] According to the techniques described herein, a capacitor on the second die 310 can be used to regulate a voltage output by a component of the first die 305. For example, a storage capacitor 320 on the second die 310 can regulate a voltage generated by a component 315 on the first die 305. Voltage regulation can be achieved through conductive lines 325 that can couple the storage capacitor 320 with the component 315. For example, one conductive line 325 can couple a first terminal of the storage capacitor 320 with a first output terminal of the component 315, while another conductive line 325 can couple a second terminal of the storage capacitor 320 with a ground reference 330 (and / or a second output terminal of the component 315). The storage capacitor 320 can have relative area efficiency, low cost, and thinness, among other advantages, compared to discrete external capacitors. For example, the storage capacitor 320 can be constructed via a custom low-cost process for constructing capacitors for DRAM memory cells, which can be more compact than discrete capacitors. Thus, according to the present disclosure, the benefits of external storage capacitors can be achieved without sacrificing package size.

[0075] While structurally similar to capacitors that operate as memory cells on the second die 310, the storage capacitor 320 can be isolated from one or more of these other capacitors to prevent damage that can occur due to voltage differences between the dies 300, among other advantages. For example, the storage capacitor 320 can be physically or electrically isolated (or both) from memory cells and conductive lines (e.g., digit lines, plate lines, etc.) or from circuitry used to access memory cells on the second die 310 (e.g., sense components). For example, each terminal of the storage capacitor 320 can be directly coupled to a respective conductive line 325 that extends from the terminal to a respective bond pad of the second die. In some examples, the conductive lines 325 extend directly from the terminals of the storage capacitor 320 to the bond pads without being electrically coupled to other devices (e.g., active devices such as transistors, switching components, etc.). In other examples, one or more switching devices can be disposed between the terminals of the two storage capacitors to enable adjustment of the effective capacitance of the capacitors. The switching components can be part of an antifuse device. In some examples, the bond pads coupled with the storage capacitor 320 can be coupled with electrostatic protection devices (e.g., electrostatically sensitive device (ESD) protection structures). Thus, in some examples, the storage capacitor 320 can be coupled with (but separate from) electrostatic protection devices.

[0076] Regardless of the isolation, the storage capacitor 320 can regulate a voltage generated by the component 315, as described herein. Thus, voltage regulation of a first die (e.g., the first die 305) can be achieved or performed through a capacitor (e.g., the storage capacitor 320) on a second die (e.g., the second die 310).

[0077] Figure 4An example of a device 400 that supports die voltage regulation is illustrated in accordance with examples disclosed herein. The device 400 can include a first die 405 and a second die 410. The first die 405 can be a logic die that includes an interface controller 115 as described with reference to Figure 1 Figure 1 Figure 2 Figure 2 Figure 3 The second die 410 can be a memory die that includes a volatile memory 120 as described with reference to Figure 1 Figure 2 Figure 3

[0078] The first die 405 and the second die 410 can be included in a physical package, such as a package 415, which can include a plastic or other non-conductive (e.g., insulating) material. The package 415 can have a height 420 that is a function of the size of the components included in the package 415. Within the package 415, the first die 405 and the second die 410 can be held in place by a material, such as an insulating material 425, that at least partially surrounds the first die 405 and the second die 410. The insulating material 425 can be in contact with (e.g., disposed on) a substrate 430. The substrate 430 can be coupled with a conductive pad 435 (also referred to as a conductive interface, a lead, a pin, a bond pad, etc.), which in turn can be coupled with another device, such as a host device as described with reference to Figure 1

[0079] ​​​​​​​​The first die 405 and the second die 410 can each be coupled with one or more conductive lines that allow electrical signals to be sent from the die to other devices (e.g., through conductive pads 435). The conductive lines can also be referred to as traces, routes, channels, buses, or other suitable terms. For example, the first die 405 can be coupled with a conductive line 440-a, and the second die 410 can be coupled with a conductive line 440-b. The conductive line 440-a can allow the first die 405 to transmit electrical signals (e.g., commands, addresses, data, etc.) to devices outside of the package 415, and the conductive line 440-b can allow the second die 410 to transmit electrical signals to devices outside of the package 415. Although each die is shown as being coupled with one conductive line 440, the dies can be coupled with any number of conductive lines 440 in various configurations.

[0080] The first die 405 and the second die 410 can also be coupled with a conductive line 445 that can allow a capacitor on the second die 410 to regulate a voltage output by a component on the first die 405. For example, the conductive line 445 can connect a component on the first die 405 (e.g., a component configured to generate a voltage, such as the component 315) with a capacitor on the second die 410 (e.g., a storage capacitor, such as the storage capacitor 320). To facilitate illustration, a single conductive line 445 is shown, but the conductive line 445 can be one of a plurality of conductive lines that connect the storage capacitor as shown. In some examples, an output terminal of the component 315 can share the same node (e.g., a conductive pad 435) as one of the conductive lines 445 and / or one of the terminals of the storage capacitor 320. In some examples, the conductive line 445 or the conductive line 440-b can couple another terminal of the storage capacitor to a ground pin (e.g., a ground conductive pad 435). Figure 3

[0081] The conductive line 445 can pass through (e.g., be disposed through) the insulating material 425 along a first direction (e.g., along the z-direction) and can pass through (e.g., be disposed through) the substrate 430 along a second direction (e.g., the y-direction). Thus, the conductive line 445 can pass through the substrate along a plane (e.g., the x-y plane) that is perpendicular to the first direction (e.g., the z-direction). In some cases, a portion or segment of a conductive line that passes through the substrate 430 can be referred to as a lateral portion or segment because it extends through the substrate 430 along the x-y plane. In some examples, the lateral portion of the conductive line 445 can be below (with respect to the z-direction) the first die 405 and the second die 410 and above the lateral portions of the conductive lines 440.

[0082] ​As illustrated, the techniques described herein are implemented as an in-package solution (e.g., in Universal Flash (UFS) applications, managed NAND (mNAND) applications, UFS-based multi-chip package (uMCP) applications) where the second die 410 is contained in the same package as the first die 405. However, the techniques described herein can also be implemented as an on-board solution (e.g., in solid state drive (SSD) applications) where the first die 405 and the second die 410 are contained in the same electronic device, but housed in different packages. Regardless of the packaging scheme, using a capacitor on the second die 410 to regulate the voltage generated by the first die 405 can provide various advantages (e.g., lower form cost, reduced package height) compared to other voltage regulation schemes.

[0083] Figure 5 An example of a device 500 that supports die voltage regulation is illustrated in accordance with examples disclosed herein. The device 500 can be an example of the device 400 described with reference to Figure 4 The device 400 described with reference to Figure 3 The first die 505 can be an example of the first die 305 described with reference to Figure 4 The first die 405 described with reference to Figure 3 The second die 510 can be an example of the second die 310 described with reference to Figure 4 The second die 410 described with reference to Figure 5 Unless otherwise specified, lines terminated with an arrow can represent a communication path for information such as data, metadata, commands, addresses, etc. Lines without arrow terminations can represent conductive lines (e.g., metal traces) connecting components.

[0084] The first die 505 can include functional components 515, which can be, among other things, a non-volatile memory array or a logic chip. For example, when the first die 505 is a reference Figure 1The described example of non-volatile memory 106, the functional component 515 can be a FeRAM array. The first die 505 can also include operating circuitry 520, which can include circuitry for interfacing with and accessing the functional component 515 or other components of the first die 505. The operating circuitry 520 can use one or more voltages that can be provided by one or more voltage generation components, such as voltage generation components 525-a through voltage generation components 525-n. The voltage generation components 525 can be examples of voltage sources, voltage pumps, LDO voltage regulators, I / O components, etc., and thus can generate and output voltages for use by other components of the first die 505. In some examples, the operating circuitry 520 can include a switching component that, when activated, transfers a voltage produced by a voltage generation component 525 to other components on the first die 505. Thus, a voltage produced by a voltage generation component 525 can be applied to one or more other components of the first die 505.

[0085] Each voltage generation component 525 can include one or more output terminals 530 that the voltage generation component 525 charges to a predetermined or configurable voltage level. For example, the voltage generation component 525-a can include output terminal 530-a-l and output terminal 530-a-2. Similarly, the voltage generation component 525-n can include output terminal 530-n-l and output terminal 530-n-2. As described above, a voltage produced by a voltage generation component 525 can be applied to another component of the first die 505 by establishing a conductive path between an output terminal 530 and the other component (e.g., composed of conductive wires, switching components). An output terminal can also be referred to as an output node, an output point, or other suitable terminology.

[0086] The second die 510 can include volatile memory 535, which can be an example of the volatile memory 120 or the volatile memory 204 described with reference to Figure 1 and 2 The second die 510 can include volatile memory 535, which can be an example of the volatile memory 120 or the volatile memory 204 described with reference to

[0087] The second die 510 can also include one or more capacitors 545 that provide voltage regulation for other components of the device 500. For example, the capacitor 545-a can regulate a voltage generated by the first die 505, while the capacitor 545-b can regulate a voltage generated by the second die 510. For example, the capacitor 545-a can regulate a voltage output by the voltage generation component 525. In some examples, the capacitor 545-a can be configured to regulate a higher voltage than the capacitor 545-a (or vice versa). The capacitors 545 can share the same form or structure as the capacitors of the volatile memory cells in the volatile memory 535, but unlike the memory cell capacitors, the capacitors 545 can be isolated from the access circuitry 540. Further, the capacitor 545-a can be isolated from the capacitor 545-b. This isolation can increase the reliability and lifetime of the capacitors 545 (or other components) by preventing exposure to harmful voltages (e.g., voltages that exceed the ratings of the capacitors 545 or other components). However, the capacitor 545-a can share a common ground reference with the capacitor 545-b and the memory cell capacitors.

[0088] In some examples, the capacitors 545 can be passive devices (e.g., components that do not require an external power source to operate and / or are capable of storing energy). In some examples, the capacitors 545 can be components having two conductive terminals separated by an insulator.

[0089] The capacitor 545-a can be connected to the voltage generation component 525 by one or more conductive lines 550. For example, the conductive line 550-a can connect n capacitors 545-a to the output terminal 530-a-l, and the conductive line 550-b can connect n capacitors 545-a to a ground reference (not shown) and / or the output terminal 530-a-2 (where n is an integer). The conductive lines 550 can be arranged as shown in FIGS. 5B and 5C. Thus, the voltage output by the voltage generation component 525-a can be regulated (e.g., kept within a voltage level band) by a set of capacitors 545-a. Figure 3 and 4 Thus, the voltage output by the voltage generation component 525-a can be regulated (e.g., kept within a voltage level band) by a set of capacitors 545-a.

[0090] In some examples, the connection between the voltage generation component 525 and the capacitor 545-a can be fixed (e.g., permanent, static, unchangeable) such that there is no variation in the capacitance provided by the capacitor 545-a. For example, the conductive line 550 can be a hardwired conductive line that forms a direct connection between the voltage generation component 525-a and the capacitor 545-a. A hardwired feature can be a feature that is implemented in the form of a permanent circuit. A direct connection can be a connection between two or more components that is not interrupted by other components, such as a switching component. A hardwired direct connection can also be referred to herein as a “short circuit.” Thus, a fixed capacitance can be provided to the voltage generation component 525-a by shorting the conductive line 550-a and the conductive line 550-b to the capacitor 545-a. The capacitance provided by a group of capacitors can be referred to in some examples as a capacitive load or a combined capacitance.

[0091] While providing a fixed capacitive load can be suitable for some applications, other applications can benefit from the ability to vary the capacitive load. In such applications, the connection between the voltage generation component 525 and the capacitor 545-a can be configurable. In one example, a switching component disposed (e.g., placed) along the conductive line 550 can be used to modify which voltage generation component 525 is connected to the capacitor 545-a. For example, deactivating a switching component coupled to the conductive line 550 can disconnect the capacitor 545-a from the voltage generation component 525-a, and activating a switching component coupled to the conductive line 550 can connect the capacitor 545-a to the voltage generation component 525-n.

[0092] Additionally or alternatively, one or more switching components can be used to modify which capacitors 545-a are connected to the voltage generation component 525. In some examples, the capacitors 545-a can include one or more groups of capacitors in a parallel configuration. For example, the group 555 can include the capacitor 545-a-l, the capacitor 545-a-2, and the capacitor 545-a-3. The capacitance provided by the group 555 can be varied by varying the number of capacitors connected in parallel. For example, the group 555 can provide a first capacitive load when two capacitors, the capacitor 545-a-l and the capacitor 545-a-2, are connected in parallel. And the group 555 can provide a second (e.g., larger) capacitive load when three capacitors, the capacitor 545-a-l, the capacitor 545-a-2, and the capacitor 545-a-3, are connected in parallel. Thus, the capacitive load provided by a group of capacitors can be increased by increasing the number of capacitors connected in parallel, and decreased by decreasing the number of capacitors connected in parallel.

[0093] In some cases, the number of capacitances connected in parallel can be changed by modifying the state of one or more switch components 560 coupled with the conductive line 550. For example, by activating a switch component 560 that can be part of a control circuit for anti-fuse that can be programmable at the factory or in the field, the capacitor 545-a-3 can be connected in parallel with the capacitor 545-a-l and the capacitor 545-a-2. And the capacitor 545-a-3 can be disconnected (e.g., isolated) from the capacitor 545-a-l and the capacitor 545-a-2 by deactivating the switch component 560. Thus, the capacitance provided by a set of capacitors can be modified by changing the active state of the switch components coupled with the capacitors. Although three capacitors 545-a are shown in the set 555, a set of capacitors can include any number of capacitors 545-a, including one capacitor. Further, the capacitors in a set can be arranged in any configuration, and are not limited to a parallel configuration.

[0094] In some examples, the conductive lines 550 can be strategically placed (e.g., arranged) such that cross-coupling between other conductive lines is reduced. For example, the device 500 can include conductive lines configured to carry information (e.g., data, commands, metadata, addresses, etc.) between the first die 505 and the second die 510. The conductive lines can be independent communication paths (e.g., the conductive line 570) or grouped together in a bus 565. The information sent over the conductive line 570 can be represented by a signal that is transmitted by an I / O interface on one die (e.g., the I / O interface 575-a) and received and processed by an I / O interface on the other die (e.g., the I / O interface 575-b). But a signal fluctuation on one conductive line (e.g., an aggressor) can interfere with the signal on a nearby conductive line (e.g., a victim). This phenomenon can be referred to as cross-coupling or crosstalk, and can negatively impact the performance of the device 500.

[0095] To mitigate cross-coupling, the conductive lines 550 can be placed between multiple conductive lines 570 that would otherwise experience cross-coupling. For example, the conductive line 550 can be placed between the conductive line 570-a and the conductive line 570-b, thereby reducing the interference caused by voltage fluctuations on the conductive lines 570. Thus, the conductive line 550 can act as a shield between the conductive lines 570 due to the relatively static voltage on the conductive line 550. In some cases, the portion of the conductive line 550 that acts as a shield can be the portion of the conductive line that traverses the substrate 430 in the x-y plane, as shown. Thus, in some examples, the conductive lines 550 can mitigate cross-coupling in addition to implementing voltage regulation through the capacitors 545-a. Figure 3

[0096] Figure 6 ​A block diagram 600 of a device 605 that supports die voltage regulation is shown, in accordance with examples disclosed herein. The device 605 can be an example of the device 400 or the device 500 described with reference to FIGS. 1-2, respectively. The device 605 can be configured such that a voltage generated on a first die of the device 605 is regulated by a capacitor on a second die of the device. The device 605 can include a voltage generation module 610, a voltage regulation module 615, a voltage application module 620, a switch component manager 625, and an information manager 630. Each of these modules can include circuitry configured to perform the functions described herein. Each of these modules can communicate, directly or indirectly, with one another (e.g., via one or more buses or other conductive connections). Figure 4 and 5 The device 605 can be configured such that a voltage generated on a first die of the device 605 is regulated by a capacitor on a second die of the device. The device 605 can include a voltage generation module 610, a voltage regulation module 615, a voltage application module 620, a switch component manager 625, and an information manager 630. Each of these modules can include circuitry configured to perform the functions described herein. Each of these modules can communicate, directly or indirectly, with one another (e.g., via one or more buses or other conductive connections).

[0097] The voltage generation module 610 can generate a voltage at a first component disposed on the first die. The voltage regulation module 615 can regulate the voltage using a capacitor coupled with the first component by a conductive line. The capacitor can be disposed on the second die, which includes a plurality of memory cells that include the capacitor. In some examples, the voltage is regulated with the capacitor isolated from the plurality of memory cells. In some examples, regulating the voltage includes maintaining a level of the voltage within a threshold range. The voltage application module 620 can apply the voltage regulated by the capacitor to one or more components disposed on the first die. In some examples, applying the voltage includes activating one or more switch components to communicate the voltage to the one or more components of the first die.

[0098] In some examples, the capacitor is included in a first set of capacitors used to regulate the voltage generated by the first component. In such examples, the voltage generation module 610 can generate a second voltage at a second component disposed on the first die. The voltage regulation module 615 can regulate the second voltage using a second set of capacitors isolated from the plurality of memory cells and coupled with the second component by a second conductive line. The voltage application module 620 can activate a switch component coupled with the conductive line, the second conductive line, or a combination thereof to select the first set of capacitors, the second set of capacitors, or a combination thereof.

[0099] The switch component manager 625 can modify a capacitive load coupled with the first component, where the capacitive load is based at least in part on the capacitor. In some examples, the switch component manager 625 can modify a state of a switch component coupled with the conductive line to modify a number of the capacitors connected in parallel from a first number to a second number.

[0100] The information manager 630 can transmit information between the first die and the second die by a second conductive line. The information manager 630 can also transmit information between the first die and the second die by a third conductive line, where the conductive line is disposed between the second conductive line and the third conductive line.

[0101] Figure 7 A flow diagram illustrating one or more methods 700 that support die voltage regulation in accordance with examples as disclosed herein is shown. The operations of method 700 can be implemented by a device as described herein or its components. For example, the operations of method 700 can be performed by a device as described with reference to FIGS. 1-6. In some examples, a device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the device can perform aspects of the described functions using special-purpose hardware. Figures 1 to 6

[0102] At 705, the method can include generating a voltage at a first component disposed on a first die. The memory address can be associated with a set of memory cells in a set of volatile memory banks. The operations of 705 can be performed according to the methods described herein. In some examples, aspects of the operations of 705 can be performed by a voltage generation module as described with reference to FIGS. 1-6. Figure 6

[0103] At 710, the method can include adjusting the voltage using a capacitor coupled with the first component by a conductive line and disposed on a second die, the second die including a plurality of memory cells including the capacitor, wherein the voltage is adjusted with the capacitor isolated from the plurality of memory cells. In some examples, adjusting the voltage includes maintaining a level of the voltage within a threshold range. The operations of 710 can be performed according to the methods described herein. In some examples, aspects of the operations of 710 can be performed by a voltage adjustment module as described with reference to FIGS. 1-6. Figure 6

[0104] At 715, the method can include applying the voltage adjusted by the capacitor to one or more components disposed on the first die. In some examples, applying the voltage includes activating one or more switching components to communicate the voltage to the one or more components of the first die. The operations of 715 can be performed according to the methods described herein. In some examples, aspects of the operations of 715 can be performed by a voltage application module as described with reference to FIGS. 1-6. Figure 6

[0105] In some examples, the apparatus described herein can perform one or more methods, such as method 700. The apparatus can include features, means, or instructions for generating a voltage at a first component disposed on a first die; adjusting the voltage using a capacitor coupled with the first component by a conductive line and disposed on a second die, the second die including a plurality of memory cells including the capacitor, wherein the voltage is adjusted with the capacitor isolated from the plurality of memory cells; and applying the voltage adjusted by the capacitor to one or more components disposed on the first die. ​​​​

[0106] In some examples, the capacitor is included in a first set of capacitors used to regulate a voltage generated by the first component. Accordingly, some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for generating a second voltage at a second component disposed on the first die; and regulating the second voltage using a second set of capacitors isolated from the plurality of memory cells and coupled with the second component by a second conductive line. Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for activating a switching component coupled with the conductive line, the second conductive line, or a combination thereof to select the first set of capacitors, the second set of capacitors, or a combination thereof.

[0107] Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for modifying a capacitive load coupled with the first component, where the capacitive load is based at least in part on the capacitor. Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for modifying a state of a switching component coupled with the conductive line to modify a number of the capacitors connected in parallel from a first number to a second number.

[0108] Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for transmitting information between the first die and the second die by a second conductive line and transmitting information between the first die and the second die by a third conductive line; where the conductive line is disposed between the second conductive line and the third conductive line.

[0109] In some examples, an apparatus described herein can perform aspects of the method 700. The apparatus can include a first die comprising a component configured to generate a voltage for use by the first die; a second die comprising a volatile memory, the volatile memory comprising a memory cell and a capacitor isolated from the memory cell, where the memory cell comprises the capacitor; and a conductive line coupling the capacitor of the second die and the component configured to generate the voltage for use by the first die.

[0110] In some examples, the apparatus includes a substrate below the first die and the second die, where a section of the conductive line passes through the substrate in a first direction. In some examples, the apparatus includes an insulating material between the substrate and the first die and the second die, where a second section of the conductive line passes through the insulating material in a second direction different from the first direction.

[0111] In some examples, the apparatus includes a second conductive line (e.g., conductive line 440-a) coupling the first die to the first conductive pad of the substrate; and a third conductive line (e.g., conductive line 440-b) coupling the second die to the second conductive pad of the substrate, where the conductive line (e.g., conductive line 445) is disposed under the first die and the second die and a lateral segment of the conductive line is disposed over a lateral segment of the second conductive line and a lateral segment of the third conductive line.

[0112] In some examples of the apparatus, the second die includes a circuit (e.g., access circuit 540) configured to access a memory cell of the volatile memory, where the capacitor is isolated from the circuit.

[0113] In some examples of the apparatus, the conductive line couples a first terminal of the capacitor to the component. In such examples, the apparatus can include a second conductive line coupling a second terminal of the capacitor to the component.

[0114] In some examples of the apparatus, the second die can include a second capacitor (e.g., capacitor 545-a-2) isolated from the memory cell and in parallel with the capacitor, where the conductive line couples the second capacitor to the component.

[0115] In some examples, the apparatus can include a second conductive line (e.g., conductive line 570-a) configured to transfer information between the first die and the second die; and a third conductive line (e.g., conductive line 570-b) configured to transfer information between the first die and the second die, where the conductive line is disposed between the second conductive line and the third conductive line.

[0116] In some examples, the apparatus can include a switching component (e.g., switching component 560) disposed along the conductive line and configured to modify a capacitive load based at least in part on the capacitor.

[0117] In some examples of the apparatus, the first die comprises a logic die or a non-volatile memory die, and the second die comprises a DRAM die.

[0118] In some examples, an apparatus described herein can perform aspects of the method 700. The apparatus can include a substrate in contact with a plurality of conductive pads; an insulating material disposed on the substrate; a first die at least partially surrounded by the insulating material and coupled with a first conductive pad of the plurality of conductive pads by a first conductive line (e.g., conductive line 440-a), the first die including a component configured to generate a voltage for the first die; a second die at least partially surrounded by the insulating material and coupled with a second conductive pad of the plurality of conductive pads by a second conductive line (e.g., conductive line 440-b), the second die including a volatile memory including a plurality of capacitors configured as memory cells, and the second die including a capacitor isolated from the plurality of capacitors; and a third conductive line (e.g., conductive line 445) coupled with the component configured to generate a voltage for the capacitors of the first die and the second die, the capacitor of the second die being isolated from the plurality of capacitors configured as memory cells.

[0119] In some examples of the apparatus, the lateral portion of the third conductive line is under the first die and the second die and over the lateral portions of the first conductive line and the second conductive line.

[0120] In some examples of the apparatus, the third conductive line is disposed through the insulating material along a first direction and through the substrate along a second direction perpendicular to the first direction.

[0121] In some examples of the apparatus, the third conductive line couples a first terminal of the capacitor with the component. In such examples, the apparatus can include a fourth conductive line coupling a second terminal of the capacitor with the component.

[0122] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more methods can be combined.

[0123] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can be represented by a bus of signals where the bus can have a variety of bit widths.

[0124] A protocol can define one or more communication processes and one or more communication parameters that are supported for use by a device or component. For example, a protocol can define the meaning of various operations, the timing and frequency of those operations, various commands or signals or both, one or more addressing schemes for one or more memories, the type of communication for which pins are reserved, the size of data handled at various components such as interfaces, the data rate supported by various components such as interfaces, or the bandwidth supported by various components such as interfaces, among other parameters and metrics, or any combination thereof. The use of a shared protocol can enable interaction between devices, as each device can operate in a manner expected, recognized, and understood by another device. For example, two devices that support the same protocol can interact according to the strategies, processes, and parameters defined by the protocol, while two devices that support different protocols can not be compatible.

[0125] To illustrate, two devices that support different protocols can not be compatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices that support different protocols can not be compatible because the protocols define different transfer processes for responding to a single command (e.g., the burst length or number of bytes allowed in response to a command can be different). Merely converting a command to an action should not be interpreted as using two different protocols. Rather, two protocols can be considered different if the corresponding processes or parameters defined by the protocols vary. For example, a device can be said to support two different protocols if the device supports different addressing schemes or different transfer processes for responding to a command.

[0126] The terms“electronically communicate,”“electrically contact,”“connected,” and“coupled” can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or electrically in contact or connected or coupled) with each other if there are any conductive pathways between the components that can support the flow of signals between the components at any time. At any given time, the conductive pathways between components that are in electronic communication (or electrically in contact or connected or coupled) with each other can be open or closed based on the operation of the device that contains the connected components. The conductive pathways between connected components can be a direct conductive pathway between the components, or the conductive pathways between connected components can be an indirect conductive pathway that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0127] The term“coupled” refers to a state in which an open circuit relationship between components moves to a closed circuit relationship between the components, in which a signal can now pass between the components through a conductive path, from a state in which a signal cannot pass between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows a signal to flow between the other components on a conductive path in which the signal was not previously allowed to flow.

[0128] The term“isolated” refers to a relationship between components in which a signal cannot currently flow between the components. Components are isolated from each other if there is an open circuit between them. For example, two components isolated by a switch located between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller effects a change that prevents a signal from flowing between the components using a conductive path in which the signal was previously allowed to flow.

[0129] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during initial formation or growth of the substrate.

[0130] Switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive material (e.g., metal). The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. A transistor can be“turned on” or“activated” when a voltage greater than or equal to a threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be“turned off” or“deactivated” when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0131] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “superior.” The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0132] In the appended figures, similar components or features can have the same reference label. Further, various components of the same type can be distinguished by following the convention of using a first reference label to designate the first occurrence of a component and a second reference label to designate the second occurrence of the component. If only the first reference label is used in the description, then the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0133] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0134] The various illustrative block diagrams and modules described in connection with the disclosure herein can be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0135] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0136] Computer-readable media includes non-transitory computer storage media and communication media. Non-transitory computer storage media, as used herein, excludes transitory physical phenomena ("carrier waves") propagating through a medium (e.g., a voltage or current traveling on a wire, light pulses traveling through a fiber-optic cable, or radio waves). Non-transitory storage media does not comprise a propagating signal per se. Computer-readable media includes, but is not limited to, any medium that can be used to

[0137] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus to support voltage regulation, comprising: a first die including a component configured to generate a voltage for use by the first die; a second die including a volatile memory including a memory cell and a capacitor isolated from the memory cell, wherein the memory cell includes a capacitor; and a conductive line coupling the capacitor of the second die and the component configured to generate the voltage for use by the first die.

2. The apparatus of claim 1, further comprising: a substrate under the first die and the second die, wherein a portion of the conductive line passes through the substrate in a first direction.

3. The apparatus of claim 2, further comprising: an insulating material between the substrate and the first die and the second die, wherein a second section of the conductive line passes through the insulating material in a second direction different from the first direction.

4. The apparatus of claim 2, further comprising: a second conductive line coupling the first die to a first conductive pad of the substrate; and a third conductive line coupling the second die to a second conductive pad of the substrate, wherein the conductive line is disposed under the first die and the second die and a lateral section of the conductive line is disposed over a lateral section of the second conductive line and a lateral section of the third conductive line.

5. The apparatus of claim 1, wherein the second die includes: a circuit configured to access the memory cell of the volatile memory, wherein the capacitor is isolated from the circuit.

6. The apparatus of claim 1, wherein the conductive line couples a first terminal of the capacitor with the component, further comprising: a second conductive line coupling a second terminal of the capacitor with a ground reference.

7. The apparatus of claim 1, wherein the second die includes: a second capacitor isolated from the memory cell and in parallel with the capacitor, wherein the conductive line couples the second capacitor to the component.

8. The apparatus of claim 1, further comprising: a second conductive line configured to communicate information between the first die and the second die; and a third conductive line configured to communicate information between the first die and the second die, wherein the conductive line is disposed between the second conductive line and the third conductive line.

9. The apparatus of claim 1, further comprising: a switch component disposed along the conductive line and configured to modify a capacitive load based at least in part on the capacitor.

10. The apparatus of claim 1, wherein the first die includes a logic die or a non-volatile memory die, and wherein the second die includes a dynamic random access memory (DRAM) die.

11. A method to support voltage regulation, comprising: generating a voltage at a first component disposed on a first die; ​ ​ ​ adjusting the voltage using a capacitor coupled with the first component by a conductive line and disposed on a second die, the second die including a plurality of memory cells including the capacitor, wherein the voltage is adjusted with the capacitor isolated from the plurality of memory cells; and applying the voltage adjusted by the capacitor to one or more components disposed on the first die.

12. The method of claim 11, wherein the capacitor is included in a first set of capacitors used to adjust the voltage generated by the first component, the method further comprising: generating a second voltage at a second component disposed on the first die; and adjusting the second voltage using a second set of capacitors isolated from the plurality of memory cells and coupled with the second component by a second conductive line.

13. The method of claim 12, further comprising: activating a switch component coupled with the conductive line, the second conductive line, or a combination thereof to select the first set of capacitors, the second set of capacitors, or a combination thereof.

14. The method of claim 11, further comprising: modifying a capacitive load coupled with the first component, wherein the capacitive load is based at least in part on the capacitor.

15. The method of claim 14, further comprising: modifying a state of a switch component coupled with the conductive line to modify a number of capacitors connected in parallel from a first number to a second number.

16. The method of claim 11, further comprising: transmitting information between the first die and the second die by a second conductive line; and transmitting information between the first die and the second die by a third conductive line, wherein the conductive line is disposed between the second conductive line and the third conductive line.

17. The method of claim 11, wherein adjusting the voltage comprises maintaining a level of the voltage within a threshold range.

18. The method of claim 11, wherein applying the voltage comprises: activating one or more switch components to communicate the voltage to one or more components of the first die.

19. An apparatus to support voltage regulation, comprising: a substrate in contact with a plurality of conductive pads; an insulating material disposed on the substrate; a first die at least partially surrounded by the insulating material and coupled with a first conductive pad of the plurality of conductive pads by a first conductive line, the first die including a component configured to generate a voltage for the first die; a second die at least partially surrounded by the insulating material and coupled with a second conductive pad of the plurality of conductive pads by a second conductive line, the second die including a volatile memory including a plurality of capacitors configured as memory cells, and the second die including a capacitor isolated from the plurality of capacitors; and a switch component coupled with the first conductive line, the second conductive line, or a combination thereof to select the first set of capacitors, the second set of capacitors, or a combination thereof. a third conductive line coupled with the component configured to generate a voltage for the capacitor of the first die and the second die, the capacitor of the second die isolated from the plurality of capacitors configured as memory cells.

20. The apparatus of claim 19, wherein a lateral portion of the third conductive line is under the first die and the second die and above lateral portions of the first conductive line and the second conductive line.

21. The apparatus of claim 19, wherein the third conductive line is disposed through the insulating material in a first direction and through the substrate in a second direction perpendicular to the first direction.

22. The apparatus of claim 19, further comprising: a second capacitor isolated from the plurality of capacitors and in parallel with the capacitor.

23. The apparatus of claim 19, wherein the third conductive line couples a first terminal of the capacitor with the component, the apparatus further comprising: a fourth conductive line coupling a second terminal of the capacitor with the component.

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