Three-Dimensional Memory and Method of Forming the Same

Abstract

The present application provides a three-dimensional memory and a method for forming the same. The three-dimensional memory includes: a first semiconductor layer including an isolation structure, the isolation structure including amorphous silicon; at least one first through contact disposed within the first semiconductor layer, wherein the isolation structure circumferentially surrounds the first through contact; and a stacked structure located on the first semiconductor layer. The width of the isolation structure of the three-dimensional memory provided by the present application in its radial direction can be greater than the sum of the dimensions of the first through contact and the isolation layer in the same direction, which can reduce the parasitic capacitance between the first through contact and adjacent devices.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a three-dimensional memory and a method for forming the same. Background Art

[0002] In a three-dimensional memory, in order to reduce the parasitic capacitance between a through-silicon contact (TSC) and adjacent devices, an isolation structure can be provided between the TSC and the adjacent devices.

[0003] It should be understood that this background art section is intended to provide useful background for understanding the technology in part. However, these contents are not necessarily known or understood by those skilled in the art before the filing date of this application. Summary of the Invention

[0004] One aspect of this application provides a three-dimensional memory, including: a first semiconductor layer including an isolation structure, the isolation structure including amorphous silicon; at least one first through contact disposed within the first semiconductor layer, wherein the isolation structure circumferentially surrounds the first through contact; and a stacked structure located on the first semiconductor layer, the stacked structure including a first region corresponding to the isolation structure, and at least one second through contact extending into the first semiconductor layer is disposed within the first region, wherein the second through contact is disposed in the same direction as the first through contact and the ends of the two are in contact with each other.

[0005] In an embodiment of this application, the first semiconductor layer further includes at least one isolation layer, the isolation layer including amorphous silicon, wherein the isolation layer correspondingly covers the sidewall of the first through contact, and the isolation structure circumferentially surrounds the isolation layer.

[0006] In an embodiment of this application, the width of the isolation structure in its radial direction is greater than the sum of the cross-sectional dimensions of the isolation layer and the first through contact in the same direction.

[0007] In an embodiment of this application, the remaining part of the first semiconductor layer that does not include the isolation structure and the isolation layer includes polysilicon.

[0008] In an embodiment of this application, the stacked structure further includes a second region, the second region including a core region and a step region located on at least one side of the core region, wherein the first region is located on a side of the step region away from the core region.

[0009] In one embodiment of the present application, the three-dimensional memory further includes a second semiconductor layer and a peripheral circuit structure located on the second semiconductor layer, and the stacked structure is bonded to the peripheral circuit structure, wherein the second through contact is electrically connected to the peripheral circuit structure.

[0010] In one embodiment of the present application, the three-dimensional memory further includes a dielectric layer on a surface of the first semiconductor layer away from the stacked structure, wherein the first through contact penetrates the dielectric layer.

[0011] Another aspect of the present application provides a method for forming a three-dimensional memory, including: forming a stacked structure and a first semiconductor layer, the stacked structure being located on the first semiconductor layer, the first semiconductor layer including a first amorphous silicon portion and at least one second amorphous silicon portion, the first amorphous silicon portion surrounding the second amorphous silicon portion in its circumferential direction; and exposing the remaining portion of the first semiconductor layer that does not include the first amorphous silicon portion and the second amorphous silicon portion to a laser beam to convert the remaining portion into a polysilicon portion.

[0012] In one embodiment of the present application, the method for generating the laser beam includes at least one of an excimer laser method and a pulsed laser method.

[0013] In one embodiment of the present application, the method further includes: forming at least one first through contact in the second amorphous silicon portion, and retaining a part of the second amorphous silicon portion on the sidewall as an isolation layer to isolate the first through contact from the polysilicon portion.

[0014] In one embodiment of the present application, wherein the stacked structure includes a first region corresponding to the second amorphous silicon portion, and at least one second through contact extending into the second amorphous silicon portion is provided in the first region, and it is characterized in that forming at least one of the first through contacts includes:

[0015] Forming a dielectric layer on a surface of the first amorphous silicon portion, the second amorphous silicon portion, and the polysilicon portion away from the stacked structure; forming an opening penetrating the dielectric layer and the second amorphous silicon portion to expose an end of the second through contact, wherein a part of the second amorphous silicon portion is retained on the sidewall of the opening as the isolation layer; and,

[0016] Filling a conductive material in the opening to form the first through contact.

[0017] In one embodiment of the present application, a radial dimension range of the opening is from 200 angstroms to 2000 angstroms.

[0018] In one embodiment of the present application, the method further includes: forming a second semiconductor layer and a peripheral circuit structure, the peripheral circuit structure being located on the second semiconductor layer; and bonding the peripheral circuit structure and the stacked structure; wherein, the second through contact is electrically connected to the peripheral circuit structure.

[0019] For the three-dimensional memory and its forming method provided by the present application, on the one hand, the first amorphous silicon portion can serve as an isolation structure, so that the through-silicon contact formed subsequently in the second amorphous silicon portion is electrically isolated from the rest of the first semiconductor layer, thereby reducing the parasitic capacitance generated between the through-silicon contact and the rest of the first semiconductor layer.

[0020] On the other hand, a part of the second amorphous silicon portion is retained on the sidewall of the through-silicon contact as an isolation layer, thereby physically isolating the through-silicon contact from the rest of the first semiconductor layer and reducing the coupling effect between the through-silicon contact and the rest of the first semiconductor layer.

[0021] On yet another hand, the method of the present application reduces the step of forming the opening of the isolation structure while forming the opening of the through-silicon contact in the related art. Thus, the radial dimension of the isolation structure formed in the present application is no longer limited by the opening dimension of the through-silicon contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings. In the drawings,

[0023] Figure 1 is a schematic structural diagram of a method for forming a three-dimensional memory in the related art after forming a through-hole;

[0024] Figure 2 is a schematic structural diagram of a method for forming a three-dimensional memory in the related art after depositing an insulating material in the through-hole;

[0025] Figure 3 is a flowchart of a method for forming a three-dimensional memory according to one embodiment of the present application;

[0026] Figure 4 is a schematic structural diagram of a method for forming a three-dimensional memory according to one embodiment of the present application before laser annealing;

[0027] Figure 5 is a schematic structural diagram of a method for forming a three-dimensional memory according to one embodiment of the present application after laser annealing;

[0028] Figure 6Schematic diagram of the structure before ion implantation for a method of forming a three-dimensional memory according to an embodiment of the present application;

[0029] Figure 7 Schematic diagram of the structure after ion implantation for a method of forming a three-dimensional memory according to an embodiment of the present application;

[0030] Figure 8 Schematic diagram of the structure after removing the hard mask layer for a method of forming a three-dimensional memory according to an embodiment of the present application;

[0031] Figure 9 Schematic diagram of the structure after forming a dielectric layer for a method of forming a three-dimensional memory according to some embodiments of the present application;

[0032] Figure 10 Schematic diagram of the structure after forming a mask layer for a method of forming a three-dimensional memory according to some embodiments of the present application;

[0033] Figure 11 Schematic diagram of the structure after forming an opening for a method of forming a three-dimensional memory according to some embodiments of the present application;

[0034] Figure 12 Schematic diagram of the structure after forming a through-silicon contact for a method of forming a three-dimensional memory according to some embodiments of the present application;

[0035] Figure 13 Top view schematic diagram of a partial structure after forming a through-silicon contact for a method of forming a three-dimensional memory according to some embodiments of the present application. Detailed implementation manners

[0036] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0037] Note that references in the specification to "one embodiment", "an embodiment", "example embodiments", "some embodiments", etc. indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include the specific feature, structure, or characteristic. In addition, these phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such feature, structure, or characteristic in connection with other embodiments will be within the knowledge of those skilled in the relevant art, whether or not explicitly described.

[0038] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey a singular usage or to convey a plural usage, at least in part, depending on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors and can alternatively allow for the existence of additional factors that are not necessarily explicitly described, again at least in part, depending on the context.

[0039] It should be readily understood that the meanings of "on", "above", and "over" in the present disclosure should be interpreted in the broadest manner such that "on" not only means "directly on something" but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above" or "over" not only means the meaning of "above" or "over" something but can also include the meaning of "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0040] Furthermore, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. are used herein for ease of description to describe the relationship of one element or feature to another (or others) as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein can be interpreted similarly.

[0041] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entire upper structure or lower structure or can have a scope less than that of the lower structure or upper structure. Additionally, the layer can be a region of a uniform or non-uniform continuous structure having a thickness less than that of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0042] In the accompanying drawings, for the sake of illustration, the thickness, dimensions, and shape of the components have been slightly adjusted. The accompanying drawings are only examples and are not drawn to an exact scale. For example, as used herein, terms such as "substantially", "about", and similar terms are used as terms indicating approximation, rather than terms indicating degree, and are intended to illustrate the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0043] It should also be understood that the terms "comprises", "comprising", "has", "including", and / or "including having", when used in this specification, denote the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of listed features, rather than individual elements in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0044] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. It should also be understood that, unless explicitly stated in this application, words defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0045] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. In addition, unless explicitly defined or in contradiction with the context, the specific steps included in the methods described in this application do not have to be limited to the order described, but can be executed in any order or executed in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0046] The framework of a three-dimensional storage device is formed, for example, by bonding a memory cell array structure (referred to as a "stacked structure" in this application, also referred to as an "array wafer") and a peripheral circuit structure (also referred to as a "CMOS wafer"). In order to form an interconnect structure (e.g., for a power bus and metal wiring) for providing vertical interconnection between the stacked structure and the peripheral circuit structure, it is usually necessary to form TSCs in the semiconductor layer of the stacked structure or the peripheral circuit structure to achieve electrical connection between the metal layers on the front and back of the semiconductor layer. TSCs are used for signal and power connection (including high-voltage HV and low-voltage LV parts), and due to the coupling effect, it will cause instantaneous noise or large voltage surges in adjacent devices, and cause a large fluctuation in the source voltage of the device. Therefore, it is necessary to shield the through-silicon contacts from adjacent devices to alleviate the coupling effect.

[0047] As Figure 1 and 2 shown, in some manufacturing processes, after the bonding stack structure 402 and the peripheral circuit structure 202, a through-hole 102 of the TSC may be formed on the semiconductor layer 422 and the insulating layer 101. An isolation layer 611 is formed on the sidewall of the through-hole 102 by atomic layer deposition to weaken the coupling effect between the subsequently formed TSC and the semiconductor substrate 422. Since the aperture of the through-hole 102 is small, when depositing an insulating material to form the isolation layer 611, the insulating material inevitably covers both the sidewall and the bottom of the through-hole 102. In order to make electrical contact between the TSC formed in the through-hole 102 and the peripheral contacts of the stack structure 402, an additional etching process is required to remove the insulating material 612 covering the bottom of the through-hole 102, and this step is usually referred to as "Blank etching".

[0048] As an example, when forming the through-hole 102, in order to simplify the process, a trench 103 may be formed in the semiconductor layer 422 at the same time, and the trench 103 is used to be further processed into a back shallow trench isolation structure 104 (Back Shallow Trench Isolation, BSTI). For example, by using the same mask plate, the patterns of the through-hole 102 and the trench 103 carried by it are transferred into the photoresist mask layer for etching to form the through-hole 102 and the trench 103. The BSTI 104 can be used to reduce interference from adjacent devices, including but not limited to providing shielding between adjacent devices, reducing parasitic capacitance, and reducing leakage current and other functions.

[0049] In some examples, in order to further simplify the process, when performing atomic layer deposition to form the isolation layer 611 in the through-hole 102, the trench 103 can be filled with an insulating material at the same time to form the BSTI 104. Therefore, the radial dimension of the trench 103 needs to be smaller than the radial dimension of the through-hole 102, so that after performing the atomic layer deposition process, the trench 103 is filled with the insulating material, while only the isolation layer 611 is formed on the sidewall of the through-hole 102, and the remaining space of the through-hole 102 is reserved for forming the TSC. Therefore, the width of the BSTI formed by the above method is limited, which is not conducive to reducing parasitic capacitance.

[0050] The present application provides a three-dimensional memory and a method for forming the same to address at least one of the above problems. It should be noted that the three-dimensional memory in the embodiments of the present application may be a part of a non-monolithic 3D memory device, which includes a peripheral circuit structure and a stacked structure, and the two are bonded face to face. In some embodiments, the stacked structure is flipped and face-down towards the peripheral circuit structure, and the stacked structure is located on the peripheral circuit structure through hybrid bonding; in another embodiment, the peripheral circuit structure is flipped and face-down towards the stacked structure, and the peripheral circuit structure is located on the stacked structure through hybrid bonding.

[0051] Embodiment 1

[0052] Figure 3 FIG. 1000 is a flowchart of a method for forming a three-dimensional memory 100 according to Embodiment 1. As Figure 3 shown, the method 1000 for forming a three-dimensional memory 100 includes:

[0053] S1: Form a stacked structure and a first semiconductor layer, the stacked structure being located on the first semiconductor layer, the first semiconductor layer including a first amorphous silicon portion and at least one second amorphous silicon portion, the first amorphous silicon portion surrounding the second amorphous silicon portion in its circumferential direction;

[0054] S2: Expose the remaining portion of the first semiconductor layer that does not include the first amorphous silicon portion and the second amorphous silicon portion to a laser beam to convert the remaining portion into a polycrystalline silicon portion;

[0055] S3: Form a dielectric layer on the surfaces of the first amorphous silicon portion, the second amorphous silicon portion, and the polycrystalline silicon portion that are away from the stacked structure;

[0056] S4: Form an opening through the dielectric layer and the second amorphous silicon portion to expose the end of a second through contact, wherein a part of the second amorphous silicon portion is retained on the sidewall of the opening as an isolation layer;

[0057] S5: Fill the opening with a conductive material to form a first through contact.

[0058] The following will be described respectively with reference to Figures 4 - 13The schematic diagrams of the respective stages of the method for forming a three-dimensional memory shown above separately describe the above steps S1 - S5. When describing the embodiments of the present application, for ease of explanation, the cross-sectional views showing the device structure are locally enlarged not in accordance with the general scale, and the said schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included. It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the operations described.

[0059] Referring to Figure 3 , the method begins with operation S1, where a stacked structure and a first semiconductor layer can be formed. The stacked structure is located on the first semiconductor layer, and the first semiconductor layer includes a first amorphous silicon portion and at least one second amorphous silicon portion. The first amorphous silicon portion surrounds the second amorphous silicon portion in its circumferential direction. Figure 4 The corresponding structure is shown.

[0060] As Figure 4 shown, the three-dimensional memory provided by the embodiment of the present application is a bonded device, including a first semiconductor structure 400 and a second semiconductor structure 200. According to some embodiments, the first semiconductor structure 400 and the second semiconductor structure 200 are joined at the bonding interface 300.

[0061] According to some embodiments, the first semiconductor structure 400 of the three-dimensional memory includes a first semiconductor layer 401, a stacked structure 402, and a first interconnect layer 403 sequentially disposed on the first semiconductor layer 401.

[0062] In some embodiments, the first semiconductor layer 401 may include, for example, amorphous silicon. As an option, the first semiconductor layer 401 can be formed on the side of the stacked structure 402 away from the second semiconductor structure 200. Exemplarily, the first semiconductor layer can also be P-type doped or N-type doped as needed.

[0063] Exemplarily, as Figure 4 shown, the stacked structure 402 includes a first region 405 and a second region 406. Among them, the first region 405 is provided with a through second through contact 410 (which can also be called a "peripheral contact"), and the second through contact 410 can extend into the first semiconductor layer 401; the second region 406 includes a core region and a step region located on at least one side of the core region. The first region 406 is located on the side of the step region away from the core region. In some examples, the first semiconductor structure 400 further includes an insulating flat layer 409, which covers the step region and fills the first region 405 to support the second through contact 410.

[0064] In some embodiments, the stacked structure 402 includes gate conductor layers 428 and dielectric layers 429 that are alternately arranged, and the dielectric layer 429 and the adjacent gate conductor layer 428 form a dielectric layer / gate layer pair. Exemplarily, the number of pairs can be selected according to various application scenarios. For example, the number of pairs can be 32, 64, 96, 128, 160, 192, 224, 256 or more.

[0065] In some embodiments, the gate conductor layer 428 includes a conductor material, which may include W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicides (such as NiSix, WSix, CoSix, TiSix) or any combination thereof. Dielectric materials that can be used for the dielectric layer 429 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., alumina, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one example, the gate conductor layer 428 can be tungsten, and the dielectric layer 429 can be silicon oxide.

[0066] In some embodiments, the stacked structure 402 further includes a channel structure 411 that penetrates and extends into the first semiconductor layer 401. The position where each gate conductor layer 428 intersects the channel structure 411 constitutes a storage cell. Exemplarily, the channel structure 411 includes a storage function layer (not shown) and a channel layer (not shown) that are sequentially formed on the sidewalls and bottom of a channel hole (not shown). The remaining space in the channel hole can also be filled with an insulating layer material. Exemplarily, the channel layer can be electrically connected to the first semiconductor layer 401 through an epitaxial layer. The storage function layer includes a blocking layer (not shown), a charge storage layer (not shown), and a tunneling layer (not shown) that are sequentially formed in the channel hole; wherein, the material of the blocking layer includes an oxide, such as silicon oxide; the material of the charge storage layer can include an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor microparticles; the material of the tunneling layer includes an oxide, such as silicon oxide.

[0067] In some embodiments, contact holes can be formed in the step region of the stacked structure 402 and filled with a conductive material to lead out the word line (also referred to as "word line contact") and connect it to the peripheral circuit structure 202.

[0068] In some embodiments, the stacked structure 402 further includes a gate line gap structure 421 that penetrates into the first semiconductor layer 401. It includes a gate line gap that penetrates the stacked structure 402 and an insulating layer and a filling layer (not shown) disposed in the gate line gap. The insulating layer includes an insulating material and can be used for electrically isolating adjacent storage cells. The filling layer includes a conductive material and can serve as an extraction channel for common source line electrical connection.

[0069] In some embodiments, the first interconnect layer 403 includes a first dielectric layer 413 and one or more first interconnect structures 423 penetrating through the first dielectric layer 413. Each of the first interconnect structures 423 includes a first interconnect contact 424 disposed perpendicular or substantially perpendicular to the first semiconductor layer 401 and a first interconnect line 425 disposed parallel to the first semiconductor layer 401. One or more portions of the first interconnect structures 423 may be exposed on the top surface of the first dielectric layer 413. The materials of the first interconnect contact 424 and the first interconnect line 425 include conductive materials, such as tungsten, cobalt, copper, aluminum, polysilicon, silicide, or any combination thereof. The material of the first dielectric layer 413 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0070] As Figure 4 shown, the second semiconductor structure 200 includes a second semiconductor layer 201, which may include single-crystalline silicon (c-Si)), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable material.

[0071] According to some embodiments, the second semiconductor structure 200 may include peripheral circuit structures 202 on the second semiconductor layer 201. In some embodiments, the peripheral circuit structures 202 are configured to control and sense the three-dimensional memory device 100. The peripheral circuit structures 202 may include transistors (not shown) formed on the second semiconductor layer 201, wherein a portion of the transistors is formed in the second semiconductor layer 201.

[0072] According to some embodiments, the second semiconductor structure 200 of the three-dimensional memory further includes a second interconnect layer 204 above the peripheral circuit structures 202. The second interconnect layer 204 includes a second dielectric layer 224 and second interconnect structures 205 penetrating through the second dielectric layer 224. Each of the second interconnect structures 205 includes a second interconnect contact 215 disposed perpendicular or substantially perpendicular to the second semiconductor layer 201 and a second interconnect line 216 disposed parallel to the second semiconductor layer 201. One or more portions of the second interconnect structures 205 may be exposed on the side of the second dielectric layer 224 facing the first semiconductor structure 400. The material of the second interconnect structures 205 may be a conductive material, such as tungsten, cobalt, copper, aluminum, or any combination thereof. The material of the second dielectric layer 224 may be the same as the material of the first dielectric layer 413, which will not be elaborated here.

[0073] In some embodiments, when the peripheral circuit structures 202 are hybrid-bonded face-to-face with the stack structure 402, the second interconnect structures 205 and the first interconnect structures 423 are correspondingly joined at the bonding interface 300.

[0074] Refer again toFigure 4 In Figure 4 , the first semiconductor layer 401 may include a first amorphous silicon portion B11 and two second amorphous silicon portions B21. Among them, the first amorphous silicon portion B11 surrounds the two second amorphous silicon portions B21 in its circumferential direction. The radial width of the first amorphous silicon portion B11 may be greater than the cross-sectional dimension of the second amorphous silicon portion B21 in the same direction, for example. In some examples, the two second vias 410 may correspondingly extend into the two second amorphous silicon portions B21. It should be understood that the number of the second vias 410 is only set to clearly show the stacked structure 402, and the actual number of the second vias 410 may be set as needed. For example, more than two second vias may be formed as needed and may correspondingly extend into multiple second amorphous silicon portions 410 of the first semiconductor layer 401.

[0075] Refer to Figure 3 In Figure 3 , the method proceeds to operation S2, and the remaining portion of the first semiconductor layer excluding the first amorphous silicon portion and the second amorphous silicon portion may be exposed to a laser beam to convert the remaining portion into a polycrystalline silicon portion. Figure 5 The corresponding structure is shown.

[0076] As Figure 5 shown, in some examples, the remaining portion of the first semiconductor layer 401 ( Figure 4 ) excluding the first amorphous silicon portion B11 and the two second amorphous silicon portions B21 may be exposed to a laser beam for laser annealing to convert the remaining portion into a polycrystalline silicon portion 401'.

[0077] In one embodiment, the method for generating a laser beam includes at least one of an excimer laser method and a pulsed laser. In an example where the first semiconductor layer 401 includes amorphous silicon, the laser beam emitted by the excimer laser may be incident on the remaining portion excluding the first amorphous silicon portion B11 and the two second amorphous silicon portions B21 from a surface of the semiconductor layer 401 ( Figure 4 ) facing away from the stacked structure 402. Among them, the spot size generated by the laser beam may be at the micron level, and the depth range of the laser beam entering the semiconductor layer 401 may be 100 - 500 nm. The above laser annealing conditions can induce the crystallization of amorphous silicon into polycrystalline silicon, thereby forming the polycrystalline silicon portion 401'.

[0078] In another example, a pulsed laser beam may also be applied to the remaining portion of the semiconductor layer 401 excluding the first amorphous silicon portion B11 and the second amorphous silicon portion B21. The device for applying the pulsed laser beam may include a gas laser, and the gas generated by the gas laser may include one or any combination of Ar, Kr, and CO2. The pulsed laser method can crystallize amorphous silicon into polycrystalline silicon with high mobility, which is beneficial to improving the electrical performance of the device.

[0079] In some other embodiments, a single-layer or multi-layer structure including amorphous silicon may be formed on the side of the stacked structure 402 away from the second semiconductor structure 200, and then the amorphous silicon is annealed and transformed into polycrystalline silicon to form the first semiconductor layer 401. For example, a thermal annealing or laser annealing process may be performed on the single-layer or multi-layer structure including amorphous silicon to transform the amorphous silicon into polycrystalline silicon to form the first semiconductor layer 401. Exemplarily, the single-layer or multi-layer structure including amorphous silicon may also be P-type doped or N-type doped as needed, so that the first semiconductor layer 401 formed by annealing may include P-type doped polycrystalline silicon or N-type doped polycrystalline silicon.

[0080] As Figure 6 shown, in an example where the first semiconductor layer 401 is polycrystalline silicon, the first semiconductor layer 401 may include a first portion A11 and two second portions A21. Among them, the first portion A11 surrounds the two second portions A21 in its circumferential direction, and the radial width of the first portion A11 may be greater than the cross-sectional dimension of the second portion A21 in the same direction, for example. In some examples, the two second through contacts 410 may correspondingly extend into the two second portions A21. It should be understood that the number of the second through contacts 410 is set only to clearly show the stacked structure 402, and the actual number of the second through contacts may be set as needed. For example, more than two second through contacts may be formed as needed and may correspondingly extend into multiple second portions of the first semiconductor layer 401.

[0081] In some examples, an ion implantation process may be performed on the first portion A11 and the two second portions A21 simultaneously to transform the first portion A11 and the two second portions A21 into a first amorphous silicon portion B11 and two second amorphous silicon portions B21, respectively. Figure 7 shows the corresponding structure.

[0082] As Figure 7 shown, in some examples, a hard mask layer 500 may be formed on a surface of the first semiconductor layer 401 away from the stacked structure 402. The composition material of the hard mask layer 500 may be, for example, silicon nitride. Subsequently, the hard mask layer 500 is patterned to expose Figure 6 the first portion A11 and the two second portions A21 in 15 atom / cm 2 to 1×10 17 atom / cm 2Between them, the energy range of ion implantation is between 30 keV and 80 keV, and the depth range of ion implantation is between 50 - 500 nm. Under the above ion implantation conditions, the crystal plane orientation and lattice structure of polysilicon are damaged, so that the first part A11 and the second part A21 can be respectively transformed into the first amorphous silicon part B11 and the second amorphous silicon part B21. Among them, the remaining part of the first semiconductor layer 401 can be the polysilicon part 401' of some embodiments of the present application.

[0083] In some embodiments, the first semiconductor layer 401 may include polysilicon doped with a first conduction type, and ions of a second conduction type can be used to perform ion implantation on the first part A11 and the second part A21 simultaneously, so that the first part A11 and the second part A21 are respectively transformed into the first amorphous silicon part doped with the second conduction type and the second amorphous silicon part B21 doped with the second conduction type.

[0084] As an example, the first semiconductor layer 401 may include N-type doped polysilicon. By implanting P-type conductive ions such as B ions into the first part A11 and the second part A21 of the first semiconductor layer 401, the first part A11 can be transformed into the first amorphous silicon part doped with P-type, and at the same time, the second part A21 can be transformed into the second amorphous silicon part B21 doped with P-type. In some examples, the first amorphous silicon part doped with P-type and the second amorphous silicon part B21 doped with P-type can respectively form PN junctions with the N-type doped polysilicon of the first semiconductor layer 401.

[0085] As Figure 8 shown, in some examples, after the first amorphous silicon part B11 and the second amorphous silicon part B21 are formed, the hard mask layer 500 can be removed.

[0086] In some examples, the first amorphous silicon part B11 can form an annular structure surrounding the second amorphous silicon part B21 in its circumferential direction, and this annular structure can be used as an isolation structure to physically isolate the device enclosed therein from the polysilicon part 401'.

[0087] In some examples, the radial width of the first amorphous silicon part B11 can be, for example, greater than the cross-sectional size of the second amorphous silicon part B21 in the same direction.

[0088] Referring to Figure 2 , the method continues to operation S3, and a dielectric layer can be formed on the surfaces of the first amorphous silicon part, the second amorphous silicon part, and the polysilicon part away from the stacked structure. Figure 9 shows the corresponding structure.

[0089] As Figure 9As shown, a dielectric layer 490 can be formed on a surface of the first semiconductor layer 401 away from the stack structure 402 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the dielectric layer 490 can include, for example, silicon oxide.

[0090] Referring Figure 2 , the method proceeds to operation S4, where an opening can be formed through the dielectric layer and the second amorphous silicon portion to expose the end of the second through contact. Here, a portion of the second amorphous silicon portion is retained as an isolation layer on the sidewall of the opening. Figure 11 The corresponding structure is shown.

[0091] As Figure 10 shown, in some examples, the opening can be formed through a lithography process. For example, a patterned mask layer 480 can be formed on the top surface of the dielectric layer 490 to expose a surface of the dielectric layer 490 corresponding to the second amorphous silicon portion B21 away from the stack structure 402, and then the dielectric layer 490 and the second amorphous silicon portion B21 are etched through this exposed surface.

[0092] As Figure 11 shown, in some embodiments, the dielectric layer 490 and the second amorphous silicon portion B21 can be etched from top to bottom to form an opening 460, thereby exposing the end of the second through contact 410. Here, the radial dimension of the opening formed in the second amorphous silicon portion B21 can be smaller than the radial dimension of the second amorphous silicon portion B21 before the opening is formed, so that a portion of the second amorphous silicon B21 is retained as an isolation layer B22 on the sidewall of the opening 460.

[0093] Exemplarily, a dry etching process such as ion milling etching, plasma etching, reactive ion etching, and laser etching can be used to form the opening 460. Subsequently, the mask layer 480 can be removed, for example, in an ashing and / or wet stripping process.

[0094] In some examples, the critical dimension of the opening 460 ranges from 200 angstroms to 2000 angstroms.

[0095] Referring Figure 2 , the method proceeds to operation S5, where a conductive material can be filled in the opening to form a first through contact. Figure 12 The corresponding structure is shown.

[0096] As Figure 12As shown, in some examples, after removing the mask layer 480, a conductive material may be filled in the opening 460 to form a first through contact 440 (also referred to as a "through silicon contact"), and the conductive material may include, for example, tungsten, cobalt, copper, aluminum, or any combination thereof. Since a portion of the second amorphous silicon portion B21 is retained on the sidewall of the opening 460 as an isolation layer B22, the isolation layer B22 may cover the sidewall of the first through contact 440, thereby physically isolating the first through contact 440 from the rest of the first semiconductor layer 401, and reducing the coupling effect between the rest of the first semiconductor layer 401 and the first through contact 440.

[0097] like Figure 13 As shown, in some embodiments, the first amorphous silicon portion B11 may form an annular structure surrounding the second amorphous silicon portion B21 in its circumference, and the annular structure may serve as an isolation structure to electrically isolate the surrounded first through contact 440 from the rest of the first semiconductor layer 401, thereby reducing the parasitic capacitance between the first through contact 440 and the rest of the first semiconductor layer 401.

[0098] like Figure 13 As shown, illustratively, the width W of the first amorphous silicon portion B11 in its radial direction may be greater than the dimension D in the same direction of the first through contact 440 covered with the isolation layer B22, thereby further reducing the parasitic capacitance generated between the first through contact 440 and the rest of the first semiconductor layer 401.

[0099] The three-dimensional memory and the method for forming the same provided by the present application, on the one hand, the first amorphous silicon portion can be used as an isolation structure, so that the through-silicon contact subsequently formed in the second amorphous silicon portion is electrically isolated from the rest of the first semiconductor layer, thereby reducing the parasitic capacitance generated between the through-silicon contact and the rest of the first semiconductor layer.

[0100] On the other hand, the side wall of the through silicon contact retains a portion of the second amorphous silicon portion as an isolation layer, thereby physically isolating the through silicon contact from the rest of the first semiconductor layer and reducing the coupling effect between the through silicon contact and the rest of the first semiconductor layer.

[0101] On the other hand, the method of the present application reduces the step of forming the opening of the isolation structure while forming the opening through the silicon contact in the related art, so that the radial size of the isolation structure formed by the present application is no longer limited by the size of the opening through the silicon contact.

[0102] In one embodiment of the present application, after forming the first through contact 440, a metal layer and an insulating layer (also referred to as a “back-end process interconnect layer”) may be formed on a surface of the dielectric layer 490 away from the stack structure 402. Figure 12(not shown) for leading out pads to transmit electrical signals. The metal layer may include a conductive material, which includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof. In one example, the metal layer includes Al. Although not shown in Figure 12 it should be understood that the metal layer can be patterned to form various types of backside interconnect structures. In some embodiments, a passivation layer may also be formed on the insulating layer, which can serve as the outermost layer for passivating and protecting the three-dimensional memory. A portion of the metal layer may be exposed from the passivation layer as bonding pads.

[0103] Another aspect of the present application provides a three-dimensional memory 100, as Figure 12 shown. The three-dimensional memory 100 is a bonding device, including a first semiconductor structure 400 and a second semiconductor structure 200. According to some embodiments, the first semiconductor structure 400 and the second semiconductor structure 200 are joined at a bonding interface 300.

[0104] In some examples, the first semiconductor structure 400 includes: a first semiconductor layer 401, a stacked structure 402, and a first through contact 440. Among them, the stacked structure 402 includes a first region 405 and a second region 406. The first region 405 is provided with a through second through contact 410, and the second through contact 410 can extend into the first semiconductor layer 401; the second region 406 includes a core region and a stepped region located on at least one side of the core region, and the first region 406 is located on the side of the stepped region away from the core region.

[0105] Exemplarily, the first semiconductor layer can also be P-type doped or N-type doped as needed.

[0106] Referring again to Figure 12 , in some embodiments, the first semiconductor layer 401 includes a first through contact 440 and a corresponding isolation layer B22. The isolation layer B22 may include amorphous silicon, and the amorphous silicon may correspondingly cover the sidewalls of the first through contact 440. Among them, the first through contact 440 and the second through contact 410 are arranged in the same direction and the ends of the two are in contact with each other. In some examples, the isolation layer can also correspondingly cover the sidewalls of the second through contact.

[0107] In some examples, the first semiconductor layer 401 further includes an isolation structure (also referred to as "the first amorphous silicon portion B11"), and the isolation structure can surround the isolation layer B22 and the first through contact 440 in its circumferential direction.

[0108] In some examples, the first amorphous silicon portion B11 may form an annular structure surrounding the second amorphous silicon portion B21 in its circumferential direction. This annular structure can serve as an isolation structure, thereby electrically isolating the devices enclosed therein from the devices outside the isolation structure, and reducing the parasitic capacitance generated between the first through contact 440 and the rest of the first semiconductor layer 401.

[0109] In some examples, the rest of the first semiconductor layer 401 that does not include the isolation layer B22 and the isolation structure may include polysilicon. The isolation layer B22 can be used to physically isolate the first through contact 440 from the rest of the first semiconductor layer 401, thereby reducing the coupling effect between the first through contact 440 and the rest and the stack structure 402.

[0110] In some examples, the first semiconductor structure 400 further includes a dielectric layer 490 located on a surface of the first semiconductor layer 401 away from the stack structure 402. Among them, the first through contact 440 can penetrate the dielectric layer 490, and the material of the dielectric layer 490 may include, for example, silicon oxide.

[0111] According to some embodiments, the second semiconductor structure 200 may include a second semiconductor layer 201 and a peripheral circuit structure 202 located on the second semiconductor layer 201. The second through contact 410 is electrically connected to the peripheral circuit structure 202 through an interconnect structure.

[0112] Exemplarily, as Figure 10 shown, the isolation structure (also referred to as the "first amorphous silicon portion B11"), the width W of which in the radial direction is not limited by the sizes of the first through contact 440 and the isolation layer B22, can be greater than the size of the first through contact 440 in the same direction, and can be greater than the sum D of the sizes of the isolation layer B22 and the first through contact 440 in the same direction, which can further reduce the parasitic capacitance between the first through contact 440 and adjacent devices.

[0113] The above description is only for the embodiments of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A three-dimensional memory, characterized in that, Comprising: A first semiconductor layer, including an isolation structure, the isolation structure including amorphous silicon; At least one first through-contact, disposed within the first semiconductor layer, wherein the isolation structure surrounds the first through-contact in its circumferential direction; and, A stacked structure, located on the first semiconductor layer, the stacked structure including a first region corresponding to the isolation structure, at least one second through-contact extending into the first semiconductor layer being provided within the first region, wherein the second through-contact is arranged in the same direction as the first through-contact and the ends of the two are in contact with each other.

2. The three-dimensional memory according to claim 1, wherein The first semiconductor layer further includes at least one isolation layer, the isolation layer including amorphous silicon, wherein the isolation layer correspondingly covers the sidewall of the first through-contact, and the isolation structure surrounds the isolation layer in its circumferential direction.

3. The three-dimensional memory according to claim 2, wherein The width of the isolation structure in its radial direction is greater than the sum of the cross-sectional dimensions of the isolation layer and the first through-contact in the same direction.

4. The three-dimensional memory according to claim 3, wherein The remaining part of the first semiconductor layer that does not include the isolation structure and the isolation layer includes polycrystalline silicon.

5. The three-dimensional memory according to claim 1, wherein The stacked structure further includes a second region, the second region including a core region and a stepped region located on at least one side of the core region, wherein the first region is located on the side of the stepped region away from the core region.

6. The three-dimensional memory according to claim 1, wherein, The three-dimensional memory further includes a second semiconductor layer and a peripheral circuit structure located on the second semiconductor layer, the stacked structure being bonded to the peripheral circuit structure, wherein the second through-contact is electrically connected to the peripheral circuit structure.

7. The three-dimensional memory according to claim 1, characterized in that, The three-dimensional memory further includes a dielectric layer located on the surface of the first semiconductor layer away from the stacked structure, wherein the first through-contact penetrates the dielectric layer.

8. A method for forming a three-dimensional memory, comprising: Forming a stacked structure and a first semiconductor layer, the stacked structure being located on the first semiconductor layer, the first semiconductor layer including a first amorphous silicon portion and at least one second amorphous silicon portion, the first amorphous silicon portion surrounding the second amorphous silicon portion in its circumferential direction; Exposing the remaining part of the first semiconductor layer that does not include the first amorphous silicon portion and the second amorphous silicon portion to a laser beam to convert the remaining part into a polycrystalline silicon portion, the first amorphous silicon portion serving as an isolation structure; And Forming at least one first through-contact in the second amorphous silicon portion.

9. The method according to claim 8, wherein The method for generating the laser beam includes at least one of an excimer laser method and a pulsed laser method.

10. The method according to claim 8, wherein The first semiconductor layer includes amorphous silicon, and a part of the second amorphous silicon portion is retained on the sidewall of the first through-contact as an isolation layer to isolate the first through-contact from the polycrystalline silicon portion.

11. The method according to claim 10, wherein, The stacked structure includes a first region corresponding to the second amorphous silicon portion, at least one second through-contact extending into the second amorphous silicon portion being provided within the first region, characterized in that forming at least one of the first through-contacts includes: Forming a dielectric layer on the surfaces of the first amorphous silicon portion, the second amorphous silicon portion, and the polycrystalline silicon portion away from the stacked structure; Form an opening through the dielectric layer and the second amorphous silicon portion to expose an end of the second through-contact, wherein sidewalls of the opening retain a portion of the second amorphous silicon portion as the isolation layer; and, Fill the opening with a conductive material to form the first through-contact.

12. The method according to claim 11, wherein A radial dimension of the opening ranges from 200 angstroms to 2000 angstroms.

13. The method according to claim 11, characterized in that The method further includes: Form a second semiconductor layer and a peripheral circuit structure, the peripheral circuit structure being located on the second semiconductor layer; and, Bond the peripheral circuit structure and the stacked structure; wherein the second through-contact is electrically connected to the peripheral circuit structure.

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