Three-dimensional memory and methods of forming the same

Abstract

The application provides a three-dimensional memory and a forming method thereof. The three-dimensional memory comprises a first semiconductor layer, an isolation structure, at least one first through-contact, and a stack structure. The isolation structure comprises amorphous silicon. The at least one first through-contact is arranged in the first semiconductor layer, and the isolation structure surrounds the first through-contact in a circumferential direction. The stack structure is arranged on the first semiconductor layer. The width of the isolation structure of the three-dimensional memory provided by the application in a radial direction can be greater than the sum of the sizes of the first through-contact and the isolation layer in the same direction, so that the parasitic capacitance of the first through-contact and the adjacent device can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a three-dimensional memory and a method for forming the same. Background Technology

[0002] In 3D memory, in order to reduce the parasitic capacitance between the through silicon contact (TSC) and adjacent devices, an isolation structure can be set between the TSC and adjacent devices.

[0003] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0004] This application provides a three-dimensional memory, comprising: a first semiconductor layer including an isolation structure comprising amorphous silicon; at least one first through contact disposed within the first semiconductor layer, wherein the isolation structure surrounds the first through contact in its circumferential direction; and a stacked structure located on the first semiconductor layer.

[0005] In one embodiment of this application, the first semiconductor layer further includes at least one isolation layer comprising amorphous silicon, wherein the isolation layer correspondingly covers the sidewall of the first through contact, and the isolation structure surrounds the isolation layer in its circumferential direction.

[0006] In one embodiment of this application, the width of the isolation structure in its radial direction is greater than the sum of the cross-sectional dimensions of the isolation layer and the first through contact in the same direction.

[0007] In one embodiment of this application, the first semiconductor layer, excluding the isolation structure and the remainder of the isolation layer, comprises polycrystalline silicon.

[0008] In one embodiment of this application, the remaining portion of the first semiconductor layer comprises polycrystalline silicon doped with a first conductivity type; and the isolation structure and / or the isolation layer comprises amorphous silicon doped with a second conductivity type.

[0009] In one embodiment of this application, the stacked structure includes a first region corresponding to the isolation structure, the first region having at least one second through contact extending into the first semiconductor layer, wherein the second through contact and the first through contact are arranged in the same direction and their ends are in contact with each other, and the isolation layer isolates the second through contact from the remaining portion.

[0010] In one embodiment of this application, the three-dimensional memory further includes a dielectric layer located on the surface of the first semiconductor layer away from the stacked structure, wherein the first through-contact penetrates the dielectric layer.

[0011] In one embodiment of this application, the stacked structure further includes a second region, the second region including a core region and a step region located on at least one side of the core region, wherein the first region is located on the side of the step region away from the core region.

[0012] In one embodiment of this application, the three-dimensional memory further includes a second semiconductor layer and a peripheral circuit structure located on the second semiconductor layer, the stacked structure being bonded to the peripheral circuit structure, wherein the second through contact is electrically connected to the peripheral circuit structure.

[0013] Another aspect of this application provides a method for forming a three-dimensional memory, comprising: forming a stacked structure and a first semiconductor layer, the stacked structure being located on the first semiconductor layer, the first semiconductor layer including a first portion and at least one second portion, the first portion surrounding the second portion in its circumferential direction; and performing an ion implantation process on the first portion to transform the first portion into a first amorphous silicon portion.

[0014] In one embodiment of this application, the first semiconductor layer is formed by annealing amorphous silicon into polycrystalline silicon.

[0015] In one embodiment of this application, the method further includes performing the same ion implantation process on the second portion to convert the second portion into a second amorphous silicon portion.

[0016] In one embodiment of this application, the first semiconductor layer further includes a remaining portion other than the first portion and the second portion, and the method further includes: forming at least one first through contact in the second amorphous silicon portion, wherein a portion of the second amorphous silicon portion is retained on its sidewall as an isolation layer to isolate the first through contact from the remaining portion.

[0017] In one embodiment of this application, the first semiconductor layer comprises polycrystalline silicon doped with a first conductivity type, and performing the ion implantation process in the first portion includes:

[0018] The ion implantation process of the second conductivity type ions is performed in the first portion to transform the first portion into the first amorphous silicon portion.

[0019] In one embodiment of this application, the method further includes performing the same ion implantation process of the second conductivity type ions on the second portion to transform the second portion into the second amorphous silicon portion.

[0020] In one embodiment of this application, performing the ion implantation process on the first portion includes: forming a hard mask layer on a surface of the first semiconductor layer away from the stacked structure; patterning the hard mask layer to expose the first portion; and performing the ion implantation process on the first portion with the hard mask layer as a mask, such that the first portion is transformed into the first amorphous silicon portion.

[0021] In one embodiment of this application, the method includes: exposing the second portion while patterning the hard mask layer to expose the first portion; and performing the same ion implantation process on the second portion while performing the ion implantation on the first portion with the hard mask layer as a mask, so that the second portion is transformed into a second amorphous silicon portion.

[0022] In one embodiment of this application, the stacked structure includes a first region corresponding to the second amorphous silicon portion, the first region having at least one second through contact extending into the second amorphous silicon portion, characterized in that forming at least one first through contact includes: forming a dielectric layer on a surface of the first semiconductor layer away from the stacked structure; forming an opening through the dielectric layer and the second amorphous silicon portion to expose an end of the second through contact, wherein the sidewall of the opening retains a portion of the second amorphous silicon portion as the isolation layer; and filling the opening with a conductive material to form the first through contact.

[0023] In one embodiment of this application, the radial dimension of the opening ranges from 200 angstroms to 2000 angstroms.

[0024] In one embodiment of this application, the dose range of ions implanted by the ion implantation process is 1×10⁻⁶. 15 atom / cm 2 Up to 1×10 17 atom / cm 2 .

[0025] In one embodiment of this application, the energy range of the ions implanted by the ion implantation process is 30 keV to 80 keV.

[0026] In one embodiment of this application, the method further includes: forming a second semiconductor layer and a peripheral circuit structure, the peripheral circuit structure being located on the second semiconductor layer; and bonding the peripheral circuit structure and the stacked structure; wherein the second through contact is electrically connected to the peripheral circuit structure.

[0027] The method for forming a three-dimensional memory provided in this application selectively transforms a first portion of a first semiconductor layer and a second portion surrounded by the first portion into a first amorphous silicon portion and a second amorphous silicon portion, respectively, through mask-assisted ion implantation. On the one hand, the first amorphous silicon portion can serve as an isolation structure, so that the first through-contact subsequently formed in the second amorphous silicon portion is electrically isolated from the rest of the first semiconductor layer, thereby reducing the parasitic capacitance generated between the first through-contact and the rest of the first semiconductor layer.

[0028] On the other hand, a portion of the second amorphous silicon portion is retained on the sidewall of the first through contact as an isolation layer, thereby physically isolating the first through contact from the rest of the first semiconductor layer and reducing the coupling effect between the first through contact and the rest of the first semiconductor layer.

[0029] Furthermore, since the first portion of the first semiconductor layer is directly transformed into the first amorphous silicon portion as the isolation structure through ion implantation, the step of forming the opening of the isolation structure at the same time as forming the opening of the first through contact is avoided in related technologies. Therefore, the radial dimension of the isolation structure formed in this application is no longer limited by the opening size of the first through contact. For example, the radial dimension of the isolation structure can be made larger than the dimension of the second amorphous silicon portion in the same direction, thereby further reducing the coupling effect between the first through contact and adjacent devices. Attached Figure Description

[0030] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings,

[0031] Figure 1 This is a flowchart of a method for forming a three-dimensional memory according to one embodiment of this application;

[0032] Figure 2 This is a schematic structural diagram of a method for forming a three-dimensional memory in related technologies after the formation of a through-hole.

[0033] Figure 3 This is a schematic structural diagram of a method for forming three-dimensional memory in related technologies after depositing insulating material through a through-hole;

[0034] Figure 4This is a schematic diagram of the structure of a method for forming a three-dimensional memory according to one embodiment of this application before ion implantation;

[0035] Figure 5 This is a schematic diagram of the structure of a method for forming a three-dimensional memory according to one embodiment of this application after ion implantation;

[0036] Figure 6 This is a schematic diagram of the structure of a method for forming a three-dimensional memory according to one embodiment of this application after removing the hard mask layer;

[0037] Figure 7 This is a schematic diagram of the structure after the formation of the dielectric layer in a method for forming a three-dimensional memory according to one embodiment of this application;

[0038] Figure 8 This is a schematic diagram of the structure after the mask layer is formed in a method for forming a three-dimensional memory according to one embodiment of this application;

[0039] Figure 9 This is a schematic diagram of the structure of a method for forming a three-dimensional memory according to one embodiment of this application after forming an opening;

[0040] Figure 10 This is a schematic diagram of the structure of a method for forming a three-dimensional memory according to an embodiment of this application after forming the first through contact.

[0041] Figure 11 This is a top view schematic diagram of a method for forming a three-dimensional memory according to an embodiment of this application, after the formation of the first through contact. Detailed Implementation

[0042] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0043] Note that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0044] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0045] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0046] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and another element(s)(s)(s) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein may be interpreted similarly.

[0047] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire upper or lower structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers.

[0048] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the terms “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0049] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0050] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0051] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0052] The framework of a three-dimensional memory device is formed by bonding a memory cell array structure (referred to herein as a "stacked structure," also called an "array wafer") and a peripheral circuit structure (also called a "CMOS wafer"). To form interconnect structures (e.g., for power buses and metal wiring) that provide vertical interconnects between the stacked structure and the peripheral circuit structure, it is typically necessary to form TSCs (Transient Silicon Contacts) in the semiconductor layers of the stacked structure or peripheral circuit structure to achieve electrical connections between the metal layers on the front and back sides of the semiconductor layers. TSCs are used for signal and power connections (including high-voltage (HV) and low-voltage (LV) portions). Due to coupling effects, transient noise or large voltage surges can occur in adjacent devices, causing significant fluctuations in the source voltage of the devices. Therefore, it is necessary to shield the through-silicon contacts from adjacent devices to mitigate coupling effects.

[0053] like Figure 2 and 3 As shown, in some manufacturing processes, after bonding the stacked structure 402 and the peripheral circuit structure 202, a through-hole 102 for the TSC can be formed on the semiconductor layer 422 and the insulating layer 101. An isolation layer 611 is formed on the sidewall of the through-hole 102 by atomic layer deposition to reduce the coupling effect between the subsequently formed TSC and the semiconductor substrate 422. Since the aperture of the through-hole 102 is small, when depositing the insulating material to form the isolation layer 611, it is inevitable that the sidewalls and bottom of the through-hole 102 are covered with insulating material. In order to make electrical contact between the TSC formed in the through-hole 102 and the peripheral contacts of the stacked structure 402, an additional etching process is required to remove the insulating material 612 covering the bottom of the through-hole 102. This step is usually called "Blank etching".

[0054] As an example, to simplify the process, a trench 103 can be formed simultaneously in the semiconductor layer 422 when forming the through-hole 102. This trench 103 is used to further process a back shallow trench isolation structure 104 (BSTI). For example, the patterns of the through-hole 102 and trench 103 can be transferred to a photoresist mask layer for etching using the same photomask to form the through-hole 102 and trench 103. The BSTI 104 can be used to mitigate interference from adjacent devices, including but not limited to providing shielding between adjacent devices, reducing parasitic capacitance, and reducing leakage current.

[0055] In some examples, to further simplify the process, when performing atomic layer deposition to form the isolation layer 611 in the through-hole 102, the trench 103 can be simultaneously filled with insulating material to form the BSTI 104. Therefore, the radial dimension of the trench 103 needs to be smaller than the radial dimension of the through-hole 102, so that after performing the atomic layer deposition process, the trench 103 is filled with insulating material, while the through-hole 102 only has the isolation layer 611 formed on its sidewalls, and the remaining space of the through-hole 102 is reserved for forming the TSC. Therefore, the width of the BSTI formed by the above method is limited, which is not conducive to reducing parasitic capacitance.

[0056] This application provides a three-dimensional memory and a method for forming the same, addressing at least one of the aforementioned problems. It should be noted that the three-dimensional memory in the embodiments of this application may be part of a non-monolithic 3D memory device, comprising a peripheral circuit structure and a stacked structure bonded face-to-face. In some embodiments, the stacked structure is flipped and faces down towards the peripheral circuit structure, and hybrid bonding is used to position the stacked structure on top of the peripheral circuit structure; in another embodiment, the peripheral circuit structure is flipped and faces down towards the stacked structure, and hybrid bonding is used to position the peripheral circuit structure on top of the stacked structure.

[0057] Figure 1 This is a flowchart 1000 of a method for forming a three-dimensional memory 100 according to one embodiment of this application. Figure 1 As shown, the method 1000 for forming a three-dimensional memory 100 includes:

[0058] S1: Form a stacked structure and a first semiconductor layer, the stacked structure being located on the first semiconductor layer, the first semiconductor layer including a first portion and at least one second portion, the first portion surrounding the second portion in its circumferential direction;

[0059] S2: Perform ion implantation process simultaneously in the first part and the second part to convert the first part and the second part into a first amorphous silicon part and a second amorphous silicon part, respectively;

[0060] S3: A dielectric layer is formed on the surface of the first semiconductor layer that is away from the stacked structure;

[0061] S4: Form an opening through the dielectric layer and the second amorphous silicon portion to expose the end of the second through contact, wherein the sidewall of the opening retains a portion of the second amorphous silicon portion as an isolation layer;

[0062] S5: Fill the opening with conductive material to form a first through contact.

[0063] The following will refer to... Figures 4-11 The schematic diagrams illustrating each stage of the method for forming a three-dimensional memory describe steps S1-S5 separately. In describing embodiments of this application, for ease of explanation, the cross-sectional views showing the device structure are partially enlarged and not to scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual fabrication, a three-dimensional spatial scale including length, width, and depth should be included. It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the described operations.

[0064] Reference Figure 1The method begins with operation S1, which can form a stacked structure and a first semiconductor layer. The stacked structure is located on the first semiconductor layer, and the first semiconductor layer includes a first portion and at least one second portion, with the first portion surrounding the second portion in its circumferential direction. Figure 4 The corresponding structure is shown.

[0065] like Figure 4 As shown, the three-dimensional memory provided in this application embodiment is a bonding device, including a first semiconductor structure 400 and a second semiconductor structure 200. According to some embodiments, the first semiconductor structure 400 and the second semiconductor structure 200 are bonded at a bonding interface 300.

[0066] According to some embodiments, the first semiconductor structure 400 of the three-dimensional memory includes a first semiconductor layer 401 and a stacked structure 402 and a first interconnect layer 403 sequentially disposed on the first semiconductor layer 401.

[0067] In some embodiments, a single-layer or multi-layer structure including amorphous silicon may be formed on the side of the stacked structure 402 away from the second semiconductor structure 200, and then the amorphous silicon may be annealed to form polycrystalline silicon to form the first semiconductor layer 401. For example, the first semiconductor layer 401 may be formed by performing a thermal annealing or laser annealing process on the single-layer or multi-layer structure including amorphous silicon to convert the amorphous silicon into polycrystalline silicon. Exemplarily, the single-layer or multi-layer structure including amorphous silicon may also be p-type doped or n-type doped as needed, so that the first semiconductor layer 401 formed by annealing may include p-type doped polycrystalline silicon or n-type doped polycrystalline silicon.

[0068] For example, such as Figure 4 As shown, the stacked structure 402 includes a first region 405 and a second region 406. The first region 405 has a through-hole second contact 410 (also referred to as a "peripheral contact") extending into the first semiconductor layer 401. The second region 406 includes a core region and a stepped region located on at least one side of the core region. The first region 406 is located on the side of the stepped region away from the core region. In some examples, the first semiconductor structure 400 also includes an insulating planarization layer 409 that covers the stepped region and fills the first region 405 to support the second through-hole contact 410.

[0069] In some embodiments, the stacked structure 402 includes alternately arranged gate conductor layers 428 and dielectric layers 429, with the dielectric layer 429 and adjacent gate conductor layers 428 forming dielectric layer / gate layer pairs. Exemplarily, the number of pairs can be selected according to various application scenarios. For example, the number of pairs can be 32, 64, 96, 128, 160, 192, 224, 256, or more.

[0070] In some embodiments, the gate conductor layer 428 includes a conductor material, which may include W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicides (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. Dielectric materials that may be used for the dielectric layer 429 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, commonly referred to as high dielectric constant (high k) dielectric oxides, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one example, the gate conductor layer 428 may be tungsten, and the dielectric layer 429 may be silicon oxide.

[0071] In some embodiments, the stacked structure 402 further includes a channel structure 411 extending through and into the first semiconductor layer 401, with each gate conductor layer 428 intersecting the channel structure 411 to form a memory cell. Exemplarily, the channel structure 411 includes a storage functional layer (not shown) and a channel layer (not shown) sequentially formed on the sidewalls and bottom of a channel via (not shown), and the remaining space in the channel via may be filled with an insulating layer material. Exemplarily, the channel layer may be electrically connected to the first semiconductor layer 401 via an epitaxial layer, and the storage functional layer includes a barrier layer (not shown), a charge storage layer (not shown), and a tunneling layer (not shown) sequentially formed in the channel via; wherein the barrier layer is made of an oxide, such as silicon oxide; the charge storage layer may be made of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles; and the tunneling layer is made of an oxide, such as silicon oxide.

[0072] In some embodiments, contact holes may be formed in the stepped area of ​​the stacked structure 402 and filled with conductive material to lead out word lines (also referred to as "word line contacts") and connect them to the peripheral circuit structure 202.

[0073] In some embodiments, the stacked structure 402 further includes a gate line slot structure 421 extending through the first semiconductor layer 401, which includes a gate line slot extending through the stacked structure 402 and an insulating layer and a filling layer (not shown) disposed in the gate line slot. The insulating layer includes an insulating material and can be used to electrically isolate adjacent memory cells. The filling layer includes a conductive material and can serve as a lead-out channel for electrical connection of a common source line.

[0074] In some embodiments, the first interconnect layer 403 includes a first dielectric layer 413 and one or more first interconnect structures 423 penetrating the first dielectric layer 413. Each first interconnect structure 423 includes a first interconnect contact 424 disposed perpendicular to or substantially perpendicular to the first semiconductor layer 401 and a first interconnect line 425 disposed parallel to the first semiconductor layer 401. One or more portions of the first interconnect structure 423 may be exposed on the top surface of the first dielectric layer 413. The materials of the first interconnect contact 424 and the first interconnect line 425 include conductive materials, such as tungsten, cobalt, copper, aluminum, polysilicon, silicides, or any combination thereof. The material of the first dielectric layer 413 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0075] like Figure 4 As shown, the second semiconductor structure 200 includes a second semiconductor layer 201, which may include single-crystal silicon (c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable material.

[0076] According to some embodiments, the second semiconductor structure 200 may include a peripheral circuit structure 202 on the second semiconductor layer 201. In some embodiments, the peripheral circuit structure 202 is configured to control and sense the three-dimensional memory device 100. The peripheral circuit structure 202 may include a transistor (not shown) formed on the second semiconductor layer 201, wherein a portion of the transistor is formed in the second semiconductor layer 201.

[0077] According to some embodiments, the second semiconductor structure 200 of the three-dimensional memory further includes a second interconnect layer 204 above the peripheral circuit structure 202. The second interconnect layer 204 includes a second dielectric layer 224 and second interconnect structures 205 penetrating the second dielectric layer 224. Each second interconnect structure 205 includes a second interconnect contact 215 disposed perpendicular to or substantially perpendicular to the second semiconductor layer 201 and a second interconnect line 216 disposed parallel to the second semiconductor layer 201. One or more portions of the second interconnect structure 205 may be exposed on the side of the second dielectric layer 224 facing the first semiconductor structure 400. The material of the second interconnect structure 205 may be a conductive material, including, for example, tungsten, cobalt, copper, aluminum, or any combination thereof. The material of the second dielectric layer 224 may be the same as the material of the first dielectric layer 413, and will not be described in detail here.

[0078] In some embodiments, when the peripheral circuit structure 202 and the stacked structure 402 are mixed-bonded face to face, the second interconnect structure 205 and the first interconnect structure 423 are correspondingly bonded at the bonding interface 300.

[0079] Refer again Figure 4The first semiconductor layer 401 includes a first portion A11 and two second portions A21, wherein the first portion A11 surrounds the two second portions A21 in its circumferential direction, and the radial width of the first portion A11 may be greater than, for example, the cross-sectional dimension of the second portions A21 in the same direction. In some examples, two second through contacts 410 may extend into the two second portions A21 respectively. It should be understood that the number of second through contacts 410 is only set to clearly illustrate the stacked structure 402, and the actual number of second through contacts can be set as needed. For example, more than two second through contacts may be formed as needed and may extend into multiple second portions of the first semiconductor layer 401 respectively.

[0080] Reference Figure 1 The method continues to operation S2, in which ion implantation processes can be performed simultaneously in the first part and the second part to convert the first part and the second part into a first amorphous silicon part and a second amorphous silicon part, respectively. Figure 6 The corresponding structure is shown.

[0081] like Figure 5 As shown, in some examples, a hard mask layer 500 may be formed on a surface of the first semiconductor layer 401 away from the stacked structure 402. The constituent material of the hard mask layer 500 may be, for example, silicon nitride. The hard mask layer 500 is then patterned to expose the substrate. Figure 4 The image contains a first portion A11 and two second portions A21. Ion implantation is then performed on the exposed portions of the first portion A11 and the two second portions A21, using the hard mask layer 500 as a mask. The portions covered by the hard mask layer 500 will not receive ion implantation. For example, the implanted ions may include phosphorus ions or arsenic ions, and the dose range of the implanted ions is 1 × 10⁻⁶. 15 atom / cm 2 Up to 1×10 17 atom / cm 2 The ion implantation energy ranges from 30 keV to 80 keV, and the ion implantation depth ranges from 50 to 500 nm. Under the above ion implantation conditions, the crystal orientation and lattice structure of polycrystalline silicon are disrupted, thereby allowing the first part A11 and the second part A21 to be transformed into the first amorphous silicon part B11 and the second amorphous silicon part B21, respectively.

[0082] In some examples, the first amorphous silicon portion B11 may form a ring structure surrounding the second amorphous silicon portion B21 in its circumferential direction. This ring structure can serve as an isolation structure, thereby physically isolating the device enclosed therein from the remainder of the first semiconductor layer 401, excluding the first amorphous silicon portion B11 and the second amorphous silicon portion B21.

[0083] In some examples, the radial width of the first amorphous silicon portion B11 may be greater than the cross-sectional dimension of the second amorphous silicon portion B21 in the same direction.

[0084] In some embodiments, the second portion A21 may include a sub-portion that may correspond in its circumference to the sidewall of the portion of the second through contact 410 extending into the second portion A21, the hard mask layer 500 is patterned to expose the sub-portion in the second portion A21, and then the sub-portion is ion implanted with the hard mask layer 500 as a mask to transform the sub-portion into an amorphous silicon isolation layer.

[0085] In some embodiments, the first semiconductor layer 401 may include polycrystalline silicon doped with a first conductivity type, and ion implantation may be performed simultaneously on the first portion A11 and the second portion A21 using ions of a second conductivity type, so that the first portion A11 and the second portion A21 are respectively transformed into a first amorphous silicon portion doped with a second conductivity type and a second amorphous silicon portion B21 doped with a second conductivity type.

[0086] As an example, the first semiconductor layer 401 may include N-type doped polysilicon. By implanting, for example, B-type conductive ions (P-type ions) into the first portion A11 and the second portion A21 of the first semiconductor layer 401, the first portion A11 can be transformed into a P-type doped first amorphous silicon portion, and the second portion A21 can be transformed into a P-type doped second amorphous silicon portion B21. In some examples, the P-type doped first amorphous silicon portion and the P-type doped second amorphous silicon portion B21 may form PN junctions with the N-type doped polysilicon of the first semiconductor layer 401, respectively.

[0087] In some embodiments, ion implantation of the second conductivity type may be performed only in the first portion A11 to transform it into a first amorphous silicon portion doped with the second conductivity type, or ion implantation of the second conductivity type may be performed only in the second portion A21 to transform it into a second amorphous silicon portion B21 doped with the second conductivity type.

[0088] like Figure 6 As shown, in some examples, the hard mask layer 500 may be removed after the formation of the first amorphous silicon portion B11 and the second amorphous silicon portion B21.

[0089] Reference Figure 2 The method continues to operation S3, where a dielectric layer can be formed on the surface of the first semiconductor layer away from the stacked structure. Figure 7 The corresponding structure is shown.

[0090] like Figure 7As shown, a dielectric layer 490 may be formed on a surface of the first semiconductor layer 401 away from the stacked structure 402 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the dielectric layer 490 may include, for example, silicon oxide.

[0091] Reference Figure 2 The method continues to operation S4, where an opening is formed through the dielectric layer and the second amorphous silicon portion to expose the end of the second through contact, wherein a portion of the second amorphous silicon portion is retained on the sidewall of the opening as an isolation layer. Figure 9 The corresponding structure is shown.

[0092] like Figure 8 As shown, in some examples, the opening can be formed by photolithography, for example, a patterned mask layer 480 can be formed on the top surface of the dielectric layer 490 to expose a surface of the dielectric layer 490 corresponding to the second amorphous silicon portion B21, away from the stacked structure 402, and then the dielectric layer 490 and the second amorphous silicon portion B21 can be etched through the exposed surface.

[0093] like Figure 9 As shown, in some embodiments, the dielectric layer 490 and the second amorphous silicon portion B21 can be etched from top to bottom to form an opening 460, thereby exposing the end of the second through contact 410. The radial dimension of the opening in the second amorphous silicon portion B21 can be smaller than the radial dimension of the second amorphous silicon portion B21 before the opening is formed, so that a portion of the second amorphous silicon is retained on the sidewall of the opening 460 as an isolation layer B22.

[0094] For example, the opening 460 can be formed using dry etching processes such as ion milling, plasma etching, reactive ion etching, and laser etching. Subsequently, the mask layer 480 can be removed, for example, in an ashing and / or wet stripping process.

[0095] In some examples, the critical dimensions of the 460 opening range from 200 angstroms to 2000 angstroms.

[0096] Reference Figure 2 The method continues to operation S5, where conductive material can be filled into the opening to form a first through contact. Figure 10 The corresponding structure is shown.

[0097] like Figure 10As shown, in some examples, after removing the mask layer 480, a conductive material can be filled into the opening 460 to form a first through contact 440 (also referred to as a "through silicon contact"). The conductive material includes, for example, tungsten, cobalt, copper, aluminum, or any combination thereof. Since a portion of the second amorphous silicon portion B21 is retained on the sidewall of the opening 460 as an isolation layer B22, the isolation layer B22 can cover the sidewall of the first through contact 440, thereby physically isolating the first through contact 440 from the rest of the first semiconductor layer 401, which can reduce the coupling effect between the rest of the first semiconductor layer 401 and the first through contact 440.

[0098] In some examples, an opening may be formed in the portion surrounded by an amorphous silicon isolation layer formed by the sub-parts to expose the end of the first through contact 410, and then the opening may be filled with a conductive material to form the first through contact 440. The amorphous silicon isolation layer can physically isolate the first through contact 440 from the rest of the first semiconductor layer 401.

[0099] like Figure 11 As shown, in some embodiments, the first amorphous silicon portion B11 may form an annular structure surrounding the second amorphous silicon portion B21 in its circumferential direction. This annular structure can serve as an isolation structure to electrically isolate the surrounded first through contact 440 from the rest of the first semiconductor layer 401, thereby reducing the parasitic capacitance between the first through contact 440 and the rest of the first semiconductor layer 401.

[0100] like Figure 11 As shown, for example, the width W of the first amorphous silicon portion B11 in its radial direction may be greater than the dimension D of the first through contact 440 covered by the isolation layer B22 in the same direction, thereby further reducing the parasitic capacitance generated between the first through contact 440 and the rest of the first semiconductor layer 401.

[0101] The method for forming a three-dimensional memory provided in this application selectively transforms a first portion of a first semiconductor layer and a second portion surrounded by the first portion into a first amorphous silicon portion and a second amorphous silicon portion, respectively, through mask-assisted ion implantation. On the one hand, the first amorphous silicon portion can serve as an isolation structure, so that the through-silicon contacts subsequently formed in the second amorphous silicon portion are electrically isolated from the rest of the first semiconductor layer, thereby reducing the parasitic capacitance generated between the through-silicon contacts and the rest of the first semiconductor layer.

[0102] On the other hand, a portion of the second amorphous silicon portion is retained in the sidewall of the through silicon contact, thereby physically isolating the through silicon contact from the rest of the first semiconductor layer and reducing the coupling effect between the through silicon contact and the rest of the first semiconductor layer.

[0103] Furthermore, since the first portion of the first semiconductor layer is directly transformed into the first amorphous silicon portion as the isolation structure through ion implantation, the step of forming the opening of the isolation structure at the same time as forming the opening through the silicon contact in related technologies is avoided. Therefore, the radial dimension of the isolation structure formed in this application is no longer limited by the opening size of the through silicon contact. For example, the radial dimension of the isolation structure can be made larger than the dimension of the second amorphous silicon portion in the same direction, thereby further reducing the coupling effect between the through silicon contact and adjacent devices.

[0104] In one embodiment of this application, after the first through contact 440 is formed, a metal layer and an insulating layer (also referred to as a "back-end process interconnect layer") may be formed on a surface of the dielectric layer 490 away from the stack structure 402. Figure 10 (Not shown) is used to bring out pads for transmitting electrical signals. The metal layer may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the metal layer includes Al. Although in Figure 10 Not shown, but it should be understood that the metal layer can be patterned to form various types of back-side interconnect structures. In some embodiments, a passivation layer may also be formed on the insulating layer, serving as the outermost layer for passivating and protecting the 3D memory. A portion of the metal layer may be exposed from the passivation layer as bonding pads.

[0105] Another aspect of this application provides a three-dimensional memory 100, such as... Figure 10 As shown, the three-dimensional memory 100 is a bonding device, including a first semiconductor structure 400 and a second semiconductor structure 200. According to some embodiments, the first semiconductor structure 400 and the second semiconductor structure 200 are bonded at a bonding interface 300.

[0106] In some examples, the first semiconductor structure 400 includes: a first semiconductor layer 401, a stacked structure 402, and a first through contact 440, wherein the stacked structure 402 includes a first region 405 and a second region 406, the first region 405 is provided with a through second through contact 410, the second through contact 410 extending into the first semiconductor layer 401; the second region 406 includes a core region and a stepped region located on at least one side of the core region, and the first region 406 is located on the side of the stepped region away from the core region.

[0107] For example, the first semiconductor layer may also be p-type doped or n-type doped as needed.

[0108] Refer again Figure 10In some embodiments, the first semiconductor layer 401 includes a first through-contact 440 and a corresponding isolation layer B22. The isolation layer B22 may include amorphous silicon, which may cover the sidewall of the first through-contact 440. The first through-contact 440 and the second through-contact 410 are arranged in the same direction and their ends are in contact with each other. In some examples, the isolation layer may also cover the sidewall of the second through-contact.

[0109] In some examples, the first semiconductor layer 401 also includes an isolation structure (also referred to as the "first amorphous silicon portion B11") that may surround the isolation layer B22 and the first through contact 440 in its circumferential direction.

[0110] In some examples, the first amorphous silicon portion B11 may form a ring structure surrounding the second amorphous silicon portion B21 in its circumferential direction. This ring structure can serve as an isolation structure, thereby electrically isolating the device enclosed therein from the device outside the isolation structure, which can reduce the parasitic capacitance generated between the first through contact 440 and the rest of the first semiconductor layer 401.

[0111] In some examples, the remainder of the first semiconductor layer 401, excluding the isolation layer B22 and the isolation structure, may include polysilicon. The isolation layer B22 may be used to physically isolate the first through contact 440 from the remainder of the first semiconductor layer 401, thereby reducing the coupling effect between the first through contact 440 and the remainder and the stacked structure 402.

[0112] In some examples, the polycrystalline silicon included in the first semiconductor layer 401 may be doped with a first conductivity type, and the amorphous silicon included in the isolation structure or isolation layer B22 may be doped with a second conductivity type; in other examples, both the isolation structure and the isolation layer B22 may include amorphous silicon doped with a second conductivity type.

[0113] As an example, the first semiconductor layer 401 may include N-type doped polysilicon, and the isolation structure and isolation layer B22 may include, for example, P-type doped amorphous silicon. The isolation structure and isolation layer B22 may form PN junctions with the P-type doped polysilicon of the first semiconductor layer 401, respectively.

[0114] In some examples, the first semiconductor structure 400 also includes a dielectric layer 490 located on a surface of the first semiconductor layer 401 away from the stacked structure 402, wherein the first through contact 440 can penetrate the dielectric layer 490, and the material of the dielectric layer 490 may include, for example, silicon oxide.

[0115] According to some embodiments, the second semiconductor structure 200 may include a second semiconductor layer 201 and a peripheral circuit structure 202 located on the second semiconductor layer 201, and the second through contact 410 is electrically connected to the peripheral circuit structure 202 through an interconnect structure.

[0116] For example, such as Figure 11 As shown, the isolation structure (also referred to as the "first amorphous silicon portion B11") has a radial width W that is not limited by the dimensions of the first through contact 440 and the isolation layer B22. Its width W can be greater than the dimension of the first through contact 440 in the same direction, and can be greater than the sum D of the dimensions of the isolation layer B22 and the first through contact 440 in the same direction, which can further reduce the parasitic capacitance between the first through contact 440 and adjacent devices.

[0117] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, characterized in that, include: A first semiconductor layer includes an isolation structure, the isolation structure including amorphous silicon; At least one first through contact is disposed within the first semiconductor layer, wherein the isolation structure surrounds the first through contact in its circumferential direction; as well as, A stacked structure is located on the first semiconductor layer.

2. The three-dimensional memory according to claim 1, characterized in that, The first semiconductor layer further includes at least one isolation layer comprising amorphous silicon, wherein the isolation layer correspondingly covers the sidewall of the first through contact, and the isolation structure surrounds the isolation layer in its circumferential direction.

3. The three-dimensional memory according to claim 2, characterized in that, The width of the isolation structure in its radial direction is greater than the sum of the cross-sectional dimensions of the isolation layer and the first through contact in the same direction.

4. The three-dimensional memory according to claim 2, characterized in that, The first semiconductor layer, excluding the isolation structure, and the remainder of the isolation layer comprises polycrystalline silicon.

5. The three-dimensional memory according to claim 4, characterized in that, The remaining portion of the first semiconductor layer comprises polycrystalline silicon doped with a first conductivity type; and the isolation structure and / or the isolation layer comprises amorphous silicon doped with a second conductivity type.

6. The three-dimensional memory according to claim 4, characterized in that, The stacked structure includes a first region corresponding to the isolation structure, the first region having at least one second through contact extending into the first semiconductor layer, wherein the second through contact and the first through contact are arranged in the same direction and their ends are in contact with each other, and the isolation layer isolates the second through contact from the remaining portion.

7. The three-dimensional memory according to claim 6, characterized in that, The stacked structure further includes a second region, which includes a core region and a stepped region located on at least one side of the core region, wherein the first region is located on the side of the stepped region away from the core region.

8. The three-dimensional memory according to claim 6, characterized in that, The three-dimensional memory further includes a second semiconductor layer and a peripheral circuit structure located on the second semiconductor layer. The stacked structure is bonded to the peripheral circuit structure, wherein the second through contact is electrically connected to the peripheral circuit structure.

9. The three-dimensional memory according to claim 1, characterized in that, The three-dimensional memory further includes a dielectric layer located on the surface of the first semiconductor layer away from the stacked structure, wherein the first through contact penetrates the dielectric layer.

10. A method for forming a three-dimensional memory, comprising: A stacked structure and a first semiconductor layer are formed, the stacked structure being located on the first semiconductor layer, the first semiconductor layer including a first portion and at least one second portion, the first portion surrounding the second portion in its circumferential direction; An ion implantation process is performed on the first portion to convert the first portion into a first amorphous silicon portion; as well as At least one first through contact is formed in the second part.

11. The method according to claim 10, characterized in that, The first semiconductor layer is formed by annealing amorphous silicon into polycrystalline silicon.

12. The method according to claim 10, characterized in that, The method further includes: The same ion implantation process is performed on the second part to transform the second part into a second amorphous silicon part.

13. The method according to claim 12, characterized in that, The first semiconductor layer further includes the remaining portions other than the first and second portions, and the method further includes: At least one first through contact is formed in the second amorphous silicon portion, and a portion of the second amorphous silicon portion is retained on its sidewall as an isolation layer to isolate the first through contact from the remaining portion.

14. The method according to claim 10, characterized in that, The first semiconductor layer comprises polycrystalline silicon doped with a first conductivity type, and performing the ion implantation process in the first portion includes: The ion implantation process of the second conductivity type ions is performed in the first portion to transform the first portion into the first amorphous silicon portion.

15. The method according to claim 14, characterized in that, The method further includes: The same ion implantation process of the second conductivity type ions is performed on the second part to transform the second part into a second amorphous silicon part.

16. The method according to claim 10, characterized in that, The step of performing the ion implantation process in the first part includes: A hard mask layer is formed on the surface of the first semiconductor layer that is away from the stacked structure; Pattern the hard mask layer to expose the first portion; and, The ion implantation process is performed on the first portion using the hard mask layer as a mask, so that the first portion is transformed into the first amorphous silicon portion.

17. The method according to claim 16, characterized in that, The method includes: While patterning the hard mask layer to expose the first portion, the second portion is also exposed; and, While performing the ion implantation on the first portion using the hard mask layer as a shield, the same ion implantation process is performed on the second portion to transform the second portion into a second amorphous silicon portion.

18. The method according to claim 13, wherein, The stacked structure includes a first region corresponding to the second amorphous silicon portion, the first region having at least one second through-contact extending into the second amorphous silicon portion, characterized in that forming at least one first through-contact includes: A dielectric layer is formed on the surface of the first semiconductor layer away from the stacked structure; An opening is formed penetrating the dielectric layer and the second amorphous silicon portion to expose the end of the second through contact, wherein the sidewalls of the opening retain a portion of the second amorphous silicon portion as the isolation layer; and, The opening is filled with conductive material to form the first through contact.

19. The method according to claim 18, characterized in that, The radial dimension of the opening ranges from 200 angstroms to 2000 angstroms.

20. The method according to claim 13, characterized in that, The dose range of ions implanted by the ion implantation process is 1×10⁻⁶. 15 atom / cm 2 Up to 1×10 17 atom / cm 2 .

21. The method according to claim 13, characterized in that, The energy range of the ions implanted by the ion implantation process is 30 keV to 80 keV.

22. The method according to claim 18, characterized in that, The method further includes: Forming a second semiconductor layer and a peripheral circuit structure, the peripheral circuit structure being located on the second semiconductor layer; and, Bonding the peripheral circuit structure and the stacked structure; The second through contact is electrically connected to the peripheral circuit structure.

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