Micro-electromechanical system device and manufacturing method thereof

Abstract

A MEMS device can be formed to include an anti-stiction polysilicon layer on one or more movable MEMS structures of a device wafer of the MEMS device to reduce, minimize and / or eliminate stiction between the movable MEMS structure and other components or structures of the MEMS device. The anti-stiction polysilicon layer can be formed such that the surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of the bonding polysilicon layer on the surface of the device wafer to be bonded to the circuit wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer can reduce the surface area of ​​the bottom of the movable MEMS structure, which can reduce the likelihood that the one or more movable MEMS structures will adhere to other components or structures.

Description

Technical Field

[0001] Embodiments of the present invention relate to a micro-electromechanical system device and a manufacturing method thereof, and more specifically, to a micro-electromechanical system device and a manufacturing method thereof for reducing roughness selectivity of moving static friction of a micro-electromechanical system. Background Art

[0002] Integrated circuits can be manufactured on semiconductor wafers. Semiconductor wafers can be stacked or bonded on top of each other to form so-called three-dimensional integrated circuits. Some semiconductor wafers include micro-electromechanical-system (MEMS) devices, which involve processes for forming miniature structures with dimensions on the micrometer scale (millionths of a meter). Typically, MEMS devices are built on silicon wafers and implemented in thin films of material. MEMS applications include inertial sensor applications, such as motion sensors, accelerometers, microphones, and gyroscopes. Other MEMS applications include optical applications such as movable mirrors and RF applications such as radio frequency (RF) switches and resonators. Summary of the invention

[0003] According to some embodiments, a micro-electromechanical system device includes a cover chip, a circuit chip, a device chip between the cover chip and the circuit chip, one or more movable micro-electromechanical system structures, a first polysilicon layer and a second polysilicon layer, the movable micro-electromechanical system structure is in a cavity formed by the cover chip, the circuit chip and the device chip, the first polysilicon layer is on the bottom surface of the one or more movable micro-electromechanical system structures, and the second polysilicon layer is between the device chip and the circuit chip, wherein the surface roughness of the first polysilicon layer is different from the surface roughness of the second polysilicon layer.

[0004] According to some embodiments, a method for manufacturing a micro-electromechanical system device includes forming a polysilicon layer above a substrate of a device wafer of the micro-electromechanical system device; increasing the surface roughness of a first portion of the polysilicon layer relative to the surface roughness of one or more second portions of the polysilicon layer so that the surface roughness of the first portion is larger relative to the surface roughness of the one or more second portions; etching through multiple portions of the first portion and through multiple associated portions of the substrate to form multiple movable micro-electromechanical system structures; and after forming the movable micro-electromechanical system structure, bonding the device wafer to a circuit wafer of the micro-electromechanical system device.

[0005] According to some embodiments, a MEMS device includes a capping wafer, a circuit wafer including a metal bonding pad, a device wafer between the capping wafer and the circuit wafer, one or more movable MEMS structures, a first polysilicon layer, and a second polysilicon layer. The device wafer includes a support structure and a germanium bonding pad between the metal bonding pad and the support structure. The movable MEMS structure is in a cavity formed by the capping wafer, the circuit wafer, and the device wafer. The first polysilicon layer is on the bottom surface of the one or more movable MEMS structures, and the second polysilicon layer is between the support structure and the germanium bonding pad, wherein the surface roughness of the first polysilicon layer is different from the surface roughness of the second polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, the various aspects of the present disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0008] Figure 2 is a diagram of an example semiconductor structure described herein.

[0009] FIG. 3A to FIG. 3K are drawings of example implementations described herein.

[0010] Figure 4 for Figure 1 A diagram of example components of one or more devices.

[0011] Figure 5 is a flow chart of an example process associated with forming the semiconductor structures described herein.

[0012] Description of Figure Numbers

[0013] 100: Environment;

[0014] 102: deposition machine;

[0015] 104: exposure machine;

[0016] 106: developing machine;

[0017] 108: Etching machine;

[0018] 110: bonding machine;

[0019] 112: Wafer / die conveyor;

[0020] 200: Micro-electromechanical systems (MEMS) devices;

[0021] 202: Circuit chip;

[0022] 204: device wafer;

[0023] 206: capping wafer;

[0024] 208: metal bonding pad;

[0025] 210: passivation layer;

[0026] 212: semiconductor substrate;

[0027] 214: Movable MEMS structures;

[0028] 216: cavity;

[0029] 218: Support structure;

[0030] 220, 224, 302: polysilicon layer;

[0031] 222: Germanium bonding pad;

[0032] 226: substrate;

[0033] 228, 304: oxide layer;

[0034] 300: instance;

[0035] 306: photoresist layer;

[0036] 308: Germanium layer;

[0037] 400: Devices;

[0038] 410: bus;

[0039] 420: processor;

[0040] 430: memory;

[0041] 440: storage component;

[0042] 450: Input component;

[0043] 460: output component;

[0044] 470: Communication components;

[0045] 500: process;

[0046] 510, 520, 530, 540: frame. DETAILED DESCRIPTION

[0047] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0048] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," and similar may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0049] A microelectromechanical system (MEMS) device may include multiple devices or wafers bonded together to form a MEMS device. For example, a MEMS device may include: a circuit wafer (such as a complementary metal oxide semiconductor (CMOS) wafer) including circuits for the MEMS device, a device wafer including suspended mechanical components that act as actuators for the MEMS device, and a cavity (or cap) wafer used to seal the mechanical components in a cavity or microchamber. The circuit wafer, device wafer, and / or cap wafer may be bonded together using a eutectic bonding process. Eutectic bonding is a wafer bonding technique by which the wafer of the MEMS device is heated to form a eutectic system between the materials of the wafer. The eutectic system typically includes silicon or germanium and a metal such as gold or aluminum. Because the eutectic system is formed, there may be no discernible interface between the bonding materials.

[0050] In some cases, a suspended mechanical component (e.g., a movable structure or actuator) may come into contact with other components or structures of a MEMS device. For example, a suspended mechanical component may come into contact with other components or structures of a MEMS device during operation of the MEMS device, during fabrication of the MEMS device, and / or at other times. In some cases, contact between the suspended mechanical component and other components or structures of the MEMS device may cause the suspended mechanical component to adhere to the other components or structures, which may cause the MEMS device to malfunction.

[0051] Some embodiments described herein provide a MEMS device that can be formed to include an anti-stiction polysilicon layer on one or more movable MEMS structures (e.g., suspended mechanical components or actuators) of a device wafer of the MEMS device to reduce, minimize, and / or eliminate stiction (or sticking) between the movable MEMS structure and other components or structures of the MEMS device. The anti-stiction polysilicon layer can be formed on the bottom surface of each of the movable MEMS structures. The anti-stiction polysilicon layer can be formed so that the surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of the bonding polysilicon layer on the surface of the device wafer to be bonded to the circuit wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer can reduce the surface area of ​​the bottom of the movable MEMS structure, which can reduce the friction between the one or more movable MEMS structures and other components or structures that can contact the one or more movable MEMS structures. This may reduce the likelihood that the one or more movable MEMS structures will adhere to other components or structures. The lower surface roughness of the bonding polysilicon layer may provide a larger surface area relative to the anti-stiction polysilicon layer, which may facilitate eutectic bonding between the device wafer and the circuit wafer.

[0052] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 , environment 100 may include a plurality of semiconductor processing machines 102 to 110 and a wafer / die conveyor 112. The plurality of semiconductor processing machines 102 to 110 may include a deposition machine 102, an exposure machine 104, a developer 106, an etch machine 108, a bonding machine 110, and / or another type of semiconductor processing machine. The machines included in the example environment 100 may be included in a semiconductor clean room, a semiconductor manufacturing plant, a semiconductor processing chamber, and / or a manufacturing facility, etc.

[0053] Deposition machine 102 is a semiconductor processing machine that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition machine 102 includes a spin coater capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, deposition machine 102 includes a chemical vapor deposition (CVD) machine, such as a plasma-enhanced CVD (PECVD) machine, a high-density plasma CVD (HDP-CVD) machine, a sub-atmospheric CVD (SACVD) machine, an atomic layer deposition (ALD) machine, a plasma-enhanced atomic layer deposition (PEALD) machine, or another type of CVD machine. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the example environment 100 includes multiple types of deposition tools 102 .

[0054] The exposure machine 104 is a semiconductor processing machine capable of exposing the photoresist layer to a radiation source (e.g., an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light source, etc.), an x-ray source, etc.). The exposure machine 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various parts of a semiconductor device, etc. In some embodiments, the exposure machine 104 includes a scanner, a stepper, or a similar type of exposure machine.

[0055] The developer station 106 is a semiconductor processing station capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure station 104. In some embodiments, the developer station 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developer station 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developer station 106 develops the pattern by dissolving the exposed or unexposed portion of the photoresist layer using a chemical developer.

[0056] The etching machine 108 is a semiconductor processing machine capable of etching substrates, wafers, or semiconductor devices of various types of materials. For example, the etching machine 108 may include a wet etching machine, a dry etching machine, etc. In some embodiments, the etching machine 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching machine 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch one or more portions isotropically or directionally.

[0057] The bonding machine 110 is a semiconductor processing machine capable of bonding two or more wafers (or two or more semiconductor substrates or two or more semiconductor devices) together. For example, the bonding machine 110 may include a eutectic bonding machine capable of forming a eutectic bond between two or more wafers. In these examples, the bonding machine 110 may heat the two or more wafers to form a eutectic system between the materials of the two or more wafers.

[0058] The wafer / die conveyor 112 includes a mobile robot, a robotic arm, a tram or rail car, and / or another type of device for transporting wafers and / or dies between semiconductor processing tool 102 to semiconductor processing tool 110 and / or to and from other locations such as wafer racks, storage chambers, etc. In some implementations, the wafer / die conveyor 112 may be a programmed device to travel a specific path and / or may operate semi-autonomously or autonomously.

[0059] supply Figure 1 The number and arrangement of the devices shown in FIG. are provided as one or more examples. Figure 1 There may be additional devices, fewer devices, different devices, or devices arranged in a different manner than those shown in FIG. Figure 1 Two or more devices shown in FIG. 1 may be implemented in a single device, or Figure 1 A single device depicted in the environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of one set of devices (eg, one or more devices) of the environment 100 may perform one or more functions described as being performed by another set of devices of the environment 100.

[0060] Figure 2 is a diagram of an example MEMS device 200 described herein. The MEMS device 200 may include an accelerometer, a microphone, a gyroscope, or another type of MEMS device including a movable MEMS structure or actuator. Figure 2, the MEMS device 200 may include a circuit wafer 202, a device wafer 204, and a capping wafer 206. The circuit wafer 202 may be bonded to the device wafer 204 on a first side thereof, and the capping wafer 206 may be bonded to the device wafer 204 on a second side thereof opposite to the first side.

[0061] Circuit wafer 202 may be a complementary metal oxide semiconductor (CMOS) wafer including semiconductor components (e.g., transistors, inductors, capacitors, and / or resistors), including integrated circuits, and / or including interconnecting metallization layers of MEMS devices 200. In other examples, circuit wafer 202 may include one or more metal bonding pads 208 formed of aluminum or another conductive material (e.g., gold, tungsten, cobalt). Metal bonding pads 208 may be bonding pads for bonding device wafer 204 and circuit wafer 202, and may provide electrical connections to the interconnecting metallization layers of the circuit and MEMS devices 200. Passivation layer 210 may be disposed between adjacent metal bonding pads 208 on the surface of circuit wafer 202 to provide electrical isolation. Passivation layer 210 may be formed of a dielectric material, such as silicon nitride (SiN x ), Silicon Carbide (SiC x ) or a mixture thereof, such as silicon carbon nitride (SiCN), silicon oxynitride (SiON), or another type of dielectric material. In some embodiments, the circuit chip 202 may include connections to the packaging or pads of the MEMS device 200.

[0062] The device wafer 204 is formed of a semiconductor substrate 212, such as a silicon substrate. One or more movable MEMS structures 214 may be formed in the device wafer 204 (e.g., in the substrate 212 of the device wafer 204) that may function as MEMS actuators of the MEMS device 200. The movable MEMS structures 214 may be formed by etching through portions of the substrate 212 to form an elongated member that is suspended above the circuit wafer 202 by a lateral connection to one side of the substrate 212 of the device wafer 204. In this manner, the movable MEMS structures 214 are permitted to move or displace to function as a vibrating mass, bungee cord or coil, or other type of actuator for performing functions in sensors, gyroscopes, microphones, accelerometers, RF devices, or optical devices.

[0063] The movable MEMS structure 214 may be located in a cavity 216 of the MEMS device 200. The cavity 216 may be a hermetically sealed micro-chamber in which a vacuum is formed to prevent outgassing and to prevent foreign objects and other contaminants from damaging the movable MEMS structure 214. The cavity 216 may be formed by a combination of the circuit wafer 202, the device wafer 204, and the capping wafer 206, which may enclose the movable MEMS structure 214 in the cavity 216.

[0064] The device wafer 204 may be supported on the circuit wafer 202 by one or more support structures 218 formed in and / or on the substrate 212 (and may be bonded to the circuit wafer 202 at the one or more support structures 218). The support structures 218 may act as a standoff for the movable MEMS structure 214 so as to permit the movable MEMS structure 214 to be suspended above the circuit wafer 202. The support structures 218 may be coated with a polysilicon layer 220 to promote and / or increase adhesion between the silicon of the substrate 212 on the polysilicon layer 220 above the support structures 218 and one or more germanium bonding pads 222. The germanium bonding pads 222 may be used to form a eutectic bond between the germanium bonding pads 222 and the associated metal bonding pads 208 to bond the device wafer 204 to the circuit wafer 202. In this manner, the germanium bonding pads 222 may increase the quality and strength of the bond between the circuit wafer 202 and the device wafer 204.

[0065] The quality and strength of the eutectic bond between the circuit wafer 202 and the device wafer 204 may be further increased by the polysilicon layer 220. The polysilicon layer 220 may be formed with a sufficiently low surface roughness to reduce the likelihood of the germanium bond pad 222 peeling or delaminating from the polysilicon layer 224. Maintaining the low surface roughness of the polysilicon layer 220 increases the surface area of ​​the polysilicon layer 220, which increases the friction between the germanium bond pad 222 and the polysilicon layer 220. The increased friction provides a stronger bond between the germanium bond pad 222 and the polysilicon layer 220 and prevents peeling and delamination.

[0066] The polysilicon layer 220 may be formed to have a root mean square roughness (Rq) of less than about 30 nanometers because the likelihood of peeling and delamination of the germanium bonding pad 222 from the polysilicon layer 224 may increase at about 30 nanometers and above. The polysilicon layer 220 may be formed to have a thickness equal to or less than about 10,000 angstroms to control the surface roughness of the polysilicon layer 220 so that the root mean square roughness (Rq) of the polysilicon layer 220 is less than about 30 nanometers. As the thickness of the polysilicon layer 220 increases to greater than about 10,000 angstroms, the surface roughness of the polysilicon layer 220 may increase to greater than about 30 nanometers.

[0067] Another polysilicon layer 224 may be included on the movable MEMS structure 214. Specifically, the polysilicon layer 224 may be included on the bottom surface of the movable MEMS structure 214. The polysilicon layer 224 may be an anti-stiction layer because the polysilicon layer 224 is included on the bottom surface of the movable MEMS structure 214 to reduce, minimize, and / or eliminate the possibility of stiction between the movable MEMS structure 214 and the circuit wafer 202 (e.g., the passivation layer 210 of the circuit wafer 202). The polysilicon layer 224 may be formed with a sufficiently high surface roughness to reduce the possibility of stiction between the movable MEMS structure 214 and the passivation layer 210. The high surface roughness of the polysilicon layer 224 reduces the surface area of ​​the polysilicon layer 224, which reduces the friction between the movable MEMS structure 214 and the passivation layer 210 when the movable MEMS structure 214 contacts the passivation layer 210. The reduced friction reduces the likelihood that the movable MEMS structure 214 will permanently adhere to the passivation layer 210 .

[0068] Because the surface roughness of the polysilicon layer 220 can be configured to promote adhesion, the surface roughness of the polysilicon layer 224 can be different from the surface roughness of the polysilicon layer 220 to reduce, minimize, and / or eliminate the possibility of stiction between the movable MEMS structure 214 and the circuit die 202. Specifically, the surface roughness of the polysilicon layer 224 can be greater than the surface roughness of the polysilicon layer 220 to reduce, minimize, and / or eliminate the possibility of stiction between the movable MEMS structure 214 and the circuit die 202. In some embodiments, the specific root mean square roughness (Rq) formed by the polysilicon layer 224 can be based on the specified performance parameters of the MEMS device 200. For example, the polysilicon layer 224 can be formed to a root mean square roughness (Rq) greater than about 30 nanometers to withstand stiction of the movable MEMS structure 214 in a specific number of drop test cycles (e.g., 10,000 drop test cycles). As another example, the polysilicon layer 224 may be formed to have a root mean square roughness (Rq) greater than about 40 nanometers to withstand stiction over a greater number of drop test cycles than if the polysilicon layer 224 were formed to have a root mean square roughness (Rq) of about 30 nanometers but less than about 40 nanometers. The drop test cycle may include dropping the MEMS device 200 from a distance in an attempt to cause the MEMS device 200 to fail. The drop test cycle may be performed to determine the durability of the MEMS device 200, to determine the reliability of the MEMS device 200, and / or to determine other performance parameters of the MEMS device 200.

[0069] The capping wafer 206 may include a substrate 226 formed of a silicon wafer or another type of wafer used in semiconductor processing that is capable of being etched and has mechanical strength and material composition to form the cavity 216 within the MEMS device 200. The capping wafer 206 may be bonded to the device wafer 204 through an oxide layer 228. As an example, the capping wafer 206 and the device wafer 204 may be fusion bonded through an intervening oxide layer 228. The oxide layer 228 may include an oxide material, such as silicon oxide, silicon dioxide, or another type of oxide material.

[0070] supply Figure 2 The number and arrangement of the structures, layers, etc. shown in FIG. are examples. Figure 2 The MEMS structure may include additional structures and / or layers, fewer structures and / or layers, different structures and / or layers, or structures and / or layers arranged in a different manner than those depicted in FIG.

[0071] FIG. 3A to FIG. 3K To form Figure 2 FIG. 3 is a diagram of an example 300 of a MEMS device 200. In some embodiments, one or more semiconductor processing tools 102 to semiconductor processing tools 110 may perform a combined FIG. 3A to FIG. 3K One or more of the techniques and / or processes described herein. In some embodiments, the combination may be performed by other semiconductor processing tools. FIG. 3A to FIG. 3K One or more of the described techniques and / or technologies.

[0072] like Figure 3A As shown in FIG. 1 , an oxide layer 228 may be formed on the capping wafer 206. For example, the deposition tool 102 may deposit the oxide layer 228 on the capping wafer 206 using a CVD process, a PVD process, an ALD process, or another type of deposition process. Figure 3B , the capping wafer 206 and the device wafer 204 may be bonded together via the intervening oxide layer 228. Specifically, the bonding tool 110 may fusion bond the capping wafer 206 and the device wafer 204 together via the intervening oxide layer 228. The fusion bond may form a hermetic seal between the capping wafer 206 and the device wafer 204.

[0073] Fusion bonding the capping wafer 206 and the device wafer 204 using the oxide layer 228 may include pressing the device wafer 204 against the oxide layer 228 on the capping wafer 206, and performing an annealing process to bond the capping wafer 206 and the device wafer 204 together due to atomic attraction. The fusion bonding process may be used to bond silicon structures together (e.g., the capping wafer 206 and the device wafer 204) through silicon oxide (SiOx) to silicon (Si) bonding, which may occur between the capping wafer 206 and the oxide layer 228, and between the device wafer 204 and the oxide layer 228.

[0074] like Figure 3C , one or more semiconductor processing machines may form a support structure 218 for the device wafer 204. The deposition machine 102 may deposit a photoresist layer on the substrate 212 (e.g., by a spin coating operation). The exposure machine 104 may form a pattern in the photoresist layer by exposing the photoresist layer to a radiation source (e.g., a UV source (e.g., a deep UV light source, an extreme UV (EUV) light source, etc.), an x-ray source, or an electron beam (e-beam) source) to transfer the pattern from a photomask to the photoresist layer. The development machine 106 may perform a development operation that includes one or more techniques for developing the pattern in the photoresist layer. After the pattern has been developed, the substrate 212 may be rinsed to remove any residual chemical developer and the substrate 212 may be spun dry. The etching machine 108 may etch the substrate 212 based on the pattern formed in the photoresist layer to form the support structure 218 for the device wafer 204. For example, the etching station 108 may perform a wet etching technique (e.g., wherein the substrate 212 is exposed or immersed in a chemical substance that etches or removes material from the substrate 212 at a specific etching rate), a dry etching device (e.g., wherein a plasma is used to sputter material from the substrate 212), or another type of etching technique. After etching the substrate 212 to form the support structure 218, the remaining portion of the photoresist layer may be removed from the substrate 212. In some embodiments, a solvent or a chemical stripper is used to remove the remaining portion of the photoresist layer. In some embodiments, a plasma ashing process is used to remove the remaining portion of the photoresist layer. In these examples, a plasma source is used to form a plasma of oxygen ions or fluorine ions to react with the photoresist material. The reaction between the ions in the plasma and the photoresist material causes the photoresist material to form ash, which is removed using a vacuum pump.

[0075] like Figure 3D, the semiconductor processing tool may form a polysilicon layer 302 over and / or on the device wafer 204. Specifically, the semiconductor processing tool may form the polysilicon layer 302 over and / or on the substrate 212 of the device wafer 204 (including over and / or on the support structure 218). For example, the deposition tool 102 may deposit the polysilicon layer 302 over and / or on the substrate 212 of the device wafer 204 (including over and / or on the support structure 218) using a CVD process, a PVD process, an ALD process, or another type of deposition process.

[0076] The polysilicon layer 220 and the polysilicon layer 224 may be formed from the polysilicon layer 302, in which case the polysilicon layer 220 and the polysilicon layer 224 may be deposited in a single (same) deposition operation. Thus, the deposition machine 102 may deposit the polysilicon layer 302 to a specific thickness so as to achieve a specific surface roughness of the polysilicon layer 302. Specifically, the deposition machine 102 may deposit the polysilicon layer 302 to a thickness equal to or less than about 10,000 angstroms to achieve a root mean square roughness (Rq) of the polysilicon layer 302 of less than about 30 nanometers.

[0077] like Figure 3D 2, the deposition machine 102 may deposit an oxide layer 304 over and / or on the polysilicon layer 220 using a CVD process, a PVD process, an ALD process, or another type of deposition process. The oxide layer 304 may be formed of an oxide material such as silicon oxide, silicon dioxide, or another material containing an oxide. The oxide layer 304 may be deposited to at least partially oxidize the top surface of the polysilicon layer 302. The oxidation of the polysilicon layer 302 may be part of a process to increase the surface roughness of the polysilicon layer 302 that will become part of the polysilicon layer 224.

[0078] like Figure 3E, one or more semiconductor processing machines may form a photoresist layer 306 on the oxide layer 304 above the support structure 218 and on one or more portions of the polysilicon layer 302 that will become the polysilicon layer 220. In this manner, the one or more portions of the polysilicon layer 302 that will become the polysilicon layer 220 are protected from etching to maintain a low surface roughness. The deposition machine 102 may deposit the photoresist layer 306 on the oxide layer 304 (e.g., by a spin coating operation). The exposure machine 104 may form a pattern in the photoresist layer 306 by exposing the photoresist layer 306 to a radiation source (e.g., a UV source (e.g., a deep UV light source, an EUV light source, etc.), an x-ray source, or an electron beam source) to transfer the pattern from a photomask to the photoresist layer 306. The development machine 106 may perform a development operation, which includes one or more techniques for developing the pattern in the photoresist layer 306. After the pattern has been developed, oxide layer 304 may be rinsed to remove any residual chemical developer and spun dry. A pattern in photoresist layer 306 may be formed to expose portions of oxide layer 304 to be etched and portions of polysilicon layer 302 that will become polysilicon layer 224.

[0079] like Figure 3F , the semiconductor processing machine may remove the portion of the oxide layer 304 exposed by the pattern in the photoresist layer 306. Specifically, the etching machine 108 may perform a wet etching operation or a dry etching operation to etch the exposed portion of the oxide layer 304 to remove the exposed portion of the oxide layer 304. The etching machine 108 may further etch the top surface of the portion of the polysilicon layer 302 under the exposed portion of the oxide layer 304. As described above, the top surface of the polysilicon layer 302 may be at least partially oxidized by the intervening oxide layer 304. The oxidation of the top surface of the polysilicon layer 302 may reduce the etching selectivity of the polysilicon layer 302. Therefore, the oxidation of the top surface of the polysilicon layer 302 may cause the top surface of the polysilicon layer 302 to be etched under the exposed portion of the oxide layer 304 during the etching operation. The combination of oxidation of the top surface of polysilicon layer 302 beneath the exposed portion of oxide layer 304 and etching of the top surface of polysilicon layer 302 beneath the exposed portion of oxide layer 304 increases the surface roughness of polysilicon layer 302 beneath the exposed portion of oxide layer 304 (e.g., relative to the portion of oxide layer 304 beneath photoresist layer 306 that will become polysilicon layer 220). Thus, the etching operation results in the formation of polysilicon layer 220 and polysilicon layer 224.

[0080] The duration of the etching operation, the etch rate of the etchant used in the etching operation, and / or other parameters of the etching operation may be selected to achieve a specific surface roughness of the polysilicon layer 224. In some embodiments, a specific surface roughness may be determined or selected based on a threshold drop test cycle to be experienced by the MEMS device 200. For example, the duration of the etching operation and / or the etch rate of the etchant may be increased to increase the surface roughness so as to meet a larger threshold drop test cycle. As another example, the duration of the etching operation and / or the etch rate of the etchant may be reduced to provide a small increase in surface roughness to meet a smaller threshold drop test cycle. In some embodiments, a specific surface roughness may be determined or selected based on a drop force or equivalent g-force to be experienced by the MEMS device 200 without failure. For example, the duration of the etching operation and / or the etch rate of the etchant may be increased to increase the surface roughness so as to meet a larger drop force. As another example, the duration of the etching operation and / or the etch rate of the etchant may be reduced to provide a small increase in surface roughness to accommodate a smaller drop force.

[0081] like Figure 3G , the remaining portion of the photoresist layer 306 can be removed from the oxide layer 304 after etching the oxide layer 304 (and portions of the polysilicon layer 302) to form the polysilicon layer 220 and the polysilicon layer 224. In some embodiments, a solvent or chemical stripper is used to remove the remaining portion of the photoresist layer 306. In some embodiments, a plasma ashing process is used to remove the remaining portion of the photoresist layer 306. In these examples, a plasma source is used to form a plasma of oxygen ions or fluorine ions to react with the photoresist material. The reaction between the ions in the plasma and the photoresist material causes the photoresist material to form ash, which is removed using a vacuum pump.

[0082] like Figure 3H , germanium layer 308 may be deposited onto polysilicon layer 220 and polysilicon layer 224. For example, a semiconductor processing tool (e.g., deposition tool 102) may deposit germanium layer 308 onto polysilicon layer 220 and polysilicon layer 224 using a CVD process, a PVD process, an ALD process, or another type of deposition process.

[0083] like Fig. 3I, one or more semiconductor processing machines may form germanium bonding pads 222. Deposition machine 102 may deposit a photoresist layer on polysilicon layer 224 and polysilicon layer 220 by a spin coating operation. Exposure machine 104 may form a pattern in the photoresist layer by exposing the photoresist layer to a radiation source to transfer the pattern from a photomask to the photoresist layer. Development machine 106 may perform a development operation that includes one or more techniques for developing the pattern in the photoresist layer. After the pattern has been developed, polysilicon layer 224 and polysilicon layer 220 may be rinsed to remove any residual chemical developer and polysilicon layer 224 and polysilicon layer 220 may be spun dry. The etching station 108 can etch the germanium layer 308 so that based on the pattern formed in the photoresist layer, portions of the germanium layer 308 are removed from the polysilicon layer 224 and from one or more portions of the polysilicon layer 220 (e.g., one or more portions of the polysilicon layer 220 that are not above the support structure 218) to form a germanium bonding pad 222 above the support structure 218. In some embodiments, a solvent or a chemical stripper is used to remove the remaining portion of the photoresist layer. In some embodiments, a plasma ashing process is used to remove the remaining portion of the photoresist layer. In these examples, a plasma source is used to form a plasma of oxygen ions or fluorine ions to react with the photoresist material. The reaction between the ions in the plasma and the photoresist material causes the photoresist material to form ash, which is removed using a vacuum pump.

[0084] like Figure 3J , one or more semiconductor processing machines can form the movable MEMS structure 214. The deposition machine 102 can deposit a photoresist layer on the polysilicon layer 224, the polysilicon layer 220, and the germanium bonding pad 222 by a spin coating operation. The exposure machine 104 can form a pattern in the photoresist layer by exposing the photoresist layer to a radiation source to transfer the pattern from the photomask to the photoresist layer. The development machine 106 can perform a development operation, which includes one or more techniques for developing the pattern in the photoresist layer. The etching machine 108 can etch through one or more portions of the polysilicon layer 224 and through one or more associated portions of the substrate 212 to form the movable MEMS structure 214. In some embodiments, a solvent or a chemical stripper is used to remove the remaining portion of the photoresist layer. In some embodiments, a plasma ashing process is used to remove the remaining portion of the photoresist layer. In these examples, a plasma source is used to form a plasma of oxygen ions or fluorine ions to react with the photoresist material. The reaction between the ions in the plasma and the photoresist material causes the photoresist material to form ash, which is removed using a vacuum pump.

[0085] like Figure 3K, the device wafer 204 and the circuit wafer 202 may be bonded. The semiconductor processing machine (e.g., the bonding machine 110) may bond the device wafer 204 and the circuit wafer 202 by performing a eutectic bonding process to form a eutectic bond between the germanium bonding pad 222 of the device wafer 204 and the metal bonding pad 208 of the circuit wafer 202. Eutectic bonding may be referred to as low temperature bonding because the bond between the materials of the germanium bonding pad 222 and the metal bonding pad 208 is formed at a temperature lower than the melting temperature of the materials of the germanium bonding pad 222 and the metal bonding pad 208. The bonding machine 110 may heat the device wafer 204 and the circuit wafer 202 so that the eutectic bond is formed between the germanium bonding pad 222 and the metal bonding pad 208. For example, if the metal bonding pad 208 is formed of an aluminum material, the bonding machine 110 may heat the device wafer 204 and the circuit wafer 202 so that the germanium bonding pad 222 and the metal bonding pad 208 are heated to about 425 degrees Celsius to form the eutectic bond. In some embodiments, the eutectic bonding process may be combined with an annealing process (eg, where the circuit wafer 202 and the device wafer 204 are heated to a high temperature of 1100 degrees Celsius or greater) to reduce stress caused by the eutectic bonding process at the bonding interface.

[0086] Eutectic bonding between device wafer 204 and circuit wafer 202 and fusion bonding between device wafer 204 and capping wafer 206 form a cavity 216 in which movable MEMS structure 214 is hermetically sealed. Cavity 216 permits movable MEMS structure 214 to move or actuate freely and prevents foreign objects and other contaminants from damaging movable MEMS structure 214.

[0087] As mentioned above, providing FIG. 3A to FIG. 3K As an example. Other examples may differ from the FIG. 3A to FIG. 3K Described example.

[0088] Figure 4 4 is a diagram of example components of device 400. In some embodiments, one or more of semiconductor processing tools 102 to semiconductor processing tools 110 and / or wafer / die transfer tool 112 may include one or more devices 400 and / or one or more components of device 400. Figure 4 As shown in FIG. 4 , device 400 may include a bus 410 , a processor 420 , a memory 430 , a storage component 440 , an input component 450 , an output component 460 , and a communication component 470 .

[0089] The bus 410 includes components that enable wired and / or wireless communications between components of the device 400. The processor 420 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit, and / or another type of processing component. The processor 420 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, the processor 420 includes one or more processors that can be programmed to perform functions. The memory 430 includes a random access memory, a read-only memory, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory).

[0090] Storage component 440 stores information and / or software related to the operation of device 400. For example, storage component 440 may include a hard disk drive, a disk drive, an optical drive, a solid state hard disk drive, a compact disc, a digital versatile disc, and / or another type of non-temporary computer-readable medium. Input component 450 enables device 400 to receive input, such as user input and / or sensed input. For example, input component 450 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, and / or an actuator. Output component 460 enables device 400 to provide output, such as via a display, a speaker, and / or one or more light-emitting diodes. Communication component 470 enables device 400 to communicate with other devices, such as via a wired connection and / or a wireless connection. For example, communication component 470 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0091] The device 400 may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 430 and / or storage component 440) may store an instruction set (e.g., one or more instructions, codes, software codes, and / or program codes) for execution by the processor 420. The processor 420 may execute the instruction set to perform one or more processes described herein. In some embodiments, execution of the instruction set by one or more processors 420 causes one or more processors 420 and / or the device 400 to perform one or more processes described herein. In some embodiments, hard-wired circuits may be used instead of or in conjunction with instructions to perform one or more processes described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardware circuits and software.

[0092] supply Figure 4 The number and arrangement of components shown in FIG. are examples. Figure 4Device 400 may include additional components, fewer components, different components, or components arranged in a different manner than those illustrated in . Additionally or alternatively, one set of components (e.g., one or more components) of device 400 may perform one or more functions described as being performed by another set of components of device 400.

[0093] Figure 5 FIG. 5 is a flow chart of an example process 500 associated with forming a semiconductor device described herein. In some embodiments, Figure 5 One or more process blocks of may be performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 to 110). Additionally or alternatively, Figure 5 One or more process blocks of may be performed by one or more components of device 400, such as processor 420, memory 430, storage component 440, input component 450, output component 460, and / or communication component 470.

[0094] like Figure 5 , process 500 may include forming a polysilicon layer over a substrate of a device wafer of a MEMS device (block 510). For example, a semiconductor processing tool (e.g., deposition tool 102) may form polysilicon layer 302 over substrate 212 of device wafer 204 of MEMS device 200, as described above.

[0095] like Figure 5 As further shown in FIG. 5 , process 500 may include increasing a surface roughness of a first portion of the polysilicon layer relative to a surface roughness of one or more second portions of the polysilicon layer such that the surface roughness of the first portion is greater relative to the surface roughness of the one or more second portions (block 520). For example, one or more semiconductor processing tools (e.g., deposition tool 102, exposure tool 104, developer tool 106, etch tool 108, and / or another semiconductor processing tool) may increase a surface roughness of a first portion of the polysilicon layer 302 (e.g., polysilicon layer 224) relative to a surface roughness of one or more second portions of the polysilicon layer 302 (e.g., polysilicon layer 220) such that the surface roughness of the first portion is greater relative to the surface roughness of the one or more second portions, as described above.

[0096] like Figure 5 As further shown in FIG. 5 , process 500 may include etching through portions of the first portion and through associated portions of the substrate to form a plurality of movable MEMS structures (block 530). For example, a semiconductor processing tool (e.g., etching tool 108) may etch through portions of the first portion and through associated portions of the substrate 212 to form a plurality of movable MEMS structures 214, as described above.

[0097] like Figure 5 As further shown in FIG. 5 , process 500 may include bonding the device wafer and the circuit wafer of the MEMS device after forming the plurality of movable MEMS structures (block 540). For example, a semiconductor processing tool (e.g., bonding tool 110) may bond device wafer 204 and circuit wafer 202 of MEMS device 200 after forming the plurality of movable MEMS structures 214, as described above.

[0098] Process 500 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0099] In a first embodiment, the surface roughness Rq of the one or more second portions is less than about 30 nanometers. In a second embodiment, alone or in combination with the first embodiment, the process 500 includes bonding the device wafer 204 of the MEMS device 200 with the capping wafer 206 (e.g., by the bonding machine 110), and wherein forming the polysilicon layer 302 includes forming the polysilicon layer 302 after bonding the device wafer 204 with the capping wafer 206. In a third embodiment, alone or in combination with one or more of the first and second embodiments, bonding the device wafer 204 and the capping wafer 206 of the MEMS device 200 includes fusion bonding the device wafer 204 and the capping wafer 206.

[0100] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 500 includes forming a germanium layer 308 on a first portion and on one or more second portions (e.g., by a deposition machine 102) before bonding the device wafer 204 and the circuit wafer 202, and removing one or more portions of the germanium layer 308 on the first portion (e.g., by a deposition machine 102, an exposure machine 104, a developer machine 106, an etch machine 108, and / or another semiconductor processing machine) to form one or more germanium bonding pads 222. In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, bonding the device wafer 204 and the circuit wafer 202 includes forming a eutectic bond between the one or more germanium bonding pads 222 and the one or more metal bonding pads 208 of the circuit wafer 202.

[0101] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, increasing the surface roughness of the first portion includes: forming an oxide layer 304 on the polysilicon layer 302 (e.g., by a deposition machine 102), wherein the oxide layer 304 oxidizes a top surface of the first portion; and etching (e.g., by an etching machine 108) the oxide layer 304 on the first portion, wherein oxidation of the top surface and etching of the oxide layer 304 on the first portion increase the surface roughness of the first portion. In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, forming the polysilicon layer 302 includes forming the polysilicon layer 302 to a thickness equal to or less than about 10,000 angstroms.

[0102] In an eighth embodiment, alone or in combination with one or more of the first to seventh embodiments, increasing the surface roughness of the first portion includes increasing the surface roughness of the first portion to reduce the possibility of stiction between the plurality of movable MEMS structures 214 and the passivation layer 210 on the circuit wafer 202. In a ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, increasing the surface roughness of the first portion includes increasing the surface roughness of the first portion to reduce the surface area on the bottom of the plurality of movable MEMS structures 214. In a tenth embodiment, alone or in combination with one or more of the first to ninth embodiments, increasing the surface roughness of the first portion includes increasing the surface roughness of the first portion to a specific surface roughness such that the MEMS device 200 meets a threshold drop test cycle.

[0103] Although Figure 5 An example block diagram of process 500 is shown, but in some implementations, Figure 5 Process 500 may include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner than the blocks depicted in . Additionally or alternatively, two or more than two of the blocks of process 500 may be performed in parallel.

[0104] In this way, a MEMS device can be formed to include an anti-static friction polysilicon layer on one or more movable MEMS structures of a device wafer of the MEMS device to reduce, minimize and / or eliminate static friction between the movable MEMS structure and other components or structures of the MEMS device. The anti-static friction polysilicon layer can be formed on the bottom surface of each of the movable MEMS structures. The anti-static friction polysilicon layer can be formed so that the surface roughness of the anti-static friction polysilicon layer is greater than the surface roughness of the bonding polysilicon layer on the surface of the device wafer to be bonded to the circuit wafer of the MEMS device. The higher surface roughness of the anti-static friction polysilicon layer can reduce the surface area of ​​the bottom of the movable MEMS structure, which may reduce the friction between the movable MEMS structure and other surfaces that can contact the movable MEMS structure. This may reduce the possibility that the movable MEMS structure will adhere to other surfaces. The lower surface roughness of the bonding polysilicon layer can provide a larger surface area relative to the anti-static friction polysilicon layer, which can promote eutectic bonding between the device wafer and the circuit wafer.

[0105] As described in more detail above, some embodiments described herein provide a MEMS device. The MEMS device includes a capping wafer. The MEMS device includes a circuit wafer. The MEMS device includes a device wafer between the capping wafer and the circuit wafer. The MEMS device includes one or more movable MEMS structures in a cavity formed by the capping wafer, the circuit wafer, and the device wafer. The MEMS device includes a first polysilicon layer on a bottom surface of the one or more movable MEMS structures. The MEMS device includes a second polysilicon layer between the device wafer and the circuit wafer, wherein the surface roughness of the first polysilicon layer is different from the surface roughness of the second polysilicon layer.

[0106] In some embodiments, the surface roughness of the second polysilicon layer has a root mean square roughness of less than about 30 nanometers to promote eutectic bonding between the device wafer and the circuit wafer. In some embodiments, the surface roughness of the first polysilicon layer is greater relative to the surface roughness of the second polysilicon layer. In some embodiments, the surface roughness of the first polysilicon layer is greater relative to the surface roughness of the second polysilicon layer to reduce static friction between the movable micro-electromechanical system structure in the one or more movable micro-electromechanical system structures and the circuit wafer. In some embodiments, the second polysilicon layer is formed on one or more support structures of the device wafer. In some embodiments, the second polysilicon layer is formed on a surface of the one or more support structures facing the circuit wafer. In some embodiments, the micro-electromechanical system device further includes a germanium layer, the germanium layer between the second polysilicon layer and the circuit wafer to promote eutectic bonding between the device wafer and the circuit wafer.

[0107] As described in more detail above, some embodiments described herein provide a method. The method includes forming a polysilicon layer over a substrate of a device wafer of a MEMS device. The method includes increasing the surface roughness of a first portion of the polysilicon layer relative to the surface roughness of one or more second portions of the polysilicon layer so that the surface roughness of the first portion is greater relative to the surface roughness of the one or more second portions. The method includes etching through multiple portions of the first portion and through multiple associated portions of the substrate to form multiple movable MEMS structures. The method includes, after forming the multiple movable MEMS structures, bonding the device wafer to a circuit wafer of the MEMS device.

[0108] In some embodiments, the surface roughness of the one or more second portions has a root mean square roughness of less than about 30 nanometers. In some embodiments, the method further includes bonding the device wafer to a capping wafer of the MEMS device, wherein forming the polysilicon layer includes forming the polysilicon layer after bonding the device wafer to the capping wafer. In some embodiments, bonding the device wafer of the MEMS device to the capping wafer includes melt bonding the device wafer to the capping wafer. In some embodiments, the method further includes forming a germanium layer on the first portion and on the one or more second portions before bonding the device wafer to the circuit wafer; and removing one or more portions of the germanium layer on the first portion to form one or more germanium bonding pads. In some embodiments, bonding the device wafer to the circuit wafer includes forming a eutectic bond between the one or more germanium bonding pads and one or more metal bonding pads of the circuit wafer. In some embodiments, increasing the surface roughness of the first portion includes forming an oxide layer on the polysilicon layer, wherein the oxide layer oxidizes the top surface of the first portion, and etching the oxide layer on the first portion, wherein the oxidation of the top surface and etching the oxide layer on the first portion increase the surface roughness of the first portion. In some embodiments, forming the polysilicon layer includes forming the polysilicon layer to a thickness equal to or less than about 10,000 angstroms. In some embodiments, increasing the surface roughness of the first portion includes increasing the surface roughness of the first portion to reduce the likelihood of stiction between the movable microelectromechanical system structure and the passivation layer on the circuit wafer. In some embodiments, increasing the surface roughness of the first portion includes increasing the surface roughness of the first portion to reduce the surface area on the bottom of the movable microelectromechanical system structure. In some embodiments, increasing the surface roughness of the first portion includes increasing the surface roughness of the first portion to a specific surface roughness so that the microelectromechanical system device meets a threshold for drop test cycles.

[0109] As described in more detail above, some embodiments described herein provide a MEMS device. The MEMS device includes a capping wafer. The MEMS device includes a circuit wafer, the circuit wafer including a metal bonding pad. The MEMS device includes a device wafer between the capping wafer and the circuit wafer, the device wafer including a support structure and a germanium bonding pad between the metal bonding pad and the support structure. The MEMS device includes one or more movable MEMS structures in a cavity formed by the capping wafer, the circuit wafer, and the device wafer. The MEMS device includes a first polysilicon layer on the bottom surface of the one or more movable MEMS structures. The MEMS device includes a second polysilicon layer between the support structure and the germanium bonding pad, wherein the surface roughness of the first polysilicon layer is different from the surface roughness of the second polysilicon layer.

[0110] In some embodiments, the capping wafer and the device wafer are fusion-bonded via an intervening oxide layer, and the circuit wafer and the device wafer are eutectic-bonded at the germanium bonding pad and the metal bonding pad.

[0111] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A micro-electromechanical system device, comprising: Capping wafer; Circuit chip; A device wafer, between the cover wafer and the circuit wafer; one or more movable MEMS structures in a cavity formed by the cap wafer, the circuit wafer, and the device wafer; a first polysilicon layer on a bottom surface of the one or more movable MEMS structures; as well as A second polysilicon layer is provided between the device wafer and the circuit wafer, wherein the surface roughness of the first polysilicon layer is different from the surface roughness of the second polysilicon layer. 2 . The MEMS device of claim 1 , wherein the surface roughness of the second polysilicon layer has a root mean square roughness of less than about 30 nanometers to facilitate eutectic bonding between the device wafer and the circuit wafer. 3 . The MEMS device according to claim 1 , wherein the surface roughness of the first polysilicon layer is greater than the surface roughness of the second polysilicon layer.

4. The MEMS device according to claim 1, wherein the surface roughness of the first polysilicon layer is greater than the surface roughness of the second polysilicon layer to reduce static friction between the movable MEMS structure in the one or more movable MEMS structures and the circuit chip. 5 . The MEMS device of claim 1 , wherein the second polysilicon layer is formed on one or more supporting structures of the device wafer. 6 . The MEMS device according to claim 5 , wherein the second polysilicon layer is formed on a surface of the one or more support structures facing the circuit wafer.

7. The MEMS device according to claim 1, further comprising: A germanium layer is between the second polysilicon layer and the circuit wafer to promote eutectic bonding between the device wafer and the circuit wafer.

8. A method for manufacturing a micro-electromechanical system device, comprising: forming a first polysilicon layer and a second polysilicon layer over a substrate of a device wafer of a MEMS device; Increasing the surface roughness of the first polysilicon layer relative to the surface roughness of the second polysilicon layer, so that the surface roughness of the first polysilicon layer is greater than the surface roughness of the second polysilicon layer; etching through portions of the first polysilicon layer and through associated portions of the substrate to form a plurality of movable MEMS structures; as well as After forming the movable MEMS structure, the device wafer and the circuit wafer of the MEMS device are bonded. 9 . The method for manufacturing a MEMS device according to claim 8 , wherein a root mean square roughness of the surface roughness of the second polysilicon layer is less than about 30 nanometers.

10. The method for manufacturing a MEMS device according to claim 8, further comprising: bonding the device wafer to a cap wafer of the MEMS device, and The forming of the polysilicon layer comprises: The polysilicon layer is formed after bonding the device wafer and the capping wafer.

11. The method for manufacturing a MEMS device according to claim 10, wherein bonding the device wafer of the MEMS device and the capping wafer comprises: The device wafer and the capping wafer are fusion bonded.

12. The method for manufacturing a MEMS device according to claim 8, further comprising: Before bonding the device wafer and the circuit wafer, forming a germanium layer on the first polysilicon layer and on the second polysilicon layer; as well as One or more portions of the germanium layer on the first polysilicon layer are removed to form one or more germanium bonding pads.

13. The method for manufacturing a MEMS device according to claim 12, wherein bonding the device wafer and the circuit wafer comprises: A eutectic bond is formed between the one or more germanium bond pads and one or more metal bond pads of the circuit wafer.

14. The method for manufacturing a MEMS device according to claim 8, wherein increasing the surface roughness of the first polysilicon layer comprises: forming an oxide layer on the polysilicon layer, wherein the oxide layer oxidizes a top surface of the first polysilicon layer; as well as The oxide layer on the first polysilicon layer is etched, wherein oxidation of the top surface and etching of the oxide layer on the first polysilicon layer increase the surface roughness of the first polysilicon layer.

15. The method for manufacturing a micro-electromechanical system device according to claim 8, wherein forming the polysilicon layer comprises: The polysilicon layer is formed to a thickness equal to or less than about 10,000 angstroms.

16. The method for manufacturing a MEMS device according to claim 8, wherein increasing the surface roughness of the first polysilicon layer comprises: The surface roughness of the first polysilicon layer is increased to reduce the likelihood of stiction between the movable MEMS structure and a passivation layer on the circuit wafer.

17. The method for manufacturing a MEMS device according to claim 8, wherein increasing the surface roughness of the first polysilicon layer comprises: The surface roughness of the first polysilicon layer is increased to reduce the surface area on the bottom of the movable MEMS structure.

18. The method for manufacturing a MEMS device according to claim 8, wherein increasing the surface roughness of the first polysilicon layer comprises: The surface roughness of the first polysilicon layer is increased to a specific surface roughness so that the micro-electromechanical system device meets a threshold of a drop test cycle.

19. A micro-electromechanical system device, comprising: Capping wafer; A circuit chip including metal bonding pads; A device wafer, between the cover wafer and the circuit wafer, the device wafer comprising: Support structures; and a germanium bonding pad between the metal bonding pad and the support structure; one or more movable MEMS structures in a cavity formed by the cap wafer, the circuit wafer, and the device wafer; a first polysilicon layer on a bottom surface of the one or more movable MEMS structures; and A second polysilicon layer is provided between the support structure and the germanium bonding pad, wherein a surface roughness of the first polysilicon layer is different from a surface roughness of the second polysilicon layer. 20 . The MEMS device according to claim 19 , wherein the capping wafer and the device wafer are melt-bonded via an intervening oxide layer, and the circuit wafer and the device wafer are eutectic-bonded at the germanium bonding pad and the metal bonding pad.

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