Signal Processing Method, Device, and Processing Chip

Abstract

Embodiments of the present invention provide a signal processing method, device, and processing chip, relating to the technical field of signal processing. The signal processing method includes: encoding an audio-visual signal to be processed into an input pulse signal that lasts for multiple pulse cycles; when the processing chip is configured for each pulse cycle of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains an output pulse signal of the spiking neural network within the pulse cycle based on the input pulse signal within the pulse cycle; according to the output pulse signals of the spiking neural network within multiple pulse cycles, a processing result after the audio-visual signal is processed by the spiking neural network is obtained. In the present invention, complex streamline operations of a spiking neural network can be implemented using a single processing chip, reducing the computing power requirements for the processing chip.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and particularly to a signal processing method, device, and processing chip. Background Art

[0002] In recent years, the research on Deep Neural Networks (DNN) has achieved rapid development and has been initially applied. However, DNN algorithms usually consume a large amount of computing power, and such a large consumption of computing power also brings greater power consumption. For example, for the classic deep convolutional network (CNN) model AlexNet, at least 720 million multiplication operations are required, and the general power consumption is about 10 to 100 watts.

[0003] To improve the classification accuracy, the structure of DNN has become increasingly complex. Currently, there are already DNNs with more than 1000 layers. Even at the edge, DNNs generally require about 50 layers. Due to the limitations of chip computing resources and storage resources, when hardware-accelerating complex DNNs, it is rarely possible to map the entire DNN onto the chip at once. Currently, a streamlining operation method is generally adopted. For example, the first layer is mapped onto the chip, and the chip performs operations while preparing the weights of the second layer. After the chip finishes calculating the first layer, it performs the second layer operation. And so on until all layers are calculated.

[0004] In recent years, Spiking Neural Networks (SNN) have attracted the attention of the academic and industrial communities due to their low power consumption and closer resemblance to the human brain. In SNN, axons are units that receive spikes, neurons are units that send spikes, a neuron is connected to multiple axons through dendrites, and the connection point between the dendrite and the axon is called a synapse. After an axon receives a spike, all dendrites with synaptic connections to this axon will receive the spike, which in turn affects the downstream neurons of the dendrite. The neuron adds the spikes from multiple axons and accumulates them with the previous membrane voltage. If the value exceeds the threshold, it sends a spike downstream. In SNN, 1-bit spikes are propagated, the activation frequency of the spikes is relatively low, and only addition and subtraction operations are required without multiplication operations, so the computing power consumption and power consumption are lower than those of DNN. Therefore, DNN can be pulsed into SNN to make full use of the low power consumption advantage of SNN.

[0005] However, when using SNN hardware to accelerate the pulsed DNN, problems of insufficient resources also occur. If the scale of the pulsed DNN is large and the network needs to be mapped onto multiple chips for parallel operation of multiple chips, it will lead to the problem of too high cost. Summary of the Invention

[0006] The object of the present invention is to provide a signal processing method, device and processing chip, which can realize the streamline operation of a complex spiking neural network by using a single processing chip, reducing the computing power requirement for the processing chip; at the same time, it is applicable to the spiking neural network obtained by pulse conversion of a deep neural network, avoiding the cost consumption caused by the need to map a complex network to multiple chips.

[0007] To achieve the above object, the present invention provides a signal processing method, including: encoding an audio-visual signal to be processed into an input pulse signal that lasts for multiple pulse cycles; when the processing chip is configured in each of the pulse cycles of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains an output pulse signal of the spiking neural network within the pulse cycle based on the input pulse signal within the pulse cycle; obtaining a processing result of the audio-visual signal after being processed by the spiking neural network according to the output pulse signals of the spiking neural network within the multiple pulse cycles.

[0008] The present invention also provides a processing chip for executing the above signal processing method.

[0009] The present invention also provides a signal processing device, including: the above processing chip.

[0010] In an embodiment of the present invention, first, an audio-visual signal to be processed is encoded into an input pulse signal that lasts for multiple pulse cycles. When the processing chip is configured in each of the pulse cycles of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains an output pulse signal of the spiking neural network within the pulse cycle based on the input pulse signal within the pulse cycle. Then, a processing result of the audio-visual signal after being processed by the spiking neural network is obtained according to the output pulse signals of the spiking neural network within the multiple pulse cycles. That is, when using a spiking neural network to process an input pulse signal including multiple pulse cycles, streamline operation is first performed on the layers, and then streamline operation is performed on the cycles, so that the streamline operation of a complex spiking neural network can be realized by using a single processing chip, reducing the computing power requirement for the processing chip; at the same time, it is applicable to the spiking neural network obtained by pulse conversion of a deep neural network, avoiding the cost consumption caused by the need to map a complex network to multiple chips.

[0011] In one embodiment, when the processing chip is configured for each pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains the output pulse signal of the spiking neural network within the pulse period based on the input pulse signal within the pulse period, including: when the processing chip is configured for the first pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains the output pulse signal of the spiking neural network within the first pulse period based on the input pulse signal within the first pulse period; when the processing chip is configured for the Nth pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains the output pulse signal of the spiking neural network within the Nth pulse period based on the input pulse signal within the Nth pulse period and the membrane voltages of each layer of the spiking neural network within the (N - 1)th pulse period.

[0012] In one embodiment, when the processing chip is configured for the first pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains the output pulse signal of the spiking neural network within the first pulse period based on the input pulse signal within the first pulse period, including: when the processing chip is configured for the first pulse period of the input pulse signal, if the first layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the spiking neural network within the first pulse period based on the input pulse signal within the first pulse period; if the Mth layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the spiking neural network within the Mth pulse period based on the output pulse signal of the spiking neural network within the (M - 1)th pulse period within the first pulse period; M is an integer greater than 1; the output pulse signal of the spiking neural network within the last layer within the first pulse period is used as the output pulse signal of the spiking neural network.

[0013] In one embodiment, when the processing chip is configured in the Nth pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip. The processing chip obtains the output pulse signal of the spiking neural network in the Nth pulse period based on the input pulse signal in the Nth pulse period and the membrane voltages of the spiking neural network in each layer in the (N - 1)th pulse period, including: when the processing chip is configured in the Nth pulse period of the input pulse signal and the first layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the spiking neural network in the first layer in the Nth pulse period according to the input pulse signal in the Nth pulse period and the membrane voltage of the spiking neural network in the first layer in the (N - 1)th pulse period; when the Mth layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the spiking neural network in the Mth layer in the Nth pulse period according to the output pulse signal of the spiking neural network in the (M - 1)th layer in the Nth pulse period and the membrane voltage of the spiking neural network in the Mth layer in the (N - 1)th pulse period, where M is an integer greater than 1; and taking the output pulse signal of the spiking neural network in the last layer in the Nth pulse period as the output pulse signal of the spiking neural network.

[0014] In one embodiment, when the first layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the spiking neural network in the first layer in the Nth pulse period according to the input pulse signal in the Nth pulse period and the membrane voltage of the spiking neural network in the first layer in the (N - 1)th pulse period, including: when the first layer of the spiking neural network is mapped into the processing chip, the processing chip calculates the weighted product of the input pulse signal in the Nth pulse period and the weights of the spiking neural network in the first layer, and calculates the sum of the product and the membrane voltage of the spiking neural network in the first layer in the (N - 1)th pulse period as the membrane voltage of the spiking neural network in the first layer in the Nth pulse period; and obtains the output pulse signal of the spiking neural network in the first layer in the Nth pulse period according to the membrane voltage of the spiking neural network in the first layer in the Nth pulse period and a preset membrane voltage threshold.

[0015] In one embodiment, when the M-th layer of the spiking neural network is mapped to the processing chip, the processing chip obtains the membrane voltage and output pulse signal of the M-th layer of the spiking neural network in the N-th pulse period based on the output pulse signal of the spiking neural network in the (M - 1)-th layer in the N-th pulse period and the membrane voltage of the spiking neural network in the M-th layer in the (N - 1)-th pulse period, including: when the M-th layer of the spiking neural network is mapped to the processing chip, the processing chip calculates the weighted product of the output pulse signal of the spiking neural network in the (M - 1)-th layer in the N-th pulse period and the weights of the spiking neural network in the M-th layer, and calculates the sum of the product and the membrane voltage of the spiking neural network in the M-th layer in the (N - 1)-th pulse period as the membrane voltage of the spiking neural network in the M-th layer in the N-th pulse period; and obtains the output pulse signal of the spiking neural network in the M-th layer in the N-th pulse period based on the membrane voltage of the spiking neural network in the M-th layer in the N-th pulse period and a preset membrane voltage threshold.

[0016] In one embodiment, the processing chip is used to map two layers of the spiking neural network simultaneously; the processing chip includes multiple neuron cores, which are divided into two groups, and each group of neuron cores is used to map at least one layer of the spiking neural network; each layer of the spiking neural network is sequentially mapped to the processing chip. When the (M - 1)-th layer of the spiking neural network is mapped to one group of neuron cores in the processing chip, the M-th layer of the spiking neural network is mapped to the other group of neuron cores in the processing chip, where M is an integer greater than 1.

[0017] In one embodiment, the cache space of each neuron core included in the processing chip includes: a first cache space and a second cache space; for each neuron core, when the first cache space of the neuron core caches the weights of the (M - 1)-th layer of the spiking neural network, the second cache space of the neuron core caches the weights of the M-th layer of the spiking neural network, where M is an integer greater than 1. Description of the Drawings

[0018] Figure 1 is the specific flowchart of the signal processing method according to the first embodiment of the present invention;

[0019] Figure 2 is the specific flowchart of the signal processing method according to the second embodiment of the present invention;

[0020] Figure 3 is Figure 2 the specific flowchart of sub-step 2021 of the signal processing method in

[0021] Figure 4 isFigure 2 Specific flowchart of sub-step 2022 of the signal processing method in

[0022] Figure 5 is the signal processing timing diagram of the three-layer pulsed neural network according to the second embodiment of the present invention;

[0023] Figure 6 is a schematic diagram of the processing chip according to the third embodiment of the present invention;

[0024] Figure 7 is a schematic diagram of the neuron core in the processing chip according to the third embodiment of the present invention;

[0025] Figure 8 is a schematic diagram of the processing chip according to the fourth embodiment of the present invention;

[0026] Figure 9 is a schematic diagram of signal processing by the processing chip according to the fourth embodiment of the present invention;

[0027] Figure 10 is a schematic diagram of the signal processing device according to the fifth embodiment of the present invention. Detailed Description of the Invention

[0028] The following will describe each embodiment of the present invention in detail with reference to the accompanying drawings to more clearly understand the purpose, features, and advantages of the present invention. It should be understood that the embodiments shown in the drawings are not limitations on the scope of the present invention, but only to illustrate the essential spirit of the technical solution of the present invention.

[0029] In the following description, for the purpose of explaining various disclosed embodiments, certain specific details are set forth to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments can be practiced without one or more of these specific details. In other instances, well-known devices, structures, and techniques associated with the present application may not be shown or described in detail so as not to unnecessarily obscure the description of the embodiments.

[0030] Unless the context requires otherwise, throughout the specification and claims, the words "comprising" and its variants, such as "including" and "having" should be understood in an open, inclusive sense, i.e., should be interpreted as "including, but not limited to".

[0031] References to "one embodiment" or "an embodiment" throughout the specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily all refer to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

[0032] As used in this specification and the appended claims, the singular forms "a" and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally used in its inclusive sense of "and / or" unless the context clearly dictates otherwise.

[0033] In the following description, in order to clearly show the structure and working mode of the present invention, many directional terms will be used for description. However, terms such as "front", "rear", "left", "right", "outer", "inner", "outward", "inward", "up", "down", etc. should be understood as convenient terms rather than restrictive terms.

[0034] The first embodiment of the present invention relates to a signal processing method applied to a processing chip. The processing chip can use this signal processing method to map a spiking neural network to process an audio-visual signal and obtain a corresponding processing result, and this processing result can be used for the classification of the audio-visual signal. Among them, the spiking neural network can also be obtained by pulseifying a deep neural network.

[0035] The specific process of the signal processing method in this embodiment is as Figure 1 shown.

[0036] Step 101, encode the audio-visual signal to be processed into an input pulse signal that lasts for multiple pulse cycles.

[0037] Specifically, after receiving the audio-visual signal to be processed, the processing chip can use the pulse coding module in the processing chip to encode the audio-visual signal into an input pulse signal including X pulse cycles, where X is an integer greater than 1. The input pulse signal of X pulse cycles can be respectively represented as: per(1), per(2),..., per(X), and per(N) represents the Nth pulse cycle among the X pulse cycles, where 1 < N ≤ X. It should be noted that in this embodiment, the example of including a pulse coding module in the processing chip is used for illustration, but it is not limited thereto. The audio-visual signal can also be encoded by an external coding module connected to the processing chip, and then the input pulse signal including X pulse cycles obtained by encoding is directly input into the processing chip.

[0038] Step 102, when the processing chip is configured for each pulse cycle of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains the output pulse signal of the spiking neural network within the pulse cycle based on the input pulse signal within the pulse cycle.

[0039] Specifically, when processing an input pulse signal including X pulse cycles using a spiking neural network, streamline operations are first performed on the layers, and then streamline operations are performed on the cycles. According to the cycle order of the input pulse signal, processing chips are sequentially configured in each pulse cycle of the input pulse signal. The spiking neural network includes Y layers, where Y is an integer greater than 1. The Y layers of the spiking neural network can be respectively represented as: layer(1), layer(2), ……, layer(Y), and layer(M) represents the Mth layer among the Y layers of the spiking neural network, where 1 < M ≤ Y. When a processing chip is configured in each pulse cycle, the processing chip sequentially maps layer(1) to layer(Y) of the spiking neural network in the order of the layers. The processing chip uses the output when mapping layer(Y) as the output pulse signal of the spiking neural network within that pulse cycle. Thus, the output pulse signals of the spiking neural network in each pulse cycle can be obtained.

[0040] Step 103: Obtain the processing result of the audio-visual signal after being processed by the spiking neural network based on the output pulse signals of the spiking neural network in multiple pulse cycles.

[0041] Specifically, in the order of the pulse cycles, the output pulse signals of the spiking neural network are combined to obtain the processing result of the audio-visual signal after being processed by the spiking neural network, and this processing result can be used for the classification of the audio-visual signal.

[0042] This embodiment provides a signal processing method. First, the audio-visual signal to be processed is encoded into an input pulse signal that lasts for multiple pulse cycles. When a processing chip is configured in each pulse cycle of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip. The processing chip obtains the output pulse signal of the spiking neural network within the pulse cycle based on the input pulse signal within the pulse cycle, and then further obtains the processing result of the audio-visual signal after being processed by the spiking neural network based on the output pulse signals of the spiking neural network in multiple pulse cycles. That is, when using a spiking neural network to process an input pulse signal including multiple pulse cycles, streamline operations are first performed on the layers, and then streamline operations are performed on the cycles, so that the streamline operations of a complex spiking neural network can be realized using a single processing chip, reducing the computing power requirement for the processing chip. At the same time, it is applicable to the spiking neural network obtained by pulse-ifying a deep neural network, avoiding the cost consumption caused by mapping a complex network to multiple chips.

[0043] The second embodiment of the present invention relates to a signal processing method. Compared with the first embodiment, in this embodiment, when the processing chip is configured for each pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains the output pulse signal of the spiking neural network within the pulse period based on the input pulse signal within the pulse period, which is a specific implementation.

[0044] The specific process of the signal processing method in this embodiment is as Figure 2 shown.

[0045] Step 201: Encode the audio-visual signal to be processed into an input pulse signal that lasts for multiple pulse periods. This is substantially the same as step 101 of the first embodiment and will not be elaborated here.

[0046] Step 202 includes the following sub-steps:

[0047] Sub-step 2021: When the processing chip is configured for the first pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains the output pulse signal of the spiking neural network within the first pulse period based on the input pulse signal within the first pulse period.

[0048] Please refer to Figure 3 , sub-step 2021 includes:

[0049] Sub-step 20211: When the processing chip is configured for the first pulse period of the input pulse signal, if the first layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the spiking neural network in the first layer within the first pulse period according to the input pulse signal within the first pulse period.

[0050] Sub-step 20212: If the Mth layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the spiking neural network in the Mth layer within the first pulse period according to the output pulse signal of the spiking neural network in the (M - 1)th layer within the first pulse period; M is an integer greater than 1.

[0051] Sub-step 20213: Use the output pulse signal of the spiking neural network in the last layer within the first pulse period as the output pulse signal of the spiking neural network.

[0052] Specifically, when the processing chip is configured for the first pulse period per(1) of the input pulse signal, within the first pulse period per(1), each layer of the spiking neural network is sequentially mapped into the processing chip, and when the processing chip maps each layer of the spiking neural network, there is no need to accumulate the membrane voltage.

[0053] When the first layer layer(1) of the spiking neural network is mapped to the processing chip, the weights of the first layer layer(1) of the spiking neural network are cached in the processing chip. At this time, the input pulse signal of the first pulse period per(1) is used as the input of the processing chip. The processing chip calculates the product of the input pulse signal of the first pulse period per(1) and the weights of the first layer layer(1). This product is the membrane voltage of the spiking neural network at the first layer during the first pulse period. A membrane voltage threshold is preset in the processing chip. Then, the membrane voltage of the spiking neural network at the first layer layer(1) during the first pulse period per(1) is compared with this membrane voltage threshold. When the membrane voltage of the spiking neural network at the first layer layer(1) during the first pulse period per(1) is greater than or equal to this membrane voltage threshold, the output pulse signal of the spiking neural network at the first layer layer(1) during the first pulse period is 1; when the membrane voltage of the first layer layer(1) is less than this membrane voltage threshold, the output pulse signal of the spiking neural network at the first layer layer(1) during the first pulse period per(1) is 0.

[0054] When the Mth layer layer(M) of the spiking neural network is mapped to the processing chip, the weights of the Mth layer layer(M) of the spiking neural network are cached in the processing chip. At this time, the output pulse signal of the (M - 1)th layer of the spiking neural network during the first pulse period per(1) is used as the input of the processing chip. The processing chip calculates the product of the output pulse signal of the (M - 1)th layer of the spiking neural network during the first pulse period per(1) and the weights of the Mth layer layer(M). This product is the membrane voltage of the spiking neural network at the Mth layer during the first pulse period. A membrane voltage threshold is preset in the processing chip. Then, the membrane voltage of the spiking neural network at the Mth layer layer(M) during the first pulse period is compared with this membrane voltage threshold. When the membrane voltage of the Mth layer layer(M) is greater than or equal to this membrane voltage threshold, the output pulse signal of the spiking neural network at the Mth layer layer(M) during the first pulse period is 1; when the membrane voltage of the Mth layer layer(M) is less than this membrane voltage threshold, the output pulse signal of the spiking neural network at the Mth layer layer(M) during the first pulse period is 0.

[0055] Taking M = 2 as an example, at this time, the second layer layer(2) of the spiking neural network is mapped to the processing chip, and the weights of the second layer layer(2) of the spiking neural network are cached in the processing chip. At this time, the output pulse signal of the first layer layer(1) of the spiking neural network in the first pulse period per(1) is used as the input of the processing chip. The processing chip calculates the product of the output pulse signal of the first layer of the spiking neural network in the first pulse period per(1) and the weights of the second layer layer(2). This product is the membrane voltage of the spiking neural network in the second layer layer(2) in the first pulse period. A membrane voltage threshold is preset in the processing chip, and then the membrane voltage of the spiking neural network in the second layer layer(2) in the first pulse period is compared with this membrane voltage threshold. When the membrane voltage of the second layer layer(2) is greater than or equal to this membrane voltage threshold, the output pulse signal of the spiking neural network in the second layer layer(2) in the first pulse period is 1; when the membrane voltage of the second layer layer(2) is less than this membrane voltage threshold, the output pulse signal of the spiking neural network in the second layer layer(2) in the first pulse period is 0.

[0056] And so on, until M = Y, the last layer layer(Y) of the spiking neural network is mapped to the processing chip to cache the weights of the Y-th layer layer(Y) of the spiking neural network. At this time, the output pulse signal of the (Y - 1)-th layer of the spiking neural network in the first pulse period per(1) is used as the input of the processing chip. The processing chip calculates the product of the output pulse signal of the (Y - 1)-th layer of the spiking neural network in the first pulse period per(1) and the weights of the Y-th layer layer(Y). This product is the membrane voltage of the spiking neural network in the Y-th layer layer(Y) in the first pulse period. A membrane voltage threshold is preset in the processing chip, and then the membrane voltage of the spiking neural network in the Y-th layer layer(Y) in the first pulse period is compared with this membrane voltage threshold. When the membrane voltage of the Y-th layer layer(Y) is greater than or equal to this membrane voltage threshold, the output pulse signal of the spiking neural network in the Y-th layer layer(Y) in the first pulse period is 1; when the membrane voltage of the Y-th layer layer(Y) is less than this membrane voltage threshold, the output pulse signal of the spiking neural network in the Y-th layer layer(Y) in the first pulse period is 0.

[0057] Subsequently, the output pulse signal of the spiking neural network in the last layer layer(Y) in the first pulse period per(1) is used as the output pulse signal of the spiking neural network in the first pulse period per(1).

[0058] Sub-step 2022: When the processing chip is configured in the Nth pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip. The processing chip obtains the output pulse signal of the spiking neural network in the Nth pulse period based on the input pulse signal in the Nth pulse period and the membrane voltages of each layer of the spiking neural network in the (N - 1)th pulse period.

[0059] Please refer to Figure 4 , sub-step 2022 includes:

[0060] Sub-step 20221: When the processing chip is configured in the Nth pulse period of the input pulse signal and the first layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the first layer of the spiking neural network in the Nth pulse period based on the input pulse signal in the Nth pulse period and the membrane voltage of the first layer of the spiking neural network in the (N - 1)th pulse period.

[0061] Sub-step 20222: When the Mth layer of the spiking neural network is mapped into the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the Mth layer of the spiking neural network in the Nth pulse period based on the output pulse signal of the (M - 1)th layer of the spiking neural network in the Nth pulse period and the membrane voltage of the Mth layer of the spiking neural network in the (N - 1)th pulse period, where M is an integer greater than 1.

[0062] Sub-step 20223: Use the output pulse signal of the last layer of the spiking neural network in the Nth pulse period as the output pulse signal of the spiking neural network.

[0063] Specifically, when the processing chip is configured in the Nth pulse period per(N) of the input pulse signal, within the Nth pulse period per(N), each layer of the spiking neural network is sequentially mapped into the processing chip. When the processing chip maps each layer of the spiking neural network, it also needs to accumulate with the membrane voltages of each layer in the (N - 1)th pulse period.

[0064] When the first layer layer(1) of the spiking neural network is mapped to the processing chip, the weights of the first layer layer(1) of the spiking neural network are cached in the processing chip. At this time, the input pulse signal of the Nth pulse period per(N) is used as the input of the processing chip. The processing chip calculates the product of the input pulse signal of the Nth pulse period per(N) and the weights of the first layer layer(1), and then calculates the sum of this product and the membrane voltage of the spiking neural network in the first layer layer(1) during the (N - 1)th pulse period per(N - 1) as the membrane voltage of the spiking neural network in the first layer layer(1) during the Nth pulse period per(N). A membrane voltage threshold is preset in the processing chip, and then the membrane voltage of the spiking neural network in the first layer layer(1) during the Nth pulse period per(N) is compared with this membrane voltage threshold. When the membrane voltage of the first layer layer(1) is greater than or equal to this membrane voltage threshold, the output pulse signal of the spiking neural network in the first layer layer(1) during the Nth pulse period per(N) is 1; when the membrane voltage of the first layer layer(1) is less than this membrane voltage threshold, the output pulse signal of the spiking neural network in the first layer layer(1) during the Nth pulse period per(N) is 0.

[0065] When the Mth layer layer(M) of the spiking neural network is mapped to the processing chip, the weights of the Mth layer layer(M) of the spiking neural network are cached in the processing chip. At this time, the output pulse signal of the (M - 1)th layer of the spiking neural network during the Nth pulse period per(N) is used as the input of the processing chip. The processing chip calculates the product of the output pulse signal of the (M - 1)th layer of the spiking neural network during the Nth pulse period per(N) and the weights of the Mth layer layer(M), and then calculates the sum of this product and the membrane voltage of the spiking neural network in the Mth layer layer(M) during the (N - 1)th pulse period per(N - 1) as the membrane voltage of the spiking neural network in the Mth layer layer(M) during the Nth pulse period per(N). A membrane voltage threshold is preset in the processing chip, and then the membrane voltage of the Mth layer layer(M) is compared with this membrane voltage threshold. When the membrane voltage of the Mth layer layer(M) is greater than or equal to this membrane voltage threshold, the output pulse signal of the spiking neural network in the Mth layer layer(M) during the Nth pulse period is 1; when the membrane voltage of the Mth layer layer(M) is less than this membrane voltage threshold, the output pulse signal of the spiking neural network in the Mth layer layer(M) during the Nth pulse period is 0.

[0066] Taking M = 2 as an example, at this time, the second layer layer(2) of the spiking neural network is mapped to the processing chip, and the weights of the second layer layer(2) of the spiking neural network are cached in the processing chip. At this time, the output pulse signal of the first layer layer(1) of the spiking neural network in the Nth pulse period per(N) is used as the input of the processing chip. The processing chip calculates the product of the output pulse signal of the first layer layer(1) of the spiking neural network in the Nth pulse period per(N) and the weights of the second layer layer(2), and then calculates the sum of this product and the membrane voltage of the spiking neural network in the second layer layer(2) in the (N - 1)th pulse period per(N - 1) as the membrane voltage of the spiking neural network in the second layer layer(2) in the Nth pulse period per(N). A membrane voltage threshold is preset in the processing chip, and then the membrane voltage of the spiking neural network in the second layer layer(2) in the Nth pulse period per(N) is compared with this membrane voltage threshold. When the membrane voltage of the second layer layer(2) is greater than or equal to this membrane voltage threshold, the output pulse signal of the spiking neural network in the second layer layer(2) in the Nth pulse period is 1; when the membrane voltage of the second layer layer(2) is less than this membrane voltage threshold, the output pulse signal of the spiking neural network in the second layer layer(2) in the Nth pulse period is 0.

[0067] And so on, when M = Y, the last layer layer(Y) of the spiking neural network is mapped to the processing chip, and the weights of the Yth layer layer(Y) of the spiking neural network are cached. At this time, the output pulse signal of the (Y - 1)th layer of the spiking neural network in the Nth pulse period per(N) is used as the input of the processing chip. The processing chip calculates the product of the output pulse signal of the (Y - 1)th layer of the spiking neural network in the Nth pulse period per(N) and the weights of the Yth layer layer(Y), and then calculates the sum of this product and the membrane voltage of the spiking neural network in the Yth layer layer(Y) in the (N - 1)th pulse period per(N - 1) as the membrane voltage of the spiking neural network in the Yth layer layer(Y) in the Nth pulse period per(N). A membrane voltage threshold is preset in the processing chip, and then the membrane voltage of the spiking neural network in the Yth layer layer(Y) in the Nth pulse period per(N) is compared with this membrane voltage threshold. When the membrane voltage of the Yth layer layer(Y) is greater than or equal to this membrane voltage threshold, the output pulse signal of the spiking neural network in the Yth layer layer(Y) in the Nth pulse period is 1; when the membrane voltage of the Yth layer layer(Y) is less than this membrane voltage threshold, the output pulse signal of the spiking neural network in the Yth layer layer(Y) in the Nth pulse period per(N) is 0.

[0068] Subsequently, the output pulse signal of the last layer layer(Y) of the spiking neural network in the Nth pulse period is used as the output pulse signal of the spiking neural network in the Nth pulse period. Repeat the above process until N = X, so as to obtain the output pulse signals of the spiking neural network in each pulse period.

[0069] For example, please refer to Figure 5 , in the figure, the spiking neural network includes 3 layers, namely the first layer layer(1), the second layer layer(2), and the third layer layer(3). The input pulse signal includes 2 pulse periods, namely the first pulse period per(1) and the second pulse period per(2). t(0) to t(7) represent the operation cycles of the processing chip. It can be seen from Figure 3 that in the operation cycle of t(0), mainly the configuration of the processing chip is executed, including weight configuration, register configuration, etc. In the operation cycles of t(1) to t(3), it means that the processing chip is configured in the first pulse period per(1), and layer(1) to layer(3) are mapped in sequence to obtain the output pulse signal of the spiking neural network in the first pulse period per(1). In the operation cycles of t(4) to t(6), it means that the processing chip is configured in the second pulse period per(2), and layer(1) to layer(3) are mapped in sequence to obtain the output pulse signal of the spiking neural network in the second pulse period per(2).

[0070] Step 203, according to the output pulse signals of the spiking neural network in multiple pulse periods, obtain the processing result after the audio-visual signal is processed by the spiking neural network. It is substantially the same as step 103 of the first embodiment and will not be elaborated here.

[0071] The third embodiment of the present invention relates to a processing chip, which is used to map a spiking neural network for processing an audio-visual signal by the signal processing method in the first or second embodiment to obtain a corresponding processing result, and this processing result can be used for the classification of the audio-visual signal. Among them, the spiking neural network can also be obtained by pulseifying a deep neural network.

[0072] Please refer to Figure 6 , the processing chip 10 includes a plurality of neuron cores 11; please refer to Figure 7 , each neuron core 11 includes: an arithmetic unit 111, a first cache 112, a second cache 113, and a third cache 114.

[0073] The arithmetic unit 111 is used to perform the layer mapping operation of the spiking neural network.

[0074] The first cache 112 is used to cache the input pulse signal, the second cache 113 is used to cache the layer weights, and the third cache 114 is used to cache the membrane voltage calculated by the arithmetic unit 111.

[0075] In one example, the second cache space 113 of each neuron core 11 includes: a first cache space and a second cache space.

[0076] For each neuron core 11, when the first cache space of the neuron core 11 caches the weights of the (M - 1)-th layer of the spiking neural network, the second cache space of the neuron core caches the weights of the M-th layer of the spiking neural network, where M is an integer greater than 1. That is, two cache spaces are set in the second cache 113, and the two cache spaces are respectively used to cache the weights of two adjacent layers of the spiking neural network, so as to reduce the weight loading from the external memory and improve the operation efficiency.

[0077] The fourth embodiment of the present invention relates to a processing chip. Compared with the third embodiment, the main improvement lies in that: the processing chip can map two layers in the spiking neural network at the same time, and the neuron cores in the processing chip are divided into two groups for layer ping-pong mapping of the spiking neural network.

[0078] In this embodiment, the processing chip includes a plurality of neuron cores, and the plurality of neuron cores are divided into two groups. Each group of neuron cores is used to map at least one layer in the spiking neural network; each layer of the spiking neural network is sequentially mapped to the processing chip. When the (M - 1)-th layer of the spiking neural network is mapped to one group of neuron cores in the processing chip, the M-th layer of the spiking neural network is mapped to the other group of neuron cores in the processing chip, where M is an integer greater than 1. It should be noted that this embodiment is described by taking the example that the processing chip can map two layers in the spiking neural network at the same time, but it is not limited thereto. If the processing chip can map P layers in the spiking neural network at the same time, the plurality of neuron cores in the processing chip can be divided into P groups, and each group of neuron cores is used to map at least one layer in the spiking neural network, so that the processing chip can map P layers of the spiking neural network each time.

[0079] Please refer to Figure 8 , the processing chip 10 is connected to the external memory 20. The processing chip 10 includes 16 neuron cores 1, and the 16 neuron cores are divided into two groups, denoted as the first group part0 and the second group part1 respectively. part0 and part1 can respectively map one layer of the neural network. In the figure, the neuron cores in the first group part0 are denoted as neuron core 0, and the neuron cores in the second group part1 are denoted as neuron core 1; the external memory 20 is used to store the configuration information of the spiking neural network, such as the weights of each layer of the spiking neural network and register configuration, etc.

[0080] During the k-th operation cycle t(k) of the processing chip 10, part0 is mapped to the M-th layer layer(M) of the pulse neural network in the N-th pulse period per(N). The internal cache of part0 stores the weights of layer(M) read from the external memory 20, and also stores the membrane voltage of layer(M) of the pulse neural network in the (N - 1)-th pulse period per(N - 1). When part0 performs operations, save_potential_part0 writes the membrane voltage of layer(M) of the pulse neural network in the N-th pulse period per(N) calculated by part0 into the external memory 20, and load_potential_part1 writes the membrane voltage of layer(M + 1) of the pulse neural network in the (N - 1)-th period per(N - 1) in the external memory 20 into part1; load_weight_part1 writes the weights of layer(M + 1) of the pulse neural network in the external memory 20 into part1; at the same time, part0 sends the output pulse signal spikeout_part0 of layer(M) calculated to part1 as the input data of part1 in the (k + 1)-th operation cycle t(k + 1). When the operation of part0 ends, the operation cycle t(k) ends.

[0081] In the operation cycle t(k + 1), part1 is mapped to the (M + 1)-th layer layer(M + 1) of the pulse neural network in the N-th pulse period per(N). When part1 performs operations, save_potential_part1 writes the operation result of the membrane voltage of layer(M + 1) of the pulse neural network in the N-th pulse period per(N) calculated by part1 into the external memory 20, and load_potential_part0 writes the membrane voltage of layer(M + 2) of the pulse neural network in the (N - 1)-th period per(N - 1) in the external memory 20 into part0; load_weight_part0 writes the weights of layer(M + 2) of the pulse neural network in the external memory 20 into part0; at the same time, part1 sends the output pulse signal spikeout_part1 of layer(M + 1) of the pulse neural network in the N-th pulse period per(N) to part0 as the input data of part0 in the (k + 2)-th operation cycle t(k + 2). When the operation of part1 ends, the operation cycle t(k + 1) ends.

[0082] Repeating the above process can obtain the output pulse signals of the spiking neural network within each pulse period. It should be noted that when the processing chip 10 is mapped to the first layer layer(1) of the spiking neural network, the input data of part0 is the input pulse signal. When the processing chip 10 is mapped to the last layer layer(Y) of the spiking neural network, if Y is even, part1 performs the mapping operation of the last layer layer(Y) of the spiking neural network, and the next operation cycle is for part0 to perform the operation of the first layer layer(1) in the (N + 1)-th pulse period per(N + 1). At this time, load_potential_part0 writes the membrane voltage of the first layer layer(1) in the N-th pulse period per(N) in the external memory 20 into part0, and load_weight_part0 writes the weights of the first layer layer(1) of the spiking neural network in the external memory 20 into part0; at the same time, the input pulse signal enc_out in the (N + 1)-th pulse period per(N + 1) is used as the input data of part0. load_potential_part1 has no operation, load_weight_part1 has no operation, and part1 does not send the output pulse signal spikeout_part1 of the last layer layer(Y) of the spiking neural network in the N-th pulse period to part0.

[0083] If Y is odd, part0 performs the mapping operation of the last layer layer(Y) of the spiking neural network. If the input pulse signal can only be connected to part0, then part0 will perform the operation of the first layer layer(1) in the (N + 1)-th pulse period per(N + 1). Among them, in this operation cycle, part0 is using the weights of layer(Y) for operation and will not write the weights of layer(1) into part0. When in the last pulse period per(X), the processing chip 10 does not need to save the membrane voltages calculated for each layer of the spiking neural network. In the next operation cycle, load_potential_part0 writes the membrane voltage of the first layer layer(1) in the N-th pulse period per(N) in the external memory 20 into part0, and load_weight_part0 writes the weights of the first layer layer(1) of the spiking neural network in the external memory 20 into part0; at the same time, the input pulse signal enc_out in the (N + 1)-th pulse period per(N + 1) is used as the input data of part0. load_potential_part1 has no operation, load_weight_part1 has no operation. In the next operation cycle, part0 performs the operation of the first layer layer(1) in the (N + 1)-th pulse period per(N + 1).

[0084] If Y is odd, part0 performs the mapping operation of the last layer layer(Y) of the spiking neural network. If the input spike signal can access part1, in the next operation cycle, part1 can also perform the operation of the first layer layer(1) in the (N + 1)-th pulse cycle per(N + 1). At this time, load_potential_part1 writes the membrane voltage of the first layer layer(1) in the N-th pulse cycle per(N) in the external memory 20 into part1, and load_weight_part1 writes the weights of the first layer layer(1) of the spiking neural network in the external memory 20 into part1; at the same time, the input spike signal enc_out in the (N + 1)-th pulse cycle per(N + 1) is used as the input data of part1. load_potential_part0 has no operation, load_weight_part0 has no operation, and part0 does not send the output spike signal spikeout_part0 of the last layer layer(Y) of the spiking neural network within the N-th pulse cycle to part1.

[0085] The following is combined with Figure 9 for further illustration. Figure 9 The spiking neural network includes three layers, namely the first layer layer(1), the second layer layer(2), and the third layer layer(3). The input spike signal includes two pulse cycles, namely the first pulse cycle per(1) and the second pulse cycle per(2). enc_out(1) represents the input spike signal in the first pulse cycle per(1), and enc_out(2) represents the input spike signal in the second pulse cycle per(2). t(0) to t(7) represent the operation cycles of the processing chip. Among them, the input spike signal enc_out including N pulse cycles obtained by the processing chip 10 only accesses part0, and the first layer layer(1) of the spiking neural network is only mapped to part0. When part0 is mapped to the first layer layer(1) of the spiking neural network, the input of part0 is the input spike signal enc_out; otherwise, the input of part0 is the output spike signal of part1, the input of part1 is the output spike signal of part0, and the output spike signal of the third layer layer(3) is the output spike signal of the spiking neural network.

[0086] The processing chip 10 has no operation in the operation cycle t(0). The input spike signal in the first pulse cycle per(1) is output to part0 and written into the internal cache of part0. The weights of layer(1) are read from the external memory 20 and written into the internal cache of part0.

[0087] The processing chip 10 performs the layer(1) operation of the first pulse period per(1) within the operation cycle t(1). The operation is completed by part0, and part1 does not operate. At the same time, the output pulse signal of part0 is sent to part1 and written into the internal cache of part1. Part0 writes the membrane voltage of layer(1) of the first pulse period per(1) obtained by calculation into the external memory 20. The weights of layer(2) are read from the external memory 20 and written into the internal cache of part1.

[0088] The processing chip 10 performs the layer(2) operation of the first pulse period per(1) within the operation cycle t(2). The operation is completed by part1, and part0 does not operate. At the same time, the output pulse signal of part1 is sent to part0 and written into the internal cache of part0. Part1 writes the membrane voltage of layer(2) of the first pulse period per(1) obtained by calculation into the external memory 20. The weights of layer(3) are read from the external memory 20 and written into the internal cache of part0.

[0089] The processing chip 10 performs the layer(3) operation of the first pulse period per(1) within the operation cycle t(3). The operation is completed by part0, and part1 does not operate. At the same time, the output pulse signal of part0 is used as the output of the pulse neural network within the first pulse period per(1). Part0 writes the membrane voltage of layer(3) of the first pulse period per(1) obtained by calculation into the external memory 20.

[0090] The processing chip 10 does not perform any operation within the operation cycle t(4). The input pulse signal of the second pulse period per(2) is output to part0 and written into the internal cache of part0. The weights of layer(1) are read from the external memory 20 and written into the internal cache of part0. The membrane voltage of layer(1) of the first pulse period per(1) is read from the external memory 20 and written into the internal cache of part0.

[0091] The processing chip 10 performs the layer (1) operation of the second pulse period per (2) within the operation cycle t(5). The operation is completed by part0, and part1 does not operate. At the same time, the output pulse signal of part0 is given to part1 and written into the internal cache of part1. Part0 writes the membrane voltage of layer (1) of the second pulse period per (2) obtained by calculation into the external memory 20. The weights of layer (2) are read from the external memory 20 and written into the internal cache of part1. The membrane voltage of layer (2) of the first pulse period per (1) is read from the external memory 20 and written into the internal cache of part1.

[0092] The processing chip 10 performs the layer (2) operation of the second pulse period per (2) within the operation cycle t(6). The operation is completed by part1, and part0 does not operate. At the same time, the output pulse signal of part1 is given to part0 and written into the internal cache of part0. Part1 writes the membrane voltage of layer (2) of the second pulse period per (2) obtained by calculation into the external memory 20. The weights of layer (3) are read from the external memory 20 and written into the internal cache of part0. The membrane voltage of layer (3) of the first pulse period per (1) is read from the external memory 20 and written into the internal cache of part0.

[0093] The processing chip 10 performs the layer (3) operation of the second pulse period per (2) within the operation cycle t(7). The operation is completed by part0, and part1 does not operate. At the same time, the output pulse signal of part0 is used as the output of the pulse neural network within the second pulse period per (2) of the layer.

[0094] As can be seen from the above, in each operation cycle, only one set of neuron cores performs operations, and the other set of neuron cores loads weights. The operations and weight loading occur in different sets of neuron cores, so as to make full use of the resources of the processing chip and further improve the utilization of the processing chip.

[0095] The fifth embodiment of the present invention relates to a signal processing device, such as electronic devices such as notebook computers, desktop hosts, and tablet computers. Please refer to Figure 10 , the signal processing device includes the processing chip 10 in the third embodiment or the fourth embodiment and the external memory 20 connected to the processing chip 10.

[0096] The preferred embodiments of the present invention have been described in detail above. However, it should be understood that if necessary, aspects of the embodiments can be modified to adopt aspects, features, and concepts of various patents, applications, and publications to provide additional embodiments.

[0097] In view of the foregoing detailed description, these and other variations can be made to the embodiments. Generally, in the claims, the terms used should not be construed as limited to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments together with the full scope of equivalents to which these claims are entitled.

Claims

1. A signal processing method, characterized in that, comprising: encoding an audio-visual signal to be processed into an input pulse signal that lasts for multiple pulse periods; when the processing chip is configured in each of the pulse periods of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains an output pulse signal of the spiking neural network within the pulse period based on the input pulse signal within the pulse period, wherein the processing chip is used to map two layers of the spiking neural network simultaneously; the processing chip includes a plurality of neuron cores, the plurality of neuron cores are divided into two groups, and each group of neuron cores is used to map at least one layer of the spiking neural network; each layer of the spiking neural network is sequentially mapped into the processing chip, and when the (M-1)th layer of the spiking neural network is mapped into a group of neuron cores in the processing chip, the Mth layer of the spiking neural network is mapped into the other group of neuron cores in the processing chip, where M is an integer greater than 1; within each operation period, one group of neuron cores performs operations and the other group of neuron cores loads weights; obtaining a processing result of the audio-visual signal after being processed by the spiking neural network according to the output pulse signals of the spiking neural network within the multiple pulse periods.

2. The signal processing method according to claim 1, characterized in that, when the processing chip is configured in each of the pulse periods of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains an output pulse signal of the spiking neural network within the pulse period based on the input pulse signal within the pulse period, including: when the processing chip is configured in the first pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains an output pulse signal of the spiking neural network within the first pulse period based on the input pulse signal within the first pulse period; when the processing chip is configured in the Nth pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains an output pulse signal of the spiking neural network within the Nth pulse period based on the input pulse signal within the Nth pulse period and the membrane voltages of each layer of the spiking neural network within the (N-1)th pulse period.

3. The signal processing method according to claim 2, characterized in that, when the processing chip is configured in the first pulse period of the input pulse signal, each layer of the spiking neural network is sequentially mapped into the processing chip, and the processing chip obtains an output pulse signal of the spiking neural network within the first pulse period based on the input pulse signal within the first pulse period, including: When the processing chip is configured in the first pulse period of the input pulse signal, if the first layer of the pulse neural network is mapped to the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the pulse neural network in the first layer within the first pulse period according to the input pulse signal within the first pulse period; If the M-th layer of the pulse neural network is mapped to the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the pulse neural network in the M-th layer within the first pulse period according to the output pulse signal of the pulse neural network in the (M - 1)-th layer within the first pulse period; M is an integer greater than 1; The output pulse signal of the pulse neural network in the last layer within the first pulse period is used as the output pulse signal of the pulse neural network.

4. The signal processing method according to claim 2, wherein, When the processing chip is configured in the N-th pulse period of the input pulse signal, each layer of the pulse neural network is sequentially mapped into the processing chip, and the processing chip obtains the output pulse signal of the pulse neural network within the N-th pulse period based on the input pulse signal within the N-th pulse period and the membrane voltages of the pulse neural network in each layer within the (N - 1)-th pulse period, including: When the processing chip is configured in the N-th pulse period of the input pulse signal and the first layer of the pulse neural network is mapped to the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the pulse neural network in the first layer within the N-th pulse period according to the input pulse signal within the N-th pulse period and the membrane voltage of the pulse neural network in the first layer within the (N - 1)-th pulse period; When the M-th layer of the pulse neural network is mapped to the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the pulse neural network in the M-th layer within the N-th pulse period according to the output pulse signal of the pulse neural network in the (M - 1)-th layer within the N-th pulse period and the membrane voltage of the pulse neural network in the M-th layer within the (N - 1)-th pulse period, M is an integer greater than 1; The output pulse signal of the pulse neural network in the last layer within the N-th pulse period is used as the output pulse signal of the pulse neural network.

5. The signal processing method according to claim 4, wherein, When the first layer of the pulse neural network is mapped to the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the pulse neural network in the first layer within the N-th pulse period according to the input pulse signal within the N-th pulse period and the membrane voltage of the pulse neural network in the first layer within the (N - 1)-th pulse period, including: When the first layer of the spiking neural network is mapped to the processing chip, the processing chip calculates the product of the input pulse signal within the Nth pulse period and the weights of the spiking neural network in the first layer, and calculates the sum of the product and the membrane voltage of the spiking neural network in the first layer within the (N - 1)th pulse period, as the membrane voltage of the spiking neural network in the first layer within the Nth pulse period; Based on the membrane voltage of the spiking neural network in the first layer within the Nth pulse period and a preset membrane voltage threshold, an output pulse signal of the spiking neural network in the first layer within the Nth pulse period is obtained.

6. The signal processing method according to claim 4, wherein, when the Mth layer of the spiking neural network is mapped to the processing chip, the processing chip obtains the membrane voltage and the output pulse signal of the spiking neural network in the Mth layer within the Nth pulse period according to the output pulse signal of the spiking neural network in the (M - 1)th layer within the Nth pulse period and the membrane voltage of the spiking neural network in the Mth layer within the (N - 1)th pulse period, including: when the Mth layer of the spiking neural network is mapped to the processing chip, the processing chip calculates the product of the output pulse signal of the spiking neural network in the (M - 1)th layer within the Nth pulse period and the weights of the spiking neural network in the Mth layer, and calculates the sum of the product and the membrane voltage of the spiking neural network in the Mth layer within the (N - 1)th pulse period, as the membrane voltage of the spiking neural network in the Mth layer within the Nth pulse period; Based on the membrane voltage of the spiking neural network in the Mth layer within the Nth pulse period and a preset membrane voltage threshold, an output pulse signal of the spiking neural network in the Mth layer within the Nth pulse period is obtained.

7. A processing chip, wherein, it is used to execute the signal processing method according to any one of claims 1 to 6.

8. The processing chip according to claim 7, wherein, the cache space of each neuron core included in the processing chip includes: a first cache space and a second cache space; For each neuron core, when the first cache space of the neuron core caches the weights of the (M - 1)th layer of the spiking neural network, the second cache space of the neuron core caches the weights of the Mth layer of the spiking neural network, where M is an integer greater than 1.

9. A signal processing device, wherein, it includes: the processing chip according to any one of claims 7 and 8.

Images