Semiconductor device structure and method for bonding two substrates

Abstract

The present invention discloses a semiconductor element structure and a method for bonding two substrates, wherein the semiconductor element structure includes a first circuit structure formed on a first substrate. A first test pad is arranged on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is arranged on the second substrate. A first connection pad of the first circuit structure is bonded to a second connection pad of the second circuit structure, and one of the first test pad and the second test pad is an inner pad, and the other of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing technology, and in particular to a semiconductor element structure and a method for bonding two substrates. Background Art

[0002] As the technology of semiconductor manufacturing develops, an integrated circuit can be divided into two parts and the corresponding parts of the circuit can be manufactured on two substrates. For a single substrate, after the circuit is manufactured, multiple bonding pads are formed at predetermined positions on the surface to be bonded with the circuit of another substrate. The bonding surfaces of the two substrates are then bonded to each other through packaging technology. Under ideal conditions, the bonding pads on the two substrates will be aligned and bonded to each other. In this way, the two partial circuits are connected together through multiple bonding pads on the surface of the substrate to form a complete integrated circuit.

[0003] In the process of bonding two substrates, the substrates need to be aligned before bonding. This alignment process will form alignment marks on the substrates. However, the size of the alignment marks used for alignment between substrates is much larger than the size of the connection pads of the component structures on the substrates, so the alignment accuracy is loose. In this way, even if the alignment marks of the substrates can be aligned, the connection pads of the more delicate component structures may be shifted, resulting in poor electrical connection or even connection failure.

[0004] Thus, if there is misalignment between the substrates, it is expected that the connection pads on the two chips will not be properly bonded, or even cause bonding failure. At the same time, it is also impossible to effectively detect individual circuits to determine the degree of circuit bonding and thereby eliminate circuits with poor bonding. Summary of the invention

[0005] The present invention provides a semiconductor element structure and a method for bonding two substrates, which can at least effectively detect the bonding state of the connection pads between two circuit parts after the two substrates are bonded, and can detect circuits with poor bonding.

[0006] In one embodiment, the present invention provides a semiconductor device structure. The semiconductor device structure includes a first circuit structure formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first connection pad of the first circuit structure is bonded to a second connection pad of the second circuit structure, and one of the first test pad and the second test pad is an inner pad, and the other of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

[0007] In one embodiment, the semiconductor device structure further includes a first lead circuit disposed on the first substrate to be connected to the first test pad; and a second lead circuit disposed on the second substrate to be connected to the second test pad.

[0008] In one embodiment, for the semiconductor device structure, the first lead circuit and the second lead circuit respectively provide test terminals for testing.

[0009] In one embodiment, for the semiconductor device structure, the inner pad includes at least one pad, and the outer pad includes a ring-shaped pad.

[0010] In one embodiment, for the semiconductor device structure, the at least one pad includes a circular pad, a rectangular pad, a triangular pad, a square pad or a geometric pad, wherein the annular pad includes at least one circular ring pad, a rectangular ring pad, a triangular ring pad, a square ring pad or a geometric ring pad.

[0011] In one embodiment, for the semiconductor device structure, the at least one pad is a single pad having a circular, rectangular, triangular, square or geometric shape, and the annular pad is a ring shape uniformly surrounding the single pad.

[0012] In one embodiment, for the semiconductor device structure, the inner pad includes at least one first pad, and the outer pad includes a plurality of second pads, forming a distribution surrounding the inner pad.

[0013] In one embodiment, for the semiconductor device structure, the at least one first pad includes a round pad, a rectangular pad, a triangular pad, a square pad or a geometric pad.

[0014] In one embodiment, for the semiconductor device structure, the at least one first pad has a single pad in a circular, rectangular, triangular, square or geometric shape, and the plurality of second pads are in a ring shape uniformly surrounding the single pad.

[0015] In one embodiment, for the semiconductor element structure, the inner pad is a single circular pad, a single rectangular pad, a single triangular pad, a single square pad or a single geometric pad, wherein the outer pad corresponding to the inner pad is a circular ring, a rectangular ring, a triangular ring, a square ring or a geometric ring.

[0016] In one embodiment, the present invention also provides a method for bonding two substrates, comprising providing a first substrate, wherein a first circuit structure and a first test pad are formed on the first substrate. Providing a second substrate, wherein a second circuit structure and a second test pad are formed on the second substrate. Bonding a first connection pad of the first circuit structure and a second connection pad of the second circuit structure, while one of the first test pad and the second test pad constitutes an inner pad, and the other of the first test pad and the second test pad constitutes an outer pad. After bonding the first circuit structure and the second circuit structure, the outer pad surrounds the inner pad.

[0017] In one embodiment, for the method of bonding two substrates, the first substrate provided further includes a first lead circuit connected to the first test pad, and the second substrate provided further includes a second lead circuit connected to the second test pad.

[0018] In one embodiment, for the method of bonding two substrates, the first lead circuit and the second lead circuit respectively provide test terminals for testing.

[0019] In one embodiment, for the method of bonding two substrates, the inner pad provided includes at least one pad, and the outer pad includes a ring-shaped pad.

[0020] In one embodiment, for the method of bonding two substrates, the at least one pad provided includes a circular pad, a rectangular pad, a triangular pad, a square pad or a geometric pad, wherein the annular pad includes at least one circular ring pad, a rectangular ring pad, a triangular ring pad, a square ring pad or a geometric ring pad.

[0021] In one embodiment, for the method of bonding two substrates, the at least one pad is a single pad having a circular, rectangular, triangular, square or geometric shape, and the annular pad is a ring shape uniformly surrounding the single pad.

[0022] In one embodiment, for the method of bonding two substrates, the inner pad provided includes at least one first pad, and the outer pad provided includes a plurality of second pads, forming a second pad distributed around the inner pad.

[0023] In one embodiment, for the method of bonding two substrates, the at least one first pad includes a circular pad, a rectangular pad, a triangular pad, a square pad, or a geometric pad.

[0024] In one embodiment, for the method of bonding two substrates, the at least one first pad is a single pad in a circular, rectangular, triangular, square or geometric shape, and the plurality of second pads are in a ring shape uniformly surrounding the single pad.

[0025] In one embodiment, for the method of bonding two substrates, the inner pad is a single circular pad, a single rectangular pad, a single triangular pad, a single square pad or a single geometric pad, wherein the outer pad corresponding to the inner pad is a circular ring, a rectangular ring, a triangular ring, a square ring or a geometric ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0027] Figure 1 is a schematic cross-sectional structure diagram of substrate-to-substrate bonding in one embodiment;

[0028] Figure 2 It is a schematic cross-sectional structure diagram of an embodiment of accurate bonding of substrates to substrates;

[0029] Figure 3 is a schematic cross-sectional structure diagram of an embodiment of an inaccurate bonding of substrates to substrates;

[0030] Figure 4 It is a schematic cross-sectional structure diagram of a semiconductor device structure provided with a test pad, wherein the substrate is bonded to the substrate;

[0031] Figure 5A is a top view schematically showing a test pad of a semiconductor device structure according to an embodiment;

[0032] Figure 5B is a top view schematically showing a test pad of a semiconductor device structure in a case of inaccurate bonding according to an embodiment; and

[0033] Figures 6 to 11 FIG. 4 is a schematic diagram of various configurations of a test pad according to an embodiment.

[0034] Description of Figure Numbers

[0035] 50:Substrate

[0036] 52:Substrate

[0037] 54: Inner dielectric layer

[0038] 56:Connection pad

[0039] 56a: plug structure 5

[0040] 56b: Circuit

[0041] 60:Substrate

[0042] 62:Substrate

[0043] 64: Inner dielectric layer

[0044] 66:Connection pad

[0045] 66a: plug structure

[0046] 66b: Circuit

[0047] 70: Joint surface

[0048] 90: Inline structure

[0049] 95: Inline structure

[0050] 100:Test structure

[0051] 102: Test pad

[0052] 104: plug structure

[0053] 106: Lead circuit

[0054] 110: Test pad

[0055] 114: Lead Circuit

[0056] 120: Local structure

[0057] 122: plug structure DETAILED DESCRIPTION

[0058] The present invention provides a test structure that can be used for substrate-to-substrate bonding. After the substrates are bonded to the substrates, the bonding state of the connection pads between two partial circuits on the two substrates can be effectively detected, so that a defective circuit can be effectively and easily detected.

[0059] The present invention is described below with reference to a plurality of embodiments, but the present invention is not limited to the plurality of embodiments. In addition, the plurality of embodiments may be appropriately combined.

[0060] Figure 1 FIG. 1 is a schematic cross-sectional view of a substrate-to-substrate bonding process according to an embodiment. Figure 1, in the substrate 50, for example, a part of the circuit of the whole circuit is manufactured based on the working substrate 52. Based on the semiconductor manufacturing technology, it needs multiple layers of dielectric layers to be manufactured and supported according to the structure to complete the expected circuit. These dielectric layers are collectively referred to as the inter-layer dielectric (ILD) layer 54. Part of the circuit on this working substrate 52 is covered and supported by the inter-layer dielectric layer 54. Part of the circuit will form an exposed connection pad 56 on the surface of the substrate 50, which can be electrically connected to the connection pad 66 of another substrate 60 during the process of substrate-to-substrate bonding. In the substrate 60, another part of the circuit of the whole circuit is manufactured based on the working substrate 62 according to the semiconductor manufacturing technology, which includes the connection pad 66 of the top layer. This part of the circuit is also covered and supported by the inner layer dielectric layer 64. After the substrate 60 and the substrate 50 are manufactured respectively, they are bonded to each other on the bonding surface 70 according to the bonding process, so that the connection pad 66 is electrically connected to the connection pad 56.

[0061] To connect the connection pad 66 with the connection pad 56, the substrate 50 and the substrate 60 need to be aligned. Alignment marks are additionally formed on the non-circuit areas of the substrate 50 and the substrate 60. The alignment marks may include a plurality of marking units, which extend in two directions perpendicular to each other, for example. The alignment marks formed on the substrate 50 and the substrate 60 can be aligned in two dimensions, so that the connection pad 66 and the connection pad 56 of the substrate 50 and the substrate 60 can be aligned and bonded in an ideal state.

[0062] However, since the size of the alignment mark is much larger than the size of the semiconductor device to be formed, even if the alignment marks of the substrate 50 and the substrate 60 are aligned within the accuracy expected by the alignment process, there may still be a possibility of shift or even no connection between the connection pads 56 and 66 of some semiconductor devices. For example, the circuit located at the edge area of ​​the substrate has a greater probability of connection shift.

[0063] Figure 2 FIG. 1 is a schematic cross-sectional view of a substrate-to-substrate accurate bonding according to an embodiment. Figure 2 For a pair of connection pads 56 and 66 to be connected, they can be connected over a large area, for example, over the entire area, in an aligned state. In an actual circuit structure, for example, the connection pads 56 and 66 are connected to the circuits 56b and 66b through plug structures 56a and 66a to form a circuit structure on the substrates 50 and 60. Since the connection pads 56 and 66 are in contact over a large area, the electrical connection state is good and is the expected connection state.

[0064] Figure 3FIG. 1 is a schematic cross-sectional view of an inaccurately bonded substrate to substrate according to an embodiment. Figure 3 Since the size of the connection pads 56, 66 and the distance between them are multiple times smaller than the size of the alignment mark, there may also be manufacturing errors in the position of individual circuits on the substrate. Therefore, some connection pads 56, 66 may be displaced, that is, misaligned.

[0065] If the contact area between the connection pads 56 and 66 is insufficient, it may cause insufficient connection conductivity, thereby affecting the performance of the circuit. Even if the connection pads 56 and 66 are substantially offset, it may cause connection failure, resulting in poor manufacturing of the entire circuit and need to be eliminated.

[0066] The present invention is at least based on the consideration that it can be more accurately aligned during the bonding stage and it is also easier to detect circuits that may have poor connections. It proposes that a test structure is also formed simultaneously with the corresponding circuit under the component structure size, which can at least assist in effectively detecting the connection status of individual circuits during the substrate-to-substrate bonding stage.

[0067] Figure 4 FIG. 1 is a schematic cross-sectional view of a semiconductor device structure with a test pad disposed thereon, wherein the substrate is bonded to the substrate. Figure 4 , the semiconductor device structure includes a substrate 50 and a substrate 60. The circuit structure on the substrate 50 includes, for example, a circuit 56b, a plug structure 56a and a connection pad 56. The connection pad 56 is to be electrically connected to a connection pad 66 on the substrate 60. The circuit 56b is further connected to another part of the circuit 66b through the plug structure 66a to form an integral circuit.

[0068] The present invention provides a test structure 100, wherein the manufacturing size range of the test pads 102 and 110 formed on the substrate 50 and the substrate 60 is comparable to the size of the connection pads 56 and 66. The test pads 102 and 110 of the test structure 100 are formed simultaneously with the connection pads 56 and 66 and exposed on the bonding surface 70.

[0069] Figure 5A FIG. 1 is a top view of a test pad of a semiconductor device structure according to an embodiment. The test structure 100 can also refer to Figure 4 and Figure 5A In one embodiment, the top view of the local structure 120 of the test structure 100 is as follows: Figure 5A The test pad 102 formed in the substrate 50 is, for example, used as an outer pad and the test pad 110 formed in the substrate 60 is, for example, used as an inner pad, but the formation of the inner pad and the outer pad can also be interchanged between the substrate 60 and the substrate 50 .

[0070] That is, one of the test pads 102 and 110 is used as an inner pad, and the other of the test pads 102 and 110 is used as an outer pad. The outer pad of the test structure 100 surrounds the inner pad. Figure 4 In the embodiment of the present invention, the test pad 102 is an outer pad and the test pad 110 is an inner pad. The test pad 102 surrounds the test pad 110.

[0071] Circuit 66b, for example, further includes an interconnect structure 90 for further external connection. At the same time, test pad 102 and test pad 110 are connected to lead circuit 114 and lead circuit 106 through plug structures 104 and 122. Lead circuit 114 and lead circuit 106 are further connected to an external test device, for example, using a test probe to measure electrical signals between test pad 102 and test pad 110, such as leakage current measurement. In addition, an interconnect structure 95 can be configured to connect to lead circuit 114, but the present invention is not limited to this. Generally speaking, test pad 102 and test pad 110, for example, respectively provide test endpoints for testing.

[0072] The detection judgment mechanism is described as follows. If the connection pad 56 and the connection pad 66 are in a well-aligned state, the test pad 110 used as the inner pad will be in the central area of ​​the test pad 102 used as the outer pad. In this way, the isolation state between the test pad 110 and the test pad 102 is a better state, and relatively no leakage current will be generated, or the leakage current value is relatively small. In this detection state, it can be determined that the connection between the connection pad 56 and the connection pad 66 is well aligned.

[0073] Figure 5B FIG. 1 is a top view of a test pad of a semiconductor device structure in the case of inaccurate bonding according to an embodiment. Figure 4 and Figure 5B When the connection between the connection pad 56 and the connection pad 66 is not well aligned, the test pad 110, which is the inner pad, will deviate from the central area of ​​the test pad 102, which is the outer pad. In one embodiment, an area of ​​the test pad 110 is closer to the test pad 102. In this state, the isolation between the test pad 110 and the test pad 102 will be relatively weakened, so a larger leakage current may be generated. If the test pad 110 and the test pad 102 are even completely offset, the test pad 110 and the test pad 102 may directly touch each other and be in a short circuit state.

[0074] Since the geometrical configuration accuracy of the test pads 110 and 102 is comparable to that of the connection pads 56 and 66 , the proximity between the test pads 110 and 102 can more accurately detect whether the connection pads 56 and 66 are well connected during the rebonding process.

[0075] Based on the configuration of the inner pad of the test pad 110 and the outer pad of the test pad 102, it is not limited to Figure 5A In the case of using the detection mechanism of the inner pad and the outer pad, various other variations are exemplified below.

[0076] Figures 6 to 11 FIG. 1 is a schematic diagram of various configurations of the test pad according to an embodiment. Figure 6 The geometric shapes of the test pads 110 and 102 can be circular. The test pads 102 are kept evenly surrounding the test pads 110 .

[0077] See also Figure 7 , the geometric shapes of the test pads 110 and 102 can be rectangular configurations. Figure 8 The geometric shapes of the test pads 110 and 102 can be a predetermined geometric shape configuration, and need not be circular, square, or rectangular. In one embodiment, the shapes of the test pads 110 and 102 are triangular. Fig. 9 In one embodiment, the shapes of the test pad 110 and the test pad 102 do not need to be the same. Figure 8 In another embodiment, the test pad 102 is triangular and the test pad 102 is circular.

[0078] See also Fig.10 In terms of the number of the test pads 110, it does not need to be a single one, but can be multiple. In the configuration of multiple test pads 110, the test pads 110 are as follows: Figure 4 and Figure 5A , can be respectively connected to the lead circuit 114. In one embodiment, the plurality of test pads 110 can also be electrically connected to each other. The number of the plurality of test pads 110 is not limited to the four mentioned above, for example, it can be two or more.

[0079] See also Fig.11 , the test pad 102 used as the outer pad may also be composed of a plurality of pads of geometric shapes, which may be distributed around the test pad 110. In the configuration of the plurality of test pads 102, the test pad 102 may be configured as follows: Figure 4 and Figure 5A , which can be connected to the lead circuit 106 respectively. In one embodiment, the plurality of test pads 102 can also be electrically connected to each other. The number of the plurality of test pads 110 is not limited to the number listed above, and the plurality of test pads 110 can be surrounded by any configuration that can show the alignment state between the connection pad 56 and the connection pad 66.

[0080] From the perspective of the mechanism of bonding two substrates, the present invention also provides a method for bonding two substrates, including providing a first substrate 50, wherein a first circuit structure and a first test pad 102 are formed on the first substrate 50. The first circuit structure, for example, includes a connection pad 56, a plug structure 56a, and a circuit 56b. In addition, a second substrate 60 is also provided, wherein a second circuit structure and a second test pad 110 are formed on the second substrate. The second circuit structure, for example, includes a connection pad 66, a plug structure 66a, and a circuit 66b. At a bonding surface 70, the connection pad 56 of the first circuit structure and the connection pad 66 of the second circuit structure are bonded, and at the same time, one of the first test pad 102 and the second test pad 110 constitutes an inner pad, and the other of the first test pad 102 and the second test pad 110 constitutes an outer pad. After bonding the first circuit structure and the second circuit structure, the outer pad surrounds the inner pad.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device structure, characterized in that: include: A first circuit structure formed on a first substrate; A first test pad disposed on the first substrate; A second circuit structure formed on a second substrate; and A second test pad is disposed on the second substrate, wherein the first connection pad of the first circuit structure is bonded to the second connection pad of the second circuit structure, and one of the first test pad and the second test pad is an inner pad, and the other of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad, The inner pad includes at least one pad, and the outer pad includes a closed ring pad.

2. The semiconductor device structure according to claim 1, characterized in that: Also includes: A first lead circuit disposed on the first substrate to connect to the first test pad; and The second lead circuit is disposed on the second substrate to be connected to the second test pad.

3. The semiconductor device structure according to claim 2, characterized in that: The first lead circuit and the second lead circuit respectively provide test terminals for testing.

4. The semiconductor device structure according to claim 1, characterized in that: The at least one pad includes a circular pad, a rectangular pad, a triangular pad or a square pad, wherein the closed ring pad includes at least one circular ring pad, a rectangular ring pad, a triangular ring pad or a square ring pad.

5. The semiconductor device structure according to claim 1, characterized in that: The at least one pad is a single pad having a circular, rectangular or square shape, wherein the closed ring pad is a ring shape uniformly surrounding the single pad.

6. The semiconductor device structure according to claim 1, characterized in that: The inner pad is a single circular pad, a single rectangular pad, a single triangular pad or a single square pad, wherein the outer pad is a circular ring, a rectangular ring, a triangular ring or a square ring corresponding to the inner pad.

7. A method for bonding two substrates, characterized in that: include: Providing a first substrate, wherein a first circuit structure and a first test pad are formed on the first substrate; Providing a second substrate, wherein a second circuit structure and a second test pad are formed on the second substrate; and The first connection pad of the first circuit structure is joined to the second connection pad of the second circuit structure, and one of the first test pad and the second test pad constitutes an inner pad, and the other of the first test pad and the second test pad constitutes an outer pad. wherein after the first circuit structure and the second circuit structure are joined, the outer pad surrounds the inner pad, The inner pad includes at least one pad, and the outer pad includes a closed ring pad.

8. The method for bonding two substrates according to claim 7, wherein: The first substrate provided further includes a first lead circuit connected to the first test pad, and the second substrate provided further includes a second lead circuit connected to the second test pad.

9. The method for bonding two substrates according to claim 8, wherein: The first lead circuit and the second lead circuit respectively provide test endpoints for testing.

10. The method for bonding two substrates according to claim 7, wherein: The at least one pad provided includes a circular pad, a rectangular pad, a triangular pad or a square pad, wherein the closed ring pad includes at least one circular ring pad, a rectangular ring pad, a triangular ring pad or a square ring pad.

11. The method for bonding two substrates according to claim 7, wherein: The at least one pad is a single pad having a circular, rectangular, triangular or square shape, wherein the closed ring pad is a ring shape uniformly surrounding the single pad.

12. The method for bonding two substrates according to claim 7, wherein: The inner pad is a single circular pad, a single rectangular pad, a single triangular pad or a single square pad, wherein the outer pad is a circular ring, a rectangular ring, a triangular ring or a square ring corresponding to the inner pad.

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