Array substrate and preparation method thereof, and display device

Abstract

The present invention discloses an array substrate and a preparation method thereof, and a display device. The preparation method comprises: forming a low-temperature polysilicon active layer, a gate insulating layer, a gate structure layer and an interlayer insulating layer on a substrate in sequence, wherein the gate structure layer comprises a gate and a gate line arranged in the same layer; forming a first semiconductor material layer and a photoresist pattern in sequence on a side of the interlayer insulating layer away from the substrate, wherein the photoresist pattern corresponds to a source electrode, a drain electrode and a data line to be formed; etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line; forming a flat layer, a pixel defining layer and a light-emitting device layer in sequence on a side of the source electrode, the drain electrode and the data line away from the substrate; wherein a groove is formed on a side of the gate line facing away from the substrate, and an orthographic projection of the gate line on the substrate and an orthographic projection of the data line on the substrate have an overlap area, and the overlap area is located within the orthographic projection area of ​​the groove on the substrate.

Description

Technical Field

[0001] The present invention generally relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] In display devices, especially LTPS (Low Temperature Poly-silicon) products, it is inevitable that there are intersecting metal drive lines (such as gate lines and data lines) in various areas, among which the Top Gate structure is a key research and development direction.

[0003] In the existing Top Gate structure, the gate metal layer (Gate) including the gate and gate line is covered by the gate insulating layer (GI) to reduce the impact of the short channel effect. The part of the edge of the GI that is longer than the edge of the Gate is the gate insulating layer tail (GITail). When the interlayer dielectric layer (ILD) is subsequently formed, the ILD needs to complete two consecutive slopes (GI slope and Gate slope) at the GI Tail position, which is prone to wrinkles. After the source and drain metal layers are deposited, a similar tip phenomenon is formed at the aforementioned slope, and the thickness of the ILD at the slope is relatively thin. In addition, when forming the data line on the same layer as the source and drain metal layer, it is easy to over-etch the ILD. If an electrostatic effect occurs, DGS (Data-Gate Short, short-circuiting the gate line and the data line) is likely to occur at the location where the metal routing crosses, thereby reducing the yield rate of the display panel process. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide an array substrate and a method for manufacturing the same, and a display device.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, comprising:

[0006] A substrate, on one side of the substrate and in a direction away from the substrate, provided in sequence: a low-temperature polysilicon active layer, a gate insulating layer, a gate structure layer, an interlayer insulating layer, a source-drain structure layer, a planarization layer, a pixel defining layer and a light-emitting device layer;

[0007] Among them, the gate structure layer includes a gate and a gate line arranged in the same layer, the source-drain structure layer includes a source, a drain and a data line arranged in the same layer, a groove is formed on the side of the gate line facing away from the substrate, and there is an overlapping area between the orthographic projection of the gate line on the substrate and the orthographic projection of the data line on the substrate, and the overlapping area is located within the orthographic projection area of ​​the groove on the substrate.

[0008] Optionally, in the extension direction of the gate line, the width of the groove is at least 1 um greater than the width of the overlap region.

[0009] Optionally, the gate line includes a first portion and a second portion outside the first portion, and an orthographic projection of the first portion on the substrate coincides with an orthographic projection of the groove on the substrate, wherein:

[0010] The thickness of the second portion is 0.25um to 0.3um; and / or,

[0011] The thickness of the first portion is 1 / 2 to 2 / 3 of the thickness of the second portion.

[0012] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned array substrate.

[0013] In a third aspect, an embodiment of the present invention provides a method for preparing an array substrate, comprising:

[0014] A low-temperature polysilicon active layer, a gate insulating layer, a gate structure layer and an interlayer insulating layer are sequentially formed on a substrate, wherein the gate structure layer includes a gate and a gate line arranged in the same layer;

[0015] A first semiconductor material layer and a photoresist pattern are sequentially formed on a side of the interlayer insulating layer away from the substrate, wherein the photoresist pattern corresponds to a source electrode, a drain electrode and a data line to be formed;

[0016] Etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line;

[0017] A flat layer, a pixel defining layer and a light emitting device layer are sequentially formed on the side of the source electrode, the drain electrode and the data line away from the substrate; wherein,

[0018] A groove is formed on the side of the gate line facing away from the substrate, and an orthographic projection of the gate line on the substrate and an orthographic projection of the data line on the substrate have an overlap area, and the overlap area is located within the orthographic projection area of ​​the groove on the substrate.

[0019] Optionally, forming a gate structure layer on a side of the gate insulation layer away from the substrate includes:

[0020] forming a second semiconductor material layer on a side of the gate insulating layer away from the substrate;

[0021] coating a photoresist on the second semiconductor material layer to form a first photoresist layer;

[0022] After masking, exposing and developing the first photoresist layer with a first half-tone mask or a first gray-tone mask, a first fully exposed area, a first partially exposed area and a first unexposed area are formed;

[0023] Performing a wet etching to etch away a portion of the thickness of the second semiconductor material layer in the first fully exposed area;

[0024] Performing an ashing process on the photoresist in the first partial exposure area to remove the photoresist in the first partial exposure area;

[0025] Performing secondary wet etching to etch away the remaining second semiconductor material layer in the first fully exposed area and a partial thickness of the second semiconductor material layer in the first partially exposed area;

[0026] The photoresist in the first unexposed area is stripped off to form the gate and the gate line; wherein,

[0027] An orthographic projection of the first partial exposure area on the substrate coincides with an orthographic projection of the groove on the substrate.

[0028] Furthermore, in the extension direction of the gate line, the width of the first partial exposure area is at least 1 um greater than the width of the overlap area.

[0029] Furthermore, before the wet etching is performed once, the thickness of the photoresist in the first partial exposure area is 0.4 um to 0.6 um.

[0030] Furthermore, the gate line includes a first portion facing the groove and a second portion outside the first portion, wherein

[0031] The thickness of the second portion is 0.25um to 0.3um; and / or,

[0032] The thickness of the first portion is 1 / 2 to 2 / 3 of the thickness of the second portion.

[0033] Optionally, forming the photoresist pattern includes:

[0034] coating a photoresist on the first semiconductor material layer to form a second photoresist layer;

[0035] After masking, exposing, and developing the second photoresist layer with a second half-tone mask or a second gray-tone mask, a photoresist pattern having a second fully exposed area, a second partially exposed area, and a second unexposed area is formed, wherein the second unexposed area has an intermediate photoresist area, and the orthographic projection of the intermediate photoresist area on the substrate coincides with the orthographic projection of the data line on the substrate;

[0036] The number of the second partial exposure areas is two; in the extending direction of the gate line, the two second partial exposure areas are symmetrically and closely distributed on both sides of the middle photoresist area.

[0037] Furthermore, the thickness of the photoresist in the second partial exposure area is 0.04um to 0.05um.

[0038] Furthermore, the width of the second partial exposure area is 1 um to 2 um.

[0039] In a second aspect, an embodiment of the present invention provides an array substrate, and the array substrate is manufactured by the manufacturing method as described above.

[0040] In a third aspect, an embodiment of the present invention provides a display device, comprising the array substrate as described above.

[0041] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0042] The array substrate and the preparation method thereof provided by the embodiments of the present invention form a gate line with a groove before forming an interlayer insulating layer, and the orthographic projection of the intersection between the data line and the gate line on the substrate falls within the orthographic projection of the groove on the substrate, that is, the thickness of the gate line in the overlapping area of ​​the gate line and the data line is reduced, so that the climbing profile of the interlayer insulating layer is smoother; a photoresist pattern corresponding to the source, drain and data line to be formed is formed on the first semiconductor material layer, and the photoresist pattern and the first semiconductor material layer are dry-etched to form the source, drain and data line, and the over-etching of the interlayer insulating layer is reduced by the photoresist pattern, thereby effectively reducing the DGS risk and improving the yield of the array substrate production. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0044] Figure 1 A schematic top view of an array substrate provided by an embodiment of the present invention;

[0045] Figures 2 to 14 A schematic diagram of a manufacturing process of an array substrate provided in an embodiment of the present invention;

[0046] Figures 15 to 17 A schematic diagram of a manufacturing process for forming a low-temperature polysilicon active layer provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It should also be noted that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0048] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] An embodiment of the present invention provides a method for preparing an array substrate, comprising:

[0050] An LTPS active layer, a gate insulating layer, a gate structure layer and an interlayer insulating layer are sequentially formed on a substrate, wherein the gate structure layer includes a gate and a gate line arranged on the same layer; a first semiconductor material layer and a photoresist pattern are sequentially formed on a side of the interlayer insulating layer away from the substrate, wherein the photoresist pattern corresponds to a source electrode, a drain electrode and a data line to be formed;

[0051] Etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line;

[0052] A flat layer, a pixel defining layer and a light emitting device layer are sequentially formed on the side of the source electrode, the drain electrode and the data line away from the substrate; wherein,

[0053] A groove is formed on the side of the gate line facing away from the substrate. The orthographic projection of the gate line on the substrate and the orthographic projection of the data line on the substrate have an overlap area, and the overlap area is located within the orthographic projection area of ​​the groove on the substrate.

[0054] In this embodiment, the gate line includes a first portion facing the groove and a second portion outside the first portion, wherein the second portion has the same thickness as the gate electrode, and the first portion is thinner than the second portion.

[0055] On the one hand, the overlapped area falls within the orthographic projection of the groove (or the first part) on the substrate, which effectively reduces the thickness of the gate line in the intersection area of ​​the gate line and the data line, so that the climbing profile of the interlayer insulating layer is relatively gentle; on the other hand, a photoresist pattern corresponding to the source, drain and data line to be formed is formed on the first semiconductor material layer, and the photoresist pattern and the first semiconductor material layer are dry-etched to form the source, drain and data line, and the over-etching of the interlayer insulating layer is reduced by the photoresist pattern. The above two aspects effectively reduce the DGS risk and improve the yield of array substrate production.

[0056] Figure 1 FIG. 1 is a schematic top view of an array substrate provided in an embodiment of the present invention. Figure 1 As shown, the gate lines 1 and the data lines 2 in the array substrate are cross-distributed vertically and horizontally, the gate lines 1 extend along a first direction, the data lines 2 extend along a second direction, there is an overlapping area 3 between the orthographic projection of the gate lines 1 on the substrate and the orthographic projection of the data lines 2 on the substrate, the array substrate has multiple overlapping areas 3, and several gate lines 1 of the array substrate have multiple first parts 171, and the first parts 171 correspond to the overlapping areas 3 one by one.

[0057] Refer to the following Figures 2 to 17 The preparation method of the array substrate provided in the above embodiment is described, and the preparation method comprises the following steps:

[0058] (1) Figure 2 As shown, a buffer layer 10 (buffer layer) is deposited on a substrate (not shown) to play a role of a barrier layer and a flattening layer. The buffer layer 10 can be a SiOx film layer or a SiNx film layer, or both of these film layers can be stacked and deposited at the same time, which can play a better role of a barrier layer and a flattening layer.

[0059] (2)Reference Figure 2 , Figures 15 to 17 , an LTPS active layer 11 is formed on the buffer layer 10 .

[0060] An amorphous silicon layer is deposited on the buffer layer 10 by using a PECVD method, and a dehydrogenation process is performed on the amorphous silicon layer to prevent hydrogen explosion during the crystallization process;

[0061] After the dehydrogenation process is completed, the LTPS process is carried out to polycrystallize the amorphous silicon layer, generally using a laser annealing process (ELA) to form a polycrystalline silicon layer;

[0062] A layer of photoresist is coated on the polysilicon layer, and the photoresist is exposed and patterned using a single-tone mask to form a fully exposed portion and an unexposed portion, and the fully exposed portion is etched, and the photoresist of the unexposed portion is stripped off to form a polysilicon pattern 12, such as Fig.15 As shown;

[0063] On the substrate having the polysilicon pattern 12 formed thereon, an LTPS active layer 11 including a heavily doped region 111, a lightly doped region 112 and an undoped region 113 is formed by a half-tone mask process or a gray tone mask process. Forming the LTPS active layer 11 includes:

[0064] A layer of photoresist is coated on the substrate formed with the polysilicon pattern 12. The photoresist is exposed and developed by a half-tone mask process or a gray tone mask process to form a third fully exposed area A1, a third partially exposed area A2 and a third unexposed area A3, wherein the third unexposed area A3 has a photoresist of a first thickness, and the third partially exposed area A2 has a photoresist of a second thickness, wherein the first thickness is greater than the second thickness. Fig.16 As shown;

[0065] By using an ion implantation method, a first ion implantation process is performed on the third fully exposed area A3 to form heavily doped regions 111 on both sides of the polysilicon pattern 12. Fig.16 As shown, it is preferred that the first ion implantation is N-type ion implantation, and the N-type ions can be phosphorus ions;

[0066] Then, the photoresist is ashed to remove the second thickness of the photoresist as a whole, that is, the photoresist in the third partial exposure area A2 is removed to expose the lightly doped area 112, and the thickness of the photoresist in the third unexposed area A3 is reduced;

[0067] By using an ion implantation method, a second ion implantation process is performed on the polysilicon pattern 12 of the third fully exposed area A3 and the third partially exposed area A2, and a lightly doped area 112 is formed between the heavily doped area 111 and the undoped area 113. The ion concentration of the lightly doped area 112 is less than that of the heavily doped area 111. The undoped area 113 is a channel area of ​​a thin film transistor (TFT). Fig.17 As shown, it is preferred that the second ion implantation is N-type ion implantation, and the N-type ions can be phosphorus ions;

[0068] The remaining photoresist in the third unexposed area A3 is stripped off to form an LTPS active layer 11 , which includes an undoped area 113 in the middle, heavily doped areas 111 on both sides, and a lightly doped area 112 between the undoped area 113 and the heavily doped area 111 .

[0069] In order to form a good electrical connection between the source and drain and the LTPS active layer 11, the present embodiment performs heavy doping in the source and drain regions of the LTPS active layer 11 by an ion implantation process to form a heavily doped region 111, and the source and drain are connected to the heavily doped region 111 of the LTPS active layer 11, thereby reducing the contact resistance and obtaining better TFT electrical characteristics. At the same time, considering that the semiconductor region is getting shorter and shorter, the short channel effect is becoming more and more obvious, and the short channel effect causes abnormal TFT characteristics, such as a large cut-off voltage Vth and a high leakage current Ioff. In order to avoid such abnormalities, a lightly doped region 112 is added between the heavily doped region and the undoped region 113, which is equivalent to connecting a resistor in series between the source and drain and the channel, thereby reducing the horizontal electric field of the channel and suppressing the leakage current. Moreover, the heavily doped region 111 and the lightly doped region 112 are formed by only one patterning process using a halftone mask or a gray tone mask, thereby simplifying the process steps.

[0070] (3) A gate insulating layer 14 is formed on the LTPS active layer 11 .

[0071] On the LTPS active layer 11, a gate insulating layer 14 is deposited by PECVD. The gate insulating layer 14 may be a composite SiOx / SiNx film layer. For example, a SiOx film layer is first deposited with a thickness of 0.03 to 0.06 um, and then a SiNx film layer is deposited with a thickness of 0.05 to 0.09 um.

[0072] (4) A gate structure layer is formed on the gate insulating layer 14 .

[0073] A second semiconductor material layer 15 is formed on the side of the gate insulating layer 14 away from the substrate by using a magnetron sputtering device (suptter). The material may be Al, Mo, composite Al / Mo, etc.;

[0074] A photoresist is coated on the second semiconductor material layer 15 to form a first photoresist layer 16. Figure 2 ;

[0075] Reference Figure 3 and Figure 5 , after masking, exposing and developing the first photoresist layer 16 with a first half-tone mask 18, a first completely exposed area B1, a first partially exposed area B2 and a first unexposed area B3 are formed;

[0076] Reference Figure 6 , performing a wet etching to etch away a portion of the second semiconductor material layer in the first fully exposed area B1;

[0077] Reference Figure 7 , performing an ashing process on the photoresist in the first partial exposure area B2 to remove the photoresist in the first partial exposure area B2;

[0078] Perform secondary wet etching to etch away the remaining second semiconductor material layer in the first fully exposed area B1 and a partial thickness of the second semiconductor material layer in the first partially exposed area B2;

[0079] The photoresist in the first unexposed area B3 is stripped to form a gate 4 and a gate line 1. Figure 8 ;in,

[0080] The gate line 1 includes a first part 171 and a second part 172. The orthographic projection of the first part exposure area B2 on the substrate coincides with the orthographic projection of the first part 171 on the substrate. The second part 172 and the gate 4 are opposite to the first unexposed area B3. The thickness of the second part 172 is the same as the thickness of the gate 4. The thickness of the first part 171 is less than the thickness of the second part 172, that is, the gate line 1 has a plurality of groove structures.

[0081] Furthermore, in the first direction (i.e., the extension direction of the gate line), the width of the first partial exposure area B2 is at least 1um greater than the width of the overlap area 3. The data line 2 and the gate line 1 are arranged to cross each other, thus ensuring that the data line 2 falls within the first thinned portion 171 of the gate line 1.

[0082] Furthermore, before the first wet etching, the thickness of the photoresist in the first partial exposure area B2 is 0.4 um to 0.6 um, thereby ensuring that the second semiconductor material layer 15 facing the first partial exposure area B2 will not be etched during the first wet etching.

[0083] Further, the thickness of the second portion 172 is 0.25um to 0.3um; and / or,

[0084] The thickness of the first portion 171 is 1 / 2 to 2 / 3 of the thickness of the second portion 172 .

[0085] Generally, it is preferred that the thickness of the first portion 171 is 1 / 2 of the thickness of the second portion 172 . The thickness of the first portion 171 can be conveniently controlled by controlling the wet etching time.

[0086] Compared with the prior art in which the gate line is provided with the same thickness as the gate, in this embodiment, the thickness of the first portion 171 where the gate line 1 and the data line 2 intersect is less than the thickness of the second portion 172, that is, the gate line 1 has the aforementioned groove structure, which can increase the thickness of the interlayer insulating layer 21 at the overlapping area of ​​the gate line 1 and the data line 2.

[0087] Reference Figure 3 , the first half-tone mask 18 performs exposure processing on the first photoresist layer 16, and the first half-tone mask 18 includes a first transparent area 181, a first semi-transparent area 182 and a first opaque area 183. The photoresist 19 is the state of the first photoresist layer 16 after exposure, wherein the area 191 corresponds to the first transparent area 181, the area 192 corresponds to the first semi-transparent area 182, and the area 193 corresponds to the first opaque area 183. The photoresist 20 is the state of the photoresist 19 after development, wherein the first fully exposed area B1 corresponds to the first transparent area 181, the first partially exposed area B2 corresponds to the first semi-transparent area 182, and the first unexposed area B3 corresponds to the first opaque area 183.

[0088] In this embodiment, the first photoresist layer 16 can be masked, exposed and developed by using a gray tone mask process to form a first fully exposed area B1, a first partially exposed area B2 and a first unexposed area B3. The gray tone mask plate uses a grating effect to make the intensity of light transmitted through the mask different in different areas, so that the photoresist is selectively exposed and developed.

[0089] Reference Figure 4, the first gray tone mask plate 18' is used to expose the first photoresist layer 16, and the first gray tone mask plate 18' includes a first transparent area 181', a first semi-transparent area 182' and a first opaque area 183'. The photoresist 19' is the state of the first photoresist layer 16 after exposure, wherein the area 191' corresponds to the first transparent area 181', the area 192' corresponds to the first semi-transparent area 182', and the area 193' corresponds to the first opaque area 183'. The photoresist 20' is the state of the photoresist 19' after development, wherein the first fully exposed area B1 corresponds to the first transparent area 181', the first partially exposed area B2 corresponds to the first semi-transparent area 182', and the first unexposed area B3 corresponds to the first opaque area 183'.

[0090] In this embodiment, only one patterning process using a halftone mask or a gray tone mask is required to form the first fully exposed area B1, the first partially exposed area B2 and the first unexposed area B3, thereby simplifying the process steps.

[0091] (5) Fig. 9 As shown, an interlayer insulating layer 21 is formed.

[0092] An interlayer insulating layer 21 is formed on the side of the gate structure layer away from the substrate by PECVD to prevent a short circuit between the gate structure layer and the source and drain. The material of the interlayer insulating layer 21 can be a composite SiOx / SiNx film layer, with a SiOx / thickness of 0.2 to 0.5 um and a SiNx thickness of 0.2 to 0.3 um.

[0093] Subsequently, two vias are formed on the interlayer insulating layer 21 and the gate insulating layer 14 through a patterning process (mask, exposure, development) and a dry etching process. The two vias correspond to the heavily doped regions of the LTPS active layer 11, and the two vias correspond to the source 221 and the drain 222 to be formed.

[0094] (6) Figures 10 to 12 , forming a source electrode 221 , a drain electrode 222 and a data line 2 .

[0095] A first semiconductor material layer 22 is formed on a side of the interlayer insulating layer 21 away from the substrate. The material may be titanium-aluminum-titanium (Ti-Al-Ti), and the film thickness is (300um-600um) / (4000um-5000um) / (300um-600um);

[0096] A photoresist is coated on the first semiconductor material layer 22 to form a second photoresist layer 23. Fig.10 ;

[0097] like Fig.11 and Fig.12, after masking, exposing and developing the second photoresist layer 23 with a second half-tone mask plate 24, a photoresist pattern 25 having a second fully exposed area C1, a second partially exposed area C2 and a second unexposed area C3 is formed, the second unexposed area C3 having an intermediate photoresist area C4, and the orthographic projection of the intermediate photoresist area C4 on the substrate coincides with the orthographic projection of the data line 2 on the substrate;

[0098] The number of the second partial exposure areas C2 is two; in the first direction, the two second partial exposure areas C2 are symmetrically and closely distributed on both sides of the middle photoresist area C4.

[0099] The photoresist pattern 25 and the first semiconductor material layer 22 are dry-etched, for example, by using boron trichloride and chlorine plasma to form a source electrode 221 , a drain electrode 222 and a data line 2 .

[0100] In this embodiment, a second gray-tone mask (not shown) may be used to mask, expose, and develop the second photoresist layer to form a photoresist pattern 25 having a second fully exposed area C1, a second partially exposed area C2, and a second unexposed area C3.

[0101] In this embodiment, only one patterning process using a halftone mask or a gray tone mask is required to form the second fully exposed area C1, the second partially exposed area C2 and the second unexposed area C3, thereby simplifying the process steps.

[0102] Furthermore, the thickness of the photoresist in the second partial exposure area is 0.04um to 0.05um, and the width of the second partial exposure area is 1um to 2um. In the overlapping area between the gate line 1 and the data line 2, the thin layer of photoresist with a thickness of 0.04um to 0.05um and a width of 1um to 2um in the second partial exposure area can effectively reduce the over-etching of the first semiconductor material layer 22, increase the thickness of the interlayer insulating layer 21 in the overlapping area between the gate line 1 and the data line 2, and reduce the DGS risk.

[0103] (7) The flat layer 26 is formed.

[0104] A planar layer 26 is formed on the side of the source electrode 221 , the drain electrode 222 and the data line 2 away from the substrate. The material may be SiNx or an organic coating. A planar layer via hole exposing the source electrode 221 is formed on the planar layer 26 .

[0105] (8) The anode 27, the pixel defining layer 28, the light emitting device layer and the cathode are formed.

[0106] An anode 27 is formed on a side of the planar layer 25 away from the substrate, and the anode 27 is connected to the source electrode 221 through a planar layer via hole;

[0107] A pixel defining layer 28 is formed on a side of the anode 27 away from the substrate, and an opening 29 exposing the anode 28 is formed by dry etching;

[0108] forming a light emitting device layer (not shown) in the opening;

[0109] A cathode (not shown) is formed on a side of the light emitting device layer away from the substrate and on a side of the pixel defining layer 28 away from the substrate.

[0110] An embodiment of the present invention further provides an array substrate, which is prepared by the above preparation method, so that the interlayer insulating layer between the gate lines and the data lines is not over-etched, the risk of DGS is reduced, and the product yield is improved.

[0111] Reference Fig.14 An embodiment of the present invention provides an array substrate, which includes a substrate, and is provided with: a low-temperature polysilicon active layer 11, a gate insulating layer 14, a gate structure layer, an interlayer insulating layer 21, a source-drain structure layer, a planarization layer 26, a pixel defining layer 28 and a light-emitting device layer in sequence on one side of the substrate and in a direction away from the substrate;

[0112] Among them, the gate structure layer includes a gate 4 and a gate line 1 arranged in the same layer, the source-drain structure layer includes a source 221, a drain 222 and a data line 2 arranged in the same layer, a groove is formed on the side of the gate line 1 facing away from the substrate, and there is an overlapping area between the orthographic projection of the gate line 1 on the substrate and the orthographic projection of the data line 2 on the substrate, and the overlapping area is located within the orthographic projection area of ​​the groove on the substrate.

[0113] Since the intersection between the gate line and the data line falls within the groove of the gate line, when forming the interlayer insulating layer, the thickness of the portion of the interlayer insulating layer facing the groove is correspondingly increased, that is, the thickness of the interlayer insulating layer between the portion of the gate line facing the data line and the data line is increased, so that in the process of forming the source-drain structure layer, over-etching of the interlayer insulating layer can be avoided, thereby avoiding the risk of DGS.

[0114] Furthermore, in the extension direction of the gate line 1, the width of the groove is at least 1 um greater than the width of the overlapped area, so as to ensure that the data line falls within the groove structure of the gate line.

[0115] Further, the gate line includes a first portion and a second portion outside the first portion, and an orthographic projection of the first portion on the substrate coincides with an orthographic projection of the groove on the substrate, wherein:

[0116] The thickness of the second part is 0.25um to 0.3um; and / or,

[0117] The thickness of the first part is 1 / 2 to 2 / 3 of the thickness of the second part.

[0118] Preferably, the thickness of the first part is 1 / 2 of the thickness of the second part. By controlling the wet etching time, the thickness of the first part can be conveniently controlled.

[0119] In this embodiment, the thickness of the first portion where the gate line 1 and the data line 2 intersect is smaller than the thickness of the second portion, that is, the groove structure of the gate line 1 can increase the thickness of the interlayer insulating layer 21 at the overlapping area of ​​the gate line 1 and the data line 2 .

[0120] The embodiment of the present invention further provides a display device, comprising the above array substrate. The display device can be: a liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, or any other product or component with a display function.

[0121] The present invention uses first, second, etc. to describe various information, but such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information.

[0122] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0123] The above description is only a preferred embodiment of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) to form a technical solution.

Claims

1. A method for preparing an array substrate, characterized in that: include: A low-temperature polysilicon active layer, a gate insulating layer, a gate structure layer and an interlayer insulating layer are sequentially formed on a substrate, wherein the gate structure layer includes a gate and a gate line arranged in the same layer; A first semiconductor material layer and a photoresist pattern are sequentially formed on a side of the interlayer insulating layer away from the substrate, wherein the photoresist pattern corresponds to a source electrode, a drain electrode and a data line to be formed; Etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line; A flat layer, a pixel defining layer and a light emitting device layer are sequentially formed on the side of the source electrode, the drain electrode and the data line away from the substrate; wherein, A groove is formed on the side of the gate line facing away from the substrate, and an orthographic projection of the gate line on the substrate and an orthographic projection of the data line on the substrate have an overlap area, and the overlap area is located within the orthographic projection area of ​​the groove on the substrate; Forming the photoresist pattern includes: coating a photoresist on the first semiconductor material layer to form a second photoresist layer; After masking, exposing, and developing the second photoresist layer with a second half-tone mask or a second gray-tone mask, a photoresist pattern having a second fully exposed area, a second partially exposed area, and a second unexposed area is formed, wherein the second unexposed area has an intermediate photoresist area, and the orthographic projection of the intermediate photoresist area on the substrate coincides with the orthographic projection of the data line on the substrate; The number of the second partial exposure areas is two; in the extending direction of the gate line, the two second partial exposure areas are symmetrically and closely distributed on both sides of the middle photoresist area.

2. The method for preparing an array substrate according to claim 1, characterized in that: Forming a gate structure layer on a side of the gate insulating layer away from the substrate comprises: forming a second semiconductor material layer on a side of the gate insulating layer away from the substrate; coating a photoresist on the second semiconductor material layer to form a first photoresist layer; After masking, exposing and developing the first photoresist layer with a first half-tone mask or a first gray-tone mask, a first fully exposed area, a first partially exposed area and a first unexposed area are formed; Performing a wet etching to etch away a portion of the thickness of the second semiconductor material layer in the first fully exposed area; Performing an ashing process on the photoresist in the first partial exposure area to remove the photoresist in the first partial exposure area; Performing secondary wet etching to etch away the remaining second semiconductor material layer in the first fully exposed area and a partial thickness of the second semiconductor material layer in the first partially exposed area; The photoresist in the first unexposed area is stripped off to form the gate and the gate line; wherein, An orthographic projection of the first partial exposure area on the substrate coincides with an orthographic projection of the groove on the substrate.

3. The method for preparing an array substrate according to claim 2, characterized in that: In the extending direction of the gate line, the width of the first partial exposure area is at least 1 um greater than the width of the overlap area.

4. The method for preparing an array substrate according to claim 2, wherein: Before the wet etching is performed once, the thickness of the photoresist in the first partial exposure area is 0.4um-0.6um.

5. The method for preparing an array substrate according to any one of claims 1 to 4, characterized in that: The gate line includes a first portion facing the first portion and a second portion outside the first portion, and the orthographic projection of the first portion on the substrate coincides with the orthographic projection of the groove on the substrate, wherein The thickness of the second part is 0.25um~0.3um; and / or, The thickness of the first part is 1 / 2 to 2 / 3 of the thickness of the second part.

6. The method for preparing an array substrate according to claim 1, characterized in that: The thickness of the photoresist in the second partial exposure area is 0.04um-0.05um.

7. The method for preparing an array substrate according to claim 1, characterized in that: The width of the second partial exposure area is 1um~2um.

8. An array substrate, characterized in that: The array substrate is formed by the method for preparing the array substrate according to any one of claims 1 to 7, comprising: A substrate, on one side of the substrate and in a direction away from the substrate, provided in sequence: a low-temperature polysilicon active layer, a gate insulating layer, a gate structure layer, an interlayer insulating layer, a source-drain structure layer, a planarization layer, a pixel defining layer and a light-emitting device layer; Among them, the gate structure layer includes a gate and a gate line arranged in the same layer, the source-drain structure layer includes a source, a drain and a data line arranged in the same layer, a groove is formed on the side of the gate line facing away from the substrate, and there is an overlapping area between the orthographic projection of the gate line on the substrate and the orthographic projection of the data line on the substrate, and the overlapping area is located within the orthographic projection area of ​​the groove on the substrate.

9. The array substrate according to claim 8, characterized in that: In the extending direction of the gate line, the width of the groove is at least 1 um greater than the width of the overlapping area.

10. A display device, characterized in that: Comprising the array substrate as described in any one of claims 8 to 9.

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