Fourth order feed forward compensation operational amplifier and design method thereof

Abstract

The application provides a fourth-order feedforward compensation operational amplifier and a design method thereof, and is based on a structural design of "mainly taking a fourth-order operational amplifier path, and sequentially feeding forward compensation from a higher first order to a lower first order in adjacent two-order operational amplifier paths", so that a gain and three zero points of a transfer function can be easily obtained, only a feedforward branch exists, no feedback branch exists, four poles can be obtained by node parameters, and a transfer function of the fourth-order feedforward compensation operational amplifier can be obtained according to the obtained direct current gain, the three zero points and the four poles, that is, the transfer function can be easily obtained based on the circuit structural design; based on the obtained transfer function and a gain requirement of a continuous-time band-pass sigma-delta modulator, a transconductance constraint relationship between each transconductance amplification unit can be deduced, each transconductance amplification unit is selected and designed according to the corresponding transconductance constraint relationship, and the formed fourth-order feedforward compensation operational amplifier can effectively meet the use requirement of the continuous-time band-pass sigma-delta modulator.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a fourth-order feedforward compensated operational amplifier and its design method. Background Technology

[0002] For continuous-time bandpass sigma-delta modulators used in intermediate frequencies of hundreds of MHz, the operational amplifier gain in its loop filter needs to meet two performance requirements: (1) a gain of at least 40 dB over the signal bandwidth; and (2) a gain of 10-20 dB at the modulator's Nyquist frequency. Traditional second-order Miller-compensated operational amplifiers struggle to meet these performance requirements, making high-order multi-path feedforward compensated operational amplifiers ideal for such applications.

[0003] However, as the order and structural complexity increase, it becomes difficult for designers to create high-order multi-path feedforward compensated operational amplifiers that meet specific requirements. Based on this, X. Yang et al. calculated the transfer function of a fourth-order feedforward compensated operational amplifier, obtaining the locations of its four poles and three zeros. They then constrained the transconductance of the main path and the feedforward branch in the operational amplifier to ensure that the three zeros were approximately equal and all within the amplifier's unity-gain bandwidth. This allowed their designed feedforward operational amplifier to maintain at least 40dB of gain over a bandwidth of several hundred MHz, while also satisfying conditional stability. However, this design method requires tedious mathematical calculations when deriving the system transfer function of high-order multi-path feedforward operational amplifiers, and the complexity of the transfer function calculation increases with the amplifier order or the complexity of the amplifier system structure. Furthermore, FTGebreyohannes et al. proposed a method based on g... m / I D The method designs an algorithm for operational amplifiers in continuous-time bandpass sigma-delta modulators. This algorithm incorporates code for each component within the operational amplifier, taking into account the performance requirements of the feedforward operational amplifier and the physical constraints of the device fabrication process, and is based on the op-amp design. m / I D The method involves writing code to design the amplifier. However, operational amplifiers implemented using such algorithms do not involve analysis and understanding of the amplifier circuit itself, thus losing a deep understanding of the circuit level of high-order multiplexed feedforward operational amplifiers.

[0004] In view of this, there is an urgent need for a high-order multiplexed feedforward operational amplifier that can derive its system transfer function without complex mathematical derivation and calculation and can effectively and deeply analyze its circuit-level structure. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a technical solution for a fourth-order feedforward compensated operational amplifier to solve the above-mentioned technical problems.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] A fourth-order feedforward compensated operational amplifier includes a first transconductance amplification unit, a second transconductance amplification unit, a third transconductance amplification unit, a fourth transconductance amplification unit, a fifth transconductance amplification unit, a sixth transconductance amplification unit, and a seventh transconductance amplification unit.

[0008] The first transconductance amplification unit, the second transconductance amplification unit, the third transconductance amplification unit, and the fourth transconductance amplification unit are cascaded in sequence, and the first transconductance amplification unit, the second transconductance amplification unit, the third transconductance amplification unit, and the fourth transconductance amplification unit constitute a fourth-order operational amplifier path;

[0009] The input terminal of the fifth transconductance amplifier unit is connected to the output terminal of the first transconductance amplifier unit, and the output terminal of the fifth transconductance amplifier unit is connected to the input terminal of the fourth transconductance amplifier unit. The first transconductance amplifier unit, the fifth transconductance amplifier unit, and the fourth transconductance amplifier unit constitute a third-order operational amplifier path.

[0010] The input terminal of the sixth transconductance amplifier unit is connected to the output terminal of the first transconductance amplifier unit, and the output terminal of the sixth transconductance amplifier unit is connected to the output terminal of the fourth transconductance amplifier unit. The first transconductance amplifier unit and the sixth transconductance amplifier unit constitute a second-order operational amplifier path.

[0011] The input terminal of the seventh transconductance amplifier unit is connected to the input terminal of the first transconductance amplifier unit, and the output terminal of the seventh transconductance amplifier unit is connected to the output terminal of the fourth transconductance amplifier unit. The seventh transconductance amplifier unit constitutes a first-order operational amplifier path.

[0012] Specifically, the first-order operational amplifier path performs feedforward compensation on the second-order operational amplifier path, the second-order operational amplifier path performs feedforward compensation on the third-order operational amplifier path, and the third-order operational amplifier path performs feedforward compensation on the fourth-order operational amplifier path.

[0013] Optionally, the first transconductance amplification unit adopts a common-source, common-gate differential amplification structure. The first transconductance amplification unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The source of the first PMOS transistor is connected to the operating voltage, and the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor. The source of the second PMOS transistor is connected to the operating voltage, and the gate of the second PMOS transistor is connected to the drain of the third PMOS transistor. The drain of the first NMOS transistor is connected to the gate of the third PMOS transistor, the drain of the second PMOS transistor is also connected to the drain of the first PMOS transistor, the source of the third PMOS transistor is connected to the operating voltage, the drain of the third PMOS transistor is also connected to the drain of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the operating voltage, the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, and the drain of the first NMOS transistor serves as the negative terminal of the differential output, the gate of the first NMOS transistor is connected to the first bias voltage, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor serves as the positive terminal of the differential input, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the second bias voltage, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is also connected to the fourth NMOS transistor. The source of the transistor, the gate of the fourth NMOS transistor is used as the negative terminal of the differential input, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the first bias voltage, the drain of the fifth NMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the fifth NMOS transistor is used as the positive terminal of the differential output.

[0014] Optionally, the second transconductance amplification unit adopts a differential amplification structure. The second transconductance amplification unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The source of the fifth PMOS transistor is connected to the operating voltage, and the gate of the fifth PMOS transistor is connected to its drain. The source of the sixth PMOS transistor is connected to the operating voltage, and the gate of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor. The drain of the sixth PMOS transistor is also connected to the drain of the fifth PMOS transistor. The source of the seventh PMOS transistor is connected to the operating voltage, and the drain of the seventh PMOS transistor is also connected to the drain of the eighth PMOS transistor. The source of the eighth PMOS transistor is connected to the operating voltage, and the gate of the eighth PMOS transistor is connected to its drain. The sixth NMOS transistor... The drain of the transistor is connected to the drain of the fifth PMOS transistor, and the drain of the sixth NMOS transistor serves as the negative terminal of the differential output. The gate of the sixth NMOS transistor serves as the positive terminal of the differential input. The source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the third bias voltage. The source of the seventh NMOS transistor is grounded. The drain of the seventh NMOS transistor is also connected to the source of the eighth NMOS transistor. The gate of the eighth NMOS transistor serves as the negative terminal of the differential input. The drain of the eighth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the eighth NMOS transistor serves as the positive terminal of the differential output.

[0015] Optionally, the third transconductance amplification unit adopts a differential amplification structure with common-mode feedback. The third transconductance amplification unit includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first operational amplifier, a first resistor, and a second resistor. The source of the ninth PMOS transistor is connected to the operating voltage, the gate of the ninth PMOS transistor serves as the positive terminal of the first differential input, the drain of the ninth PMOS transistor is connected to the drain of the tenth PMOS transistor, the source of the tenth PMOS transistor is connected to the operating voltage, the gate of the tenth PMOS transistor is connected to the gate of the eleventh PMOS transistor, the source of the eleventh PMOS transistor is connected to the operating voltage, and the drain of the eleventh PMOS transistor is connected to the drain of the twelfth PMOS transistor. The source of the transistor is connected to the operating voltage. The gate of the twelfth PMOS transistor serves as the negative terminal of the first differential input. The drain of the ninth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the drain of the ninth NMOS transistor serves as the negative terminal of the differential output. The gate of the ninth NMOS transistor serves as the positive terminal of the second differential input. The source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor. The gate of the tenth NMOS transistor is connected to the fourth bias voltage. The source of the tenth NMOS transistor is grounded. The drain of the tenth NMOS transistor is also connected to the source of the eleventh NMOS transistor. The gate of the NMOS transistor serves as the negative terminal of the second differential input. The drain of the eleventh NMOS transistor is connected to the drain of the eleventh PMOS transistor, and the drain of the eleventh NMOS transistor serves as the positive terminal of the differential output. The non-inverting input of the first operational amplifier is connected to the drain of the ninth NMOS transistor via the first resistor in series. The non-inverting input of the first operational amplifier is also connected to the drain of the eleventh NMOS transistor via the second resistor in series. The inverting input of the first operational amplifier is connected to the first reference signal. The output of the first operational amplifier is connected to the gate of the tenth PMOS transistor.

[0016] Optionally, the fourth transconductance amplification unit adopts a complementary differential amplification structure with common-mode feedback. The fourth transconductance amplification unit includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a second operational amplifier, a third resistor, and a fourth resistor. The source of the thirteenth PMOS transistor is connected to the operating voltage, the gate of the thirteenth PMOS transistor serves as the positive terminal of the first differential input, and the drain of the thirteenth PMOS transistor is connected to the drain of the fourteenth PMOS transistor. The source of the fourteenth PMOS transistor is connected to the operating voltage, the gate of the fourteenth PMOS transistor is connected to the gate of the fifteenth PMOS transistor, the source of the fifteenth PMOS transistor is connected to the operating voltage, the drain of the fifteenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor, the source of the sixteenth PMOS transistor is connected to the operating voltage, and the gate of the sixteenth PMOS transistor serves as the negative terminal of the first differential input. The source of the seventeenth PMOS transistor is connected to the operating voltage, the drain of the seventeenth PMOS transistor is connected to the drain of the fourteenth PMOS transistor, and the source of the eighteenth PMOS transistor is connected to the operating voltage. The drain of the 18th PMOS transistor is connected to the drain of the 15th PMOS transistor, the drain of the 12th NMOS transistor is connected to the drain of the 14th PMOS transistor, and the drain of the 12th NMOS transistor serves as the negative terminal of the differential output. The gate of the 12th NMOS transistor is connected to the gate of the 17th PMOS transistor and serves as the positive terminal of the second differential input. The source of the 12th NMOS transistor is connected to the drain of the 13th NMOS transistor, the gate of the 13th NMOS transistor is connected to the fifth bias voltage, the source of the 13th NMOS transistor is grounded, and the drain of the 13th NMOS transistor is also connected to the source of the 14th NMOS transistor. The gate of the OS transistor is connected to the gate of the eighteenth PMOS transistor and serves as the negative terminal of the second differential input. The drain of the fourteenth NMOS transistor is connected to the drain of the fifteenth PMOS transistor, and the drain of the fourteenth NMOS transistor serves as the positive terminal of the differential output. The non-inverting input of the second operational amplifier is connected to the drain of the twelfth NMOS transistor via the third resistor in series. The non-inverting input of the second operational amplifier is also connected to the drain of the fourteenth NMOS transistor via the fourth resistor in series. The inverting input of the second operational amplifier is connected to the second reference signal. The output of the second operational amplifier is connected to the gate of the fourteenth PMOS transistor.

[0017] Optionally, the fifth transconductance amplification unit adopts a differential amplification structure with common-mode feedback. The fifth transconductance amplification unit includes a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, a third operational amplifier, a fifth resistor, and a sixth resistor. The source of the nineteenth PMOS transistor is connected to the operating voltage, the gate of the nineteenth PMOS transistor serves as the positive terminal of the first differential input, and the drain of the nineteenth PMOS transistor is connected to the drain of the twentieth PMOS transistor. The source of the twentieth PMOS transistor is connected to the operating voltage. The gate of the twentieth PMOS transistor is connected to the gate of the twentieth eleventh PMOS transistor, and the source of the twentieth PMOS transistor is connected to the operating voltage. The drain of the twentieth PMOS transistor is connected to the drain of the twentieth twelfth PMOS transistor, and the source of the twentieth PMOS transistor is connected to the operating voltage. The gate of the twentieth PMOS transistor serves as the negative terminal of the first differential input. The drain of the fifteenth NMOS transistor is connected to the drain of the nineteenth PMOS transistor, and the drain of the fifteenth NMOS transistor serves as the negative terminal of the differential output. The gate of the fifteenth NMOS transistor serves as the positive terminal of the second differential input. The source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor. The gate of the transistor is connected to the sixth bias voltage. The source of the sixteenth NMOS transistor is grounded. The drain of the sixteenth NMOS transistor is also connected to the source of the seventeenth NMOS transistor. The gate of the seventeenth NMOS transistor serves as the negative terminal of the second differential input. The drain of the seventeenth NMOS transistor is connected to the drain of the twenty-first PMOS transistor, and the drain of the seventeenth NMOS transistor serves as the positive terminal of the differential output. The non-inverting input of the third operational amplifier is connected to the drain of the fifteenth NMOS transistor via the fifth resistor in series. The non-inverting input of the third operational amplifier is also connected to the drain of the seventeenth NMOS transistor via the sixth resistor in series. The inverting input of the third operational amplifier is connected to the third reference signal. The output of the third operational amplifier is connected to the gate of the twentieth PMOS transistor.

[0018] Optionally, the sixth transconductance amplification unit adopts a complementary differential amplification structure with common-mode feedback. The sixth transconductance amplification unit includes a 23rd PMOS transistor, a 24th PMOS transistor, a 25th PMOS transistor, a 26th PMOS transistor, a 27th PMOS transistor, a 28th PMOS transistor, an 18th NMOS transistor, a 19th NMOS transistor, a 20th NMOS transistor, a fourth operational amplifier, a seventh resistor, and an eighth resistor. The source of the 23rd PMOS transistor is connected to the operating voltage, the gate of the 23rd PMOS transistor serves as the positive terminal of the first differential input, and the drain of the 23rd PMOS transistor is connected to the drain of the 24th PMOS transistor. The source of the fourteenth PMOS transistor is connected to the operating voltage. The gate of the fourteenth PMOS transistor is connected to the gate of the twenty-fifth PMOS transistor. The source of the twenty-fifth PMOS transistor is connected to the operating voltage. The drain of the twenty-fifth PMOS transistor is connected to the drain of the twenty-sixth PMOS transistor. The source of the twenty-sixth PMOS transistor is connected to the operating voltage. The gate of the twenty-sixth PMOS transistor serves as the negative terminal of the first differential input. The source of the twenty-seventh PMOS transistor is connected to the operating voltage. The drain of the twenty-seventh PMOS transistor is connected to the drain of the twenty-fourth PMOS transistor. The source of the twenty-eighth PMOS transistor is connected to the operating voltage. The drain of the transistor is connected to the drain of the 25th PMOS transistor, the drain of the 18th NMOS transistor is connected to the drain of the 24th PMOS transistor, and the drain of the 18th NMOS transistor serves as the negative terminal of the differential output. The gate of the 18th NMOS transistor is connected to the gate of the 27th PMOS transistor and serves as the positive terminal of the second differential input. The source of the 18th NMOS transistor is connected to the drain of the 19th NMOS transistor, the gate of the 19th NMOS transistor is connected to the seventh bias voltage, the source of the 19th NMOS transistor is grounded, and the drain of the 19th NMOS transistor is also connected to the source of the 20th NMOS transistor. The gate of the second operational amplifier is connected to the gate of the 28th PMOS transistor and serves as the negative terminal of the second differential input. The drain of the 20th NMOS transistor is connected to the drain of the 25th PMOS transistor, and the drain of the 20th NMOS transistor serves as the positive terminal of the differential output. The non-inverting input of the fourth operational amplifier is connected to the drain of the 18th NMOS transistor via the 7th resistor in series. The non-inverting input of the fourth operational amplifier is also connected to the drain of the 20th NMOS transistor via the 8th resistor in series. The inverting input of the fourth operational amplifier is connected to the fourth reference signal. The output of the fourth operational amplifier is connected to the gate of the 24th PMOS transistor.

[0019] Optionally, the seventh transconductance amplification unit adopts a complementary differential amplification structure. The seventh transconductance amplification unit includes a 29th PMOS transistor, a 30th PMOS transistor, a 31st PMOS transistor, a 32nd PMOS transistor, a 33rd PMOS transistor, a 34th PMOS transistor, a 21st NMOS transistor, a 22nd NMOS transistor, a 23rd NMOS transistor, a first capacitor, and a second capacitor. The source of the 29th PMOS transistor is connected to the operating voltage, and the gate of the 29th PMOS transistor is connected to its drain. The drain of the 29th PMOS transistor is connected to the drain of the 30th PMOS transistor. The source of the 30th PMOS transistor is connected to the operating voltage, and the gate of the 30th PMOS transistor is connected to the drain of the 31st PMOS transistor. The source of the 31st PMOS transistor is connected to the operating voltage, and the gate of the 31st PMOS transistor is connected to its drain. The drain of the 31st PMOS transistor is connected to the drain of the 32nd PMOS transistor, and the source of the 32nd PMOS transistor is connected to the operating voltage. The gate of the transistor is connected to the drain of the thirty-second PMOS transistor, the source of the thirty-third PMOS transistor is connected to the operating voltage, the drain of the thirty-third PMOS transistor is connected to the drain of the thirtieth PMOS transistor, the source of the thirty-fourth PMOS transistor is connected to the operating voltage, the drain of the thirty-fourth PMOS transistor is connected to the drain of the thirty-first PMOS transistor, the drain of the twenty-first NMOS transistor is connected to the drain of the thirtieth PMOS transistor, and the drain of the twenty-first NMOS transistor, after being connected in series with the first capacitor, serves as the negative terminal of the differential output. The gate of the twenty-first NMOS transistor is connected to the gate of the thirty-third PMOS transistor and serves as the positive terminal of the differential input. The source of the twenty-first NMOS transistor is connected to the drain of the twenty-second NMOS transistor, the gate of the twenty-second NMOS transistor is connected to the eighth bias voltage, the source of the twenty-second NMOS transistor is grounded, the drain of the twenty-second NMOS transistor is also connected to the source of the twenty-third NMOS transistor, and the gate of the twenty-third NMOS transistor is connected to the gate of the thirty-fourth PMOS transistor and serves as the negative terminal of the differential input. The drain of the transistor is connected to the drain of the thirty-first PMOS transistor, and the drain of the twenty-third NMOS transistor is connected in series with the second capacitor to serve as the positive terminal of the differential output.

[0020] Optionally, the fourth-order feedforward compensated operational amplifier is designed based on a 65nm CMOS process.

[0021] A design method for a fourth-order feedforward compensated operational amplifier includes the following steps:

[0022] It provides a first transconductance amplification unit, a second transconductance amplification unit, a third transconductance amplification unit, a fourth transconductance amplification unit, a fifth transconductance amplification unit, a sixth transconductance amplification unit, and a seventh transconductance amplification unit;

[0023] A fourth-order operational amplifier path is constructed using the first transconductance amplification unit, the second transconductance amplification unit, the third transconductance amplification unit, and the fourth transconductance amplification unit;

[0024] The first transconductance amplification unit, the fifth transconductance amplification unit, and the fourth transconductance amplification unit are used to form a third-order operational amplifier path, and the fourth-order operational amplifier path is fed forward compensation through the third-order operational amplifier path.

[0025] The first transconductance amplification unit and the sixth transconductance amplification unit are used to form a second-order operational amplifier path, and the third-order operational amplifier path is fed forward compensation through the second-order operational amplifier path.

[0026] The seventh transconductance amplifier unit is used to construct a first-order operational amplifier path, and the second-order operational amplifier path is fed forward to compensate through the first-order operational amplifier path.

[0027] Optionally, the first transconductance amplification unit is formed based on the cascode differential amplification technique, the second transconductance amplification unit is formed based on the differential amplification technique, the third and fifth transconductance amplification units are formed based on the differential amplification technique with common-mode feedback, the fourth and sixth transconductance amplification units are formed based on the complementary differential amplification technique with common-mode feedback, and the seventh transconductance amplification unit is formed based on the complementary differential amplification technique.

[0028] As described above, the fourth-order feedforward compensated operational amplifier and its design method of the present invention have at least the following beneficial effects:

[0029] The highest-order path of this fourth-order feedforward compensated operational amplifier is a fourth-order op-amp path. Since the gain of the operational amplifier increases with the cascade order, the DC gain of this fourth-order feedforward compensated operational amplifier can be approximated by the DC gain of its fourth-order op-amp path. Based on the structural design of "first-order op-amp path feedforward compensation to second-order op-amp path, second-order op-amp path feedforward compensation to third-order op-amp path, and third-order op-amp path feedforward compensation to fourth-order op-amp path," the zeros generated by adjacent op-amp paths are equal to the zeros of the equivalent second-order feedforward operational amplifier excluding the common parts. Therefore, it is easy to obtain the three zeros of the corresponding transfer function based on this structural design. Furthermore, this fourth-order feedforward compensated operational amplifier only has feedforward branches and no feedback branches, so the extreme zeros of its transfer function are... The poles are determined by the individual nodes. The corresponding poles can be obtained based on the parasitic capacitance and output impedance of each node. Based on the obtained DC gain, three zeros, and four poles, the transfer function of the fourth-order feedforward compensated operational amplifier can be derived. Based on the circuit structure design of this fourth-order feedforward compensated operational amplifier, its transfer function can be easily obtained. Furthermore, based on the obtained transfer function and the gain requirements of the continuous-time bandpass sigma-delta modulator, the transconductance constraint relationship between the transconductance amplification units in the fourth-order feedforward compensated operational amplifier can be derived in reverse. By selecting and designing each transconductance amplification unit according to the corresponding transconductance constraint relationship, the resulting fourth-order feedforward compensated operational amplifier can effectively meet the usage requirements of the continuous-time bandpass sigma-delta modulator. Attached Figure Description

[0030] Figure 1 The diagram shows the steps of the design method for a fourth-order feedforward compensated operational amplifier in this invention.

[0031] Figure 2 The diagram shown is a schematic of the structure of the fourth-order feedforward compensated operational amplifier in this invention.

[0032] Figure 3 The first transconductance amplification unit g shown in an embodiment of the present invention is shown as... m1 The circuit structure diagram.

[0033] Figure 4 The second transconductance amplification unit g shown in an embodiment of the present invention m2 The circuit structure diagram.

[0034] Figure 5 The third transconductance amplification unit g shown in an embodiment of the present invention is shown as... m3 The circuit structure diagram.

[0035] Figure 6 The fourth transconductance amplification unit g shown in an embodiment of the present invention is shown as... m4 The circuit structure diagram.

[0036] Figure 7 Displayed as the fifth transconductance amplification unit g in an embodiment of the present invention m5 The circuit structure diagram.

[0037] Figure 8 The sixth transconductance amplification unit g shown in an embodiment of the present invention m6 The circuit structure diagram.

[0038] Figure 9 The seventh transconductance amplification unit g shown in an embodiment of the present invention m7 The circuit structure diagram.

[0039] Figure 10 The diagram shown is an equivalent structural schematic of the fourth-order feedforward compensated operational amplifier in this invention.

[0040] Figure 11 The diagram shows the equivalent structure of a second-order feedforward compensated operational amplifier.

[0041] Figure 12 The diagram shows the amplitude frequency response curve and phase frequency response curve of a fourth-order feedforward compensated operational amplifier in one embodiment of the present invention. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0044] As described in the background section, the inventors discovered that for continuous-time bandpass sigma-delta modulators used in intermediate frequencies of hundreds of MHz, traditional second-order Miller-compensated operational amplifiers (PCA) are insufficient to meet their gain performance requirements. Only higher-order multiplexed feedforward compensated PCA can be used. However, as the order and structural complexity of the higher-order multiplexed feedforward compensated PCA increase, it becomes difficult for designers to create PCA that meets specific requirements. Existing technologies either rely on tedious mathematical calculations to derive the system transfer function of the higher-order multiplexed feedforward PCA, and the complexity of this calculation increases with the amplifier order or the complexity of the amplifier system structure; or they rely on code-based algorithms that completely abandon physical structures, relying on the performance requirements of the feedforward PCA to be designed and the physical constraints of the device fabrication process, and are based on the operational amplifier design g... m / I D The method involves writing code to design the amplifier, but the code writing algorithm does not analyze and understand the amplifier circuit itself, thus losing a deep understanding of the high-order multiplexed feedforward operational amplifier circuit level.

[0045] Based on this, such as Figures 1-2 As shown, this invention proposes a design method for a fourth-order feedforward compensated operational amplifier, which includes the following steps:

[0046] S1, providing the first transconductance amplification unit g m1 Second transconductance amplification unit g m2 Third transconductance amplification unit g m3 Fourth transconductance amplification unit g m4 Fifth transconductance amplification unit g m5 The sixth transconductance amplification unit g m6 and the seventh transconductance amplification unit g m7 ;

[0047] S2, using the first transconductance amplification unit g m1 Second transconductance amplification unit g m2 Third transconductance amplification unit g m3 and the fourth transconductance amplification unit g m4 This forms a fourth-order operational amplifier path;

[0048] S3, using the first transconductance amplification unit g m1 Fifth transconductance amplification unit g m5 and the fourth transconductance amplification unit g m4 A third-order operational amplifier path is constructed, and feedforward compensation is performed on the fourth-order operational amplifier path through the third-order operational amplifier path.

[0049] S4, using the first transconductance amplification unit g m1 and the sixth transconductance amplification unit gm6 A second-order operational amplifier path is constructed, and feedforward compensation is performed on the third-order operational amplifier path through the second-order operational amplifier path.

[0050] S5, utilizing the seventh transconductance amplification unit g m7 A first-order operational amplifier path is constructed, and the second-order operational amplifier path is fed forward to compensate through the first-order operational amplifier path.

[0051] Optionally, in step S1, a first transconductance amplifier unit g is formed based on the differential amplification technique using a common source and common gate. m1 The second transconductance amplifier unit g is formed based on differential amplification technology. m2 The third transconductance amplifier unit g is formed based on the differential amplification technique with common-mode feedback. m3 and the fifth transconductance amplification unit g m5 The fourth transconductance amplifier unit g is formed based on the complementary differential amplification technique with common-mode feedback. m4 and the sixth transconductance amplification unit g m6 The seventh transconductance amplifier unit g is formed based on complementary differential amplification technology. m7 .

[0052] In detail, by performing steps S2 to S5, the following results are obtained: Figure 2 The fourth-order feedforward compensated operational amplifier shown includes a first transconductance amplification unit g. m1 Second transconductance amplification unit g m2 Third transconductance amplification unit g m3 Fourth transconductance amplification unit g m4 Fifth transconductance amplification unit g m5 The sixth transconductance amplification unit g m6 and the seventh transconductance amplification unit g m7 First transconductance amplification unit g m1 Second transconductance amplification unit g m2 Third transconductance amplification unit g m3 and the fourth transconductance amplification unit g m4 Cascaded sequentially to form a fourth-order operational amplifier path; the fifth transconductance amplification unit g m5 The input terminal is connected to the first transconductance amplifier unit g. m1 The output terminal, the fifth transconductance amplifier unit g m5 The output terminal is connected to the fourth transconductance amplifier unit g. m4 The input terminal, the first transconductance amplifier unit g m1 Fifth transconductance amplification unit g m5 and the fourth transconductance amplification unit g m4 This constitutes a third-order operational amplifier path; the sixth transconductance amplification unit g m6 The input terminal is connected to the first transconductance amplifier unit g. m1 The output terminal of the sixth transconductance amplifier single g m6The output terminal of the element is connected to the fourth transconductance amplifier unit g. m4 The output terminal of the first transconductance amplifier unit g m1 and the sixth transconductance amplification unit g m6 This constitutes the second-order operational amplifier path; the seventh transconductance amplification unit g m7 The input terminal is connected to the first transconductance amplifier unit g. m1 The input terminal, the seventh transconductance amplifier unit g m7 The output terminal is connected to the fourth transconductance amplifier unit g. m4 The output terminal, the seventh transconductance amplifier unit g m7 This constitutes a first-order operational amplifier path; wherein, the first-order operational amplifier path performs feedforward compensation on the second-order operational amplifier path, the second-order operational amplifier path performs feedforward compensation on the third-order operational amplifier path, and the third-order operational amplifier path performs feedforward compensation on the fourth-order operational amplifier path, that is, in two adjacent operational amplifier paths, the lower first-order path successively performs feedforward compensation on the higher first-order path.

[0053] The fourth-order feedforward compensated operational amplifier of this invention is designed based on a 65nm CMOS process.

[0054] In an optional embodiment of the present invention, such as Figure 3 As shown, the first transconductance amplification unit g m1 The differential amplifier structure using a common source and common gate is adopted, and the first transconductance amplifier unit g m1 This includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. The source of the first PMOS transistor P1 is connected to the operating voltage VDD, and the gate of the first PMOS transistor P1 is connected to the drain of the first PMOS transistor P1. The source of the second PMOS transistor P2 is connected to the operating voltage VDD. The gate of transistor P2 is connected to the drain of the third PMOS transistor P3. The drain of the second PMOS transistor P2 is connected to the gate of the third PMOS transistor P3. The drain of the second PMOS transistor P2 is also connected to the drain of the first PMOS transistor P1. The source of the third PMOS transistor P3 is connected to the operating voltage VDD. The drain of the third PMOS transistor P3 is also connected to the drain of the fourth PMOS transistor P4. The source of the fourth PMOS transistor P4 is connected to the operating voltage VDD. The gate of the fourth PMOS transistor P4 is connected to the drain of the fourth PMOS transistor P4. The drain of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1, and the drain of the first NMOS transistor N1 serves as the negative terminal of the differential output V. A- The gate of the first NMOS transistor N1 is connected to the first bias voltage V. B1 The source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, and the gate of the second NMOS transistor N2 serves as the positive terminal of the differential input V. IN+The source of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3, and the gate of the third NMOS transistor N3 is connected to the second bias voltage V. B2 The source of the third NMOS transistor N3 is grounded, and the drain of the third NMOS transistor N3 is also connected to the source of the fourth NMOS transistor N4. The gate of the fourth NMOS transistor N4 serves as the negative terminal of the differential input V. IN- The drain of the fourth NMOS transistor N4 is connected to the source of the fifth NMOS transistor N5, and the gate of the fifth NMOS transistor N5 is connected to the first bias voltage V. B1 The drain of the fifth NMOS transistor N5 is connected to the drain of the third PMOS transistor P3, and the drain of the fifth NMOS transistor N5 serves as the positive terminal V of the differential output. A+ .

[0055] In an optional embodiment of the present invention, such as Figure 4 As shown, the second transconductance amplification unit g m2 A differential amplifier structure is adopted, and the second transconductance amplifier unit g m2 This includes PMOS transistors P5, P6, P7, P8, N6, N7, and N8. The source of PMOS transistor P5 is connected to the operating voltage VDD, and its gate is connected to its drain. The source of PMOS transistor P6 is connected to VDD, its gate is connected to the drain of P7, and its drain is also connected to the gate of P7. The drain of P6 is also connected to the drain of P5. The source of P7 is connected to VDD, and its drain is also connected to the gate of P7. The drain of transistor P8 is connected to the source of the eighth PMOS transistor P8, and the gate of the eighth PMOS transistor P8 is connected to the drain of the eighth PMOS transistor P8. The drain of the sixth NMOS transistor N6 is connected to the drain of the fifth PMOS transistor P5, and the drain of the sixth NMOS transistor P6 serves as the negative terminal of the differential output V. B- The gate of the sixth NMOS transistor N6 serves as the positive terminal of the differential input V. A+ The source of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7, and the gate of the seventh NMOS transistor N7 is connected to the third bias voltage V. B3 The source of the seventh NMOS transistor N7 is grounded, and the drain of the seventh NMOS transistor N7 is also connected to the source of the eighth NMOS transistor N8. The gate of the eighth NMOS transistor N8 serves as the negative terminal of the differential input V. A- The drain of the eighth NMOS transistor N8 is connected to the drain of the seventh PMOS transistor P7, and the drain of the eighth NMOS transistor N8 serves as the positive terminal V of the differential output. B+ .

[0056] In an optional embodiment of the present invention, such as Figure 5 As shown, the third transconductance amplification unit g m3 A differential amplifier structure with common-mode feedback is adopted, and the third transconductance amplifier unit g m3 This includes a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a ninth NMOS transistor N9, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11, a first operational amplifier A1, a first resistor R1, and a second resistor R2. The source of the ninth PMOS transistor P9 is connected to the operating voltage VDD, and the gate of the ninth PMOS transistor P9 serves as the positive terminal of the first differential input VDD. B+ The drain of the ninth PMOS transistor P9 is connected to the drain of the tenth PMOS transistor P10. The source of the tenth PMOS transistor P10 is connected to the operating voltage VDD. The gate of the tenth PMOS transistor P10 is connected to the gate of the eleventh PMOS transistor P11. The source of the eleventh PMOS transistor P11 is connected to the operating voltage VDD. The drain of the eleventh PMOS transistor P11 is connected to the drain of the twelfth PMOS transistor P12. The source of the twelfth PMOS transistor P12 is connected to the operating voltage VDD. The gate of the twelfth PMOS transistor P12 serves as the negative terminal of the first differential input V. B- The drain of the ninth NMOS transistor N9 is connected to the drain of the ninth PMOS transistor P9, and the drain of the ninth NMOS transistor N9 serves as the negative terminal of the differential output V. C- The gate of the ninth NMOS transistor N9 serves as the positive terminal V of the second differential input. A+ The source of the ninth NMOS transistor N9 is connected to the drain of the tenth NMOS transistor N10, and the gate of the tenth NMOS transistor N10 is connected to the fourth bias voltage V. B4 The source of the tenth NMOS transistor N10 is grounded, and the drain of the tenth NMOS transistor N10 is also connected to the source of the eleventh NMOS transistor N11. The gate of the eleventh NMOS transistor N11 serves as the negative terminal of the second differential input V. A- The drain of the eleventh NMOS transistor N11 is connected to the drain of the eleventh PMOS transistor P11, and the drain of the eleventh NMOS transistor N11 serves as the positive terminal V of the differential output. C+ The non-inverting input of the first operational amplifier A1 is connected to the drain of the ninth NMOS transistor N9 via a series resistor R1. The non-inverting input of the first operational amplifier A1 is also connected to the drain of the eleventh NMOS transistor N11 via a series resistor R2. The inverting input of the first operational amplifier A1 is connected to the first reference signal V. ref1 The output of the first operational amplifier A1 is connected to the gate of the tenth PMOS transistor P10.

[0057] In an optional embodiment of the present invention, such as Figure 6 As shown, the fourth transconductance amplification unit gm4 A complementary differential amplifier structure with common-mode feedback is adopted, and the fourth transconductance amplifier unit g m4 This includes the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, the fifteenth PMOS transistor P15, the sixteenth PMOS transistor P16, the seventeenth PMOS transistor P17, the eighteenth PMOS transistor P18, the twelfth NMOS transistor N12, the thirteenth NMOS transistor N13, the fourteenth NMOS transistor N14, the second operational amplifier A2, the third resistor R3, and the fourth resistor R4. The source of the thirteenth PMOS transistor P13 is connected to the operating voltage VDD, and the gate of the thirteenth PMOS transistor P13 serves as the positive terminal of the first differential input VDD. C+ The drain of the thirteenth PMOS transistor P13 is connected to the drain of the fourteenth PMOS transistor P14. The source of the fourteenth PMOS transistor P14 is connected to the operating voltage VDD. The gate of the fourteenth PMOS transistor P14 is connected to the gate of the fifteenth PMOS transistor P15. The source of the fifteenth PMOS transistor P15 is connected to the operating voltage VDD. The drain of the fifteenth PMOS transistor P15 is connected to the drain of the sixteenth PMOS transistor P16. The source of the sixteenth PMOS transistor P16 is connected to the operating voltage VDD. The gate of the sixteenth PMOS transistor P16 serves as the negative terminal of the first differential input V. C- The source of the seventeenth PMOS transistor P17 is connected to the operating voltage VDD, and the drain of the seventeenth PMOS transistor P17 is connected to the drain of the fourteenth PMOS transistor P14. The source of the eighteenth PMOS transistor P18 is connected to the operating voltage VDD, and the drain of the eighteenth PMOS transistor P18 is connected to the drain of the fifteenth PMOS transistor P15. The drain of the twelfth NMOS transistor N12 is connected to the drain of the fourteenth PMOS transistor P14, and the drain of the twelfth NMOS transistor N12 serves as the negative terminal of the differential output VDD. OUT- The gate of the twelfth NMOS transistor N12 is connected to the gate of the seventeenth PMOS transistor P12 and serves as the positive terminal V of the second differential input. A+ The source of the twelfth NMOS transistor N12 is connected to the drain of the thirteenth NMOS transistor N13, and the gate of the thirteenth NMOS transistor N13 is connected to the fifth bias voltage V. B5 The source of the thirteenth NMOS transistor N13 is grounded, and the drain of the thirteenth NMOS transistor N13 is also connected to the source of the fourteenth NMOS transistor N14. The gate of the fourteenth NMOS transistor N14 is connected to the gate of the eighteenth PMOS transistor P18 and serves as the negative terminal of the second differential input V. A+ The drain of the fourteenth NMOS transistor N14 is connected to the drain of the fifteenth PMOS transistor P15, and the drain of the fourteenth NMOS transistor N14 serves as the positive terminal V of the differential output. OUT+The non-inverting input of the second operational amplifier A2 is connected to the drain of the twelfth NMOS transistor N12 via a third resistor R3 in series. The non-inverting input of the second operational amplifier A2 is also connected to the drain of the fourteenth NMOS transistor N14 via a fourth resistor R4 in series. The inverting input of the second operational amplifier A2 is connected to the second reference signal V. ref2 The output of the second operational amplifier A2 is connected to the gate of the fourteenth PMOS transistor P14.

[0058] In an optional embodiment of the present invention, such as Figure 7 As shown, the fifth transconductance amplification unit g m5 Employing a differential amplifier structure with common-mode feedback, the fifth transconductance amplifier unit g m5 This includes the nineteenth PMOS transistor P19, the twentieth PMOS transistor P20, the twenty-first PMOS transistor P21, the twenty-second PMOS transistor P22, the fifteenth NMOS transistor N15, the sixteenth NMOS transistor N16, the seventeenth NMOS transistor N17, the third operational amplifier A3, the fifth resistor R5, and the sixth resistor R6. The source of the nineteenth PMOS transistor P19 is connected to the operating voltage VDD, and the gate of the nineteenth PMOS transistor P19 serves as the positive terminal of the first differential input VDD. B+ The drain of the nineteenth PMOS transistor P19 is connected to the drain of the twentieth PMOS transistor P20. The source of the twentieth PMOS transistor P20 is connected to the operating voltage VDD. The gate of the twentieth PMOS transistor P20 is connected to the gate of the twenty-first PMOS transistor P21. The source of the twenty-first PMOS transistor P21 is connected to the operating voltage VDD. The drain of the twenty-first PMOS transistor P21 is connected to the drain of the twenty-second PMOS transistor P22. The source of the twenty-second PMOS transistor P22 is connected to the operating voltage VDD. The gate of the twenty-second PMOS transistor P20 serves as the negative terminal of the first differential input V. B- The drain of the fifteenth NMOS transistor N15 is connected to the drain of the nineteenth PMOS transistor P19, and the drain of the fifteenth NMOS transistor N15 serves as the negative terminal V of the differential output. C- The gate of the fifteenth NMOS transistor N15 serves as the positive terminal of the second differential input V. A+ The source of the fifteenth NMOS transistor N15 is connected to the drain of the sixteenth NMOS transistor N16, and the gate of the sixteenth NMOS transistor N16 is connected to the sixth bias voltage V. B6 The source of the sixteenth NMOS transistor N16 is grounded, and the drain of the sixteenth NMOS transistor N16 is also connected to the source of the seventeenth NMOS transistor N17. The gate of the seventeenth NMOS transistor N17 serves as the negative terminal of the second differential input V. A- The drain of the seventeenth NMOS transistor N17 is connected to the drain of the twenty-first PMOS transistor P21, and the drain of the seventeenth NMOS transistor N17 serves as the positive terminal V of the differential output. C-The non-inverting input of the third operational amplifier A3 is connected to the drain of the fifteenth NMOS transistor N15 via a series fifth resistor R5. The non-inverting input of the third operational amplifier A3 is also connected to the drain of the seventeenth NMOS transistor N17 via a series sixth resistor R6. The inverting input of the third operational amplifier A3 is connected to the third reference signal V. ref3 The output of the third operational amplifier A3 is connected to the gate of the twentieth PMOS transistor P20.

[0059] In an optional embodiment of the present invention, such as Figure 8 As shown, the sixth transconductance amplification unit g m6 Employing a complementary differential amplifier structure with common-mode feedback, the sixth transconductance amplifier unit g m6 This includes the 23rd PMOS transistor P23, the 24th PMOS transistor P24, the 25th PMOS transistor P25, the 26th PMOS transistor P26, the 27th PMOS transistor P27, the 28th PMOS transistor P28, the 18th NMOS transistor N18, the 19th NMOS transistor N19, the 20th NMOS transistor N20, the fourth operational amplifier A4, the seventh resistor R7, and the eighth resistor R8. The source of the 23rd PMOS transistor P23 is connected to the operating voltage VDD, and the gate of the 23rd PMOS transistor P23 serves as the positive terminal of the first differential input VDD. C+ The drain of the 23rd PMOS transistor P23 is connected to the drain of the 24th PMOS transistor P24. The source of the 24th PMOS transistor P24 is connected to the operating voltage VDD. The gate of the 24th PMOS transistor P24 is connected to the gate of the 25th PMOS transistor P25. The source of the 25th PMOS transistor P25 is connected to the operating voltage VDD. The drain of the 25th PMOS transistor P25 is connected to the drain of the 26th PMOS transistor P26. The source of the 26th PMOS transistor P26 is connected to the operating voltage VDD. The gate of the 26th PMOS transistor P26 serves as the negative terminal of the first differential input V. C- The source of the 27th PMOS transistor P27 is connected to the operating voltage VDD, and the drain of the 27th PMOS transistor P27 is connected to the drain of the 24th PMOS transistor P24. The source of the 28th PMOS transistor P28 is connected to the operating voltage VDD, and the drain of the 28th PMOS transistor is connected to the drain of the 25th PMOS transistor. The drain of the 18th NMOS transistor is connected to the drain of the 24th PMOS transistor, and the drain of the 18th NMOS transistor serves as the negative terminal of the differential output. The gate of the 18th NMOS transistor N18 is connected to the gate of the 27th PMOS transistor P27 and serves as the positive terminal of the second differential input VDD. A+ The source of the eighteenth NMOS transistor N18 is connected to the drain of the nineteenth NMOS transistor N19, and the gate of the nineteenth NMOS transistor N19 is connected to the seventh bias voltage V. B7The source of the nineteenth NMOS transistor N19 is grounded, and its drain is also connected to the source of the twentieth NMOS transistor N20. The gate of the twentieth NMOS transistor N20 is connected to the gate of the twenty-eighth PMOS transistor P28 and serves as the negative terminal V of the second differential input. A- The drain of the twentieth NMOS transistor N20 is connected to the drain of the twenty-fifth PMOS transistor P25, and the drain of the twentieth NMOS transistor N20 serves as the positive terminal V of the differential output. OUT+ The non-inverting input of the fourth operational amplifier A4 is connected to the drain of the eighteenth NMOS transistor N18 via the seventh resistor R7 in series. The non-inverting input of the fourth operational amplifier A4 is also connected to the drain of the twentieth NMOS transistor N20 via the eighth resistor R8 in series. The inverting input of the fourth operational amplifier A4 is connected to the fourth reference signal V. ref4 The output of the fourth operational amplifier A4 is connected to the gate of the twenty-fourth PMOS transistor P24.

[0060] In an optional embodiment of the present invention, such as Figure 9 As shown, the seventh transconductance amplification unit g m7 Employing a complementary differential amplification structure, the seventh transconductance amplification unit g m7Including the 29th PMOS transistor P29, the 30th PMOS transistor P30, and the 31st PMOS transistor... PMOS transistors P31, P32 (32nd), P33 (33rd), P34 (34th), NMOS transistors N21 (21st), N22 (22nd), and N23 (23rd), along with capacitors C1 and C2, are connected to the following: the source of PMOS transistor P29 is connected to the operating voltage VDD; the gate of PMOS transistor P29 is connected to its drain; the drain of PMOS transistor P29 is connected to the drain of PMOS transistor P30; the source of PMOS transistor P30 is connected to the operating voltage VDD; the gate of PMOS transistor P30 is connected to the drain of PMOS transistor P31 (31st); the source of PMOS transistor P31 is connected to the operating voltage VDD; the gate of PMOS transistor P31 is connected to the drain of PMOS transistor P30 (30th); and the drain of PMOS transistor P31 is connected to the drain of PMOS transistor P32 (32nd). The drain of transistor P32 is connected to the operating voltage VDD. The gate of transistor P32 is connected to the drain of transistor P32. The source of transistor P33 is connected to the operating voltage VDD. The drain of transistor P33 is connected to the drain of transistor P30. The source of transistor P34 is connected to the operating voltage VDD. The drain of transistor P34 is connected to the drain of transistor P31. The drain of transistor N21 is connected to the drain of transistor P30. The drain of transistor N21 is connected to the drain of transistor P30. The drain of transistor N21 is connected to the drain of transistor P30. The drain of transistor N21 is connected in series with capacitor C1 and serves as the negative terminal of the differential output V. OUT- The gate of the twenty-first NMOS transistor N21 is connected to the gate of the thirty-third PMOS transistor P33 and serves as the positive terminal V of the differential input. IN+ The source of the twenty-first NMOS transistor N21 is connected to the drain of the twenty-second NMOS transistor N22, and the gate of the twenty-second NMOS transistor N22 is connected to the eighth bias voltage V. B8 The source of the twenty-second NMOS transistor N22 is grounded, and the drain of the twenty-second NMOS transistor N22 is also connected to the source of the twenty-third NMOS transistor N23. The gate of the twenty-third NMOS transistor N23 is connected to the gate of the thirty-fourth PMOS transistor P34 and serves as the negative terminal of the differential input V. IN- The drain of the 23rd NMOS transistor N23 is connected to the drain of the 31st PMOS transistor P33, and the drain of the 23rd NMOS transistor N23, after being connected in series with the second capacitor C2, serves as the positive terminal V of the differential output. OUT+ .

[0061] In detail, after performing steps S1 to S5, the following results are obtained: Figure 2 Or such as Figure 10The fourth-order feedforward compensated operational amplifier shown has a first transconductance amplification unit g. m1 Second transconductance amplification unit g m2 Third transconductance amplification unit g m3 and the fourth transconductance amplification unit g m4 This forms the fourth-order operational amplifier path, which is the main amplification path; the remaining fifth transconductance amplification unit g m5 The sixth transconductance amplification unit g m6 and the seventh transconductance amplification unit g m7 It consists of three feedforward stages, with the first transconductance amplifier unit g m1 Fifth transconductance amplification unit g m5 and the fourth transconductance amplification unit g m4 This forms the path of a third-order operational amplifier, with the first transconductance amplification unit g. m1 and the sixth transconductance amplification unit g m6 This forms the path of a second-order operational amplifier, the seventh transconductance amplification unit g. m7 This constitutes a first-order operational amplifier path; and the first-order operational amplifier path performs feedforward compensation on the second-order operational amplifier path, the second-order operational amplifier path performs feedforward compensation on the third-order operational amplifier path, and the third-order operational amplifier path performs feedforward compensation on the fourth-order operational amplifier path.

[0062] More in detail, such as Figure 10 As shown, due to manufacturing limitations, parasitic capacitances inevitably exist at the connection nodes between the transconductance amplification units of each stage in a fourth-order feedforward compensated operational amplifier. Furthermore, due to the multi-stage cascading, the output impedance of the corresponding nodes also plays a significant role. Since the main parameters determining the transfer function of an operational amplifier are gain, poles, and zeros, solving for these three parameters sequentially yields the transfer function of a high-order multi-channel feedforward compensated operational amplifier.

[0063] First, from Figure 2 and Figure 10 It can be seen that the highest-order path of this fourth-order feedforward compensated operational amplifier is the first transconductance amplification unit g. m1 Second transconductance amplification unit g m2 Third transconductance amplification unit g m3 and the fourth transconductance amplification unit g m4 The fourth-order operational amplifier path is constructed such that the gain of the operational amplifier increases with the cascade order. Therefore, the DC gain of this fourth-order feedforward compensated operational amplifier can be approximately equal to the DC gain of its fourth-order operational amplifier path, i.e.:

[0064] A0≈A1A2A3A4 (1)

[0065] Where A0 is the gain of this fourth-order feedforward compensated operational amplifier, and A1-A4 are the gains of the first transconductance amplification unit g. m1 Second transconductance amplification unit g m2Third transconductance amplification unit g m3 and the fourth transconductance amplification unit g m4 The gain.

[0066] Secondly, since this fourth-order feedforward operational amplifier only has feedforward branches and no feedback branches, the poles of its transfer function are determined by its individual nodes, that is:

[0067]

[0068] Among them, capacitors C1-C3 are the parasitic capacitances of nodes A, B, and C, respectively; capacitor C4 is the sum of the parasitic capacitance of the output node and the load capacitance of the operational amplifier; resistors r1-r3 are the output impedances of nodes A, B, and C, respectively; and resistor r4 is the parallel impedance of the output impedance and the load impedance of the output node.

[0069] Finally, for a very simple second-order feedforward compensated operational amplifier, such as Figure 11 As shown, its main route is the transconductance amplification unit g. ma and transconductance amplification unit g mb Composition, the feedforward branch is a transconductance amplifier unit g mc Composition, capacitor C a -C b These are the parasitic capacitance and resistance r of the node, respectively. a -r b Let be the output impedances of the nodes. The transfer function of this feedforward operational amplifier system has a zero and can be expressed as:

[0070]

[0071] Where, ω Z For the frequency zero point, G ma ~G mc These are transconductance amplification units g ma ~g mc The transconductance value.

[0072] exist Figure 2 or Figure 10 In the fourth-order feedforward compensated operational amplifier shown, the fourth-order op-amp path is compensated by the third-order op-amp path, the third-order op-amp path is compensated by the second-order op-amp path, and the second-order op-amp path is compensated by the first-order op-amp path. This three-stage compensation results in three zeros for the operational amplifier.

[0073] For the zeros generated by the fourth-order and third-order operational amplifier paths, due to the first transconductance amplification unit g m1 Second transconductance amplification unit g m2 Since these two paths share the same zeros, the zeros generated by these two paths are related to the second transconductance amplification unit g. m2Third transconductance amplification unit g m3 and the fifth transconductance amplification unit g m5 The generated zeros are equal, and using equation (3), we can obtain the zero as:

[0074]

[0075] Where, ω Z1 For the first frequency zero point, G m2 For the second transconductance amplification unit g m2 The transconductance value, G m3 For the third transconductance amplification unit g m3 The transconductance value, G m5 For the fifth transconductance amplification unit g m5 The transconductance value.

[0076] Similarly, for the zeros generated by the third-order and second-order op-amp paths, we can use ω... Z1 Solving using the same method, this zero point is related to the fourth transconductance amplification unit g. m4 Fifth transconductance amplification unit g m5 and the sixth transconductance amplification unit g m6 The generated zeros are equal and can be expressed as:

[0077]

[0078] Where, ω Z2 For the second frequency zero, G m4 For the fourth transconductance amplification unit g m4 The transconductance value, G m6 For the sixth transconductance amplification unit g m6 The transconductance value.

[0079] Similarly, for the zeros generated by the second-order and first-order op-amp paths, we can use ω... Z1 The same method is used to solve for this zero point, which is related to the first transconductance amplification unit g. m1 The sixth transconductance amplification unit g m6 and the seventh transconductance amplification unit g m7 The generated zeros are equal, and using equation (3), we can obtain the zero as:

[0080]

[0081] Where, ω Z3 For the third frequency zero point, G m1 For the first transconductance amplification unit g m1 The transconductance value, G m7 The seventh transconductance amplification unit g m7 The transconductance value.

[0082] It should be noted that the three zeros represented by equations (4)-(6) above ignore the zeros of the other two op-amp paths of the feedforward operational amplifier, and are not the true zeros of the transfer function of the entire fourth-order feedforward operational amplifier system. According to equations (1)-(2) and (4)-(6), the overall system transfer function of the fourth-order feedforward operational amplifier can be obtained as follows:

[0083]

[0084] Finally, by constraining the transconductance of each stage in this fourth-order feedforward compensated operational amplifier, it can be made to meet the gain and stability requirements. The constraint relationship used in an optional embodiment of the present invention is as follows:

[0085]

[0086] Therefore, this invention proposes a method to obtain the system transfer function of a high-order multi-channel feedforward operational amplifier system through an intuitive understanding of its structure, without requiring complex mathematical derivations and calculations. Furthermore, the fourth-order feedforward compensated operational amplifier of this invention is designed and implemented using a 65nm CMOS process. In addition, the circuit-level implementation of this fourth-order feedforward compensated operational amplifier utilizes amplifier performance optimization techniques such as current multiplexing, cascode structure, parallel structures of diode-connected transistor pairs and cross-coupled transistor pairs of the same size, and complementary differential Class AB operation.

[0087] In detail, several optimization techniques were employed to improve the performance of the operational amplifier. One of these was the first transconductance amplification unit g... m1 The first NMOS transistor N1 and the second NMOS transistor N2 employ a common-source, common-gate structure to achieve high gain and reduce noise contribution from subsequent stages. Secondly, the first transconductance amplifier unit g... m1 Second transconductance amplification unit g m2 and the seventh transconductance amplification unit g m7 The system employs PMOS transistors with diode connections of the same size and cross-coupled PMOS transistor pairs to simultaneously achieve high gain and a defined output DC voltage. However, to ensure sufficient output voltage swing for this operational amplifier, additional voltage is required in the third transconductance amplification unit g. m3 Fourth transconductance amplification unit g m4 Fifth transconductance amplification unit g m5 and the sixth transconductance amplification unit g m6 This technology was not used in China. Thirdly, as can be seen from equation (8), the transconductance of the feedforward branch of the operational amplifier is relatively large, therefore the third transconductance amplification unit g... m3 and the fourth transconductance amplification unit g m4 This can be implemented using a PMOS transistor differential pair, while the feedforward branch transconductance fifth transconductance amplifier unit g m5The sixth transconductance amplification unit g m6 and the seventh transconductance amplification unit g m7 A differential pair of NMOS transistors with higher carrier mobility must be used for implementation. Fourth, in the fourth transconductance amplification unit g... m4 The sixth transconductance amplification unit g m6 and the seventh transconductance amplification unit g m7 Current reuse technology is used to reduce power consumption. Fifth, because the output stage is in the fourth transconductance amplifier unit g m4 The sixth transconductance amplification unit g m6 and the seventh transconductance amplification unit g m7 The transconductance is the highest in the two stages, so these two operational amplifiers adopt a complementary differential Class AB operating mode.

[0088] In an optional embodiment of the present invention, a corresponding fourth-order feedforward compensated operational amplifier is designed and implemented based on a 65nm CMOS process, and its amplitude-frequency response and phase-frequency response curves when driving a 400fF capacitive load are as follows: Figure 12 As shown, Figure 12 As shown, the horizontal axis represents Frequency, with the corresponding unit being Hertz (Hz), and the vertical axes represent Magnitude and Phase, respectively, with the corresponding units being Decibels (dB) and Degrees (deg). Figure 12 It can be seen that its gains at DC, 250MHz, 340MHz, and 1GHz are 64.6dB, 44.0dB, 40.1dB, and 11.5dB, respectively, and its phase margin and power consumption are 72.1° and 12.96mW, respectively. Therefore, the fourth-order feedforward compensated operational amplifier proposed in this invention can meet the gain requirements of operational amplifiers in continuous-time bandpass sigma-delta modulators with intermediate frequencies up to 340MHz and sampling frequencies up to 2GHz.

[0089] In summary, in the fourth-order feedforward compensated operational amplifier and its design method provided by this invention, based on the structural design of "primarily using the fourth-order operational amplifier path," its highest-order path is the fourth-order operational amplifier path. The gain of the operational amplifier increases with the cascade order, and its DC gain can be approximately equal to the DC gain of its fourth-order operational amplifier path. Based on the structural design of "the lower-order operational amplifier path successively feedforwards the higher-order operational amplifier path," the zeros generated by adjacent operational amplifier paths are equal to the zeros of a second-order feedforward operational amplifier excluding the common parts. Therefore, it is easy to obtain the three zeros of the corresponding transfer function based on this structural design. Furthermore, this fourth-order feedforward compensated operational amplifier only has feedforward branches and no feedback branches, so the poles of its transfer function are determined by… The poles of the fourth-order feedforward compensated operational amplifier can be obtained by determining the parasitic capacitance and output impedance of each node. Based on the obtained DC gain, three zeros, and four poles, the transfer function of the fourth-order feedforward compensated operational amplifier can be obtained. Based on the circuit structure design of the fourth-order feedforward compensated operational amplifier, its transfer function can be easily derived. In addition, based on the obtained transfer function and the gain requirements of the continuous-time bandpass sigma-delta modulator, the transconductance constraint relationship between each transconductance amplification unit in the fourth-order feedforward compensated operational amplifier can be derived in reverse. By selecting and designing each transconductance amplification unit according to the corresponding transconductance constraint relationship, the resulting fourth-order feedforward compensated operational amplifier can effectively meet the usage requirements of the continuous-time bandpass sigma-delta modulator.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A fourth order feed forward compensated operational amplifier characterized by, The first trans-impedance amplification unit, the second trans-impedance amplification unit, the third trans-impedance amplification unit, the fourth trans-impedance amplification unit, the fifth trans-impedance amplification unit, the sixth trans-impedance amplification unit and the seventh trans-impedance amplification unit are connected in cascade. The first trans-impedance amplification unit, the second trans-impedance amplification unit, the third trans-impedance amplification unit and the fourth trans-impedance amplification unit are connected in cascade to form a four-stage operational amplifier path. The input end of the fifth trans-impedance amplification unit is connected to the output end of the first trans-impedance amplification unit, the output end of the fifth trans-impedance amplification unit is connected to the input end of the fourth trans-impedance amplification unit, and the first trans-impedance amplification unit, the fifth trans-impedance amplification unit and the fourth trans-impedance amplification unit form a three-stage operational amplifier path. The input end of the sixth trans-impedance amplification unit is connected to the output end of the first trans-impedance amplification unit, the output end of the sixth trans-impedance amplification unit is connected to the output end of the fourth trans-impedance amplification unit, and the first trans-impedance amplification unit and the sixth trans-impedance amplification unit form a two-stage operational amplifier path. The input end of the seventh trans-impedance amplification unit is connected to the input end of the first trans-impedance amplification unit, the output end of the seventh trans-impedance amplification unit is connected to the output end of the fourth trans-impedance amplification unit, and the seventh trans-impedance amplification unit forms a one-stage operational amplifier path. The one-stage operational amplifier path feeds forward compensates the two-stage operational amplifier path, the two-stage operational amplifier path feeds forward compensates the three-stage operational amplifier path, and the three-stage operational amplifier path feeds forward compensates the four-stage operational amplifier path. The first trans-impedance amplification unit is formed based on a common-source common-gate differential amplification technology, the second trans-impedance amplification unit is formed based on a differential amplification technology, the third trans-impedance amplification unit and the fifth trans-impedance amplification unit are formed based on a common-mode feedback differential amplification technology, the fourth trans-impedance amplification unit and the sixth trans-impedance amplification unit are formed based on a common-mode feedback complementary differential amplification technology, and the seventh trans-impedance amplification unit is formed based on a complementary differential amplification technology.

2. The fourth-order feedforward compensated operational amplifier of claim 1, wherein, The first trans-impedance amplification unit adopts a common-source common-gate differential amplification structure, and comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube. The source of the first PMOS tube is connected to a working voltage, the gate of the first PMOS tube is connected to the drain of the first PMOS tube, the source of the second PMOS tube is connected to the working voltage, the gate of the second PMOS tube is connected to the drain of the third PMOS tube, the drain of the second PMOS tube is connected to the gate of the third PMOS tube, the drain of the second PMOS tube is also connected to the drain of the first PMOS tube, the source of the third PMOS tube is connected to the working voltage, the drain of the third PMOS tube is also connected to the drain of the fourth PMOS tube, the source of the fourth PMOS tube is connected to the working voltage, the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube, the drain of the first NMOS tube is connected to the drain of the first PMOS tube, and the drain of the first NMOS tube serves as a differential output negative terminal, the gate of the first NMOS tube is connected to a first bias voltage, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube serves as a differential input positive terminal, the source of the second NMOS tube is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to a second bias voltage, the source of the third NMOS tube is connected to the ground, the drain of the third NMOS tube is also connected to the source of the fourth NMOS tube, the gate of the fourth NMOS tube serves as a differential input negative terminal, the drain of the fourth NMOS tube is connected to the source of the fifth NMOS tube, the gate of the fifth NMOS tube is connected to the first bias voltage, the drain of the fifth NMOS tube is connected to the drain of the third PMOS tube, and the drain of the fifth NMOS tube serves as a differential output positive terminal.

3. The fourth-order feedforward compensated operational amplifier of claim 2, wherein, The second trans-impedance amplification unit adopts a differential amplification structure, and comprises a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube. The source of the fifth PMOS tube is connected to the working voltage, and the gate of the fifth PMOS tube is connected to the drain of the fifth PMOS tube. The source of the sixth PMOS tube is connected to the working voltage, the gate of the sixth PMOS tube is connected to the drain of the seventh PMOS tube, the drain of the sixth PMOS tube is connected to the gate of the seventh PMOS tube, the drain of the sixth PMOS tube is also connected to the drain of the fifth PMOS tube, the source of the seventh PMOS tube is connected to the working voltage, the drain of the seventh PMOS tube is also connected to the drain of the eighth PMOS tube, the source of the eighth PMOS tube is connected to the working voltage, the gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube, the drain of the sixth NMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the sixth NMOS tube serves as a differential output negative terminal, the gate of the sixth NMOS tube serves as a differential input positive terminal, the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube, the gate of the seventh NMOS tube is connected to a third bias voltage, the source of the seventh NMOS tube is connected to the ground, the drain of the seventh NMOS tube is also connected to the source of the eighth NMOS tube, the gate of the eighth NMOS tube serves as a differential input negative terminal, the drain of the eighth NMOS tube is connected to the drain of the seventh PMOS tube, and the drain of the eighth NMOS tube serves as a differential output positive terminal.

4. The fourth-order feedforward compensated operational amplifier of claim 3, wherein, The third trans-impedance amplification unit adopts a differential amplification structure with common-mode feedback, and comprises a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a first operational amplifier, a first resistor and a second resistor, the source of the ninth PMOS tube is connected to the working voltage, the gate of the ninth PMOS tube is a first differential input positive terminal, the drain of the ninth PMOS tube is connected to the drain of the tenth PMOS tube, the source of the tenth PMOS tube is connected to the working voltage, the gate of the tenth PMOS tube is connected to the gate of the eleventh PMOS tube, the source of the eleventh PMOS tube is connected to the working voltage, the drain of the eleventh PMOS tube is connected to the drain of the twelfth PMOS tube, the source of the twelfth PMOS tube is connected to the working voltage, the gate of the twelfth PMOS tube is a first differential input negative terminal, the drain of the ninth NMOS tube is connected to the drain of the ninth PMOS tube, and the drain of the ninth NMOS tube is a differential output negative terminal, the gate of the ninth NMOS tube is a second differential input positive terminal, the source of the ninth NMOS tube is connected to the drain of the tenth NMOS tube, the gate of the tenth NMOS tube is connected to a fourth bias voltage, the source of the tenth NMOS tube is connected to the ground, the drain of the tenth NMOS tube is also connected to the source of the eleventh NMOS tube, the gate of the eleventh NMOS tube is a second differential input negative terminal, the drain of the eleventh NMOS tube is connected to the drain of the eleventh PMOS tube, and the drain of the eleventh NMOS tube is a differential output positive terminal, the non-inverting input terminal of the first operational amplifier is connected to the drain of the ninth NMOS tube through the first resistor in series, the non-inverting input terminal of the first operational amplifier is also connected to the drain of the eleventh NMOS tube through the second resistor in series, the inverting input terminal of the first operational amplifier is connected to a first reference signal, and the output terminal of the first operational amplifier is connected to the gate of the tenth PMOS tube.

5. The fourth-order feed-forward compensated operational amplifier of claim 4, wherein, The fourth trans-impedance amplification unit adopts a complementary differential amplification structure with common-mode feedback, and comprises a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a second operational amplifier, a third resistor and a fourth resistor, the source of the thirteenth PMOS tube is connected to the working voltage, the gate of the thirteenth PMOS tube is a first differential input positive terminal, the drain of the thirteenth PMOS tube is connected to the drain of the fourteenth PMOS tube, the source of the fourteenth PMOS tube is connected to the working voltage, the gate of the fourteenth PMOS tube is connected to the gate of the fifteenth PMOS tube, the source of the fifteenth PMOS tube is connected to the working voltage, the drain of the fifteenth PMOS tube is connected to the drain of the sixteenth PMOS tube, the source of the sixteenth PMOS tube is connected to the working voltage, the gate of the sixteenth PMOS tube is a first differential input negative terminal, the source of the seventeenth PMOS tube is connected to the working voltage, the drain of the seventeenth PMOS tube is connected to the drain of the fourteenth PMOS tube, the source of the eighteenth PMOS tube is connected to the working voltage, the drain of the eighteenth PMOS tube is connected to the drain of the fifteenth PMOS tube, the drain of the twelfth NMOS tube is connected to the drain of the fourteenth PMOS tube and is a differential output negative terminal, the gate of the twelfth NMOS tube is connected to the gate of the seventeenth PMOS tube and is a second differential input positive terminal, the source of the twelfth NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate of the thirteenth NMOS tube is connected to a fifth bias voltage, the source of the thirteenth NMOS tube is connected to the ground, the drain of the thirteenth NMOS tube is also connected to the source of the fourteenth NMOS tube, the gate of the fourteenth NMOS tube is connected to the gate of the eighteenth PMOS tube and is a second differential input negative terminal, the drain of the fourteenth NMOS tube is connected to the drain of the fifteenth PMOS tube and is a differential output positive terminal, the non-inverting input terminal of the second operational amplifier is connected to the drain of the twelfth NMOS tube through the third resistor in series, the non-inverting input terminal of the second operational amplifier is also connected to the drain of the fourteenth NMOS tube through the fourth resistor in series, the inverting input terminal of the second operational amplifier is connected to a second reference signal, and the output terminal of the second operational amplifier is connected to the gate of the fourteenth PMOS tube.

6. The fourth-order feedforward compensated operational amplifier of claim 5, wherein, The fifth trans-impedance amplification unit adopts a differential amplification structure with common-mode feedback, and comprises a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, a third operational amplifier, a fifth resistor and a sixth resistor. The source of the nineteenth PMOS tube is connected to the working voltage, the gate of the nineteenth PMOS tube serves as a first differential input positive terminal, and the drain of the nineteenth PMOS tube is connected to the drain of the twentieth PMOS tube. The source of the twentieth PMOS tube is connected to the working voltage, the gate of the twentieth PMOS tube is connected to the gate of the twenty-first PMOS tube, the source of the twenty-first PMOS tube is connected to the working voltage, the drain of the twenty-first PMOS tube is connected to the drain of the twenty-second PMOS tube, the source of the twenty-second PMOS tube is connected to the working voltage, and the gate of the twenty-second PMOS tube serves as a first differential input negative terminal. The drain of the fifteenth NMOS tube is connected to the drain of the nineteenth PMOS tube, and the drain of the fifteenth NMOS tube serves as a differential output negative terminal. The gate of the fifteenth NMOS tube serves as a second differential input positive terminal, the source of the fifteenth NMOS tube is connected to the drain of the sixteenth NMOS tube, the gate of the sixteenth NMOS tube is connected to a sixth bias voltage, the source of the sixteenth NMOS tube is connected to the ground, and the drain of the sixteenth NMOS tube is also connected to the source of the seventeenth NMOS tube. The gate of the seventeenth NMOS tube serves as a second differential input negative terminal, the drain of the seventeenth NMOS tube is connected to the drain of the twenty-first PMOS tube, and the drain of the seventeenth NMOS tube serves as a differential output positive terminal. The non-inverting input terminal of the third operational amplifier is connected to the drain of the fifteenth NMOS tube through the fifth resistor in series, the non-inverting input terminal of the third operational amplifier is also connected to the drain of the seventeenth NMOS tube through the sixth resistor in series, the inverting input terminal of the third operational amplifier is connected to a third reference signal, and the output terminal of the third operational amplifier is connected to the gate of the twentieth PMOS tube.

7. The fourth-order feedforward compensated operational amplifier of claim 6, wherein, The sixth trans-impedance amplification unit adopts a complementary differential amplification structure with common-mode feedback, and comprises a twenty-third PMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a fourth operational amplifier, a seventh resistor and an eighth resistor. The source of the twenty-third PMOS tube is connected to the working voltage, the gate of the twenty-third PMOS tube serves as a first differential input positive terminal, and the drain of the twenty-third PMOS tube is connected to the drain of the twenty-fourth PMOS tube. The source of the twenty-fourth PMOS tube is connected to the working voltage, the gate of the twenty-fourth PMOS tube is connected to the gate of the twenty-fifth PMOS tube, the source of the twenty-fifth PMOS tube is connected to the working voltage, the drain of the twenty-fifth PMOS tube is connected to the drain of the twenty-sixth PMOS tube, the source of the twenty-sixth PMOS tube is connected to the working voltage, the gate of the twenty-sixth PMOS tube serves as a first differential input negative terminal, the source of the twenty-seventh PMOS tube is connected to the working voltage, the drain of the twenty-seventh PMOS tube is connected to the drain of the twenty-fourth PMOS tube, the source of the twenty-eighth PMOS tube is connected to the working voltage, the drain of the twenty-eighth PMOS tube is connected to the drain of the twenty-fifth PMOS tube, the drain of the eighteenth NMOS tube is connected to the drain of the twenty-fourth PMOS tube and serves as a differential output negative terminal, the gate of the eighteenth NMOS tube is connected to the gate of the twenty-seventh PMOS tube and serves as a second differential input positive terminal, the source of the eighteenth NMOS tube is connected to the drain of the nineteenth NMOS tube, the gate of the nineteenth NMOS tube is connected to a seventh bias voltage, the source of the nineteenth NMOS tube is connected to the ground, the drain of the nineteenth NMOS tube is also connected to the source of the twentieth NMOS tube, the gate of the twentieth NMOS tube is connected to the gate of the twenty-eighth PMOS tube and serves as a second differential input negative terminal, the drain of the twentieth NMOS tube is connected to the drain of the twenty-fifth PMOS tube and serves as a differential output positive terminal, the non-inverting input terminal of the fourth operational amplifier is connected to the drain of the eighteenth NMOS tube through the seventh resistor in series, the non-inverting input terminal of the fourth operational amplifier is also connected to the drain of the twentieth NMOS tube through the eighth resistor in series, the inverting input terminal of the fourth operational amplifier is connected to a fourth reference signal, and the output terminal of the fourth operational amplifier is connected to the gate of the twenty-fourth PMOS tube.

8. The fourth-order feedforward compensated operational amplifier of claim 7, wherein, The seventh trans-impedance amplification unit adopts a complementary differential amplification structure, and comprises a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a first capacitor and a second capacitor, the source of the twenty-ninth PMOS tube is connected to the working voltage, the gate of the twenty-ninth PMOS tube is connected to the drain of the twenty-ninth PMOS tube, the drain of the twenty-ninth PMOS tube is connected to the drain of the thirtieth PMOS tube, the source of the thirtieth PMOS tube is connected to the working voltage, the gate of the thirtieth PMOS tube is connected to the drain of the thirty-first PMOS tube, the source of the thirty-first PMOS tube is connected to the working voltage, the gate of the thirty-first PMOS tube is connected to the drain of the thirtieth PMOS tube, the drain of the thirty-first PMOS tube is connected to the drain of the thirty-second PMOS tube, the source of the thirty-second PMOS tube is connected to the working voltage, the gate of the thirty-second PMOS tube is connected to the drain of the thirty-second PMOS tube, the source of the thirty-third PMOS tube is connected to the working voltage, the drain of the thirty-third PMOS tube is connected to the drain of the thirtieth PMOS tube, the source of the thirty-fourth PMOS tube is connected to the working voltage, the drain of the thirty-fourth PMOS tube is connected to the drain of the thirty-first PMOS tube, the drain of the twenty-first NMOS tube is connected to the drain of the thirtieth PMOS tube, and the drain of the twenty-first NMOS tube is connected to the first capacitor in series and serves as a differential output negative terminal, the gate of the twenty-first NMOS tube is connected to the gate of the thirty-third PMOS tube and serves as a differential input positive terminal, the source of the twenty-first NMOS tube is connected to the drain of the twenty-second NMOS tube, the gate of the twenty-second NMOS tube is connected to an eighth bias voltage, the source of the twenty-second NMOS tube is connected to the ground, the drain of the twenty-second NMOS tube is also connected to the source of the twenty-third NMOS tube, the gate of the twenty-third NMOS tube is connected to the gate of the thirty-fourth PMOS tube and serves as a differential input negative terminal, the drain of the twenty-third NMOS tube is connected to the drain of the thirty-first PMOS tube, and the drain of the twenty-third NMOS tube is connected to the second capacitor in series and serves as a differential output positive terminal.

9. The fourth-order feedforward compensated operational amplifier of any of claims 1-8, wherein, The fourth-order feed-forward compensation operational amplifier is designed based on a 65nm CMOS process.

10. A design method of a fourth order feed forward compensated operational amplifier characterized by, The method comprises the following steps: providing a first trans-impedance amplification unit, a second trans-impedance amplification unit, a third trans-impedance amplification unit, a fourth trans-impedance amplification unit, a fifth trans-impedance amplification unit, a sixth trans-impedance amplification unit and a seventh trans-impedance amplification unit; forming a fourth-order operational amplifier path by using the first trans-impedance amplification unit, the second trans-impedance amplification unit, the third trans-impedance amplification unit and the fourth trans-impedance amplification unit; The first trans-impedance amplification unit, the fifth trans-impedance amplification unit and the fourth trans-impedance amplification unit are used to form a third-order operational amplifier path, and the fourth-order operational amplifier path is fed forwardly compensated through the third-order operational amplifier path; The first trans-impedance amplification unit and the sixth trans-impedance amplification unit are used to form a second-order operational amplifier path, and the third-order operational amplifier path is fed forwardly compensated through the second-order operational amplifier path; The seventh trans-impedance amplification unit is used to form a first-order operational amplifier path, and the second-order operational amplifier path is fed forwardly compensated through the first-order operational amplifier path; The first trans-impedance amplification unit is formed based on a common-source common-gate differential amplification technology, the second trans-impedance amplification unit is formed based on a differential amplification technology, the third trans-impedance amplification unit and the fifth trans-impedance amplification unit are formed based on a common-mode feedback differential amplification technology, the fourth trans-impedance amplification unit and the sixth trans-impedance amplification unit are formed based on a common-mode feedback complementary differential amplification technology, and the seventh trans-impedance amplification unit is formed based on a complementary differential amplification technology.

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