Push-pull class-E amplifier

Abstract

The present invention relates to a push-pull class-E amplifier. In addition, the present invention relates to a device including such a push-pull amplifier. In the push-pull class-E amplifier of the present invention, a balun is implemented using a multilayer printed circuit board, wherein the balanced terminals and connection lines are implemented in an upper metal layer, while the unbalanced terminals and connection lines are implemented in at least two lower metal layers.

Description

Technical Field

[0001] The present invention relates to push - pull class - E amplifiers. Furthermore, the present invention relates to a device comprising such a push - pull solid - state amplifier, which is used for industrial, scientific, and medical applications such as RF heating, drying, and defrosting, as well as magnetic resonance imaging. Such a device can be incorporated, for example, in plasma - generating devices, laser systems, and particle accelerators. Background Art

[0002] A push - pull amplifier typically comprises a first amplification unit having a first input terminal and a first output terminal, and a second amplification unit having a second input terminal and a second output terminal. The first and second amplification units are driven with a 180 - degree phase shift relative to each other. For this purpose, a signal received at the input of the amplifier is split with a 180 - degree phase difference to the first input terminal and the second input terminal. Typically, the input of the amplifier is unbalanced, and a balun can be used to transform the unbalanced input signal into a balanced signal, which is fed to the first and second input terminals.

[0003] A class - E amplifier is an amplifier in which its transistor is used as a switch. Figure 1 The operating principle of a class - E amplifier is illustrated. In this figure, the drain of a field - effect transistor (FET) FET1 is connected to a radio - frequency (RF) choke Lch, through which a direct - current (DC) bias voltage Vdd is provided. Furthermore, the drain is connected to a parallel capacitor Cd and a load R L .

[0004] The gate of FET1 is driven such that FET1 is fully open (as shown in the lower - right figure) or fully closed (as shown in the lower - left figure). When closed, a current Ids flows through Lch and FET1. At this time, the voltage across Cd is preferably as low as possible. When FET1 is open, the stored magnetic energy is released from Lch through the current Ids flowing through Cd and R L When FET1 is closed again, the voltage across Cd is preferably very low, and this cycle can be repeated. When operated in this way, the time overlap between the current flowing through FET1 and the drain - source voltage greater than 0V can be limited, thereby reducing the power consumption inside FET1 and increasing the efficiency.

[0005] Push - pull class - E amplifiers are known in the art. An example thereof is shown in Figure 2 . In this figure, the amplifier comprises an input transformer T0, through which an unbalanced signal Vi received at the input is distributed as a balanced signal across the input terminals of a field - effect transistor FET1 and FET2, where the signal Vi is provided as the gate - source voltage V gs1 and V gs2Here, the source of transistor FET1 and the source of FET2 are connected at node A. The drains of transistor FET1 and FET2 are connected to capacitor Cd which are connected to each other at node B. Instead of grounding two capacitors Cd, a single capacitor arranged between the drains of FET1 and FET2 can also be used. In Figure 2 the drain-source voltages of FET1 and FET2 are respectively denoted as V ds1 and V ds2 .

[0006] The drains of each field-effect transistor FET1 and FET2 are connected to a part of the primary side of transformer T1. The secondary side of transformer T1 is connected to load R via a series resonance circuit of capacitor C and inductor L L . This latter resonance circuit is configured to resonate at a frequency within the operating frequency range of the amplifier. This circuit can be used to suppress higher harmonics.

[0007] Transistors FET1 and FET2 are fed using voltage source V1 through choke inductor RFC which is connected to a virtual ground point on the primary side of transformer T1. It should also be noted that nodes A and B also serve as virtual grounds and are connected to the physical ground at node C.

[0008] Figure 2 The amplifier of can be implemented on a printed circuit board including a dielectric layer. More specifically, a quarter-wavelength balun can be used to implement transformer T1. In this case, a first line segment having a first end connected to the output terminal of FET1, for example the drain, and a second line segment having a first end connected to the output terminal of FET2 can be used to form the primary side of transformer T1. Then, the second ends of the first line segment and the second line segment are connected to each other. The first line segment and the second line segment can form a loop and can be arranged on the first side of the dielectric layer of the printed circuit board. The first line segment and the second line segment can together with capacitor Cd form part of a class-E matching network.

[0009] The secondary side of transformer T1 can be formed using a third line segment which is arranged on the side of the dielectric layer opposite to the first side. The first end of the third line segment can be grounded and the second end of the third line segment can be directly connected to load R L , or connected to load R through an impedance matching and / or harmonic filtering stage L . The third line segment can form a second loop including m turns. In addition, the first line segment, the second line segment and the third line segment can be formed using coupled transmission lines.

[0010] In a quarter-wavelength balun, the length of the third line segment corresponds to a quarter-wavelength at a frequency within the operating frequency range of the amplifier. Additionally, the length of the first line segment and the length of the second line segment each correspond to one-eighth of the wavelength divided by m at a frequency within the operating frequency range of the amplifier.

[0011] When operating at a relatively low frequency (i.e., less than 200 MHz) with a high output power (i.e., greater than 500 W), the first and second line segments cannot be too narrow because the current that can flow through the first and second line segments is too high. Additionally, under these conditions, the output impedance of the transistor FET1 and FET2 will be relatively low. To provide an acceptable impedance match to the load R L , the third line segment preferably includes as many turns as possible. However, for most amplifiers, the space for these turns is limited, so only 2 or 3 turns can be used. SUMMARY OF THE INVENTION

[0012] An object of the present invention is to provide an amplifier of the above type in which, for a given physical size of the amplifier, more output power can be generated.

[0013] According to the present invention, this object is achieved by using an amplifier as defined in claim 1. The amplifier includes a printed circuit board, which includes a first dielectric layer and a second dielectric layer. The amplifier of the present invention differs from Figure 2 the amplifier shown when implemented using a quarter-wavelength balun in that: the third line segment is arranged between the first dielectric layer and the second dielectric layer. Additionally, the amplifier further includes a fourth line segment, which is arranged on the second dielectric layer on the side facing away from the first dielectric layer and has a first end and a second end. The fourth line segment forms a third loop including n turns. The first end of the fourth line segment is connected to the second end of the third line segment through a via hole extending through the second dielectric layer, and the second end of the fourth line segment is connected to the output end of the amplifier.

[0014] The third line segment and the fourth line segment are formed by using coupled transmission lines. It should be noted that due to the shielding of the third line segment, the fourth line segment has only a very weak coupling with the first line segment and the second line segment. For the first line segment, the second line segment, the third line segment, and the fourth line segment, microstrip line technology or stripline technology can be used.

[0015] According to the present invention, the combined length of the third line segment and the fourth line segment is equal to a quarter-wavelength at a frequency within the operating frequency range of the amplifier. The length of the first line segment and the length of the second line segment each correspond to one-eighth of the wavelength divided by (n + m) at a frequency within the operating frequency range of the amplifier.

[0016] The applicant has found that, despite the shielding through the third line segment, the addition of the fourth line segment provides significant advantages. More specifically, the addition of the fourth line segment enables the shortening of the lengths of the first and second line segments. This allows a higher capacitance value to be used for the capacitor Cd, resulting in a higher output power.

[0017] In one embodiment, at least m or n can be greater than 1. For example, both m and n can be equal to 2.

[0018] The first and second line segments can occupy a first annular surface area on the first dielectric layer. The third and fourth line segments can respectively occupy a second annular surface area and a third annular surface area, and when the second and third annular surface areas are projected onto the first surface area in a direction perpendicular to the printed circuit board, the second and third annular surface areas substantially fall within the first surface area. For example, the first and second line segments can form a circular ring having an inner radius and an outer radius relative to the center of the ring. Each of the third and fourth line segments can include one or more turns extending around a respective center, and the respective center is aligned with the center of the ring formed by the first and second line segments in a lateral direction. The one or more turns of the third and fourth line segments extend within the region defined by the inner and outer radii relative to the respective centers. The inner and / or outer perimeters of each of the first, second, and third annular regions can have a square shape, a rectangular shape, a circular shape, or an oval shape.

[0019] For example, a push - pull class - E amplifier can further include: a first ground patch, a first loop extending around the first ground patch; a second ground patch, a second loop extending around the second ground patch; and a third ground patch, a third loop extending around the third ground patch, where the surface areas of the first ground patch, the second ground patch, and the third ground patch are substantially the same, and the first ground patch, the second ground patch, and the third ground patch are electrically connected by using one or more vias extending through the first dielectric layer and / or the second dielectric layer. Generally, the first ground patch, the second ground patch, and the third ground patch are aligned in a lateral direction.

[0020] The push - pull class - E amplifier can further include a first ground surrounding area around the first loop, a second ground surrounding area around the second loop, and a third ground surrounding area around the third loop. The first ground surrounding area, the second ground surrounding area, and the third ground surrounding area are electrically connected to each other by using one or more vias extending through the first dielectric layer and / or the second dielectric layer.

[0021] The first end of the third line segment can be physically and electrically connected to the second ground surrounding area.

[0022] The push-pull class-E amplifier may further include: one or more electrically isolated thermal bridges, each thermal bridge connecting the first segment or the second segment to the first ground patch or the area around the first ground. These thermal bridges can be implemented, for example, using a suitable ceramic material such as aluminum nitride or beryllium oxide, and enable the first segment and the second segment carrying the maximum current to be sufficiently cooled.

[0023] One or more turns of the third segment may travel around the second ground patch in the same direction as the direction in which one or more turns of the fourth segment travel around the third ground patch.

[0024] The first amplification unit and the second amplification unit may each be included in a package that includes a pair of different and spaced-apart connection terminals, which are respectively connected to the first output terminal and the second output terminal inside the package. The package may be mounted on the first dielectric layer. The connection terminals may be implemented in the form of leads.

[0025] The package may include a first power transistor and a second power transistor, and each of the first power transistor and the second power transistor is a silicon-based laterally diffused metal oxide semiconductor (LDMOS) transistor, a vertical double-diffused metal oxide semiconductor (VDMOS) transistor, or a gallium nitride (GaN)-based field effect transistor (FET).

[0026] The first segment and the second segment may be capacitively coupled to ground at or near the point where the first segment and the second segment are connected. In this way, the point where the first segment and the second segment are connected can be radio frequency (RF) shorted to ground without introducing a DC path to ground.

[0027] Each of the first segment and the second segment may be connected to a respective bias network for supplying DC current to the first amplification unit and the second amplification unit respectively, where the bias network is part of a class-E matching network. Alternatively, a single bias network may be used to bias the first amplification unit and the second amplification unit simultaneously. Such a bias network may be configured to provide DC current at or near the point where the first segment and the second segment are connected, or at or near another virtual ground point (e.g., as Figure 2 indicated by nodes A or B) or near another virtual ground point.

[0028] The operating frequency range may be in the range of 1 MHz to 200 MHz. In addition, the power of the output signal may be in the range of 100 W to 10 kW.

[0029] According to a second aspect, the present invention relates to a balun, which is used to convert a balanced signal received at a first balanced terminal and a second balanced terminal into an unbalanced signal output at an unbalanced terminal. The balun includes a printed circuit board having a first dielectric layer and a second dielectric layer. The balun further includes: a first line segment having a first end and a second end, the first end of the first line segment being coupled to the first balanced terminal; and a second line segment having a first end and a second end, the first end of the second line segment being coupled to the second balanced terminal. The second end of the first line segment and the second end of the second line segment are connected to each other, and the first line segment and the second line segment are arranged on the first dielectric layer. In addition, the first line segment and the second line segment form a first loop.

[0030] The balun further includes a third line segment, which is arranged between the first dielectric layer and the second dielectric layer and has a first end and a second end, wherein the first end is grounded. The third line segment forms a second loop including m turns. In addition, the balun includes a fourth line segment, which is arranged on the second dielectric layer on a side opposite to the first dielectric layer and has a first end and a second end. The first end of the fourth line segment is connected to the second end of the third line segment through a via hole extending through the second dielectric layer, and the second end of the fourth line segment is connected to the unbalanced terminal. The fourth line segment forms a third loop including n turns.

[0031] The combined length of the third line segment and the fourth line segment corresponds to a quarter wavelength at a frequency within the operating frequency range of the balun. The length of the first line segment and the length of the second line segment each correspond to one-eighth of the wavelength divided by (n + m) at a frequency within the operating frequency range of the amplifier. In addition, the first line segment, the second line segment, and the third line segment are formed by using coupled transmission lines, and the third line segment and the fourth line segment are formed by using coupled transmission lines.

[0032] According to a third aspect, the present invention provides an electronic device, which includes the above push-pull class-E amplifier or balun. Description of the Drawings

[0033] Next, the present invention will be described in more detail by referring to the accompanying drawings, in which:

[0034] Figure 1 The operating principle of a known class-E amplifier is shown;

[0035] Figure 2 A known push-pull class-E amplifier is shown;

[0036] Figure 3 An embodiment of a push-pull class-E amplifier according to the present invention is shown;

[0037] Figure 4 shows the Figure 3 electrical equivalent circuit of the amplifier;

[0038] Figure 5 shows the Figure 3 second metal layer of the printed circuit board used in the amplifier; and

[0039] Figure 6 shows the Figure 3 third metal layer of the printed circuit board used in the amplifier. DETAILED DESCRIPTION

[0040] Figure 3 shows an embodiment of a push - pull class - E amplifier according to the present invention. The electrical equivalent of the amplifier is shown in Figure 4 .

[0041] In Figure 3 , a package 100 is shown, in which two laterally diffused metal - oxide - semiconductor (LDMOS) power transistors FET1 and FET2 are arranged, but gallium nitride - based field - effect transistors (GaN FETs), vertical double - diffused metal - oxide - semiconductor (VDMOS) transistors, or combinations thereof can equally be used. Figure 4 shows the equivalent circuit of the package 100.

[0042] Each transistor has its own output leads 101A, 101B and input leads 102A, 102B, which are connected to the metal layer on the first dielectric layer of the printed circuit board 150. The upper transistor is connected to the first line segment W1A, while the lower transistor is connected to the second line segment W1B. These line segments form a first loop around the ground patch 104. In addition to the ground patch 104, a ground surrounding area 105 is provided. The point where the line segments W1A, W1B are physically connected is RF - short - circuited using capacitors C15, C16, C17. Further, heat bridges QB1 - QB8 are provided to ensure proper cooling of the line segments W1A, W1B during operation.

[0043] From Figure 2 , the capacitor Cd is implemented by using capacitors C7 and C10. Bias networks B1 and B2 are used to provide DC power to the output terminals of the power transistors. Here, the bias network B1 includes resistors R6 and R7, inductors L5 and L7, and capacitors C5, C8, C11 and C13. Similarly, the bias network B2 includes resistors R5 and R8, inductors L6 and L8, and capacitors C6, C9, C12 and C14.

[0044] Similar bias networks B3 and B4 are provided at the input end. Here, the bias network B3 includes resistors R1 and R2, inductor L3, and capacitors C1 and C3. Similarly, the bias network B4 includes resistors R3 and R4, inductor L4, and capacitors C2 and C4.

[0045] The transformer network T3 is used to transform the unbalanced signal received at the input end RF IN into a balanced signal for feeding to the power transistor inside the package 100.

[0046] Figure 5 and Figure 6 The internal metal layer of the printed circuit board 150 is shown. In Figure 5 a third line segment W2 is shown, which is connected to the ground surrounding area 112 at one end 111. The other end 113 is connected to the fourth line segment W3 shown in Figure 6 by using a plurality of vias 114. The third line segment W2 is formed in two turns around the central ground patch 115, which is aligned with the ground patch 104 and is electrically connected to the ground patch 104 and the ground patch 124 by using a plurality of vias 116. As shown, the area occupied by the third line segment W2 roughly corresponds to the area occupied by the first line segment W1A and the second line segment W1B. As Figure 6 shown, the same applies to the setting of the fourth line segment W3. One end 121 of the fourth line segment W3 is connected to the end 113 of the third line segment W2, and the other end 122 of the fourth line segment W3 is connected to the output end RF OUT of the amplifier by using a plurality of vias 123 extending through the first dielectric layer and the second dielectric layer. The fourth line segment W3 is formed in two turns around the central ground patch 124, and the central ground patch is electrically connected to the patches 115 and 104 by using the vias 116.

[0047] As Figure 5 seen in, when starting from the end 111, both the third line segment W2 and the fourth line segment W3 travel clockwise around their respective ground patches 115 and 124.

[0048] By using additional turns in the fourth line segment W3, the lengths of the line segments W1A and W1B are reduced. This allows one or more larger capacitors to be selected and arranged between the output ends of the amplification unit. Further, for a given Vdd, this will increase the power that the amplifier can output while reducing the physical size of the amplifier.

[0049] In the above, detailed embodiments of the present invention have been used to explain the present invention. However, the present invention is not limited to these embodiments. On the contrary, various modifications can be made without departing from the scope of the present invention described by the appended claims and their equivalents.

[0050] For example, although the embodiments herein are characterized by a third line segment and a fourth line segment, the present invention also relates to embodiments that implement more line segments in different metal layers.

Claims

1. A push - pull class - E amplifier, comprising: An input terminal configured to receive a signal to be amplified; An output terminal configured to output an amplified signal; A printed circuit board having a first dielectric layer and a second dielectric layer; A first amplification unit having a first input terminal and a first output terminal; A second amplification unit having a second input terminal and a second output terminal, wherein the first amplification unit and the second amplification unit are configured to operate in class - E; A balun having an unbalanced port connected to the input terminal, a first balanced port connected to the first input terminal, and a second balanced port connected to the second input terminal; A capacitor unit including a capacitor coupled between the first output terminal and ground, and a capacitor coupled between the second output terminal and ground, or a capacitor coupled between the first output terminal and the second output terminal; A first line segment having a first end and a second end, wherein the first end of the first line segment is coupled to the first output terminal; A second line segment having a first end and a second end, wherein the first end of the second line segment is coupled to the second output terminal, and the second end of the first line segment and the second end of the second line segment are connected to each other, and the first line segment, the second line segment, and the capacitor unit form part of a class - E matching network for the first amplification unit and the second amplification unit; Wherein the first line segment and the second line segment are arranged on the first dielectric layer; The push - pull class - E amplifier further comprises: A third line segment arranged between the first dielectric layer and the second dielectric layer and having a first end and a second end, wherein the first end is grounded; A fourth line segment arranged on the second dielectric layer on a side opposite to the first dielectric layer and having a first end and a second end, wherein the first end of the fourth line segment is connected to the second end of the third line segment through a via hole extending through the second dielectric layer, and the second end of the fourth line segment is connected to the output terminal of the amplifier; Wherein the combined length of the third line segment and the fourth line segment corresponds to a quarter - wavelength at a frequency within the operating frequency range of the amplifier; Wherein the first line segment and the second line segment form a first loop; Wherein the third line segment forms a second loop including m turns; Wherein the fourth line segment forms a third loop including n turns; Wherein the length of the first line segment and the length of the second line segment each correspond to an eighth - wavelength divided by (n + m) at a frequency within the operating frequency range of the amplifier; Wherein the first line segment, the second line segment, and the third line segment are formed by using coupled transmission lines; and Wherein the third line segment and the fourth line segment are formed by using coupled transmission lines.

2. The push-pull class-E amplifier according to claim 1, wherein, At least one of m or n is greater than 1.

3. The push-pull class-E amplifier according to claim 1, wherein, The first line segment and the second line segment occupy a first annular surface area on the first dielectric layer, and wherein the third line segment and the fourth line segment respectively occupy a second annular surface area and a third annular surface area; when the second annular surface area and the third annular surface area are projected onto the first annular surface area in a direction perpendicular to the printed circuit board, the second annular surface area and the third annular surface area substantially fall within the first annular surface area; wherein, the inner circumference and / or the outer circumference of each of the first annular surface area, the second annular surface area, and the third annular surface area has a square shape, a rectangular shape, a circular shape, or an oval shape.

4. The push-pull class-E amplifier according to claim 3, wherein the push-pull class-E amplifier further comprises: A first ground patch, the first loop extending around the first ground patch; A second ground patch, the second loop extending around the second ground patch; And a third ground patch, the third loop extending around the third ground patch, the surface areas of the first ground patch, the second ground patch, and the third ground patch being substantially the same, and the first ground patch, the second ground patch, and the third ground patch being electrically connected by using one or more vias extending through the first dielectric layer and / or the second dielectric layer.

5. The push-pull class-E amplifier according to claim 4, the push-pull class-E amplifier further comprising a first ground surrounding area around the first loop, a second ground surrounding area around the second loop, and a third ground surrounding area around the third loop, the first ground surrounding area, the second ground surrounding area, and the third ground surrounding area being electrically connected to each other by using one or more vias extending through the first dielectric layer and / or the second dielectric layer.

6. The push-pull class-E amplifier according to claim 5, wherein, A first end of the third line segment is physically and electrically connected to the second ground surrounding area.

7. The push-pull class-E amplifier according to claim 4, wherein the push-pull class-E amplifier further comprises: One or more electrically isolated thermal bridges, each thermal bridge connecting the first line segment or the second line segment to the first ground patch.

8. The push-pull class-E amplifier according to claim 5, wherein the push-pull class-E amplifier further comprises: One or more electrically isolated thermal bridges, each thermal bridge connecting the first line segment or the second line segment to the first ground surrounding area.

9. The push-pull class-E amplifier according to any one of claims 4-8, wherein, One or more turns of the third line segment travel around the second ground patch in a direction the same as the direction in which one or more turns of the fourth line segment travel around the third ground patch.

10. The push-pull class-E amplifier according to any one of claims 1-8, wherein, The first amplification unit and the second amplification unit are included in a package, the package including a pair of different and spaced-apart connection terminals that are respectively connected to the first output end and the second output end inside the package, the package being mounted on the first dielectric layer.

11. The push-pull class-E amplifier according to claim 10, wherein, The package includes a first power transistor and a second power transistor, each of the first power transistor and the second power transistor being a silicon-based laterally diffused metal oxide semiconductor LDMOS transistor, a vertical double-diffused metal oxide semiconductor VDMOS transistor, or a gallium nitride-based field effect transistor FET.

12. The push-pull class-E amplifier according to any one of claims 1-8, wherein, The first line segment and the second line segment are capacitively coupled to ground at or near the point where the first line segment and the second line segment are connected.

13. The push-pull class-E amplifier according to any one of claims 1-8, wherein, Each of the first line segment and the second line segment is connected to a respective bias network, the bias network being configured to supply a direct current (DC) current to the first amplification unit and the second amplification unit respectively, and the bias network being part of the class-E matching network.

14. The push-pull class-E amplifier according to any one of claims 1-8, the push-pull class-E amplifier further comprising a bias network configured to supply a direct current (DC) current to the first amplification unit and the second amplification unit at or near the point where the first line segment and the second line segment are connected.

15. The push-pull class-E amplifier according to any one of claims 1-8, wherein, The operating frequency range is in the range of 1 MHz to 200 MHz.

16. The push-pull class-E amplifier according to any one of claims 1-8, wherein, The power of the output signal is in the range of 100 W to 10 kW.

17. An electronic device comprising a push-pull class-E amplifier according to any one of the preceding claims.

18. The electronic device according to claim 17, wherein, The electronic device is one of push-pull solid-state amplifiers for industrial, scientific or medical applications, wherein the electronic device is incorporated in a plasma generation device, a laser system or a particle accelerator.

19. The electronic device according to claim 18, wherein, The industrial, scientific or medical applications include RF heating, drying and defrosting, or magnetic resonance imaging.

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