NAND gate logic circuit and preparation method thereof

Abstract

The present invention discloses a NAND gate logic circuit and a preparation method thereof. The NAND gate logic circuit comprises: a depletion-type transistor, wherein the first end of the depletion-type transistor is used to access a power supply, the control end of the depletion-type transistor is electrically connected to the second end of the depletion-type transistor, and the second end of the depletion-type transistor serves as the output end of the NAND gate logic circuit; an enhanced dual-gate transistor, wherein the first end of the dual-gate transistor is electrically connected to the second end of the depletion-type transistor, the second end of the dual-gate transistor is grounded, the first control end of the dual-gate transistor serves as the first input end of the NAND gate logic circuit, and the second control end of the dual-gate transistor serves as the second input end of the NAND gate logic circuit. The embodiment of the present invention can reduce the size of the NAND gate logic circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor technology, and in particular to a NAND gate logic circuit and a preparation method thereof. Background Art

[0002] The NAND gate logic circuit is one of the basic units of digital logic circuits and is widely used in control circuits, memories and other fields.

[0003] However, the size of the existing NAND gate logic circuit is relatively large, and a large number of NAND gate logic circuits are required in the control circuit and the memory circuit, resulting in the large size of the control circuit and the memory circuit, which is not conducive to improving the integration. Summary of the invention

[0004] The invention provides a NAND gate logic circuit and a preparation method thereof, so as to reduce the size of the NAND gate logic circuit.

[0005] In a first aspect, an embodiment of the present invention provides a NAND gate logic circuit, wherein the NAND gate logic circuit comprises:

[0006] A depletion-mode transistor, wherein a first end of the depletion-mode transistor is used to connect to a power source, a control end of the depletion-mode transistor is electrically connected to a second end of the depletion-mode transistor, and the second end of the depletion-mode transistor serves as an output end of the NAND gate logic circuit;

[0007] An enhancement-type dual-gate transistor, wherein the first end of the dual-gate transistor is electrically connected to the second end of the depletion-type transistor, the second end of the dual-gate transistor is grounded, the first control end of the dual-gate transistor serves as the first input end of the NAND gate logic circuit, and the second control end of the dual-gate transistor serves as the second input end of the NAND gate logic circuit.

[0008] Optionally, the depletion-mode transistor is a GaN transistor, and the dual-gate transistor is a GaN transistor.

[0009] Optionally, the dual-gate transistor comprises a substrate, a channel layer and an aluminum gallium nitride epitaxial layer stacked in sequence, a surface of the aluminum gallium nitride epitaxial layer away from the channel layer is provided with a first groove and a second groove, a surface of the aluminum gallium nitride epitaxial layer away from the channel layer is provided with a first source metal, a first drain metal and a dielectric layer, wherein the dielectric layer covers the first groove and the second groove;

[0010] The dual-gate transistor further includes a first gate metal and a second gate metal, wherein the first gate metal is disposed on a side of the dielectric layer away from the channel layer and fills the first groove;

[0011] The second gate metal is disposed on a side of the dielectric layer away from the channel layer and fills the second groove.

[0012] Optionally, the material of the dielectric layer is aluminum oxide.

[0013] Optionally, the first source metal and the first drain metal are in ohmic contact with the aluminum gallium nitride epitaxial layer.

[0014] In a second aspect, an embodiment of the present invention further provides a method for preparing a NAND gate logic circuit, wherein the NAND gate logic circuit comprises: a depletion-type transistor, wherein the first end of the depletion-type transistor is used to access a power supply, the control end of the depletion-type transistor is electrically connected to the second end of the depletion-type transistor, and the second end of the depletion-type transistor serves as the output end of the NAND gate logic circuit; an enhanced dual-gate transistor, wherein the first end of the dual-gate transistor is electrically connected to the second end of the depletion-type transistor, the second end of the dual-gate transistor is grounded, the first control end of the dual-gate transistor serves as the first input end of the NAND gate logic circuit, and the second control end of the dual-gate transistor serves as the second input end of the NAND gate logic circuit;

[0015] The preparation method comprises:

[0016] forming the dual-gate transistor and the depletion-mode transistor;

[0017] The first terminal of the dual-gate transistor is electrically connected to the second terminal of the depletion-mode transistor.

[0018] Optionally, forming the dual-gate transistor and the depletion-mode transistor includes:

[0019] Epitaxially forming a stacked channel layer and an aluminum gallium nitride epitaxial layer on a substrate, wherein the NAND gate logic circuit has a depletion transistor region and a dual-gate transistor region;

[0020] Forming a first groove and a second groove on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the dual-gate transistor region;

[0021] A first source metal and a first drain metal are formed on the surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the dual-gate transistor region, and a second source metal and a second drain metal are formed on the surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the depletion-mode transistor region; wherein the first source metal serves as the second end of the dual-gate transistor, the first drain metal serves as the first end of the dual-gate transistor, the second source metal serves as the second end of the depletion-mode transistor, and the second drain metal serves as the first end of the depletion-mode transistor;

[0022] forming a dielectric layer on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer, wherein the dielectric layer covers the first groove and the second groove;

[0023] A first gate metal is formed in the first groove, a second gate metal is formed in the second groove, and a third gate metal is formed in a portion of the dielectric layer away from the aluminum gallium nitride epitaxial layer and located in the depletion transistor region.

[0024] Optionally, forming a first groove and a second groove on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer comprises:

[0025] forming a silicon nitride sacrificial layer on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer;

[0026] Partial openings are formed in the silicon nitride sacrificial layer corresponding to the first groove and the second groove to expose the aluminum gallium nitride epitaxial layer;

[0027] Etching the aluminum gallium nitride epitaxial layer exposed by the opening to form the first groove and the second groove;

[0028] The remaining sacrificial silicon nitride layer is removed.

[0029] Optionally, forming a first source metal and a first drain metal on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the dual-gate transistor region, and forming a second source metal and a second drain metal on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the depletion transistor region includes:

[0030] The first source metal, the second source metal, the first drain metal and the second drain metal are grown by electron beam evaporation, and the first source metal, the second source metal, the first drain metal and the second drain metal are annealed to form ohmic contacts.

[0031] Optionally, electrically connecting the first terminal of the dual-gate transistor to the second terminal of the depletion-mode transistor comprises:

[0032] forming a passivation layer covering the first source metal, the second source metal, the first drain metal and the second drain metal on the entire surface;

[0033] Opening holes in the passivation layer to expose the first source metal, the second source metal, the first drain metal, the second drain metal, the first gate metal, the second gate metal and the third gate metal respectively;

[0034] forming electrode metals contacting the first drain metal, the second drain metal, the first gate metal, the second gate metal and the third gate metal respectively;

[0035] A connection metal is formed that contacts both the electrode metal corresponding to the second source metal and the electrode metal corresponding to the first drain metal.

[0036] The technical solution of this embodiment of the present invention adopts a NAND gate logic circuit including: a depletion-type transistor, the first end of the depletion-type transistor is used to access the power supply, the control end of the depletion-type transistor is electrically connected to the second end of the depletion-type transistor, and the second end of the depletion-type transistor serves as the output end of the NAND gate logic circuit; an enhanced dual-gate transistor, the first end of the dual-gate transistor is electrically connected to the second end of the depletion-type transistor, the second end of the dual-gate transistor is grounded, the first control end of the dual-gate transistor serves as the first input end of the NAND gate logic circuit, and the second control end of the dual-gate transistor serves as the second input end of the NAND gate logic circuit. Using a dual-gate transistor to form a NAND gate logic circuit instead of two independent transistors is equivalent to merging the source and drain of the two independent transistors, thereby greatly reducing the size of the NAND gate logic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the circuit structure of a NAND gate logic circuit provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of the structure of a dual-gate transistor provided by an embodiment of the present invention;

[0039] Figure 3 A flowchart of a method for preparing a NAND gate logic circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0041] Figure 1 A schematic diagram of a circuit structure of a NAND gate logic circuit provided by an embodiment of the present invention, referring to Figure 1The NAND gate logic circuit includes: a depletion transistor D1, a first end of the depletion transistor D1 is used to access a power supply VDD, a control end of the depletion transistor D1 is electrically connected to a second end of the depletion transistor D1, and the second end of the depletion transistor D1 serves as an output end Vout of the NAND gate logic circuit; an enhanced dual-gate transistor E, a first end of the dual-gate transistor E is electrically connected to a second end of the depletion transistor D1, a second end of the dual-gate transistor E is grounded, a first control end of the dual-gate transistor E serves as a first input end V1 of the NAND gate logic circuit, and a second control end of the dual-gate transistor E serves as a second input end V2 of the NAND gate logic circuit.

[0042] Specifically, the logical expression of the NAND gate logic circuit is Wherein, Y is the output of the NAND gate logic circuit, A and B are the inputs of the NAND gate logic circuit, when A is 0 and B is 0, Y is 1; when A is 0 and B is 1, Y is 1; when A is 1 and B is 0, Y is 1; when A is 1 and B is 0, Y is 1; when A is 1 and B is 1, Y is zero; in this embodiment, the depletion transistor D1 and the enhanced dual-gate transistor E are both N-type transistors, and the depletion transistor D1 can still be turned on when its gate bias is 0, that is, when the power supply VDD is applied, the depletion transistor D1 is always in the on state, at this time, the output terminal Vout of the NAND gate logic circuit is connected to the power supply VDD, when at least one of the first input terminal V1 and the second input terminal V2 is at a low level, the dual-gate transistor E is always in the off state, that is, at this time, the output terminal Vout of the NAND gate logic circuit always outputs a high-level signal, and the dual-gate transistor E is an enhanced type, and when its gate bias is 0, it cannot be turned on, so as to avoid the dual-gate transistor from being mis-turned on and causing the NAND gate logic circuit to produce When the first input terminal V1 and the second input terminal V2 are both at high levels, the dual-gate transistor E is in the on state, and the output terminal Vout of the NAND logic circuit is pulled low, that is, only when the first input terminal V1 and the second input terminal V2 are both at high levels, the output terminal Vout of the NAND logic circuit will output a low level, thereby realizing the logic NAND function; and in this embodiment, a dual-gate transistor E is used to form the NAND logic circuit instead of two independent transistors, which is equivalent to merging the source and drain of the two independent transistors, thereby greatly reducing the size of the NAND logic circuit; at the same time, due to the simplification of the circuit between the ground terminal and the output terminal Vout, the on-resistance of the dual-gate transistor is small, which can further reduce the potential of the logic low level of the output terminal of the NAND logic circuit and improve the anti-noise capability; in addition, the distance between the first input terminal V1 and the second input terminal V2 can be shortened, and the complexity of the circuit can be significantly reduced.

[0043] The technical solution of this embodiment adopts a NAND gate logic circuit including: a depletion-type transistor, the first end of the depletion-type transistor is used to access the power supply, the control end of the depletion-type transistor is electrically connected to the second end of the depletion-type transistor, and the second end of the depletion-type transistor serves as the output end of the NAND gate logic circuit; an enhanced dual-gate transistor, the first end of the dual-gate transistor is electrically connected to the second end of the depletion-type transistor, the second end of the dual-gate transistor is grounded, the first control end of the dual-gate transistor serves as the first input end of the NAND gate logic circuit, and the second control end of the dual-gate transistor serves as the second input end of the NAND gate logic circuit. Using a dual-gate transistor to form a NAND gate logic circuit instead of two independent transistors is equivalent to merging the source and drain of the two independent transistors, thereby greatly reducing the size of the NAND gate logic circuit.

[0044] Optionally, the depletion-mode transistor D1 is a GaN transistor, and the dual-gate transistor E is a GaN transistor.

[0045] Specifically, GaN materials have physical properties such as wide bandgap, and GaN transistors conduct electricity through high-concentration two-dimensional electron gas (2DEG) generated by piezoelectric and polarization effects between the AlGaN epitaxial layer and the GaN layer, and have the characteristics of high mobility and low on-resistance. Using GaN transistors as depletion-mode transistors D1 and dual-gate transistors E can greatly improve the switching speed of depletion-mode transistors D1 and dual-gate transistors E, thereby improving the operation speed of NAND gate logic circuits.

[0046] Optionally, Figure 2 A schematic diagram of a dual-gate transistor according to an embodiment of the present invention is provided. Figure 2 The dual-gate transistor includes a substrate 1, a channel layer 2 and an aluminum gallium nitride epitaxial layer 3 stacked in sequence, a surface of the aluminum gallium nitride epitaxial layer 3 away from the channel layer 2 is provided with a first groove 31 and a second groove 32, a surface of the aluminum gallium nitride epitaxial layer 3 away from the channel layer 2 is provided with a first source metal 4, a first drain metal 5 and a dielectric layer 6, wherein the dielectric layer 6 covers the first groove 31 and the second groove 32; the dual-gate transistor also includes a first gate metal 7 and a second gate metal 8, the first gate metal 7 is provided on a side of the dielectric layer 6 away from the channel layer 3 and fills the first groove 31; the second gate metal 8 is provided on a side of the dielectric layer 6 away from the channel layer 3 and fills the second groove 32.

[0047] Specifically, the substrate 1 may be, for example, a Si substrate, a gallium nitride buffer layer may be further provided between the substrate 1 and the channel layer 2, the channel layer 2 may be, for example, a gallium nitride channel layer, the dielectric layer 6 may be, for example, an aluminum oxide dielectric layer, and a grooved enhancement mode device is used as a dual-gate device, the first source metal 4 serves as the first end of the dual-gate transistor, and the first drain metal 5 serves as the second end of the dual-gate transistor; the first gate metal 7 serves as the first control end of the dual-gate transistor, and the second gate metal 8 serves as the second control end of the dual-gate transistor. Only when a high level is applied to both the first gate metal 7 and the second gate metal 8, a conductive channel is formed between the first source metal 4 and the first drain metal 5, so that the dual-gate transistor is turned on, and the two gates of the dual-gate transistor (the first gate metal 7 and the second gate metal 8) can realize the input function without interfering with each other, thereby realizing the logic function of the NAND gate.

[0048] Optionally, the first source metal 4 and the first drain metal 5 are in ohmic contact with the aluminum gallium nitride epitaxial layer 3 .

[0049] Specifically, the first source metal 4 and the first drain metal 5 can form an ohmic contact with the aluminum gallium nitride epitaxial layer 3 by means of rapid annealing, so that the contact impedance is small, the on-resistance of the dual-gate transistor is small, the potential of the logic low level at the output end of the NAND gate logic circuit can be reduced, and the anti-noise capability is improved.

[0050] Figure 3 A flowchart of a method for preparing a NAND gate logic circuit provided in an embodiment of the present invention, wherein the NAND gate logic circuit includes the NAND gate logic circuit provided in any embodiment of the present invention, and the method for preparing the NAND gate logic circuit includes:

[0051] Step S101, forming a dual-gate transistor and a depletion-mode transistor;

[0052] Specifically, the dual-gate transistor and the depletion-mode transistor can be formed separately. For example, the dual-gate transistor can be formed first and then the depletion-mode transistor, or the depletion-mode transistor can be formed first and then the dual-gate transistor, or the dual-gate transistor and the depletion-mode transistor can be formed simultaneously.

[0053] Step S102 , electrically connecting the first terminal of the dual-gate transistor to the second terminal of the depletion-mode transistor.

[0054] Specifically, the second end of the dual-gate transistor can be electrically connected to the metal ground to achieve ground connection, and after the dual-gate transistor is connected to the depletion-type transistor, the electrical connection of the NAND gate logic circuit is achieved. It should be noted that after the production is completed, the NAND gate logic circuit can also be tested and packaged to finally complete the production of the NAND gate logic circuit.

[0055] By adopting the method for preparing the NAND gate logic circuit of the embodiment of the present invention, the prepared NAND gate logic circuit uses a dual-gate transistor to constitute the NAND gate logic circuit instead of using two independent transistors, which is equivalent to merging the source and drain of the two independent transistors, thereby greatly reducing the size of the NAND gate logic circuit.

[0056] Optionally, forming a dual-gate transistor and a depletion-mode transistor includes:

[0057] epitaxially forming a stacked channel layer and an aluminum gallium nitride epitaxial layer on a substrate;

[0058] Specifically, a gallium nitride channel layer and an aluminum gallium nitride epitaxial layer can be formed on a Si substrate by epitaxy. Figure 2 As shown, the NAND gate logic circuit has a depletion transistor region D1A and a dual-gate transistor region EA.

[0059] A first groove 31 and a second groove 32 are formed on the surface of the GaN epitaxial layer away from the channel layer and located in the dual-gate transistor area EA;

[0060] Specifically, a silicon nitride sacrificial layer can be first formed on the surface of the aluminum gallium nitride epitaxial layer away from the channel layer, and the silicon nitride sacrificial layer can be deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition); then the silicon nitride sacrificial layer is etched to etch away the portions corresponding to the first groove and the second groove, that is, holes are opened in the portions of the silicon nitride sacrificial layer corresponding to the first groove and the second groove, thereby exposing the aluminum gallium nitride epitaxial layer; then the aluminum gallium nitride epitaxial layer exposed by the opening is etched to form the first groove and the second groove, and specifically, the aluminum gallium nitride epitaxial layer exposed by the opening can be etched by wet etching (oxygen etching plus hydrochloric acid soaking) to produce the first groove and the second groove; after the etching of the first groove and the second groove is completed, the remaining silicon nitride sacrificial layer is removed.

[0061] A first source metal 4 and a first drain metal 7 are formed on the surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the dual-gate transistor region, and a second source metal 101 and a second drain metal 103 are formed on the surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the depletion-mode transistor region; wherein the first source metal serves as the second end of the dual-gate transistor, the first drain metal serves as the first end of the dual-gate transistor, the second source metal serves as the second end of the depletion-mode transistor, and the second drain metal serves as the first end of the depletion-mode transistor;

[0062] Specifically, a first source metal 4, a first drain metal 5, a second source metal 101 and a second drain metal 103 may be formed at both ends of the surface of the aluminum gallium nitride epitaxial layer away from the channel layer, respectively. For example, the first source metal 4, the first drain metal 5, the second source metal 101 and the second drain metal 103 may be grown by electron beam evaporation and rapidly annealed to achieve ohmic contact.

[0063] Forming a dielectric layer on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer, wherein the dielectric layer covers the first groove and the second groove;

[0064] Specifically, an aluminum oxide layer may be deposited by ALD (Atomic layer deposition) as the dielectric layer.

[0065] A first gate metal is formed in the first groove, a second gate metal is formed in the second groove, and a third gate metal 102 is formed in a portion of the dielectric layer away from the AlGaN epitaxial layer and located in the depletion transistor region.

[0066] Specifically, after the dielectric layer is produced, the first gate metal 7, the second gate metal 8 and the third gate metal 102 can be formed simultaneously by electron beam evaporation. The first gate metal serves as the first control terminal of the dual-gate transistor, the second gate metal serves as the second control terminal of the dual-gate transistor, and the third gate metal 102 serves as the control terminal of the depletion-mode transistor.

[0067] Optionally, electrically connecting the first terminal of the dual-gate transistor to the second terminal of the depletion-mode transistor comprises:

[0068] A passivation layer 10 is formed on the entire surface to cover the first source metal 4 , the second source metal 101 , the first drain metal 5 and the second drain metal 103 ; for example, a silicon nitride passivation layer may be grown by PECVD.

[0069] A hole is opened on the passivation layer 10 to expose the first source metal 4, the second source metal 101, the first drain metal 5, the second drain metal 103, the first gate metal 7, the second gate metal 8 and the third gate metal 102 respectively; for example, the passivation layer 10 can be opened with carbon tetrafluoride, and since an aluminum oxide layer will exist on the surface of the first source metal 4, the second source metal 101, the first drain metal 5, the second drain metal 103, the first gate metal 7, the second gate metal 8 and the third gate metal 102 when the dielectric layer is grown, BOE (Buffered Oxide Etch, buffered oxide etching solution) solution removes aluminum oxide at the opening to prevent the first source metal 4, the second source metal 101, the first drain metal 5, the second drain metal 103, the first gate metal 7, the second gate metal 8 and the third gate metal 102 from being unable to transmit signals to the outside; then, electrode metals 104 are formed respectively to contact the first drain metal, the second drain metal, the first gate metal, the second gate metal and the third gate metal, and the electrode metal 104 can be aluminum;

[0070] A connection metal 105 is formed that contacts both the electrode metal corresponding to the second source metal and the electrode metal corresponding to the first drain metal; for example, aluminum can be evaporated by electron beam to interconnect the metal and the device, and a NAND gate logic circuit is also formed. It is understandable that the NAND gate logic circuit can also be tested and packaged in the end.

[0071] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A NAND gate logic circuit, characterized in that: The NAND gate logic circuit comprises: A depletion-mode transistor, wherein a first end of the depletion-mode transistor is used to connect to a power source, a control end of the depletion-mode transistor is electrically connected to a second end of the depletion-mode transistor, and the second end of the depletion-mode transistor serves as an output end of the NAND gate logic circuit; an enhancement-type double-gate transistor, wherein the first terminal of the double-gate transistor is electrically connected to the second terminal of the depletion-type transistor, the second terminal of the double-gate transistor is grounded, the first control terminal of the double-gate transistor serves as the first input terminal of the NAND gate logic circuit, and the second control terminal of the double-gate transistor serves as the second input terminal of the NAND gate logic circuit; The dual-gate transistor comprises a substrate, a channel layer and an aluminum gallium nitride epitaxial layer stacked in sequence, a surface of the aluminum gallium nitride epitaxial layer away from the channel layer is provided with a first groove and a second groove, a surface of the aluminum gallium nitride epitaxial layer away from the channel layer is provided with a first source metal, a first drain metal and a dielectric layer, wherein the dielectric layer covers the first groove and the second groove; The dual-gate transistor further includes a first gate metal and a second gate metal, wherein the first gate metal is disposed on a side of the dielectric layer away from the channel layer and fills the first groove; The second gate metal is disposed on a side of the dielectric layer away from the channel layer and fills the second groove.

2. The NAND gate logic circuit according to claim 1, characterized in that: The depletion-mode transistor is a GaN transistor, and the dual-gate transistor is a GaN transistor.

3. The NAND gate logic circuit according to claim 1, characterized in that: The material of the dielectric layer is aluminum oxide.

4. The NAND gate logic circuit according to claim 1, characterized in that: The first source metal and the first drain metal are both in ohmic contact with the aluminum gallium nitride epitaxial layer.

5. A method for preparing a NAND gate logic circuit, characterized in that: The NAND gate logic circuit comprises: a depletion-type transistor, wherein the first end of the depletion-type transistor is used to connect to a power supply, the control end of the depletion-type transistor is electrically connected to the second end of the depletion-type transistor, and the second end of the depletion-type transistor serves as the output end of the NAND gate logic circuit; an enhanced double-gate transistor, wherein the first end of the double-gate transistor is electrically connected to the second end of the depletion-type transistor, and the second end of the double-gate transistor is grounded, the first control end of the double-gate transistor serves as the first input end of the NAND gate logic circuit, and the second control end of the double-gate transistor serves as the second input end of the NAND gate logic circuit; The preparation method comprises: forming the dual-gate transistor and the depletion-mode transistor; electrically connecting the first terminal of the dual-gate transistor to the second terminal of the depletion-mode transistor; Forming the dual-gate transistor and the depletion-mode transistor includes: Epitaxially forming a stacked channel layer and an aluminum gallium nitride epitaxial layer on a substrate, wherein the NAND gate logic circuit has a depletion transistor region and a dual-gate transistor region; Forming a first groove and a second groove on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the dual-gate transistor region; A first source metal and a first drain metal are formed on the surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the dual-gate transistor region, and a second source metal and a second drain metal are formed on the surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the depletion-mode transistor region; wherein the first source metal serves as the second end of the dual-gate transistor, the first drain metal serves as the first end of the dual-gate transistor, the second source metal serves as the second end of the depletion-mode transistor, and the second drain metal serves as the first end of the depletion-mode transistor; forming a dielectric layer on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer, wherein the dielectric layer covers the first groove and the second groove; A first gate metal is formed in the first groove, a second gate metal is formed in the second groove, and a third gate metal is formed in a portion of the dielectric layer away from the aluminum gallium nitride epitaxial layer and located in the depletion transistor region.

6. The preparation method according to claim 5, characterized in that: Forming a first groove and a second groove on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer comprises: forming a silicon nitride sacrificial layer on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer; Partial openings are formed in the silicon nitride sacrificial layer corresponding to the first groove and the second groove to expose the aluminum gallium nitride epitaxial layer; Etching the aluminum gallium nitride epitaxial layer exposed by the opening to form the first groove and the second groove; The remaining sacrificial silicon nitride layer is removed.

7. The preparation method according to claim 5, characterized in that: The forming of a first source metal and a first drain metal on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the dual-gate transistor region, and the forming of a second source metal and a second drain metal on a surface of the aluminum gallium nitride epitaxial layer away from the channel layer and located in the depletion transistor region comprises: The first source metal, the second source metal, the first drain metal and the second drain metal are grown by electron beam evaporation, and the first source metal, the second source metal, the first drain metal and the second drain metal are annealed to form ohmic contacts.

8. The preparation method according to claim 5, characterized in that: Electrically connecting the first terminal of the dual-gate transistor to the second terminal of the depletion-mode transistor comprises: forming a passivation layer covering the first source metal, the second source metal, the first drain metal and the second drain metal on the entire surface; Opening holes in the passivation layer to expose the first source metal, the second source metal, the first drain metal, the second drain metal, the first gate metal, the second gate metal and the third gate metal respectively; forming electrode metals contacting the first drain metal, the second drain metal, the first gate metal, the second gate metal and the third gate metal respectively; A connection metal is formed that contacts both the electrode metal corresponding to the second source metal and the electrode metal corresponding to the first drain metal.

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