command filter that filters commands having a predetermined pulse width

Abstract

The present disclosure relates to command filters that filter commands having a predetermined pulse width. Disclosed herein is an apparatus including a command shifter configured to receive a command pulse and concurrently generate a plurality of first command shifted pulses, wherein each of the plurality of first command shifted pulses has a same width as the command pulse, and the plurality of first command shifted pulses have different phases from one another; and a command filter configured to determine whether a plurality of second command shifted pulses are generated corresponding to the plurality of first command shifted pulses or are not generated in response to pulse overlap between at least a plurality of the plurality of first command shifted pulses.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] In a semiconductor device such as a dynamic random access memory (DRAM), in some cases, external read commands are issued consecutively with the shortest period. In these cases, each time an external read command is issued, when an internal read command changes from an inactive level to an active level, current consumption increases. Therefore, in some semiconductor devices, in the case where external read commands are issued consecutively with the shortest period, the pulse width of the internal read command is extended to the same length as the shortest period of the external read command to reduce current consumption.

[0003] Meanwhile, for external commands that are not issued consecutively, such as a mode register read command, there is no need to extend the pulse width of the internal command. However, if a command shifter that counts the delay of an internal command is provided for each internal command having a different pulse width, there is a problem of an increase in circuit size or current consumption. Therefore, there is a need for a semiconductor device that can allocate internal commands having different pulse widths to a common command shifter. SUMMARY

[0004] One aspect of the present disclosure relates to an apparatus comprising: a command shifter configured to receive a command pulse and concurrently generate a plurality of first command shift pulses, wherein each of the plurality of first command shift pulses has a same width as the command pulse and the plurality of first command shift pulses have different phases from one another; and a command filter configured to determine whether a plurality of second command shift pulses are generated corresponding to the plurality of first command shift pulses or are not generated in response to pulse overlap between at least a plurality of the plurality of first command shift pulses.

[0005] Another aspect of the present disclosure relates to an apparatus comprising: a command decoder configured to be supplied with an external command signal and generate a first command signal and a second command signal having a first pulse width; a first command extender configured to generate a third command signal having a second pulse width greater than the first pulse width by extending a pulse width of the second command signal having the first pulse width to the second pulse width; a command shifter supplied with the first command signal and the third command signal and configured to generate a plurality of first shifted signals having different phases from one another by shifting the first command signal and the third command signal in synchronization with a clock signal; and a second command extender configured to generate a plurality of second shifted signals by extending a pulse width of the first shifted signal having the first pulse width to the second pulse width.

[0006] Yet another aspect of the present disclosure relates to an apparatus comprising: a command shifter configured to generate a plurality of first shifted signals having different phases from each other by shifting a command signal in synchronization with a clock signal; and a command filter configured to be supplied with the first shifted signals and to generate a plurality of second shifted signals having different phases from each other, wherein the command filter is configured to activate each of the second shifted signals when an associated one of the first shifted signals is activated while a preceding one of the first shifted signals and a succeeding one of the first shifted signals are deactivated. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A and 2B is a timing chart for explaining an operation of a command shifter according to an embodiment of the present disclosure.

[0009] Figure 3 is a circuit diagram of a read command shifter according to an embodiment of the present disclosure.

[0010] Figure 4 is a circuit diagram of a selection circuit according to an embodiment of the present disclosure.

[0011] Figure 5 is a circuit diagram of a command filter according to an embodiment of the present disclosure.

[0012] Figure 6A and 6B is a waveform chart for explaining an operation of a command filter according to an embodiment of the present disclosure.

[0013] Figure 7 is a timing chart for explaining an operation of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Various embodiments of the present application will be explained in detail below with reference to the attached drawings. The following detailed description references the drawings in which, by way of illustration, specific aspects and embodiments of the present application are shown. The various embodiments described herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0015] Figure 1is a block diagram of a semiconductor device 100 according to one embodiment of the present disclosure. Figure 1 The semiconductor device 100 shown is a DRAM and includes a memory cell array 101, a clock address input buffer 102, a command decoder 103, a bank logic circuit 104, and an I / O buffer circuit 105. The memory cell array 101 includes a plurality of word lines SWL, a plurality of bit lines BL, and a plurality of memory cells MC respectively placed at intersections between the word lines SWL and the bit lines BL. The word lines SWL are selected in accordance with a word line selection signal WL output from the bank logic circuit 104. The bit lines BL are selected in accordance with a column switch selection signal YS output from the bank logic circuit 104.

[0016] A clock signal CLK and an address signal ADR are supplied from the outside to the clock address input buffer 102. The clock signal CLK and the address signal ADR input to the clock address input buffer 102 are supplied to the command decoder 103. The command decoder 103 decodes the address signal ADR to generate a plurality of internal commands including an internal read command RD, an internal write command WR, and an internal mode register read command MRR, and supplies an internal address signal IADR to the bank logic circuit 104. The command decoder 103 includes a clock generator 103a. The clock generator 103a generates an internal clock signal PCLK. The internal clock signal PCLK and the internal read command RD are supplied to a read command shifter 106. The read command shifter 106 provides a predetermined delay to the read command RD in synchronization with the internal clock signal PCLK to define the timing of the column selection operation of the bank logic circuit 104. Column selection signals CYE<7:0> and a precharge signal PRE are supplied from the read command shifter 106 to the bank logic circuit 104.

[0017] In a read operation, read data read from the memory cell array 101 is transferred to the main I / O lines MIO<63:0>. The read data transferred to the main I / O lines MIO<63:0> is transferred to the I / O buffer circuit 105 via a data sense amplifier DSA / error correction circuit ECC 107 and a global bus GBUS<63:0>, and is output to the outside in synchronization with various timing signals generated by a control circuit 108. In a write operation, write data input from the outside to the I / O buffer circuit 105 is written to the memory cell array 101 via the global bus GBUS<63:0>, the DSA / ECC 107, and the main I / O lines MIO<63:0>. In a mode register read operation, a mode signal MRR<3:0> read from a mode register 109 is transferred to the I / O buffer circuit 105 and is output to the outside in synchronization with various timing signals generated by the control circuit 108.

[0018] The pulse width (period of maintaining an active level) of the internal read command RD, the internal write command WR, and the internal mode register read command MRR generated by the command decoder 103 is all one clock period (= 1T) of the internal clock signal PCLK. Among these commands, the internal read command RD and the internal mode register read command MRR are supplied to the read command shifter 110, and the internal write command WR is supplied to the write command shifter 111. That is, the read command shifter 110 is commonly assigned to the internal read command RD and the internal mode register read command MRR. The internal read command RD is supplied to the read command shifter 110 in a state in which the pulse width has been expanded. In some embodiments of the present disclosure, the pulse width of the internal read command RD is expanded to more than one clock period of the internal clock signal PCLK. In some embodiments of the present disclosure, the pulse width is expanded to more than two clock periods of the internal clock signal PCLK. For example, in some embodiments of the present disclosure, the pulse width is expanded from 1T to 4T by the command expander 112 without being directly supplied to the read command shifter 110. The operation of the command expander 112 according to embodiments of the present disclosure is shown in Figure 2A and 2B The command expander 112 converts the internal read command RD (1T) having a pulse width (period of maintaining an active level) of 1T to the internal read command RD (4T) having a pulse width of 4T in synchronization with the internal clock signal PCLK. That is, the expanded pulse width of the internal read command RD is four clock periods (= 4T) of the internal clock signal PCLK. The shortest period of the internal read command RD (1T) is four clock periods (= 4T). Therefore, when the internal read command RD (1T) is continuously activated within the shortest period as shown in Figure 2B , the internal read command RD (4T) maintains an active level (high level) without changing to an inactive level (low level).

[0019] The internal read command RD (4T) having the pulse width expanded to 4T and the internal mode register read command MRR (1T) having a pulse width of 1T are supplied to the read command shifter 110 via the OR gate circuit 113. The read command shifter 110 and the write command shifter 111 shift the phase of the input internal command in response to the internal clock signal PCLK. Figure 3 is a circuit diagram of the read command shifter 110 according to embodiments of the present disclosure. As Figure 3As shown, the read command shifter 110 is a shift register including 31 latches 301 to 331 connected in cascade. The latches 301 to 331 each perform a latching operation in synchronization with an internal clock signal PCLK. Thus, the internal read command RD(4T) and the internal mode register read command MRR(lT) input to the read command shifter 110 are shifted in synchronization with the internal clock signal PCLK. Read shift signals RDsft<31:0> are output from the latches 301 to 331, respectively. Of the read shift signals RDsft<31:0>, the read shift signal RDsft<22> is supplied to the control circuit 108 via an OR gate circuit 114. A write timing signal WRWL generated by the write command shifter 111 is supplied to the control circuit 108.

[0020] The read shift signals RDsft<31:0> are supplied to a command filter 115. The command filter 115 removes one of the read shift signals RDsft<31:0> based on the internal read command RD(4T) whose pulse width has been expanded to 4T, and passes only one of the read shift signals RDsft<31:0> based on the internal mode register read command MRR whose pulse width is 1T, thereby generating read decode signals RDdec<28:19>. Of the read decode signals RDdec<28:19>, the read decode signals RDdec<22,24:28> are converted into mode register read signals MRR_RL<5:0> by a buffer circuit 116 and supplied to the mode register 109. When the mode register read signals MRR_RL<5:0> are sequentially activated, the mode register 109 outputs mode signals MRR<3:0> to the I / O buffer circuit 105 in response thereto. The read decode signal RDdec<19> is supplied to a selection circuit 117. As shown in FIG. 2, the selection circuit 117 is a circuit that selects one of the read decode signals RDdec<19> and the read decode signal RDdec<18> based on the write timing signal WRWL and outputs the selected signal as a read timing signal RDsft<19>. Figure 4As shown, the selection circuit 117 includes an SR latch circuit 401, which reads the decoding signal RDdec. <19> Set and respond to the read decoding signal RDdec <19> The selection signal MRRSEL is activated. When the selection signal MRRSEL is activated, the I / O buffer circuit 105 outputs the mode signal MRR<3:0> to the outside. On the other hand, when the selection signal MRRSEL is in an invalid state, the I / O buffer circuit 105 outputs the read data read from the memory cell array 101 to the outside. The selection circuit 117 further includes an AND gate circuit 402, which receives the read shift signal RDsft<21:24> and resets the SR latch circuit 401 to deactivate the selection signal MRRSEL in response to the state where all read shift signals RDsft<21:24> are activated. Read decoding signal RDdec <22> The pulse width is extended from 1T to 4T via command expander 118. That is, the decoded signal RDdec is read. <22> The extended pulse width is four clock cycles (=4T) of the internal clock signal PCLK. The read / decode signal RDdec, with its pulse width extended to 4T, is then used. <22> and read the shift signal RDsft <22> The signal is supplied to the OR gate 114. The OR gate 114 generates the read timing signal preQed and supplies the generated read timing signal preQed to the control circuit 108. The read shift signal RDsft or read decode signal RDdec input to the OR gate 114 does not need to be the read shift signal RDsft. <22> Or read the decoded signal RDdec <22> Furthermore, it allows input of read shift signals or read decoding signals that vary depending on the read latency.

[0021] When the read timing signal preQed is activated, the control circuit 108 activates the read selection signal COE and the read timing signals Qes and Qed. When the I / O buffer circuit 105 performs a read operation, the read selection signal COE is activated. During the period when the read selection signal COE is activated, the I / O buffer circuit 105 synchronously activates the read timing signals Qes and Qed with the internal clock signal PCLKD. The read timing signal Qes is the signal that enables the output strobe signal DQS, and the read timing signal Qed is the signal that enables the output of read data DQ.

[0022] Figure 5 This is a circuit diagram of a command filter 115 according to an embodiment of the present disclosure. Figure 5 As shown, the command filter 115 contains 10 NOR gates 501 to 510. The NOR gates 5xx receive the corresponding read shift signal RDsft. <x>inverted signal of the read signal, a read shift signal RDsft <x>previous read shift signal RDsft <x-1>and reading the shift signal RDsft <x>The read shift signals RDsft <x+1> are then read, and read decode signals RDdec are generated based on these signals <x>For example, when the corresponding read shift signal RDsft<19> is at a high level and the read signals RDsft<18> and RDsft<20> are at low levels, the "NOR" gate circuit 501 activates the read decode signal RDdec<19> to a high level.

[0023] Figure 6A is a waveform chart for explaining operations performed according to an embodiment of the present disclosure when the read shift signals RDsft<31:0> having a pulse width of 1T are input to the command filter 115. The read shift signals RDsft<31:0> having a pulse width of 1T occur when the internal mode register read command MRR is activated. In the case of the read shift signals RDsft<31:0> having a pulse width of 1T, when a certain read shift signal RDsft <x>When activated to the high level, the read shift signal RDsft <x>read shift signal RDsft of the former <x-1>and the subsequent read shift signal RDsft<x+1> Always in the state of being deactivated to low level, such as Figure 6A As shown. That is, the shift signals RDsft<31:0> are read from each other and do not overlap. Shift signals are considered "overlapping" when one or more shift signals are high simultaneously. Although the previous pulse (i.e., RDsft)... <0> The falling edge of ) and the next pulse (i.e., RDsft) <1> The rising edges of ) may coincide with each other (e.g., as Figure 6A (As shown), however, in this case, the read shift signal containing the previous pulse and the next pulse is not considered "overlapping". Therefore, the waveform of the read decode signal RDdec<28:19> is consistent with the waveform of the read shift signal RDsft<28:19>. That is, the read shift signal RDsft<31:0> with a pulse width of 1T passes through the command filter 115 as is without being filtered by the command filter 115.

[0024] Figure 6B This is a waveform diagram used to explain the operation performed according to embodiments of the present disclosure when a read shift signal RDsft<31:0> with a pulse width of 4T is input to the command filter 115. When the internal read command RD is activated, a read shift signal RDsft<31:0> with a pulse width of 4T appears. In the case where the pulse width of the read shift signal RDsft<31:0> is 4T, when a certain read shift signal RDsft... <x>When activated to the high level, the read shift signal RDsft <x>read shift signal RDsft of the former <x-1>or the read shift signal RDsft <x+1> of the one after it is always in the state of being activated to the high level, as Figure 6B That is, the read shift signal RDsft <x>During the period of action, the next read shift signal RDsft < x+1 > becomes high, and thus the partial read shift signals RDsft < 31 : 0 > overlap each other. Therefore, the read decode signals RDdec < 28 : 19 > are all fixed to low. That is, the read shift signals RDsft < 31 : 0 > having a pulse width of 4T are filtered by the command filter 115.

[0025] As a result, when the internal mode register read command MRR is activated, the circuit provided at the subsequent stage of the command filter 115 performs a mode register read operation, whereas when the internal read command RD is activated, the mode register read operation is not performed. In this way, the internal read command RD and the internal mode register read command MRR synthesized by the OR gate circuit 113 are separated by the command filter 115.

[0026] The pulse width of the read decode signal RDdec < 22 > is expanded from 1T to 4T by the command expander 118, and the expanded read decode signal RDdec < 22 > is input to the control circuit 108. Therefore, in the case where the internal read command RD is activated and in the case where the internal mode register read command MRR is activated, the control circuit 108 activates the read selection signal COE and the read timing signals Qes and Qed. Therefore, when the internal read command RD is activated, the I / O buffer circuit 105 outputs the read data DQ read from the memory cell array 101 to the outside, and when the internal mode register read command MRR is activated, the mode signal MRR < 3 : 0 > read from the mode register 109 is output to the outside.

[0027] Figure 7 is a timing chart for explaining the operation of the semiconductor device 100 according to one embodiment. In Figure 7 In the example shown, the read command is issued at time t0, the mode register read command is issued at time tl which is 28 clock cycles (28T) after time t0, and the read command is issued at time t2 which is 4 clock cycles (4T) after time tl. The shortest period from the issuance of the read command to the issuance of the mode register read command is 28 clock cycles (28T), and the shortest period from the issuance of the mode register read command to the issuance of the read command is four clock cycles (4T).

[0028] When a read command is issued from the outside at time tO, the command decoder 103 generates an internal read command RD in response thereto. The pulse width of the internal read command RD is extended to four clock periods (4T) by the command expander 112. The internal read command RD having the pulse width extended to four clock periods (4T) is input to the read command shifter 110, whereby read shift signals RDsft<31:0> having different phases from each other are generated. Since the pulse widths of the read shift signals RDsft<31:0> in response to the internal read command RD are all 4T, the read shift signals RDsft<31:0> are filtered by the command filter 115, and a read decode signal RDdec<28:19> is maintained at a low level. Therefore, a selection signal MRRSEL is brought to a low level. The read shift signal RDsft<22> is converted into a read timing signal preQed by the "OR" gate circuit 114, and is input to the control circuit 108. The control circuit 108 activates a read selection signal COE, and read timing signals Qes and Qed in response to the read timing signal preQed. This enables read data DQ read from the memory cell array 101 to be burst output to the outside.

[0029] Thereafter, when a mode register read command is issued from the outside at time tl, the command decoder 103 generates an internal mode register read command MRR in response thereto. The pulse width of the internal mode register read command MRR is IT. The internal mode register read command MRR is input to the read command shifter 110, whereby read shift signals RDsft<31:0> having different phases from each other are generated. Since the pulse widths of the read shift signals RDsft<31:0> in response to the internal mode register read command MRR are all IT, the read shift signals RDsft<31:0> are not filtered by the command filter 115, and a read decode signal RDdec<28:19> is generated. Therefore, a selection signal MRRSEL is activated to a high level in response to the read decode signal RDdec<19>. Further, mode register read signals MRR_RL<5:0> are generated in response to the read decode signals RDdec<22, 24:28>, and mode signals MRR<3:0> are output to the I / O buffer circuit 105 in response thereto. After the pulse width of the read decode signal RDdec<22> is extended to 4T by the command filter 118, the read decode signal RDdec<22> is input to the control circuit 108 via the "OR" gate circuit 114. Therefore, the mode signals MRR<3:0> read from the mode register 109 are burst output to the outside.

[0030] Thereafter, when a read command is issued from the outside at time t2, the command decoder 103 generates an internal read command RD in response to this. The operation performed in response to this is the same as that performed when the read command is issued at time tO. Because the timing at which the selection circuit 117 becomes high when all the read shift signals RDsft<21:24> become high is reset, the selection signal MRRSEL changes to low. Therefore, the I / O buffer circuit 105 bursts the output of the read data DQ after the mode signal MRR<3:0>.

[0031] In this way, the semiconductor device 100 according to one embodiment of the present application uses the same read command shifter 110 to count the delay of the internal read command RD(4T) having a pulse width of 4T and the delay of the internal mode register read command MRR(lT) having a pulse width of IT. Therefore, the circuit scale can be reduced. Further, the read shift signals RDsft<31:0> generated by the read command shifter 110 are input to the command filter 115. Therefore, the read decode signals RDdec<28:19> can be generated on the basis of the internal mode register read command MRR(lT) on the basis of the read shift signals RDsft<31:0>, while the read shift signals RDsft<31:0> are filtered on the basis of the internal read command RD(4T).

[0032] While the application has been disclosed in connection with certain preferred embodiments and examples, it will be understood that it extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the application and obvious modifications and equivalents thereof. Further, it is intended that the scope of the application extend to all articles made by the process and that the scope of the present application extend to all changes and modifications that come within the meaning and range of equivalents of the recited claims. It is also to be understood that various features and aspects of the disclosed embodiments can be combined or substituted with features and aspects of other embodiments to form new embodiments within the scope of the application. It is intended that the scope of the present application encompass all technical equivalents which perform similar functions, have similar structures or equivalent results, to those described above, regardless of structural similarities or functional similarities.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A semiconductor device comprising: a command shifter configured to receive a command pulse and concurrently generate a plurality of first command shift pulses, wherein each of the plurality of first command shift pulses has a same width as the command pulse and the plurality of first command shift pulses have different phases from one another; and a command filter configured to determine whether a plurality of second command shift pulses are generated corresponding to the plurality of first command shift pulses or are not generated in response to pulse overlap between at least a plurality of the plurality of first command shift pulses.

2. The semiconductor device of claim 1, wherein the command pulse enters a first pulse width in response to a first external command signal and enters a second pulse width different from the first pulse width in response to a second external command signal.

3. The semiconductor device of claim 2, wherein the second pulse width is greater than the first pulse width.

4. The semiconductor device of claim 3, wherein the command shifter is configured to generate the plurality of first command shift pulses in synchronization with a clock signal, wherein the first pulse width is one period of the clock signal, and wherein the second pulse width is greater than one period of the clock signal.

5. The semiconductor device of claim 4, wherein the second pulse width is greater than two periods of the clock signal.

6. The semiconductor device of claim 5, further comprising: a command decoder configured to generate a first internal command signal having the first pulse width in response to the first external command signal and generate a second internal command signal having the first pulse width in response to the second external command signal; and a command expander configured to generate the command pulse having the second pulse width based on the second internal command signal.

7. The semiconductor device of claim 6, wherein the command filter is configured to activate each of the second command shift pulses when an associated one of the first command shift pulses is activated while a preceding one of the first command shift pulses and a following one of the first command shift pulses are deactivated.

8. The semiconductor device of claim 2, further comprising: a memory cell array storing user data; a mode register storing a mode signal; and an I / O buffer circuit, wherein the user data is output to an external via the I / O buffer circuit in response to the first command shift pulse having the second pulse width, and wherein the mode signal is output to the external via the I / O buffer circuit in response to the second command shift pulse.

9. The semiconductor device of claim 8, further comprising a control circuit configured to activate the I / O buffer circuit based on the first command shift pulse having the second pulse width.

10. The semiconductor device of claim 9, further comprising another command expander configured to be supplied with the second command shift pulses to generate third command shift pulses having the second pulse width, wherein the control circuit is further configured to activate the I / O buffer circuit based on the third command shift pulses.

11. The semiconductor device of claim 10, further comprising a selection circuit configured to generate a selection signal that enables the I / O buffer circuit to output the mode signal, wherein the selection circuit is configured to activate the selection signal in response to one predetermined one of the second command shift pulses.

12. The semiconductor device of claim 11, wherein the selection circuit is configured to deactivate the selection signal when two or more predetermined ones of the first command shift pulses are simultaneously active.

13. A semiconductor device comprising: a command decoder configured to be supplied with an external command signal and to generate a first command signal and a second command signal having a first pulse width; a first command expander configured to generate a third command signal having a second pulse width greater than the first pulse width by expanding a pulse width of the second command signal having the first pulse width to the second pulse width; a command shifter supplied with the first command signal and the third command signal and configured to generate a plurality of first shift signals having different phases from each other by shifting the first command signal and the third command signal in synchronization with a clock signal; and a second command expander configured to generate a plurality of second shift signals by expanding a pulse width of the first shift signals having the first pulse width to the second pulse width.

14. The semiconductor device of claim 13, further comprising a command filter connected between the command shifter and the second command expander and configured to filter the first shift signals having the second pulse width.

15. The semiconductor device of claim 14, wherein the command filter is configured to activate each of the second shift signals when an associated one of the first shift signals is activated while a preceding one of the first shift signals and a succeeding one of the first shift signals are deactivated.

16. The semiconductor device of claim 13, further comprising: a mode register configured to store a mode signal; and an I / O buffer circuit, wherein the mode signal is output to an external via the I / O buffer circuit in response to the second shift signals.

17. The semiconductor device of claim 16, further comprising an array of memory cells storing user data, wherein the mode signal is output to the external in response to the second shift signals. wherein in response to the first shift signal having the second pulse width, the user data is output to external via the I / O buffer circuit.

18. A semiconductor device comprising: a command shifter configured to generate a plurality of first shift signals having different phases from each other by shifting a command signal in synchronization with a clock signal; and a command filter configured to be supplied with the first shift signals and generate a plurality of second shift signals having different phases from each other, wherein the command filter is configured to activate each of the second shift signals when an associated one of the first shift signals is activated while a preceding one of the first shift signals and a succeeding one of the first shift signals are deactivated.

19. The semiconductor device of claim 18, wherein the command signal includes a first command signal having one cycle of the clock signal and a second command signal having more than two cycles of the clock signal.

20. The semiconductor device of claim 19, wherein a first occurrence of the second command signal and a second occurrence of the second command signal are integrated such that a logic level of the second command signal is fixed within the first occurrence and the second occurrence.

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