semiconductor memory devices

Abstract

A semiconductor memory device includes a memory cell array, a page buffer, control logic, and a voltage generator. The memory cell array includes memory cells. The page buffer is connected to the memory cells via bit lines and is configured to read data from the memory cells. The control logic generates a control signal for controlling the page buffer. The voltage generator generates an activation voltage for the control signal. The page buffer includes a first transistor between the bit line and a first node, a second transistor between a power supply voltage and a second node, a third transistor between the first node and the second node, a fourth transistor between the second node and a third node, and a fifth transistor between the first node and the third node. The voltage generator controls a first control signal for controlling the fifth transistor based on the temperature of the semiconductor memory device.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to semiconductor memory devices. Background Art

[0002] Semiconductor memory devices can be formed in a two-dimensional structure in which individual strings are horizontally arranged on a semiconductor substrate, or in a three-dimensional structure in which individual strings are vertically stacked on a semiconductor substrate. Three-dimensional memory devices have been designed to address the integration limitations of two-dimensional memory devices and may include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0003] One embodiment of the present disclosure provides a semiconductor memory device having improved read performance according to temperature variation.

[0004] A semiconductor memory device according to one embodiment of the present disclosure includes a memory cell array, a page buffer, control logic, and a voltage generator. The memory cell array includes a plurality of memory cells for storing data. The page buffer is connected to at least one of the plurality of memory cells via a bit line and is configured to read the data stored in the memory cell. The control logic generates a plurality of control signals for controlling the operation of the page buffer. The voltage generator generates activation voltages for the plurality of control signals. The page buffer includes a first transistor connected between the bit line and a first node, a second transistor connected between a power supply voltage and a second node, a third transistor connected between the first node and the second node, a fourth transistor connected between the second node and a third node, and a fifth transistor connected between the first node and the third node. The voltage generator is further configured to control the activation voltage of a first control signal for controlling the fifth transistor among the plurality of control signals based on the temperature of the semiconductor memory device.

[0005] In one embodiment, the first transistor, the third transistor, and the fifth transistor may be NMOS transistors, and the second transistor and the fourth transistor may be PMOS transistors.

[0006] In one embodiment, the voltage generator may increase the activation voltage of the first control signal when the temperature of the semiconductor memory device decreases.

[0007] In one embodiment, the voltage generator may be further configured to control an activation voltage of a second control signal controlling the third transistor among the plurality of control signals based on a temperature of the semiconductor memory device.

[0008] In one embodiment, the voltage generator may increase the activation voltage of the second control signal when the temperature of the semiconductor memory device decreases.

[0009] In one embodiment, the voltage generator may be further configured to control an activation voltage of a third control signal for controlling the first transistor among the plurality of control signals based on a temperature of the semiconductor memory device.

[0010] In one embodiment, the voltage generator may increase the activation voltage of the third control signal when the temperature of the semiconductor memory device decreases.

[0011] In one embodiment, the page buffer may further include: a sixth transistor and a seventh transistor connected in series between the first node and a ground voltage; and a latch circuit connected to a gate of the second transistor and a gate of the seventh transistor.

[0012] In one embodiment, the page buffer may further include an eighth transistor connected between the power supply voltage and the third node.

[0013] In one embodiment, the semiconductor memory device may further include a temperature sensor configured to generate a temperature code by sensing the temperature of the semiconductor memory device. The voltage generator may control activation voltages of the first control signal, the second control signal, and the third control signal based on the temperature code.

[0014] In one embodiment, the voltage generator may include a variable resistor whose resistance value varies based on the temperature code.

[0015] In one embodiment, the activation voltage of the first control signal may be greater than the activation voltage of the second control signal.

[0016] In one embodiment, the activation voltage of the second control signal may be greater than the activation voltage of the third control signal.

[0017] A semiconductor memory device according to another embodiment of the present disclosure includes a page buffer and a voltage generator. The page buffer is connected to a bit line and is configured to sense the threshold voltage of a memory cell. The voltage generator generates an activation voltage for a plurality of control signals to be input to the page buffer. The page buffer includes a first NMOS transistor connected between the bit line and a common node, a first PMOS transistor connected between a power supply voltage and a sense amplifier node, a second NMOS transistor connected between the sense amplifier node and the common node, a second PMOS transistor connected between the sense amplifier node and a sense node, and a third NMOS transistor connected between the common node and the sense node. The voltage generator is configured to control the activation voltage of a sense amplifier sensing signal applied to the gate of the third NMOS transistor among the plurality of control signals based on the temperature of the semiconductor memory device.

[0018] In one embodiment, the voltage generator may be further configured to control an activation voltage of a current sensing signal applied to a gate of the second NMOS transistor among the plurality of control signals based on a temperature of the semiconductor memory device.

[0019] In one embodiment, when the temperature of the semiconductor memory device decreases, the voltage generator may increase an activation voltage of the sense amplifier sensing signal and an activation voltage of the current sensing signal.

[0020] In one embodiment, the activation voltage of the sense amplifier sensing signal may be greater than the activation voltage of the current sensing signal.

[0021] In one embodiment, the voltage generator may be further configured to control an activation voltage of the page buffer sensing signal applied to the gate of the first NMOS transistor among the plurality of control signals based on a temperature of the semiconductor memory device.

[0022] In one embodiment, when the temperature of the semiconductor memory device decreases, the voltage generator may increase the activation voltage of the page buffer sensing signal.

[0023] In one embodiment, the page buffer transistor may further include a fourth NMOS transistor and a fifth NMOS transistor connected in series between a common node and a ground voltage, a third PMOS transistor connected between a power supply voltage and a sensing node, and a sensing latch circuit connected to a gate of the first PMOS transistor and a gate of the fifth NMOS transistor.

[0024] A semiconductor memory device according to another embodiment of the present disclosure includes a memory cell array, a page buffer, and a voltage controller. The memory cell array is connected to a bit line. The page buffer is configured to electrically connect the bit line and the common node according to the activation voltage level of the page buffer sensing signal, maintain the voltage level of the common node according to the activation voltage level of the current sensing signal, electrically connect the common node and the sensing node according to the activation voltage level of the sense amplifier sensing signal, and latch data corresponding to the voltage level of the sensing node. The voltage controller is configured to independently adjust each activation voltage level to a different level according to the temperature of the device. The voltage controller is also configured to prevent a reduction in the margin between the activation voltage level of the current sensing signal and the activation voltage level of the sense amplifier sensing signal.

[0025] The present technology can provide a semiconductor memory device having improved read performance according to temperature changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0027] Figure 2 is to show that Figure 1 A memory cell array is a block diagram of an embodiment of such a memory cell array.

[0028] Figure 3 is to show that Figure 1 FIG. 1 is a diagram of an embodiment of such a memory cell array.

[0029] Figure 4 is to show that Figure 1 FIG. 1 is a diagram of another embodiment of such a memory cell array.

[0030] Figure 5 is a circuit diagram illustrating a page buffer of a semiconductor memory device according to an embodiment of the present disclosure.

[0031] Figure 6 is a graph showing operating characteristics of a memory cell according to temperature.

[0032] Figure 7 is a circuit diagram illustrating a voltage generator that generates an activation voltage of a page buffer sensing signal and an activation voltage of a current sensing signal according to an embodiment of the present disclosure.

[0033] Figure 8 is a timing diagram illustrating control signals of a semiconductor memory device according to an embodiment of the present disclosure.

[0034] Figure 9 is a circuit diagram illustrating a voltage generator that generates an activation voltage of a page buffer sensing signal, an activation voltage of a current sensing signal, and an activation voltage of a sense amplifier sensing signal according to an embodiment of the present disclosure.

[0035] Figure 10 is a timing diagram illustrating control signals of a semiconductor memory device according to an embodiment of the present disclosure.

[0036] Figure 11 It is shown that including Figure 1 A semiconductor memory device is a block diagram of a memory system of such a semiconductor memory device.

[0037] Figure 12 is to show that Figure 11 A block diagram of an example application of such a memory system is shown.

[0038] Figure 13 It is shown that including Figure 12 A memory system of a computing system is a block diagram of such a memory system. DETAILED DESCRIPTION

[0039] The specific structural and functional descriptions provided herein are intended only to describe embodiments of the present disclosure. However, the present invention can be implemented in various ways and in various forms. Therefore, the present invention is not limited to the embodiments described herein. Throughout this specification, references to "one embodiment" or "another embodiment" are not necessarily limited to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment.

[0040] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0041] Reference Figure 1 , the semiconductor memory device 100 includes a memory cell array 110 , an address decoder 120 , a read and write circuit 130 , a control logic 140 , a voltage generator 150 , and a temperature sensor 160 .

[0042] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz, which are connected to the address decoder 120 via word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read and write circuit 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells are non-volatile memory cells, which may be configured with a vertical channel structure. The memory cell array 110 may be configured as a two-dimensional memory cell array. According to another embodiment, the memory cell array 110 may be configured as a three-dimensional memory cell array. Each of the plurality of memory cells in the memory cell array may store at least one bit of data. In various embodiments, each of the plurality of memory cells in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) storing four bits of data. According to another embodiment, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

[0043] The address decoder 120, the read and write circuit 130, the control logic 140, the voltage generator 150, and the temperature sensor 160 serve as peripheral circuits for driving the memory cell array 110. The address decoder 120 is connected to the memory cell array 110 through word lines WL. The address decoder 120 is configured to operate in response to the control of the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) inside the semiconductor memory device 100.

[0044] The address decoder 120 is configured to decode a block address from among the received addresses. The address decoder 120 selects at least one memory block based on the decoded block address. Furthermore, during a read voltage application operation during a read operation, the address decoder 120 applies a read voltage Vread generated in the voltage generator 150 to a selected word line of the selected memory block, and applies a pass voltage Vpass to the remaining unselected word lines. Furthermore, during a program verification operation, the address decoder 120 applies a verification voltage generated in the voltage generator 150 to a selected word line of the selected memory block, and applies a pass voltage Vpass to the remaining unselected word lines.

[0045] The address decoder 120 is configured to decode the column address of the received address and transmit the decoded column address to the read and write circuit 130 .

[0046] The read and program operations of the semiconductor memory device 100 are performed in units of pages. The addresses received when requesting read and program operations include a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line based on the block address and the row address. The column address is decoded by the address decoder 120 and provided to the read and write circuit 130.

[0047] The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

[0048] The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during a read operation of the memory cell array 110, and can operate as a "write circuit" during a write operation of the memory cell array 110. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. During a read operation and a program verification operation, in order to sense the threshold voltage of a memory cell, the plurality of page buffers PB1 to PBm senses a change in the amount of flowing current according to the programming state of the corresponding memory cell through a sensing node while continuously supplying a sensing current to the bit line connected to the memory cell, and latches the sensed change as sensing data. The read and write circuit 130 responds to a page buffer control signal CTR output from the control logic 140. PB And operate.

[0049] During a read operation, the read and write circuit 130 senses data of a memory cell, temporarily stores the read data, and outputs the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, the read and write circuit 130 may further include a column selection circuit, etc., in addition to a page buffer (or page register).

[0050] The control logic 140 is connected to the address decoder 120, the read and write circuit 130, and the voltage generator 150. The control logic 140 receives a command CMD and a control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 is configured to control the overall operation of the semiconductor memory device 100 in response to the control signal CTRL. In addition, the control logic 140 outputs a control signal CTR for controlling a plurality of page buffers PB1 to PBm included in the read and write circuit 130. PB The control logic 140 may control the read and write circuit 130 to perform a read operation on the memory cell array 110 .

[0051] The voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a voltage generator control signal output from the control logic 140. In addition, the voltage generator 150 may generate voltages for generating various control signals for controlling operations of the semiconductor memory device.

[0052] The temperature sensor 160 can sense the temperature of the semiconductor memory device 100 and generate a temperature code T based on the sensing result. CODE , and the temperature code T CODE Transmitted to voltage generator 150. Temperature code T CODE The voltage generator 150 may be a digital code indicating the temperature of the semiconductor memory device sensed. CODE To control at least some voltages required for the operation of the semiconductor memory device 100.

[0053] The control logic 140 may output a control signal CTR for controlling the plurality of page buffers PB1 to PBm included in the read and write circuit 130. PB The control signal CTR may be generated based on the voltage generated by the voltage generator 150. PB The temperature sensor 160 can generate a temperature code T based on the sensed temperature of the semiconductor memory device 100. CODE Output to voltage generator 150. Voltage generator 150 can be based on temperature code T CODE To control the generation of at least one control signal CTR PB voltage level.

[0054] Generally, the operating characteristics of the memory cells included in the memory cell array 110 may vary according to temperature variations. In this case, when a constant control signal CTR is used regardless of temperature, PBAccording to one embodiment of the present disclosure, the control signal CTR for controlling the page buffers PB1 to PBm is controlled according to the temperature change of the semiconductor memory device 100. PB and thus, it is possible to prevent the reliability of the read operation from being reduced due to temperature changes.

[0055] Figure 2 It shows Figure 1 A block diagram of an embodiment of a memory cell array.

[0056] Reference Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged along the +X, +Y and +Z directions. Figure 3 and Figure 4 The structure of a representative three-dimensional storage block is described in more detail. In another embodiment, Figure 2 Different from the structure shown, each memory block of the memory cell array 110 may have a two-dimensional structure.

[0057] Figure 3 It shows Figure 1 FIG. 1 is a diagram of one embodiment 110_1 of a memory cell array 110 .

[0058] Reference Figure 3 , the memory cell array 110_1 includes a plurality of memory blocks BLK1 to BLKz. Figure 3 , an internal configuration of a first memory block BLK1 representing each of the other memory blocks BLK2 to BLKz is shown by way of example. Each of the second to z-th memory blocks BLK2 to BLKz is configured similarly to the first memory block BLK1.

[0059] Reference Figure 3 , the first memory block BLK1 includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the first memory block BLK1, m cell strings are arranged in a row direction (ie, +X direction). Figure 3 In FIG. 2 , two cell strings are arranged in the column direction (ie, +Y direction). However, this is for clarity of illustration; three or more cell strings may be arranged in the column direction.

[0060] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0061] Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. In one embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. In one embodiment, a pillar for providing a channel layer may be provided in each cell string. In one embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating film, the charge storage film, and the blocking insulating film may be provided in each cell string.

[0062] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

[0063] In one embodiment, the source selection transistors of cell strings arranged in the same row are connected to one source selection line extending in the row direction, and the source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 4 , the source selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first source selection line SSL1, and the source selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second source selection line SSL2.

[0064] In another embodiment, the source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0065] The first to nth memory cells MC1 to MCn of each cell string are connected between a source select transistor SST and a drain select transistor DST.

[0066] The first to nth memory cells MC1 to MCn can be divided into first to pth memory cells MC1 and (p+1)th memory cells MCp+1 to nth memory cells MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in the -Z direction and are connected in series between the source select transistor SST and the tubular transistor PT. The (p+1)th memory cells MCp+1 to nth memory cells MCn are arranged sequentially in the +Z direction and are connected in series between the tubular transistor PT and the drain select transistor DST. The first to pth memory cells MC1 and (p+1)th memory cells MCp+1 to nth memory cells MCn are connected to each other via the tubular transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are connected to the first to nth word lines WL1 to WLn, respectively.

[0067] The gate of the tube transistor PT of each cell string is connected to the pipeline PL.

[0068] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0069] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. Figure 4 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1, and the cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

[0070] Memory cells connected to the same word line in cell strings arranged in the row direction constitute a page. For example, the memory cells connected to the first word line WL1 in the cell strings CS11 to CS1m in the first row constitute one page. The memory cells connected to the first word line WL1 in the cell strings CS21 to CS2m in the second row constitute another page. Cell strings arranged in a row direction can be selected by selecting any one of the drain select lines DSL1 and DSL2. A page of the selected cell strings can be selected by selecting any one of the word lines WL1 to WLn.

[0071] Figure 4 It shows Figure 1 FIG. 1 is a diagram of another embodiment 110_2 of the memory cell array 110 .

[0072] Reference Figure 4, the memory cell array 110_2 includes a plurality of memory blocks BLK1' to BLKz'. Figure 4 , the internal configuration of the first memory block BLK1' representing each of the other memory blocks BLK2' to BLKz' is shown by way of example. It can be understood that the second memory block BLK2' to the zth memory block BLKz' are configured similarly to the first memory block BLK1'.

[0073] The first memory block BLK1' includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. In the first memory block BLK1', m cell strings are arranged in the +X direction. Figure 4 In FIG, two cell strings are arranged in the +Y direction. However, this is for clarity of illustration; three or more cell strings may be arranged in the column direction.

[0074] Each of the plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′ includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0075] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MCl to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to a second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' can be connected to a common source select line.

[0076] The first to nth memory cells MC1 to MCn of each cell string are connected in series between a source select transistor SST and a drain select transistor DST, and gates of the first to nth memory cells MC1 to MCn are connected to first to nth word lines WL1 to WLn, respectively.

[0077] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0078] As a result, in addition to excluding the tube transistor PT from each cell string, Figure 4 The memory block BLK1' has a similar Figure 3 The equivalent circuit of the memory block BLK1.

[0079] Figure 5 is a circuit diagram illustrating a page buffer PB1 included in the semiconductor memory device 100 according to an embodiment of the present disclosure. Figure 5 PB1 shown represents Figure 1 Any one of the page buffers PB1 to PBm in the read and write circuit 130. That is, each of the plurality of page buffers PB1 to PBm in the read and write circuit 130 may be similarly configured; therefore, the page buffer PB1 will be described as an example.

[0080] The page buffer PB1 may operate in response to signals output from the control logic 140. Signals PB_SENSE, SA_PRECH_N, SA_SENSE, SA_CSOC, SA_DISCH, and PRECHSO_N described below may be included in the control signal CTR output from the control logic 140. PB middle.

[0081] Reference Figure 5 The page buffer PB1 can be connected to the memory cell through the bit line BL1 and can perform a bit line precharge operation of charging the bit line BL1 with charge supplied from the power supply voltage VCORE through the first to fifth NMOS transistors N1 to N5 and the first to third PMOS transistors P1 to P3. In addition, the page buffer PB1 can discharge the charge in the bit line BL1 to the ground voltage through the first NMOS transistor N1, the fourth NMOS transistor N4, and the fifth NMOS transistor N5.

[0082] A first NMOS transistor N1 is connected between a bit line BL1 and a common node CSO. A first PMOS transistor P1 is connected between a power supply voltage VCORE and a sense amplifier node SAN. A second NMOS transistor N2 is connected between the common node CSO and the sense amplifier node SAN. A second PMOS transistor P2 is connected between the sense amplifier node SAN and a sense node SO. A third NMOS transistor N3 is connected between the sense node SO and the common node CSO. A third PMOS transistor P3 is connected between the power supply voltage VCORE and the sense node SO. A fourth transistor N4 and a fifth transistor N5 are connected in series between the common voltage CSO and a ground voltage.

[0083] The first NMOS transistor N1 is controlled by the page buffer sense signal PB_SENSE, the second NMOS transistor N2 is controlled by the current sense signal SA_CSOC, and the third NMOS transistor N3 is controlled by the sense amplifier sense signal SA_SENSE. Furthermore, the fourth NMOS transistor N4 is controlled by the sense amplifier discharge signal SA_DISCH, and the fifth NMOS transistor N5 and the first PMOS transistor P1 are controlled by the voltage at node QS of the sense latch circuit LATS. The second PMOS transistor P2 is controlled by the sense amplifier precharge signal SA_PRECH_N, and the third PMOS transistor P3 is controlled by the sense node precharge signal PRECHSO_N. That is, the page buffer sense signal PB_SENSE is applied to the gate of the first NMOS transistor N1, the current sense signal SA_CSOC is applied to the gate of the second NMOS transistor N2, and the sense amplifier sense signal SA_SENSE is applied to the gate of the third NMOS transistor N3. In addition, the sense amplifier discharge signal SA_DISCH is applied to the gate of the fourth NMOS transistor N4, and the voltage of the node QS of the sense latch circuit LATS is applied to the gate of the fifth NMOS transistor N5 and the gate of the PMOS transistor P1. The sense amplifier precharge signal SA_PRECH_N is applied to the gate of the second PMOS transistor P2, and the sense node precharge signal PRECHSO_N is applied to the gate of the third PMOS transistor P3. The activation voltage level V PB_SENSE The bit line BL1 is electrically connected to the common node CSO. The activation voltage level V of the current sensing signal SA_CSOC is SA_CSOC The voltage level of the common node CSO can be maintained. The activation voltage level V of the sense amplifier sensing signal SA_SENSE SA_SENSE The common node CSO and the sensing node SO are electrically coupled. The voltage level of the sensing node SO is latched by the sensing latch circuit LATS. The activation voltage level (or activation voltage) V PB_SENSE、V SA_CSOC and V SA_SENSE .

[0084] The sensing latch circuit LATS may include a latch composed of two inverters (not shown) connected to the node QS, and a reset transistor (not shown) and a set transistor (not shown) for controlling the voltage of the node QS. Since this structure of the sensing latch circuit LATS is well known, Figure 5 The detailed configuration thereof is omitted in FIG. 1. The sense latch circuit LATS may control the bit line precharge operation by turning on or off the first PMOS transistor P1 via the voltage of the node QS.

[0085] During a memory cell sensing operation, the voltage of the sense node SO is determined based on the threshold voltage of the memory cell MC. For example, the voltage of the bit line BL1 can be determined based on the threshold voltage of the selected memory cell. When the first NMOS transistor N1 and the third NMOS transistor N3 are turned on, the bit line BL1 and the sense node SO are electrically connected via the common node CSO. Therefore, the voltage of the sense node SO can be determined based on the threshold voltage of the selected memory cell. The sense latch circuit LATS can store the result of sensing the threshold voltage of the memory cell. More specifically, the sense latch circuit LATS can latch data corresponding to the potential level of the sense node SO.

[0086] According to one embodiment of the present disclosure, during a read operation or a program verification operation, the page buffer sense signal PB_SENSE applied to the first NMOS transistor N1 can be adjusted according to the temperature of the semiconductor memory device 100. In this specification, the "activation voltage" of a control signal may refer to a voltage level corresponding to a logic high state of the control signal. For example, the activation voltage of the page buffer sense signal PB_SENSE may be a relatively high voltage level of the page buffer sense signal PB_SENSE for turning on the first NMOS transistor. In contrast, the "deactivation voltage" of the control signal may refer to a voltage level corresponding to a logic low state of the control signal. For example, the deactivation voltage of the page buffer sense signal PB_SENSE may be a relatively low voltage level (e.g., a ground voltage) of the page buffer sense signal PB_SENSE for turning off the first NMOS transistor. More specifically, during a bit line precharge operation in a read operation or a program verification operation, the activation voltage of the page buffer sense signal PB_SENSE applied to the first NMOS transistor N1 may be adjusted according to the temperature of the semiconductor memory device 100. For example, as the temperature of the semiconductor memory device 100 decreases, the activation voltage of the page buffer sense signal PB_SENSE applied to the first NMOS transistor N1 may increase to a relatively high level. Similarly, as the temperature of the semiconductor memory device 100 increases, the activation voltage of the page buffer sense signal PB_SENSE applied to the first NMOS transistor N1 may decrease to a relatively low level.

[0087] According to one embodiment of the present disclosure, during a read operation or a program verification operation, the current sensing signal SA_CSOC applied to the second NMOS transistor N2 may be adjusted according to the temperature of the semiconductor memory device 100. More specifically, during a bit line precharge operation in the read operation or the program verification operation, the activation voltage of the current sensing signal SA_CSOC applied to the second NMOS transistor N2 may be adjusted according to the temperature of the semiconductor memory device 100. For example, as the temperature of the semiconductor memory device 100 decreases, the activation voltage of the current sensing signal SA_CSOC applied to the second NMOS transistor N2 may increase to a relatively high level. Similarly, as the temperature of the semiconductor memory device 100 increases, the activation voltage of the current sensing signal SA_CSOC applied to the second NMOS transistor N2 may decrease to a relatively low level.

[0088] Figure 6 is a graph showing the operating characteristics of a memory cell according to temperature. Figure 6, showing the gate voltage Vg and the cell current I according to the temperature of the semiconductor memory device during a read operation or a program verification operation on a selected memory cell CELL The relationship between them.

[0089] like Figure 6 As shown, under the same gate voltage Vg, when the temperature of the semiconductor memory device 100 is higher, the cell current I flowing through the memory cell CELL When the temperature of the semiconductor memory device 100 is low, the cell current I flowing through the memory cell is large. CELL This means that the amount of the reference current Itrip may vary as the temperature of the semiconductor memory device 100 changes between a high current (hot state) and a low current (cold state).

[0090] According to one embodiment of the present disclosure, in order to compensate for the characteristics of the memory cell according to temperature changes, during a read operation or a program verification operation, the control signal CTR applied to the page buffer may be determined based on the temperature. PB The activation voltage of the page buffer sense signal PB_SENSE and the activation voltage of the current sense signal SA_CSOC are adjusted. That is, as the temperature of the semiconductor memory device 100 decreases, the activation voltage of the page buffer sense signal PB_SENSE applied to the first NMOS transistor N1 and the activation voltage of the current sense signal SA_CSOC applied to the second NMOS transistor N2 can increase to a relatively high level. Similarly, as the temperature of the semiconductor memory device 100 increases, the activation voltage of the page buffer sense signal PB_SENSE applied to the first NMOS transistor N1 and the activation voltage of the current sense signal SA_CSOC applied to the second NMOS transistor N2 can decrease to a relatively low level. Therefore, changes in the current flowing through the memory cell can be compensated when the temperature changes. Therefore, the read performance or program verification performance of the semiconductor memory device can be improved.

[0091] Figure 7 is a circuit diagram illustrating a voltage generator 150 a that generates an activation voltage of a page buffer sensing signal PB_SENSE and an activation voltage of a current sensing signal SA_CSOC according to an embodiment of the present disclosure. Figure 7 The voltage generator 150a shown is Figure 1 An example of a voltage generator 150 is shown.

[0092] Reference Figure 7 The voltage generator 150a may include transistors TR1, TR2, TR3 and TR4, operational amplifiers AMP1, AMP2 and AMP3, and resistors R1 and R V1. Transistors TR1 and TR3 are connected in series at a high voltage V H and low voltage V L Between transistor TR2, resistor R1, transistor TR4 and resistor R V1 Connect in series with a high voltage V H and low voltage V L The transistors TR1 and TR2 may be PMOS transistors, and the transistors TR3 and TR4 may be NMOS transistors. The output terminal of the operational amplifier AMP1 is connected to the gate terminal of the transistor TR3. In addition, the inverting input terminal of the operational amplifier AMP1 is connected to the low voltage V L Bandgap reference voltage V BGR It is input to the non-inverting input terminal of the operational amplifier AMP1. BGR It is insensitive to temperature changes and can be generated by a bandgap reference voltage generation circuit. The bandgap reference voltage generation circuit can generate a temperature-insensitive bandgap reference voltage V by appropriately combining a voltage proportional to absolute temperature (PTAT) and a voltage complementary to absolute temperature (CTAT). BGR A bandgap reference voltage generating circuit may also be included in the voltage generator 150a.

[0093] The non-inverting input terminal of operational amplifier AMP3 is connected to node Nd1, which is connected to resistor R1 and transistor TR4. The inverting input terminal of operational amplifier AMP3 is connected to the output terminal of operational amplifier AMP3. The non-inverting input terminal of operational amplifier AMP2 is connected to node Nd2, which is connected to resistor R1 and transistor TR2. The inverting input terminal of operational amplifier AMP2 is connected to the output terminal of operational amplifier AMP2. In other words, operational amplifiers AMP2 and AMP3 can be buffer circuits with a gain of 1.

[0094] Transistors TR1, TR2 and TR3 can form a current mirror. BGR It is not sensitive to temperature changes, so even if the high voltage V H and low voltage V L A constant current may also flow through the transistor TR2 in accordance with the temperature change.

[0095] The resistor R1 may be a fixed value resistor, and the resistor R V1 It can be a variable resistor. More specifically, the resistor R V1 The resistance value can be determined based on the temperature code T received from the temperature sensor 160. CODE For example, when the temperature code T CODE When indicating high temperature, the resistor RV1 The value can be reduced, and when the temperature code T CODE When indicating low temperature, the resistor R V1 The value can be increased.

[0096] When the resistor R V1 When the value of decreases, the activation voltage V of the page buffer sense signal PB_SENSE output from the operational amplifier AMP3 PB_SENSE Similarly, when the resistor R V1 When the value of decreases, the activation voltage V of the current sensing signal SA_CSOC output from the operational amplifier AMP2 SA_CSOC It can also be reduced.

[0097] That is, when the temperature of the semiconductor memory device 100 increases, the resistor R V1 The value of can be reduced, so the activation voltage V PB_SENSE and the activation voltage V of the current sensing signal SA_CSOC SA_CSOC Can be reduced.

[0098] On the contrary, when the temperature of the semiconductor memory device 100 decreases, the resistor R V1 The value of can be increased, so the activation voltage V PB_SENSE and the activation voltage V of the current sensing signal SA_CSOC SA_CSOC Can be enlarged.

[0099] according to Figure 7 As shown in the circuit diagram, according to the voltage distribution principle, the activation voltage V SA_CSOC is greater than the activation voltage V of the page buffer sensing signal PB_SENSE PB_SENSE .

[0100] Figure 8 1 is a diagram showing a control signal CTR of a semiconductor memory device according to an embodiment of the present disclosure. PB As described above, the control signal CTR output from the control logic 140 and applied to the page buffers PB1 to PBm PB Includes a sense amplifier precharge signal SA_PRECH_N, a sense amplifier sense signal SA_SENSE, a current sense signal SA_CSOC, and a page buffer sense signal PB_SENSE.

[0101] The activation voltage of the sense amplifier sensing signal SA_SENSE may be the power supply voltage VCORE. When the temperature of the semiconductor memory device 100 is relatively high, the activation voltage of the page buffer sensing signal PB_SENSE may be the first voltage V1, and the activation voltage of the current sensing signal SA_CSOC may be the second voltage V2. When the semiconductor memory device 100 is in a high temperature state, the first voltage V1 may be the voltage generated by the current sensing signal SA_CSOC. Figure 7 The activation voltage V of the page buffer sensing signal PB_SENSE output by the voltage generator 150a is PB_SENSE In addition, when the semiconductor memory device 100 is in a high temperature state, the second voltage V2 may be Figure 7 The activation voltage V of the current sensing signal SA_CSOC output by the voltage generator 150a is SA_CSOC As mentioned above, according to the voltage distribution principle, the activation voltage V of the current sensing signal SA_CSOC is SA_CSOC is greater than the activation voltage V of the page buffer sensing signal PB_SENSE PB_SENSE Therefore, the second voltage V2 may be greater than the first voltage V1.

[0102] When the temperature of the semiconductor memory device 100 changes from a relatively high temperature to a relatively low temperature, the activation voltage of the page buffer sense signal PB_SENSE can be obtained by increasing the first voltage V1 by a first deviation Δa. In addition, when the temperature of the semiconductor memory device 100 changes from a relatively high temperature to a relatively low temperature, the activation voltage of the current sense signal SA_CSOC can be obtained by increasing the second voltage V2 by a second deviation Δb. Figure 7 As described above, when the temperature of the semiconductor memory device 100 decreases, the resistor R V1 The value of can be increased, so the activation voltage V PB_SENSE and the activation voltage V of the current sensing signal SA_CSOC SA_CSOC Can be enlarged.

[0103] according to Figure 7 and Figure 8 In the embodiment shown, when the temperature changes, the activation voltage V PB_SENSE and the activation voltage V of the current sensing signal SA_CSOC SA_CSOCThe activation voltage of the sense amplifier sense signal SA_SENSE is fixed to the power supply voltage VCORE. To ensure stable operation of the page buffer PB1, the activation voltage of the sense amplifier sense signal SA_SENSE is designed to be greater than the activation voltage of the current sense signal SA_CSOC. As the activation voltage of the current sense signal SA_CSOC increases as the temperature of the semiconductor memory device 100 decreases, the margin between the activation voltages of the sense amplifier sense signal SA_SENSE and the current sense signal SA_CSOC decreases. If this margin is not sufficiently maintained, the operational stability of the page buffer PB1 may be reduced.

[0104] According to another embodiment of the present disclosure, the activation voltage of the sense amplifier sensing signal SA_SENSE can be adjusted together with the activation voltage of the current sensing signal SA_CSOC according to temperature changes in the semiconductor memory device 100. That is, when the activation voltage of the current sensing signal SA_CSOC increases as the temperature of the semiconductor memory device 100 decreases, the activation voltage of the sense amplifier sensing signal SA_SENSE can also increase. Therefore, even when the activation voltage of the current sensing signal SA_CSOC increases to compensate for changes in the current flowing through the memory cells due to temperature changes in the semiconductor memory device 100, the margin between the activation voltage of the sense amplifier sensing signal SA_SENSE and the activation voltage of the current sensing signal SA_CSOC can be sufficiently ensured. Therefore, the operational stability of the page buffer PB1 can be improved.

[0105] Figure 9 is a circuit diagram illustrating a voltage generator 150 b that generates an activation voltage of a page buffer sensing signal PB_SENSE, an activation voltage of a current sensing signal SA_CSOC, and an activation voltage of a sense amplifier sensing signal SA_SENSE according to an embodiment of the present disclosure. Figure 9 The voltage generator 150b shown in FIG. Figure 1 An example of a voltage generator 150 is shown in FIG.

[0106] Reference Figure 9 The voltage generator 150b may include transistors TR5, TR6, TR7 and TR8, operational amplifiers AMP5, AMP6, AMP7 and AMP8, and resistors R3, R2 and R V2 . Transistors TR5 and TR7 are connected in series at a high voltage V H and low voltage V L Between transistor TR6, resistor R3, resistor R2, transistor TR8 and resistor R V2 Connect in series with a high voltage V H and low voltage VL The transistors TR5 and TR6 may be PMOS transistors, and the transistors TR7 and TR8 may be NMOS transistors. The output terminal of the operational amplifier AMP5 is connected to the gate terminal of the transistor TR7. In addition, the inverting input terminal of the operational amplifier AMP5 is connected to the low voltage V L Bandgap reference voltage V BGR It is input to the non-inverting input terminal of the operational amplifier AMP5. BGR It is insensitive to temperature changes and can be generated by a bandgap reference voltage generation circuit. The bandgap reference voltage generation circuit can generate a temperature-insensitive bandgap reference voltage V by appropriately combining a voltage proportional to absolute temperature (PTAT) and a voltage complementary to absolute temperature (CTAT). BGR A bandgap reference voltage generating circuit may also be included in the voltage generator 150b.

[0107] The non-inverting input terminal of operational amplifier AMP8 is connected to node Nd3, which is connected to resistor R2 and transistor TR8. The inverting input terminal of operational amplifier AMP8 is connected to the output terminal of operational amplifier AMP8. The non-inverting input terminal of operational amplifier AMP7 is connected to node Nd4, which is connected to resistor R2 and resistor R3. The inverting input terminal of operational amplifier AMP7 is connected to the output terminal of operational amplifier AMP7. The non-inverting input terminal of operational amplifier AMP6 is connected to node Nd5, which is connected to resistor R3 and transistor TR6. The inverting input terminal of operational amplifier AMP6 is connected to the output terminal of operational amplifier AMP6. In other words, operational amplifiers AMP6, AMP7, and AMP8 can be buffer circuits with a gain of 1.

[0108] Transistors TR5, TR6 and TR7 can form a current mirror. BGR It is not sensitive to temperature changes, so even if the high voltage V H and low voltage V L A constant current may also flow through the transistor TR6 in accordance with the temperature variation.

[0109] Resistors R2 and R3 may be fixed value resistors, and resistor R V2 It can be a variable resistor. More specifically, the resistor R V2 The resistance value can be determined based on the temperature code T received from the temperature sensor 160. CODE For example, when the temperature code T CODE When indicating high temperature, the resistor R V2 The value can be reduced, and when the temperature code T CODE Indicates low temperature, resistor R V2 The value can be increased.

[0110] When the resistor R V2 When the value of decreases, the activation voltage V of the page buffer sense signal PB_SENSE output from the operational amplifier AMP8 PB_SENSE Similarly, when the resistor R V2 When the value of decreases, the activation voltage V of the current sensing signal SA_CSOC output from the operational amplifier AMP7 SA_CSOC It can also be reduced. When the resistor R V2 When the value of decreases, the activation voltage V of the sense amplifier sensing signal SA_SENSE output from the operational amplifier AMP6 SA_SENSE It can also be reduced.

[0111] That is, when the temperature of the semiconductor memory device 100 increases, the resistor R V2 The value of can be reduced, so the activation voltage V PB_SENSE , the activation voltage V of the current sensing signal SA_CSOC SA_CSOC and the activation voltage V of the sense amplifier sensing signal SA_SENSE SA_SENSE Can be reduced.

[0112] On the contrary, when the temperature of the semiconductor memory device 100 decreases, the resistor R V2 The value of can be increased, so the activation voltage V PB_SENSE , the activation voltage V of the current sensing signal SA_CSOC SA_CSOC and the activation voltage V of the sense amplifier sensing signal SA_SENSE SA_SENSE Can be enlarged.

[0113] according to Figure 9 As shown in the circuit diagram, according to the voltage distribution principle, the activation voltage V SA_CSOC is greater than the activation voltage V of the page buffer sensing signal PB_SENSE PB_SENSE , and the sense amplifier senses the activation voltage V of the signal SA_SENSE SA_SENSE is greater than the activation voltage V of the current sensing signal SA_CSOC SA_CSOC .according to Figure 9 The circuit diagram shown in FIG. 1 shows an embodiment including only one variable resistor, but the present disclosure is not limited thereto. For example, at least one of the resistor R2 or the resistor R3 can be configured as a variable resistor. In such an embodiment, when the temperature code T CODE When a high temperature is indicated, the value of the variable resistor replacing R2 or R3 can be reduced, and when the temperature code T CODE When a low temperature is indicated, the value of the variable resistor replacing R2 or R3 can be increased.

[0114] Figure 10 1 is a diagram showing a control signal CTR of a semiconductor memory device according to an embodiment of the present disclosure. PB As described above, the control signal CTR output from the control logic 140 and applied to the page buffers PB1 to PBm PB Includes a sense amplifier precharge signal SA_PRECH_N, a sense amplifier sense signal SA_SENSE, a current sense signal SA_CSOC, and a page buffer sense signal PB_SENSE.

[0115] When the semiconductor memory device 100 is in a relatively high temperature state, the activation voltage of the page buffer sensing signal PB_SENSE may be the third voltage V3, and the activation voltage of the current sensing signal SA_CSOC may be the fourth voltage V4. The activation voltage of the sense amplifier sensing signal SA_SENSE may be the fifth voltage V5. In the state where the semiconductor memory device 100 is in a high temperature state, the third voltage V3 may be the activation voltage of the current sensing signal SA_CSOC. Figure 9 The activation voltage V of the page buffer sensing signal PB_SENSE output by the voltage generator 150b is PB_SENSE When the semiconductor memory device 100 is in a high temperature state, the fourth voltage V4 may be Figure 9 The activation voltage V of the current sensing signal SA_CSOC output by the voltage generator 150b is SA_CSOC When the semiconductor memory device 100 is at a high temperature, the fifth voltage V5 may be Figure 9 The activation voltage V of the sense amplifier sensing signal SA_SENSE output by the voltage generator 150b is SA_SENSE As mentioned above, according to the voltage distribution principle, the activation voltage V of the current sensing signal SA_CSOC is SA_CSOC is greater than the activation voltage V of the page buffer sensing signal PB_SENSE PB_SENSE , and the sense amplifier senses the activation voltage V of the signal SA_SENSE SA_SENSE is greater than the activation voltage V of the current sensing signal SA_CSOC SA_CSOC Therefore, the fourth voltage V4 may be greater than the third voltage V3, and the fifth voltage V5 may be greater than the fourth voltage V4.

[0116] When the temperature of the semiconductor memory device 100 changes from a relatively high temperature to a relatively low temperature, the activation voltage of the page buffer sensing signal PB_SENSE can be obtained by increasing the third voltage V3 by a third deviation Δc. In addition, when the temperature of the semiconductor memory device 100 changes from a relatively high temperature to a relatively low temperature, the activation voltage of the current sensing signal SA_CSOC can be obtained by increasing the fourth voltage V4 by a fourth deviation Δd. When the temperature of the semiconductor memory device 100 changes from a relatively high temperature to a relatively low temperature, the activation voltage of the sense amplifier sensing signal SA_SENSE can be obtained by increasing the fifth voltage V5 by a fifth deviation Δe. As described above with reference to Figure 9 As described, when the temperature of the semiconductor memory device 100 decreases, the resistor R V2 The value of can be increased, so the activation voltage V PB_SENSE , the activation voltage V of the current sensing signal SA_CSOC SA_CSOC and the activation voltage V of the sense amplifier sensing signal SA_SENSE SA_SENSE Can be enlarged.

[0117] according to Figure 9 and Figure 10 In the illustrated embodiment, the activation voltage of the sense amplifier sensing signal SA_SENSE can be adjusted together with the activation voltage of the current sensing signal SA_CSOC according to temperature variations of the semiconductor memory device 100. Specifically, as the activation voltage of the current sensing signal SA_CSOC increases as the temperature of the semiconductor memory device 100 decreases, the activation voltage of the sense amplifier sensing signal SA_SENSE can also increase. Therefore, even when the activation voltage of the current sensing signal SA_CSOC increases to compensate for variations in the current flowing through the memory cells due to temperature variations of the semiconductor memory device 100, a sufficient margin can be maintained between the activation voltages of the sense amplifier sensing signal SA_SENSE and the activation voltages of the current sensing signal SA_CSOC. Consequently, the operational stability of the page buffer PB1 can be improved.

[0118] Figure 11 It is shown that Figure 1 1 is a block diagram of a memory system 1000 of a semiconductor memory device 100.

[0119] Reference Figure 11 , the memory system 1000 includes a semiconductor memory device 100 and a controller 1200 .

[0120] The semiconductor memory device 100 can be configured as shown in FIG. Figure 1 Therefore, the semiconductor memory device 100 will not be described further herein.

[0121] The controller 1200 is connected to a host and the semiconductor memory device 100. The controller 1200 is configured to access the semiconductor memory device 100 in response to a request from the host. For example, the controller 1200 is configured to control read, write, erase, and background operations of the semiconductor memory device 100. The controller 1200 is configured to provide an interface between the semiconductor memory device 100 and the host. The controller 1200 is configured to drive firmware for controlling the semiconductor memory device 100.

[0122] The controller 1200 includes a random access memory (RAM) 1210, a processing unit 1220, a host interface 1230, a memory interface 1240, and an error correction block 1250. The RAM 1210 is used as at least one of a working memory of the processing unit 1220, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processing unit 1220 controls the overall operation of the controller 1200.

[0123] The host interface 1230 includes a protocol for performing data exchange between the host and the controller 1200. In one embodiment, the controller 1200 is configured to communicate with the host through at least one of various interface protocols such as a Universal Serial Bus (USB) protocol, a MultiMediaCard (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced MiniDisk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and / or a proprietary protocol.

[0124] The memory interface 1240 interfaces with the semiconductor memory device 100. For example, the memory interface includes a NAND interface or a NOR interface.

[0125] The error correction block 1250 is configured to detect and correct errors of data received from the semiconductor memory device 100 using an error correction code (ECC).

[0126] The controller 1200 and the semiconductor memory device 100 may be integrated into one semiconductor device. In one embodiment, the controller 1200 and the semiconductor memory device 100 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), and / or a Universal Flash Storage (UFS).

[0127] The controller 1200 and the semiconductor memory device 100 may be integrated into a single semiconductor device to configure a semiconductor drive (solid-state drive (SSD)). The semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is significantly improved.

[0128] As another example, the memory system 1000 is provided as one of various components of an electronic device such as a computer, an ultra-portable PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a device capable of sending and receiving information in a wireless environment, one of the various electronic devices configuring a home network, one of the various electronic devices configuring a computer network, one of the various electronic devices configuring a telematics network, an RFID device, or one of the various components configuring a computing system.

[0129] In one embodiment, the semiconductor memory device 100 or the memory system 1000 can be mounted as any of various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 can be packaged and mounted in a method such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle die package, wafer die form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), system in package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level handling package on package (WSP).

[0130] Figure 12 It shows Figure 11 1 is a block diagram of an example application of a memory system 1000.

[0131] Reference Figure 12 , the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups, for example, k groups.

[0132] exist Figure 12 In the embodiment, k groups communicate with the controller 2200 through the first channel CH1 to the kth channel CHk. Figure 2 The described semiconductor memory device 100 is similarly configured and operates.

[0133] Each group is configured to communicate with the controller 2200 via a common channel. The controller 2200 and the reference Figure 11 The described controller 1200 is similarly configured, and is configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

[0134] exist Figure 12 In the embodiment of the present invention, a plurality of semiconductor memory chips of the same group are connected to one channel. However, it is understood that the memory system 2000 can be modified so that each semiconductor memory chip is connected to its own channel.

[0135] Figure 13 It is shown including reference Figure 12 A block diagram of a computing system 3000 is depicted with memory system 2000 .

[0136] Reference Figure 13 , the computing system 3000 includes a central processing unit 3100 , a random access memory (RAM) 3200 , a user interface 3300 , a power supply 3400 , a system bus 3500 , and a memory system 2000 .

[0137] The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0138] exist Figure 13 In the embodiment, the semiconductor memory device 2100 is connected to the system bus 3500 through the controller 2200. However, the semiconductor memory device 2100 may be configured to be directly connected to the system bus 3500. The functions of the controller 2200 may be performed by the central processing unit 3100 and the RAM 3200.

[0139] exist Figure 13 References are provided in Figure 12 However, the memory system 2000 described herein may be used with reference to Figure 11 The memory system 1000 described above may be used to replace the memory system 2000. In another embodiment, the computing system 3000 may be configured to include Figure 11 and Figure 12 Both memory systems 1000 and 2000.

[0140] Although specific embodiments of the present disclosure have been illustrated and described, those skilled in the art will appreciate that various changes and modifications may be made in light of the present disclosure without departing from the scope and technical spirit of the present disclosure. Therefore, the present invention is not limited to the above-described embodiments. On the contrary, the present invention encompasses all variations that fall within the scope of the claims (including their equivalents).

[0141] CROSS-REFERENCE TO RELATED APPLICATIONS

[0142] This application claims priority from Korean Patent Application No. 10-2020-0088923, filed on Jul. 17, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a memory cell array comprising a plurality of memory cells for storing data; a page buffer connected to at least one of the plurality of memory cells through a bit line and configured to read data stored in the memory cell; control logic configured to generate a plurality of control signals for controlling an operation of the page buffer; as well as a voltage generator configured to generate activation voltages of the plurality of control signals, Wherein, the page buffer includes: a first transistor connected between the bit line and a first node; a second transistor connected between the power supply voltage and the second node; a third transistor connected between the first node and the second node; a fourth transistor connected between the second node and a third node; and a fifth transistor connected between the first node and the third node, and The voltage generator is further configured to control an activation voltage of a first control signal for controlling the fifth transistor among the plurality of control signals based on a temperature of the semiconductor memory device, and The activation voltage of the first control signal is greater than the activation voltage of the second control signal for controlling the third transistor among the plurality of control signals.

2. The semiconductor memory device according to claim 1, wherein The first transistor, the third transistor, and the fifth transistor are NMOS transistors, and the second transistor and the fourth transistor are PMOS transistors.

3. The semiconductor memory device according to claim 1, wherein The voltage generator increases an activation voltage of the first control signal when a temperature of the semiconductor memory device decreases.

4. The semiconductor memory device according to claim 1, wherein The voltage generator is further configured to control an activation voltage of the second control signal based on a temperature of the semiconductor memory device.

5. The semiconductor memory device according to claim 4, wherein The voltage generator increases an activation voltage of the second control signal when a temperature of the semiconductor memory device decreases.

6. The semiconductor memory device according to claim 4, wherein The voltage generator is further configured to control an activation voltage of a third control signal controlling the first transistor among the plurality of control signals based on a temperature of the semiconductor memory device.

7. The semiconductor memory device according to claim 6, wherein The voltage generator increases an activation voltage of the third control signal when a temperature of the semiconductor memory device decreases.

8. The semiconductor memory device according to claim 1, wherein The page buffer further includes: a sixth transistor and a seventh transistor connected in series between the first node and a ground voltage; and A latch circuit is connected to the gate of the second transistor and the gate of the seventh transistor.

9. The semiconductor memory device according to claim 8, wherein The page buffer further includes an eighth transistor connected between the power supply voltage and the third node.

10. The semiconductor memory device according to claim 6, The semiconductor memory device further includes a temperature sensor configured to generate a temperature code by sensing a temperature of the semiconductor memory device. in, The voltage generator controls activation voltages of the first control signal, the second control signal, and the third control signal based on the temperature code.

11. The semiconductor memory device according to claim 10, wherein The voltage generator includes a variable resistor whose resistance value varies based on the temperature code.

12. The semiconductor memory device according to claim 10, wherein An activation voltage of the second control signal is greater than an activation voltage of the third control signal.

13. A semiconductor memory device, comprising: a page buffer connected to the bit line and configured to sense a threshold voltage of a memory cell; as well as a voltage generator configured to generate an activation voltage of a plurality of control signals to be input to the page buffer, Wherein, the page buffer includes: a first NMOS transistor connected between the bit line and a common node; a first PMOS transistor connected between a supply voltage and a sense amplifier node; a second NMOS transistor connected between the sense amplifier node and the common node; a second PMOS transistor connected between the sense amplifier node and a sense node; and a third NMOS transistor connected between the common node and the sensing node, and wherein the voltage generator is further configured to control an activation voltage of a sense amplifier sensing signal applied to a gate of the third NMOS transistor among the plurality of control signals based on a temperature of the semiconductor memory device, and The voltage generator is further configured to control an activation voltage of a current sensing signal applied to a gate of the second NMOS transistor among the plurality of control signals based on a temperature of the semiconductor memory device.

14. The semiconductor memory device according to claim 13, wherein When the temperature of the semiconductor memory device decreases, the voltage generator controls the activation voltages of the sense amplifier sensing signal and the current sensing signal by increasing the activation voltages of the sense amplifier sensing signal and the current sensing signal.

15. The semiconductor memory device according to claim 14, wherein An activation voltage of the sense amplifier sensing signal is greater than an activation voltage of the current sensing signal.

16. The semiconductor memory device according to claim 15, wherein The voltage generator is further configured to control an activation voltage of a page buffer sensing signal applied to a gate of the first NMOS transistor among the plurality of control signals based on a temperature of the semiconductor memory device.

17. The semiconductor memory device according to claim 16, wherein The voltage generator increases an activation voltage of the page buffer sensing signal when a temperature of the semiconductor memory device decreases.

18. The semiconductor memory device according to claim 13, wherein The page buffer further includes: a fourth NMOS transistor and a fifth NMOS transistor connected in series between the common node and a ground voltage; a third PMOS transistor connected between the power supply voltage and the sensing node; and A sense latch circuit is connected to a gate of the first PMOS transistor and a gate of the fifth NMOS transistor.

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