A read-write method and read-write circuit based on SOT-MRAM and SOT-MRAM

Abstract

The application provides a read-write method, a read-write circuit and SOT-MRAM based on SOT-MRAM. The read-write method comprises the following steps: inputting a write current into a SOT layer to reverse the magnetization direction of a free layer in a magnetic tunnel junction, so that the magnetization directions of the free layer and a reference layer are in a parallel state or an anti-parallel state; reading the capacitance value of the magnetic tunnel junction; and determining whether the magnetic tunnel junction is in a first state or a second state according to the capacitance value of the magnetic tunnel junction. The capacitance value of the magnetic tunnel junction is read, and whether the magnetic tunnel junction is in the first state or the second state is determined according to the capacitance value of the magnetic tunnel junction, so that the data '0' and '1' in the storage unit are recognized and read. The SOT-MRAM in the magnetic capacitance type has lower requirements for the growth conditions, material selection and sensitivity of the read circuit of the MTJ relative to the SOT-MRAM in the resistance type, so that the growth conditions and material selection of the magnetic tunnel junction of the SOT-MRAM in the magnetic capacitance type are not as harsh as those of the SOT-MRAM in the magnetic resistance type, and the difficulty of manufacturing and reading the SOT-MRAM is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a read / write method, read / write circuit, and SOT-MRAM based on SOT-MRAM. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is one of the most promising new memory technologies, with the potential to replace Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). MRAM is classified into two types based on its writing method: STT and SOT. The core structure of SOT-MRAM consists of a magnetic tunnel junction (MTJ) and an SOT layer adjacent to the free layer of the MTJ. The MTJ is a sandwich structure composed of two ferromagnetic layers and one tunneling layer. Of the two ferromagnetic layers, the magnetization of one layer can be flipped by a current or magnetic field; this is called the free layer. The magnetization of the other layer remains constant; this is called the reference layer (fixed layer). SOT-MRAM is written by using the spin torque generated by the write current through the SOT layer to flip the magnetization direction of the free layer. Reading is done by detecting the resistance of the MTJ. When the magnetization directions of the free layer and the reference layer are parallel, the MTJ is in a low-resistance state; when they are antiparallel, the MTJ is in a high-resistance state. These high and low resistance states can be used to store data "0" and "1". The resistance difference between the high and low resistivity states of MTJ depends on the interface effect of the MTJ multilayer film, which places stringent requirements on the growth conditions of MTJ. This requires maintaining a very high vacuum (10⁻⁶) throughout the entire MTJ fabrication process. -9 The process involves several key considerations, including the presence of water molecules in residual gases. The deposition of the dozen or so extremely thin film layers (approximately 1 nm thick) that constitute the MTJ requires clean, flat interfaces between layers with a variability less than one atomic layer, and no diffusion or mixing between layers. The tunneling layer of the MTJ must also be a single crystal of MgO to achieve the maximum high-resistivity to low-resistivity ratio. Since the other layers of the MTJ must be grown under high vacuum via magnetron sputtering, and single-crystal MgO is very difficult to grow via magnetron sputtering, this process is challenging. Summary of the Invention

[0003] This invention provides a read / write method, read / write circuit, and SOT-MRAM based on SOT-MRAM, thereby reducing the difficulty of manufacturing and reading SOT-MRAM and solving the problem that resistive SOT-MRAM cannot be mass-produced due to its demanding preparation conditions and complex preparation process.

[0004] In a first aspect, the present invention provides a read / write method based on SOT-MRAM, wherein the SOT-MRAM includes a storage cell, the storage cell including an SOT layer and a magnetic tunnel junction disposed on the SOT layer, the magnetic tunnel junction including a free layer disposed on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer. The read / write method includes: passing a write current through the SOT layer to reverse the magnetization direction of the free layer in the magnetic tunnel junction, so that the magnetization directions of the free layer and the reference layer are parallel or antiparallel; reading the capacitance value of the magnetic tunnel junction; and determining whether the magnetic tunnel junction is in a first state or a second state based on the capacitance value of the magnetic tunnel junction.

[0005] In the above scheme, the capacitance value of the magnetic tunnel junction is read, and the state of the magnetic tunnel junction (MTJ) is determined based on this value, thus enabling the identification and reading of the stored data "0" and "1" within the memory cell. Since the resistance value of the magnetic tunnel junction is not detected during the reading process, the requirement for the resistance difference between the high and low resistance states of the MTJ is reduced. Furthermore, the requirements for the growth conditions, material selection, and sensitivity of the read circuit in SOT-MRAM using the capacitive reading method are lower than those in resistive SOT-MRAM, making the growth conditions and material selection for the magnetic tunnel junction less demanding than those for magnetoresistive SOT-MRAM. Therefore, the capacitive SOT-MRAM used in this application has higher compatibility with current semiconductor processes, facilitating large-scale production based on existing semiconductor technologies. Furthermore, the reading method of capacitive SOT-MRAM is compatible with the current DRAM reading method, which is more conducive to utilizing and drawing on current DRAM technology to achieve mass production of capacitive SOT-MRAM, thereby reducing the difficulty of manufacturing and reading SOT-MRAM and solving the problem that resistive SOT-MRAM cannot be mass-produced due to its harsh preparation conditions and complex preparation process.

[0006] In one specific implementation, reading the capacitance value of a magnetic tunnel junction includes: charging and discharging the magnetic tunnel junction to obtain the amount of charge in the magnetic tunnel junction; and determining the capacitance value of the magnetic tunnel junction based on the obtained amount of charge. This facilitates obtaining the capacitance values ​​of the magnetic tunnel junction in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction is "0" or "1".

[0007] In one specific implementation, reading the capacitance value of a magnetic tunnel junction includes: charging and discharging the magnetic tunnel junction to obtain the decay rate of the charging voltage and / or discharging voltage over time; and determining the capacitance value of the magnetic tunnel junction based on the obtained decay rate of the charging voltage and / or discharging voltage over time. This facilitates obtaining the capacitance values ​​of the magnetic tunnel junction in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction is "0" or "1".

[0008] In one specific implementation, charging and discharging a magnetic tunnel junction to obtain the decay rate of its charging voltage and / or discharging voltage over time includes: charging and discharging the magnetic tunnel junction to obtain the changes in its charging voltage and / or discharging voltage over a set time period after the start of charging and / or discharging; and determining the decay rate of the charging voltage and / or discharging voltage over time based on the obtained changes in the charging voltage and / or discharging voltage over the set time period. By collecting the changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction over a set time period as a characterization of the decay rate of the charging voltage and / or discharging voltage over time, only a few voltage values ​​at a few time points need to be collected, reducing the difficulty of data collection and facilitating operation and application.

[0009] In one specific implementation, reading the capacitance value of a magnetic tunnel junction includes: passing an oscillating current signal into the magnetic tunnel junction to obtain an oscillating current feedback signal of the magnetic tunnel junction; and determining the capacitance value of the magnetic tunnel junction based on the obtained oscillating current feedback signal. This facilitates obtaining the capacitance values ​​of the magnetic tunnel junction in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction is "0" or "1".

[0010] Secondly, the present invention also provides a read / write circuit based on SOT-MRAM. The SOT-MRAM includes a memory cell, which includes an SOT layer and a magnetic tunnel junction disposed on the SOT layer. The magnetic tunnel junction includes a free layer disposed on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer. The read / write circuit includes a write circuit electrically connected to the SOT layer, a read circuit electrically connected to the magnetic tunnel junction, and a determination circuit. The write circuit is used to pass a write current to the SOT layer to reverse the magnetization direction of the free layer in the magnetic tunnel junction, making the magnetization directions of the free layer and the reference layer parallel or antiparallel. The read circuit is used to read the capacitance value of the magnetic tunnel junction. The determination circuit is used to determine whether the magnetic tunnel junction is in a first state or a second state based on the capacitance value of the magnetic tunnel junction.

[0011] In the above scheme, the capacitance value of the magnetic tunnel junction is read, and the state of the magnetic tunnel junction (MTJ) is determined based on this value, thus enabling the identification and reading of the stored data "0" and "1" within the memory cell. Since the resistance value of the magnetic tunnel junction is not detected during the reading process, the requirement for the resistance difference between the high and low resistance states of the MTJ is reduced. Furthermore, the requirements for the growth conditions, material selection, and sensitivity of the read circuit in SOT-MRAM using the capacitive reading method are lower than those in resistive SOT-MRAM, making the growth conditions and material selection for the magnetic tunnel junction less demanding than those for magnetoresistive SOT-MRAM. Therefore, the capacitive SOT-MRAM used in this application has higher compatibility with current semiconductor processes, facilitating large-scale production based on existing semiconductor technologies. Furthermore, the reading method of capacitive SOT-MRAM is compatible with the current DRAM reading method, which is more conducive to utilizing and drawing on current DRAM technology to achieve mass production of capacitive SOT-MRAM, thereby reducing the difficulty of manufacturing and reading SOT-MRAM and solving the problem that resistive SOT-MRAM cannot be mass-produced due to its harsh preparation conditions and complex preparation process.

[0012] In one specific embodiment, the read circuit includes: a charge / discharge circuit electrically connected to the magnetic tunnel junction, at least one current integration circuit electrically connected to the charge / discharge circuit, and a capacitance value calculation circuit electrically connected to the at least one current integration circuit. The charge / discharge circuit is used to charge and discharge the magnetic tunnel junction. The at least one current integration circuit is used to acquire the amount of charge in the magnetic tunnel junction during the charge / discharge process. The capacitance value calculation circuit is used to determine the capacitance value of the magnetic tunnel junction based on the acquired amount of charge. Furthermore, the capacitance value calculation circuit is also electrically connected to a judgment circuit to transmit the capacitance value of the magnetic tunnel junction to the judgment circuit. This facilitates the acquisition of the capacitance values ​​of the magnetic tunnel junction in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction is "0" or "1".

[0013] In one specific embodiment, the read circuit includes: a charge / discharge circuit electrically connected to the magnetic tunnel junction, a voltage decay identification circuit electrically connected to the magnetic tunnel junction, and a capacitance value calculation circuit electrically connected to the voltage decay identification circuit. The charge / discharge circuit is used to charge and discharge the magnetic tunnel junction. The voltage decay identification circuit is used to acquire the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction over time during the charge / discharge process. The capacitance value calculation circuit is used to determine the capacitance value of the magnetic tunnel junction based on the acquired degree of decay of the charging voltage and / or discharging voltage over time. Furthermore, the capacitance value calculation circuit is also electrically connected to a judgment circuit to transmit the capacitance value of the magnetic tunnel junction to the judgment circuit. This facilitates the acquisition of the capacitance values ​​of the magnetic tunnel junction in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction is "0" or "1".

[0014] In one specific embodiment, the voltage decay identification circuit includes: a voltage identification circuit electrically connected to the charging and discharging circuit, and a voltage recording circuit electrically connected to the voltage identification circuit. The voltage identification circuit is used to acquire the charging voltage and / or discharging voltage of the magnetic tunnel junction at a certain time point during the charging and discharging process of the magnetic tunnel junction. The voltage recording circuit is used to record the changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction within a set time period after the start of charging and / or discharging, and to determine the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction over time based on the acquired changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction over the set time period. By acquiring the charging voltage and / or discharging voltage of the magnetic tunnel junction within a set time period as a characterization of the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction over time, only a few voltage values ​​at a few time points need to be acquired, reducing the difficulty of acquisition and facilitating operation and application.

[0015] In one specific embodiment, the read circuit includes: an oscillation circuit electrically connected to the magnetic tunnel junction (MTJ), a spectrum analysis circuit electrically connected to the MTJ, and a capacitance calculation circuit electrically connected to both the oscillation circuit and the spectrum analysis circuit. The oscillation circuit supplies an oscillating current signal to the MTJ. The spectrum analysis circuit acquires the oscillating current feedback signal of the MTJ. The capacitance calculation circuit determines the capacitance value of the MTJ based on the acquired oscillating current feedback signal. Furthermore, the capacitance calculation circuit is electrically connected to a judgment circuit to transmit the capacitance value of the MTJ to the judgment circuit. This facilitates the acquisition of the capacitance values ​​of the MTJ in different states, thereby accurately identifying whether the data stored in the MTJ is "0" or "1".

[0016] Thirdly, the present invention also provides a SOT-MRAM, which includes a memory cell and any of the above-described SOT-MRAM-based read / write circuits. The memory cell includes an SOT layer and a magnetic tunnel junction disposed on the SOT layer; wherein the magnetic tunnel junction includes a free layer disposed on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer.

[0017] In the above scheme, the capacitance value of the magnetic tunnel junction is read, and the state of the magnetic tunnel junction (MTJ) is determined based on this value, thus enabling the identification and reading of the stored data "0" and "1" within the memory cell. Since the resistance value of the magnetic tunnel junction is not detected during the reading process, the requirement for the resistance difference between the high and low resistance states of the MTJ is reduced. Furthermore, the requirements for the growth conditions, material selection, and sensitivity of the read circuit in SOT-MRAM using the capacitive reading method are lower than those in resistive SOT-MRAM, making the growth conditions and material selection for the magnetic tunnel junction less demanding than those for magnetoresistive SOT-MRAM. Therefore, the capacitive SOT-MRAM used in this application has higher compatibility with current semiconductor processes, facilitating large-scale production based on existing semiconductor technologies. Furthermore, the reading method of capacitive SOT-MRAM is compatible with the current DRAM reading method, which is more conducive to utilizing and drawing on current DRAM technology to achieve mass production of capacitive SOT-MRAM, thereby reducing the difficulty of manufacturing and reading SOT-MRAM and solving the problem that resistive SOT-MRAM cannot be mass-produced due to its harsh preparation conditions and complex preparation process.

[0018] In one specific embodiment, the SOT layer is made of a metal, alloy, or topological material with spin-orbit coupling effect; the free layer and reference layer are both made of ferromagnetic materials; and the insulating layer is made of a metal oxide. Compared to resistive SOT-MRAM in the prior art, the insulating layer in each magnetic tunnel junction of the capacitive SOT-MRAM provided in this application is not limited to using MgO single crystal material, but can use materials such as AlO. x MgO, SiO2, HfO x Metal oxides, such as those used in manufacturing, reduce the difficulty of material selection and manufacturing. Attached Figure Description

[0019] Figure 1 A flowchart illustrating a read / write method based on SOT-MRAM provided in an embodiment of the present invention;

[0020] Figure 2This is a schematic diagram of a capacitive SOT-MRAM provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the magnetocapacitance of a magnetic tunnel junction provided in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram illustrating the change of charging current over time in a magnetic tunnel junction according to an embodiment of the present invention.

[0023] Figure 5 This invention provides a circuit diagram for reading the capacitance value of a magnetic tunnel junction by reading the amount of charge and discharge.

[0024] Figure 6 A schematic diagram illustrating the charging voltage variation of a magnetic track junction in different states over a set time period, as provided in an embodiment of the present invention.

[0025] Figure 7 A circuit diagram for reading the capacitance value of a magnetic tunnel junction by means of the oscillation current feedback signal of an oscillation circuit, provided in an embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of the structure of a Hall rod formed during the manufacturing process of a magnetic tunnel junction, as provided in an embodiment of the present invention.

[0027] Figure 9 This is a schematic diagram of the structure after a magnetic tunnel junction is fabricated on a Hall rod, as provided in an embodiment of the present invention.

[0028] Figure 10 This is a test diagram illustrating the testing of a single memory cell in a capacitive SOT-MRAM.

[0029] Figure label:

[0030] 10-Substrate; 11-SOT layer; 111-Transverse Hall rod; 112-Vertical Hall rod

[0031] 12-Magnetic Tunnel Junction; 121-Free Layer; 122-Insulating Layer; 123-Reference Layer; 13-Additional Layer

[0032] 14-Dielectric layer; 21-Current integrator circuit; 22-Oscillator circuit; 23-Spectrum analysis circuit Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] To facilitate understanding of the SOT-MRAM-based read / write method provided in this embodiment of the invention, the application scenario of the read / write method provided in this embodiment of the invention is first described below. This read / write method is applied to SOT-MRAM containing storage units, such as... Figure 2 The illustrated SOT-MRAM includes a storage cell comprising an SOT layer 11 and a magnetic tunnel junction 12 disposed on the SOT layer 11. The magnetic tunnel junction 12 includes a free layer 121 disposed on the SOT layer 11, an insulating layer 122 stacked on the free layer 121, and a reference layer 123 stacked on the insulating layer 122. The read / write method of this SOT-MRAM will now be described in detail with reference to the accompanying drawings.

[0035] refer to Figure 1 and Figure 2 The read / write method based on SOT-MRAM provided in this embodiment of the invention includes:

[0036] S10: A write current is applied to the SOT layer 11 to reverse the magnetization direction of the free layer 121 in the magnetic tunnel junction 12, so that the magnetization direction of the free layer 121 is parallel or antiparallel to that of the reference layer 123.

[0037] S20: Read the capacitance value of magnetic tunnel junction 12;

[0038] S30: Determine whether the magnetic tunnel junction 12 is in the first state or the second state based on the capacitance value of the magnetic tunnel junction 12.

[0039] In the above scheme, the capacitance value of the magnetic tunnel junction 12 is read, and based on this value, the state of the magnetic tunnel junction 12 (first or second) is determined, thereby enabling the identification and reading of the stored data "0" and "1" in the memory cell. Since the resistance value of the magnetic tunnel junction 12 is not detected during the reading process, the requirement for the resistance difference between the high and low resistance states of the magnetic tunnel junction 12 is reduced. Furthermore, the SOT-MRAM using the magnetocapacitive reading method has lower requirements for the growth conditions, material selection, and sensitivity of the reading circuit compared to resistive SOT-MRAM. Therefore, the magnetocapacitive SOT-MRAM is less demanding in terms of the growth conditions and material selection of the magnetic tunnel junction 12 than the magnetoresistive SOT-MRAM. Thus, the capacitive SOT-MRAM used in this application has higher compatibility with current semiconductor processes, facilitating large-scale production based on existing semiconductor technologies. Furthermore, the reading method of capacitive SOT-MRAM is compatible with the current DRAM reading method, which is more conducive to utilizing and drawing on current DRAM technology to achieve mass production of capacitive SOT-MRAM. This reduces the difficulty of manufacturing and reading SOT-MRAM, and solves the problem that resistive SOT-MRAM cannot be mass-produced due to its demanding preparation conditions and complex preparation process. The following section provides a detailed description of each step with reference to the accompanying diagram.

[0040] First, such as Figure 1 and Figure 2 As shown, a write current is applied to the SOT layer 11 to reverse the magnetization direction of the free layer 121 in the magnetic tunnel junction 12, making the magnetization direction of the free layer 121 parallel or antiparallel to that of the reference layer 123. That is, during data writing, similar to resistive SOT-MRAM, the free layer 121 is reversed by the spin torque generated in the SOT layer 11 by the write current. Figure 3 As shown, when the magnetization directions of the free layer 121 and the reference layer 123 are parallel, the magnetic tunnel junction 12 is in a capacitance state of "0". When the free layer 121 and the reference layer 123 are antiparallel, the magnetic tunnel junction 12 is in a capacitance state of "1". That is, when the magnetization directions of the free layer 121 and the reference layer 123 in the magnetic tunnel junction 12 are parallel or antiparallel, the capacitance value of the magnetic tunnel junction 12 will exhibit two different values, and the data "0" and "1" can be stored through the high and low capacitance values ​​of the magnetic tunnel junction.

[0041] Next, continue to refer to Figure 1 and Figure 2The capacitance value of magnetic tunnel junction 12 is read, i.e., its capacitance value is obtained, so that the data written into magnetic tunnel junction 12 can be determined as "0" or "1" by subsequently reading its capacitance value. Different read circuits can be designed to achieve this in various ways. During data reading, the read circuit can charge and discharge magnetic tunnel junction 12, and the relationship between the charging / discharging current and time is as follows: Figure 4 As shown. The capacitance value of the magnetic tunnel junction 12 can be calculated by obtaining some capacitance-related parameters during the charging and discharging process.

[0042] For example, the capacitance value of the magnetic tunnel junction 12 can be obtained by determining the maximum amount of charge that the magnetic tunnel junction 12 can accept during charging and discharging. Specifically, the magnetic tunnel junction 12 is first charged and discharged to obtain the maximum amount of charge it can accept. Then, the capacitance value of the magnetic tunnel junction 12 is determined based on the obtained charge amount. The schematic diagram of the reading circuit is shown below. Figure 5 The circuit shown employs at least one current integrator 21 to calculate the amount of charge and discharge of the magnetic tunnel junction 12 based on the integral of the charging and discharging current over time. The capacitance value of the magnetic tunnel junction 12 is then determined based on the amount of charge and discharge, so as to obtain the capacitance value of the magnetic tunnel junction 12 in different states and thus accurately identify whether the data stored in the magnetic tunnel junction 12 is "0" or "1".

[0043] In some other embodiments, reference is made to Figure 6 Alternatively, the change in charging voltage and / or discharging voltage over time during the charging or discharging process of the magnetic tunnel junction 12 can be obtained first, and then the capacitance value of the magnetic tunnel junction 12 can be determined based on this change. Specifically, the magnetic tunnel junction 12 is first charged and discharged to obtain the decay rate of the charging voltage and / or discharging voltage over time. Specifically, the decay rate of the charging voltage over time can be obtained; the decay rate of the discharging voltage over time can also be obtained; or both the decay rate of the charging voltage and the decay rate of the discharging voltage over time can be obtained for dual calculation and verification. Figure 6The shown Δt represents a set time period. Then, based on the degree of decay of the acquired charging voltage and / or discharging voltage over time, the capacitance value of the magnetic tunnel junction 12 is determined. While maintaining the same initial charging voltage, the voltage change across the magnetic tunnel junction 12 is judged within the set time period. Since the charging and discharging times of the magnetic tunnel junction 12 differ in its high and low capacitance states, the voltage change across the magnetic tunnel junction 12 also differs within the set time period. Therefore, the capacitance value of the magnetic tunnel junction 12 can be determined by measuring the voltage change across the magnetic tunnel junction 12. This allows for the acquisition of the capacitance value of the magnetic tunnel junction 12 in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction 12 is "0" or "1".

[0044] Specifically, when charging and discharging the magnetic tunnel junction 12 to obtain the decay of its charging voltage and / or discharging voltage over time, the changes in charging voltage and / or discharging voltage over a specific time period can be obtained, without needing to obtain the voltage changes throughout the entire charging or discharging process. For details, refer to... Figure 6 When charging and discharging the magnetic tunnel junction 12, the changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 within a set time period (Δt) after the start of charging or / and discharging can be acquired. Then, based on the acquired changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 within the set time period, the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 over time can be determined. In other words, by acquiring the voltage changes within a set time period after the start of charging or discharging, and using the changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 within the set time period as a characterization of the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 over time, only a few voltage values ​​at a few time points need to be acquired, reducing the difficulty of data acquisition and facilitating operation and application.

[0045] In other embodiments, an oscillating current signal may be input to the magnetic tunnel junction 12, and the oscillating current feedback signal output from the magnetic tunnel junction 12 may be detected. The capacitance value of the magnetic tunnel junction 12 may be determined based on the oscillating current feedback signal. Specifically, refer to... Figure 7The diagram illustrates a read circuit comprising an oscillation circuit 22 and a spectrum analysis circuit 23. An oscillation current signal is first supplied to the magnetic tunnel junction 12 via the oscillation circuit 22 to obtain the oscillation current feedback signal of the magnetic tunnel junction 12. Then, based on the obtained oscillation current feedback signal, the capacitance value of the magnetic tunnel junction 12 is determined. That is, the oscillation current signal input to the magnetic tunnel junction 12 is formed by a certain oscillation frequency and amplitude. As the magnetic tunnel junction 12 passes through it, different states of the magnetic tunnel junction 12 change the frequency and amplitude of the oscillation current signal in different ways. By detecting the oscillation current feedback signal of the magnetic tunnel junction 12, the capacitance value of this tunnel junction is calculated. In other words, by judging the frequency and amplitude of the oscillation current feedback signal, the capacitance value in the magnetic tunnel junction 12 is read, so as to obtain the capacitance value of the magnetic tunnel junction 12 in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction 12 is "0" or "1".

[0046] Of course, it should be noted that the methods for reading the capacitance value of the magnetic tunnel junction 12 are not limited to the methods shown above. In addition, other methods can be used to obtain the capacitance value of the magnetic tunnel junction 12.

[0047] Next, based on the capacitance value of the magnetic tunnel junction 12, it is determined whether the magnetic tunnel junction 12 is in the first state or the second state. That is, based on the obtained capacitance value of the magnetic tunnel junction 12, a certain threshold is applied, and the state where the capacitance value of the magnetic tunnel junction 12 is greater than the threshold is determined as the first state, and the state where the capacitance value of the magnetic tunnel junction 12 is less than the threshold is determined as the second state. The first state and the second state can respectively represent data "0" and "1" to realize the storage and retrieval of capacitive SOT-MRAM.

[0048] By reading the capacitance value of the magnetic tunnel junction 12 and determining whether it is in a first or second state based on that value, the system can identify and read the stored data "0" and "1" within the memory cell. Since the resistance value of the magnetic tunnel junction 12 is not detected during the reading process, the requirement for resistance difference between its high and low resistance states is reduced. Furthermore, the SOT-MRAM using the magnetocapacitive reading method has lower requirements for the growth conditions, material selection, and sensitivity of the MTJ compared to resistive SOT-MRAM. Therefore, the magnetocapacitive SOT-MRAM is less demanding in terms of the growth conditions and material selection for the magnetic tunnel junction 12 than the magnetoresistive SOT-MRAM. Consequently, the capacitive SOT-MRAM used in this application has higher compatibility with current semiconductor processes, facilitating large-scale production based on existing semiconductor technologies. Furthermore, the reading method of capacitive SOT-MRAM is compatible with the current DRAM reading method, which is more conducive to utilizing and drawing on current DRAM technology to achieve mass production of capacitive SOT-MRAM, thereby reducing the difficulty of manufacturing and reading SOT-MRAM and solving the problem that resistive SOT-MRAM cannot be mass-produced due to its harsh preparation conditions and complex preparation process.

[0049] In addition, embodiments of the present invention also provide a read / write circuit based on SOT-MRAM. (See reference) Figure 2 , Figure 3 The SOT-MRAM includes a memory cell comprising an SOT layer 11 and a magnetic tunnel junction 12 disposed on the SOT layer 11. The magnetic tunnel junction 12 includes a free layer 121 disposed on the SOT layer 11, an insulating layer 122 stacked on the free layer 121, and a reference layer 123 stacked on the insulating layer 122. The read / write circuit includes a write circuit electrically connected to the SOT layer 11, a read circuit electrically connected to the magnetic tunnel junction 12, and a determination circuit. The write circuit is used to apply a write current to the SOT layer 11 to reverse the magnetization direction of the free layer 121 in the magnetic tunnel junction 12, making the magnetization directions of the free layer 121 parallel or antiparallel to the reference layer 123. The read circuit is used to read the capacitance value of the magnetic tunnel junction 12. The determination circuit is used to determine whether the magnetic tunnel junction 12 is in a first state or a second state based on the capacitance value of the magnetic tunnel junction 12.

[0050] By reading the capacitance value of the magnetic tunnel junction 12 and determining whether it is in a first or second state based on that value, the system can identify and read the stored data "0" and "1" within the memory cell. Since the resistance value of the magnetic tunnel junction 12 is not detected during the reading process, the requirement for resistance difference between its high and low resistance states is reduced. Furthermore, the SOT-MRAM using the magnetocapacitive reading method has lower requirements for the growth conditions, material selection, and sensitivity of the MTJ compared to resistive SOT-MRAM. Therefore, the magnetocapacitive SOT-MRAM is less demanding in terms of the growth conditions and material selection for the magnetic tunnel junction 12 than the magnetoresistive SOT-MRAM. Consequently, the capacitive SOT-MRAM used in this application has higher compatibility with current semiconductor processes, facilitating large-scale production based on existing semiconductor technologies. Furthermore, the read method of capacitive SOT-MRAM is compatible with the current DRAM read method, which is more conducive to utilizing and drawing on current DRAM technology to achieve mass production of capacitive SOT-MRAM. This reduces the difficulty of manufacturing and reading SOT-MRAM, and solves the problem that resistive SOT-MRAM cannot be mass-produced due to its demanding manufacturing conditions and complex manufacturing process. The circuit structures mentioned above are described in detail below with reference to the accompanying drawings.

[0051] The write circuit can be any existing circuit capable of supplying write current to the SOT layer 11 to achieve the flipping of the free layer 121. The specific principle of the flipping is described in the aforementioned read / write method section and will not be repeated here. The read circuit can be configured in various ways; only a few circuits are listed below as examples.

[0052] For example, refer to Figure 5 The read circuit may include: a charge / discharge circuit electrically connected to the magnetic tunnel junction 12, at least one current integration circuit 21 electrically connected to the charge / discharge circuit, and a capacitance value calculation circuit electrically connected to the at least one current integration circuit 21. The charge / discharge circuit is used to charge and discharge the magnetic tunnel junction 12. The at least one current integration circuit 21 is used to acquire the amount of charge in the magnetic tunnel junction 12 during the charge / discharge process. The capacitance value calculation circuit is used to determine the capacitance value of the magnetic tunnel junction 12 based on the acquired amount of charge. The capacitance value calculation circuit is also electrically connected to a judgment circuit to transmit the capacitance value of the magnetic tunnel junction 12 to the judgment circuit. This facilitates the acquisition of the capacitance value of the magnetic tunnel junction 12 in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction 12 is "0" or "1". The specific principle of determining the capacitance value of the magnetic tunnel junction 12 by acquiring the amount of charge in the magnetic tunnel junction 12 is described in the aforementioned read / write method section and will not be repeated here.

[0053] In some other embodiments, the read circuit may include: a charge / discharge circuit electrically connected to the magnetic tunnel junction 12, a voltage decay identification circuit electrically connected to the magnetic tunnel junction 12, and a capacitance value calculation circuit electrically connected to the voltage decay identification circuit. The charge / discharge circuit is used to charge and discharge the magnetic tunnel junction 12. The voltage decay identification circuit is used to acquire the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 over time during the charge / discharge process. The capacitance value calculation circuit is used to determine the capacitance value of the magnetic tunnel junction 12 based on the acquired degree of decay of the charging voltage and / or discharging voltage over time. The capacitance value calculation circuit is also electrically connected to a judgment circuit to transmit the capacitance value of the magnetic tunnel junction 12 to the judgment circuit. This facilitates the acquisition of the capacitance value of the magnetic tunnel junction 12 in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction 12 is "0" or "1". Specifically, the principle of determining the capacitance value of the magnetic tunnel junction 12 by acquiring the voltage change across the magnetic tunnel junction during the charge / discharge process is described in the aforementioned read / write method section and will not be repeated here.

[0054] When setting up the voltage decay recognition circuit, the voltage decay recognition circuit may include: a voltage recognition circuit electrically connected to the charging and discharging circuit, and a voltage recording circuit electrically connected to the voltage recognition circuit. The voltage recognition circuit is used to acquire the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 at a certain time point during the charging and discharging process of the magnetic tunnel junction 12. The voltage recording circuit is used to record the changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 within a set time period after the start of charging and / or discharging, and to determine the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 over time based on the acquired changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 over the set time period. By acquiring the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 within a set time period as a characterization of the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction 12 over time, only a few voltage values ​​at a few time points need to be acquired, reducing the difficulty of acquisition and facilitating operation and application. For details, please refer to the description in the aforementioned read / write method section, which will not be repeated here.

[0055] In other embodiments, reference is made to Figure 7The read circuit may include: an oscillation circuit 22 electrically connected to the magnetic tunnel junction 12, a spectrum analysis circuit 23 electrically connected to the magnetic tunnel junction 12, and a capacitance calculation circuit electrically connected to both the oscillation circuit 22 and the spectrum analysis circuit 23. The oscillation circuit 22 is used to supply an oscillating current signal to the magnetic tunnel junction 12. The spectrum analysis circuit 23 is used to acquire the oscillation current feedback signal of the magnetic tunnel junction 12. The capacitance calculation circuit is used to determine the capacitance value of the magnetic tunnel junction 12 based on the acquired oscillation current feedback signal. The capacitance calculation circuit is also electrically connected to a judgment circuit to transmit the capacitance value of the magnetic tunnel junction 12 to the judgment circuit. This facilitates the acquisition of the capacitance value of the magnetic tunnel junction 12 in different states, thereby accurately identifying whether the data stored in the magnetic tunnel junction 12 is "0" or "1". The specific implementation of the read method is described in the aforementioned read / write method section and will not be repeated here.

[0056] The determination circuit can determine whether the magnetic tunnel junction 12 is in a first state or a second state based on the capacitance value of the magnetic tunnel junction 12. Specifically, the determination circuit uses the obtained capacitance value of the magnetic tunnel junction 12 and, based on the magnitude of the capacitance value, applies a certain threshold. The state where the capacitance value of the magnetic tunnel junction 12 is greater than the threshold is determined as the first state, and the state where the capacitance value of the magnetic tunnel junction 12 is less than the threshold is determined as the second state. The first and second states can respectively represent data "0" and "1" to realize the storage and retrieval of capacitive SOT-MRAM.

[0057] In addition, embodiments of the present invention also provide a SOT-MRAM, see reference. Figure 2 , Figure 3The SOT-MRAM includes a memory cell and any of the aforementioned SOT-MRAM-based read / write circuits. The memory cell includes an SOT layer 11 and a magnetic tunnel junction 12 disposed on the SOT layer 11. The magnetic tunnel junction 12 includes a free layer 121 disposed on the SOT layer 11, an insulating layer 122 stacked on the free layer 121, and a reference layer 123 stacked on the insulating layer 122. By reading the capacitance value of the magnetic tunnel junction 12 and determining whether the magnetic tunnel junction 12 is in a first or second state based on the capacitance value, the identification and reading of the stored data "0" and "1" in the memory cell can be achieved. Since the resistance value of the magnetic tunnel junction 12 is not detected during the reading process, the requirement for the resistance difference between the high and low resistance states of the magnetic tunnel junction 12 is reduced. Furthermore, SOT-MRAM employing a magnetocapacitive readout method has lower requirements for MTJ growth conditions, material selection, and readout circuit sensitivity compared to resistive SOT-MRAM. This makes the growth conditions and material selection for the magnetic tunnel junction 12 less demanding than those for magnetoresistive SOT-MRAM. Therefore, the capacitive SOT-MRAM used in this application has higher compatibility with current semiconductor processes, facilitating large-scale production based on existing semiconductor technologies. Moreover, the readout method of capacitive SOT-MRAM is compatible with current DRAM readout methods, making it easier to utilize and leverage existing DRAM technology to achieve mass production of capacitive SOT-MRAM. This reduces the difficulty of manufacturing and reading SOT-MRAM, solving the problem that resistive SOT-MRAM cannot be mass-produced due to its demanding fabrication conditions and complex fabrication process.

[0058] When determining the materials for different structural layers, the SOT layer 11 can be a metal, alloy, or topological material with spin-orbit coupling effect. For example, one or several metals selected from Pt, Ta, W, Mo, Au, Al, BiSe, IrMn, etc., or an alloy formed by combining several metals, can be used as the material for the SOT layer 11. The free layer 121 and reference layer 123 can both be ferromagnetic materials. For example, metals Fe, Co, Ni, CoFeB, or any combination thereof can be used as the materials for the free layer 121 and reference layer 123. The insulating layer 122 can be a metal oxide. Compared to the resistive SOT-MRAM in the prior art, the insulating layer 122 in each magnetic tunnel junction 12 of the capacitive SOT-MRAM provided in this application is not limited to using MgO single crystal material, but can use materials such as AlO. x MgO, SiO2, HfO x Metal oxides such as those used as the material for the insulating layer 122 in the magnetic tunnel junction 12 reduce the difficulty of material selection and manufacturing.

[0059] In addition, such as Figure 2 As shown, other additional layers 13 can also be stacked on top of the reference layer 123. These other additional layers 13 can be buffer layers or seed layers between the reference layer 123 and the upper electrode layer, or they can be layer structures with other functions.

[0060] In manufacturing the capacitive SOT-MRAM shown in the embodiments of the present invention, such as Figures 8-10 This illustrates a method for fabricating capacitive SOT-MRAM. (Reference) Figure 8 First, an 8 nm thick Ta layer is sputtered onto substrate 10 (Si wafer), and patterned into a Hall bar structure, serving as the SOT layer 11 in each memory cell. The Hall bar structure includes a lateral Hall bar 111 and a vertical Hall bar 112. The lateral Hall bar 111 can have a width of 5 μm and a length of 100 μm; the vertical Hall bar 112 can have a width of 5 μm and a length of 50 μm. Then, a 0.8 nm thick CoFeB material layer is deposited sequentially on substrate 10 and the Hall bar structure as the material layer for processing free layer 121; a 2 nm thick MgO material layer is deposited as the material layer for processing insulating layer 122; and a 1.2 nm thick CoFeB material layer is deposited as the material layer for processing reference layer 123. Afterwards, the reference... Figure 9 A circular magnetic tunnel junction 12 with a diameter of 2 micrometers was fabricated in the intersection region of the longitudinal and transverse Hall rods 111, with an area of ​​5 micrometers × 5 micrometers, using photolithography and etching. (Reference) Figure 10 After etching, SiO2 is filled around the magnetic tunnel junction 12 as the dielectric layer 14. Then, a third photolithography step is performed, and Ti 10nm / Cu 50nm / Au 50nm is deposited as the top electrode. The sample preparation is then complete. Figure 10 As shown. Of course, before depositing the upper electrode material layer, a 15 nm thick Ta material layer can also be deposited on the reference layer 123 as a buffer layer for processing other additional layers 13, so as to increase the adhesion strength of the upper electrode and prevent the upper electrode from falling off.

[0061] In the preparation of such Figure 10 After the capacitive SOT-MRAM shown, a magnetocapacitance test can be performed. This can be done using a multi-function multimeter. The test connections are as follows: Figure 10As shown. First, an external magnetic field is applied to the surface perpendicular to the SOT-MRAM. This external magnetic field changes the magnetization direction of the free layer 121 in the magnetic tunnel junction 12. The capacitance value of the magnetic tunnel junction 12 is tested when the magnetization directions of the free layer 121 and the reference layer 123 are parallel or antiparallel. Second, a gradually changing current write pulse is applied to both sides of the transverse Hall bar 111. After each pulse is applied, the capacitance value of the magnetic tunnel junction 12 is read using a multimeter to determine whether the free layer 121 has flipped. Finally, the direction of the pulsed write current is changed to flip the free layer 121, causing the magnetic tunnel junction 12 to switch between high and low capacitance states, thereby realizing data writing and reading. Of course, the correctness of the obtained magnetic tunnel junction state can also be verified by the transverse Hall bar 111.

[0062] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A read / write method based on SOT-MRAM, wherein, The SOT-MRAM includes a memory cell, the memory cell comprising an SOT layer and a magnetic tunnel junction disposed on the SOT layer, the magnetic tunnel junction comprising a free layer disposed on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer, characterized in that the SOT-MRAM is a capacitive SOT-MRAM, and the read / write method includes: A write current is passed into the SOT layer to reverse the magnetization direction of the free layer in the magnetic tunnel junction, so that the magnetization direction of the free layer is parallel or antiparallel to that of the reference layer. Read the capacitance value of the magnetic tunnel junction; Based on the capacitance value of the magnetic tunnel junction, a threshold is used to determine whether the magnetic tunnel junction is in a first state or a second state, which includes: determining the state when the capacitance value of the magnetic tunnel junction is greater than the threshold as the first state, and determining the state when the capacitance value of the magnetic tunnel junction is less than the threshold as the second state; The step of reading the capacitance value of the magnetic tunnel junction includes: An oscillating current signal is passed through the magnetic tunnel junction to obtain the oscillating current feedback signal of the magnetic tunnel junction; The capacitance value of the magnetic tunnel junction is determined based on the obtained oscillating current feedback signal.

2. The read / write method as described in claim 1, characterized in that, The process of reading the capacitance value of the magnetic tunnel junction includes: The magnetic tunnel junction is charged and discharged to obtain the amount of charge in the magnetic tunnel junction; The capacitance value of the magnetic tunnel junction is determined based on the amount of charge obtained.

3. The read / write method as described in claim 1, characterized in that, The process of reading the capacitance value of the magnetic tunnel junction includes: The magnetic tunnel junction is charged and discharged to obtain the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction over time. The capacitance value of the magnetic tunnel junction is determined based on the degree of decay of the obtained charging voltage and / or discharging voltage over time.

4. The read / write method as described in claim 3, characterized in that, The charging and discharging of the magnetic tunnel junction to obtain the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction over time includes: The magnetic tunnel junction is charged and discharged to obtain the changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction within a set time period after the start of charging and / or discharging. Based on the changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction within a set time period, the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction over time is determined.

5. A read / write circuit based on SOT-MRAM, wherein, The SOT-MRAM includes a memory cell, the memory cell comprising an SOT layer and a magnetic tunnel junction disposed on the SOT layer, the magnetic tunnel junction comprising a free layer disposed on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer, characterized in that the SOT-MRAM is a capacitive SOT-MRAM, and the read / write circuit includes: A write circuit electrically connected to the SOT layer, the write circuit being used to pass a write current into the SOT layer to reverse the magnetization direction of the free layer in the magnetic tunnel junction, so that the magnetization direction of the free layer is parallel or antiparallel to that of the reference layer. A read circuit electrically connected to the magnetic tunnel junction, the read circuit being used to read the capacitance value of the magnetic tunnel junction; A determination circuit is used to determine whether the magnetic tunnel junction is in a first state or a second state based on the capacitance value of the magnetic tunnel junction using a threshold. The circuit includes: determining the state when the capacitance value of the magnetic tunnel junction is greater than the threshold as the first state, and determining the state when the capacitance value of the magnetic tunnel junction is less than the threshold as the second state. The read circuit includes: An oscillating circuit electrically connected to the magnetic tunnel junction is used to supply an oscillating current signal to the magnetic tunnel junction. A spectrum analysis circuit electrically connected to the magnetic tunnel junction is used to obtain the oscillating current feedback signal of the magnetic tunnel junction; A capacitance calculation circuit electrically connected to both the oscillation circuit and the spectrum analysis circuit is used to determine the capacitance value of the magnetic tunnel junction based on the acquired oscillation current feedback signal. Furthermore, the capacitance calculation circuit is electrically connected to the judgment circuit to transmit the capacitance value of the magnetic tunnel junction to the judgment circuit.

6. The read / write circuit as described in claim 5, characterized in that, The read circuit includes: A charging and discharging circuit electrically connected to the magnetic tunnel junction is used to charge and discharge the magnetic tunnel junction. At least one current integrating circuit electrically connected to the charging and discharging circuit, the at least one current integrating circuit being used to obtain the amount of charge of the magnetic tunnel junction during the charging and discharging process of the magnetic tunnel junction; A capacitance calculation circuit electrically connected to the at least one current integration circuit, the capacitance calculation circuit being used to determine the capacitance value of the magnetic tunnel junction based on the amount of charge acquired; Furthermore, the capacitance calculation circuit is electrically connected to the judgment circuit to transmit the capacitance value of the magnetic tunnel junction to the judgment circuit.

7. The read / write circuit as described in claim 5, characterized in that, The read circuit includes: A charging and discharging circuit electrically connected to the magnetic tunnel junction is used to charge and discharge the magnetic tunnel junction. A voltage decay identification circuit electrically connected to the magnetic tunnel junction, the voltage decay identification circuit being used to obtain the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction over time during the charging and discharging process of the magnetic tunnel junction; A capacitance value calculation circuit electrically connected to the voltage decay identification circuit is used to determine the capacitance value of the magnetic tunnel junction based on the degree of decay of the acquired charging voltage and / or discharging voltage over time. Furthermore, the capacitance calculation circuit is electrically connected to the judgment circuit to transmit the capacitance value of the magnetic tunnel junction to the judgment circuit.

8. The read / write circuit as described in claim 7, characterized in that, The voltage attenuation detection circuit includes: A voltage identification circuit electrically connected to the charging and discharging circuit is used to obtain the charging voltage and / or discharging voltage of the magnetic tunnel junction at a certain time point during the charging and discharging process of the magnetic tunnel junction. A voltage recording circuit electrically connected to the voltage identification circuit is used to record the changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction within a set time period after the start of charging or / and discharging, and to determine the degree of decay of the charging voltage and / or discharging voltage of the magnetic tunnel junction over time based on the recorded changes in the charging voltage and / or discharging voltage of the magnetic tunnel junction within the set time period.

9. A SOT-MRAM, characterized in that, The SOT-MRAM is a capacitive SOT-MRAM, which includes: A storage cell, the storage cell including a SOT layer and a magnetic tunnel junction disposed on the SOT layer; wherein the magnetic tunnel junction includes a free layer disposed on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer; The read / write circuit based on SOT-MRAM as described in any one of claims 5 to 8.

10. The SOT-MRAM as described in claim 9, characterized in that, The material of the SOT layer is a metal, alloy, or topological material with spin-orbit coupling effect; Both the free layer and the reference layer are made of ferromagnetic materials. The insulating layer is made of metal oxide.

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