A method for determining a reliability factor, a reliability assessment method, and related devices

Abstract

The present invention provides a reliability factor determination method, a reliability evaluation method, and related devices, including: analyzing signals of a logic unit to obtain the probability of a first event occurring in the logic unit; obtaining the influence probability of the first event on the performance of the logic unit and the performance change of the logic unit when the first event occurs according to the result of simulating the occurrence of the first event in the logic unit; determining the reliability factor of the logic unit when the first event occurs according to the probability of the first event occurring, the influence probability, and the performance change, so that the influence of the first event on the reliability of the logic unit can be judged more accurately through the reliability factor, and further, the reliability of an integrated circuit including the logic unit can be evaluated more accurately through the reliability factor.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuit design, and particularly to a method for determining a reliability factor, a reliability evaluation method, and related devices. Background Art

[0002] Integrated circuits mainly consist of logic units. Events such as signal mutations occurring in logic units will cause changes in the performance of logic units, and further cause integrated circuits to fail to meet the timing requirements for normal operation. Therefore, how to accurately judge the impact of events such as signal mutations on the performance reliability of logic units is one of the problems that those skilled in the art urgently need to solve. Summary of the Invention

[0003] In view of this, the embodiments of the present invention provide a method for determining a reliability factor, a reliability evaluation method, and related devices, so as to more accurately judge the impact of events such as signal mutations on the performance reliability of logic units through the reliability factor.

[0004] To solve the above problems, the embodiments of the present invention provide the following technical solutions:

[0005] The first aspect of the present application provides a method for determining a reliability factor, including:

[0006] Analyze the signals of the logic unit to determine the probability of the first event occurring in the logic unit;

[0007] According to the result of simulating the occurrence of the first event in the logic unit, determine the probability of the impact of the first event on the performance of the logic unit and the performance change of the logic unit when the first event occurs;

[0008] According to the probability of the occurrence of the first event, the impact probability, and the performance change, determine the reliability factor of the logic unit when the first event occurs; the reliability factor is used to verify the reliability of the performance of the logic unit.

[0009] The second aspect of the present application provides a reliability evaluation method, including:

[0010] Determine each logic unit in the circuit to be verified, where the circuit to be verified includes multiple logic units;

[0011] Determine the reliability factors of each logic unit in the circuit to be verified when a first event occurs. The reliability factor is determined based on the probability of the first event occurring in the logic unit, the probability of the first event affecting the performance of the logic unit, and the performance change of the logic unit when the first event occurs. The probability of the first event occurring is determined by analyzing the signals of the logic unit, and the influence probability and the performance change are determined based on the results of simulating the first event occurring in the logic unit;

[0012] Evaluate the reliability of the circuit to be verified when the first event occurs according to the reliability factors of each logic unit in the circuit to be verified.

[0013] The third aspect of the present application provides a reliability factor determination device, including:

[0014] An analysis module for analyzing the signals of the logic unit to obtain the probability of the first event occurring in the logic unit;

[0015] A first processing module for obtaining the probability of the first event affecting the performance of the logic unit and the performance change of the logic unit when the first event occurs according to the results of simulating the first event occurring in the logic unit;

[0016] A second processing module for determining the reliability factor of the logic unit when the first event occurs according to the probability of the first event occurring, the influence probability, and the performance change; the reliability factor is used to verify the reliability of the performance of the logic unit.

[0017] The fourth aspect of the present application provides a reliability evaluation device, including:

[0018] A first determination module for determining each logic unit in the circuit to be verified, where the circuit to be verified includes a plurality of logic units;

[0019] A second determination module for determining the reliability factor of each logic unit in the circuit to be verified when the first event occurs. The reliability factor is determined based on the probability of the first event occurring in the logic unit, the probability of the first event affecting the performance of the logic unit, and the performance change of the logic unit when the first event occurs. The probability of the first event occurring is determined by analyzing the signals of the logic unit, and the influence probability and the performance change are determined based on the results of simulating the first event occurring in the logic unit;

[0020] A verification module for evaluating the reliability of the circuit to be verified when the first event occurs according to the reliability factors of each logic unit in the circuit to be verified.

[0021] A fifth aspect of the present application provides a computer device, including:

[0022] A memory storing at least one set of instructions;

[0023] A processor that executes the at least one set of instructions to perform the delay impact factor determination method described in any one of the above, or the reliability determination method described in any one of the above.

[0024] A sixth aspect of the present application provides a readable storage medium storing at least one set of instructions for causing a processor to execute the delay impact factor determination method described in any one of the above, or the reliability determination method described in any one of the above.

[0025] The reliability factor determination method, reliability evaluation method, and related devices provided by the embodiments of the present invention analyze the signals of a logic unit to obtain the probability of a first event occurring in the logic unit. According to the result of simulating the occurrence of the first event in the logic unit, the impact probability of the first event on the performance of the logic unit and the performance change of the logic unit when the first event occurs are obtained. According to the probability of the occurrence of the first event, the impact probability, and the performance change, the reliability factor of the logic unit when the first event occurs is determined. Since when determining the reliability factor, not only the probability of the occurrence of the first event is considered, but also the impact probability of the first event on the performance is considered, therefore, the impact of the first event on the reliability of the logic unit can be judged more accurately through the reliability factor, and further, the reliability of the integrated circuit including the logic unit can be evaluated more accurately through the reliability factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0027] Figure 1 It is a flowchart of a reliability factor determination method provided by an embodiment of the present invention;

[0028] Figure 2 It is a flowchart of a reliability factor determination method provided by another embodiment of the present invention;

[0029] Figure 3 It is a schematic structural diagram of a NAND gate provided by an embodiment of the present invention;

[0030] Figure 4 It is a signal timing diagram of a NAND gate without the occurrence of a simultaneous flip event provided by an embodiment of the present invention;

[0031] Figure 5 This is the signal timing diagram of the NAND gate in the case of a simultaneous flip event provided by the embodiment of the present invention;

[0032] Figure 6 This is the flowchart for determining the probability of a first event occurring in a logic unit provided by an embodiment of the present invention;

[0033] Figure 7 This is the structural schematic diagram of the NAND gate provided by another embodiment of the present invention;

[0034] Figure 8 This is the timing diagram of the input signal of the logic unit provided by an embodiment of the present invention;

[0035] Figure 9 This is the timing diagram of the input signal of the logic unit provided by another embodiment of the present invention;

[0036] Figure 10 This is the flowchart of the reliability assessment method provided by an embodiment of the present invention;

[0037] Figure 11 This is the structural schematic diagram of the reliability factor determination device provided by an embodiment of the present invention;

[0038] Figure 12 This is the structural schematic diagram of the reliability assessment device provided by an embodiment of the present invention. Detailed implementation manners

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0040] Meeting timing requirements such as setup / hold is one of the necessary conditions for the normal operation of an integrated circuit. An integrated circuit mainly consists of logic units. Among them, logic units include sequential logic units and combinational logic units. Sequential logic units include registers, etc., and combinational logic units include logic gates, etc. Logic gates include NAND gates, NOR gates, etc.

[0041] However, events such as signal mutations can cause changes in the performance of logic units, and the performance changes of logic units can lead to the integrated circuit not meeting the timing requirements for normal operation, resulting in poor reliability of the integrated circuit. For example, the delay change of a logic unit caused by a simultaneous switching (SSW) event can lead to poor reliability of the logic unit. Among them, the simultaneous switching event refers to an event in which multiple input signals of a logic unit flip simultaneously, and here the flip means that the signal flips at the rising edge or falling edge.

[0042] Generally, the reliability of an integrated circuit is evaluated by judging the impact of events such as signal mutations on the performance of logic units. However, for the performance changes of logic units caused by probabilistic events, the accuracy of this method for evaluating the reliability of integrated circuits is relatively poor.

[0043] This is because generally, the performance changes of logic units caused by such probabilistic events are determined under the assumption that this probabilistic event has occurred 100%. However, this probabilistic event does not occur 100%, but has a certain probability. For example, generally, the delay change of a logic unit caused by the simultaneous switching phenomenon is determined under the assumption that the input signals of the logic unit flip simultaneously 100%. However, the occurrence of the simultaneous switching event has a certain probability. Not every logic unit will have a simultaneous switching event, and moreover, not every simultaneous switching event will affect the delay of the logic unit.

[0044] Therefore, it is inaccurate to judge the impact of the performance changes caused by probabilistic events on the reliability of integrated circuits by assuming that the probabilistic event occurs 100%, which in turn leads to inaccurate evaluation results of the reliability evaluation method based on this. Optimizing the integrated circuit based on this inaccurate evaluation result will lead to over-design of the integrated circuit, resulting in a large power consumption and area of the integrated circuit.

[0045] Based on this, the embodiments of the present invention provide a method for determining a reliability factor, a reliability evaluation method, and related devices to solve the above problems. Among them, the method for determining a reliability factor includes:

[0046] Analyze the signals of the logic unit to determine the probability that the logic unit has a first event;

[0047] According to the result of simulating the occurrence of the first event for the logic unit, determine the probability of the impact of the first event on the performance of the logic unit and the performance change of the logic unit when the first event occurs;

[0048] Determine a reliability factor of the logic unit when the first event occurs according to the probability of the occurrence of the first event, the impact probability, and the performance change; the reliability factor is used to evaluate the reliability of the performance of the logic unit.

[0049] In the reliability factor determination method, reliability evaluation method, and related device provided by the embodiments of the present invention, when determining the reliability factor, not only the probability of the occurrence of the first event is considered, but also the impact probability of the first event on the performance is considered. Therefore, the impact of the first event on the reliability of the logic unit can be judged more accurately through the reliability factor, and then the reliability of the integrated circuit including the logic unit can be evaluated more accurately through the reliability factor. Furthermore, according to the more accurate reliability evaluation result, the design of the integrated circuit can be reasonably optimized to reduce the power consumption and area of the integrated circuit.

[0050] As an optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide a reliability factor determination method for determining the reliability of a logic unit when a first event occurs. As Figure 1 shown, Figure 1 is a flowchart of the reliability factor determination method provided by an embodiment of the present invention. The reliability factor determination method includes:

[0051] S101: Analyze the signals of the logic unit to determine the probability of the occurrence of the first event in the logic unit;

[0052] In the embodiments of the present invention, the logic unit includes a sequential logic unit and a combinational logic unit. The sequential logic unit includes registers, and the combinational logic unit includes logic gates. That is to say, the logic unit in the embodiments of the present invention can be a register, or a logic gate such as a NAND gate or a NOR gate. Of course, the logic unit can also be other logic devices, which will not be elaborated here.

[0053] S102: Determine the impact probability of the first event on the performance of the logic unit and the performance change of the logic unit when the first event occurs according to the result of simulating the occurrence of the first event in the logic unit;

[0054] In the embodiments of the present invention, after simulating the occurrence of the first event in the logic unit and obtaining the simulation result data, the impact probability of the first event on the performance of the logic unit and the performance change of the logic unit when the first event occurs are determined according to the simulation result data. Among them, the impact probability of the first event on the performance of the logic unit refers to the probability that the first event affects the performance of the logic unit, or in other words, the probability that the first event has a greater impact on the performance of the logic unit. The performance change of the logic unit when the first event occurs refers to the change in the performance of the logic unit caused by the first event when the first event occurs.

[0055] S103: Determine the reliability factor of the logic unit when the first event occurs based on the probability of the first event occurring, the impact probability, and the performance change; the reliability factor is used to evaluate the reliability of the performance of the logic unit.

[0056] After determining the probability of the first event occurring in the logic unit, the impact probability of the first event on the performance of the logic unit, and the performance change of the logic unit when the first event occurs, based on the probability of the first event occurring, the impact probability, and the performance change, determine the reliability factor of the logic unit when the first event occurs. The reliability factor is used to evaluate the performance reliability of the logic unit.

[0057] Optionally, the reliability factor is equal to the product of the probability of the first event occurring, the impact probability, and the performance change. Among them, the greater the probability of the first event, the greater the impact probability, and the greater the performance change, the larger the value of the reliability factor, and the worse the performance reliability of the logic unit; on the contrary, the smaller the probability of the first event, the smaller the impact probability, and the smaller the performance change, the smaller the value of the reliability factor, and the better the performance reliability of the logic unit.

[0058] In the embodiments of the present invention, the probability of the first event occurring in the logic unit, the impact probability of the first event on the performance of the logic unit, and the performance change of the logic unit when the first event occurs are used to determine the reliability factor of the logic unit when the first event occurs, so that the impact of the first event on the reliability of the logic unit can be judged more accurately through the reliability factor. Furthermore, the reliability of the integrated circuit including the logic unit can be evaluated more accurately through the reliability factor. Furthermore, based on the more accurate reliability evaluation result, the design of the integrated circuit can be reasonably optimized to reduce the power consumption and area of the integrated circuit.

[0059] In some embodiments of the present invention, the first event includes: an event in which at least some input signals flip simultaneously, and the performance includes: delay performance. Of course, the present invention is not limited to this. In other embodiments, the first event may also be other signal mutation events, which will not be elaborated here one by one.

[0060] In some embodiments of the present invention, as Figure 2 shown, Figure 2 is a flowchart of a method for determining a reliability factor provided for another embodiment of the present invention. The method for determining the reliability factor includes:

[0061] S201: Analyze the signals of the logic unit to determine the probability of the event that at least some input signals of the logic unit flip simultaneously;

[0062] S202: Determine the influence probability of the event of at least partial input signals flipping simultaneously on the performance of the logic unit and the delay change of the logic unit when the event of at least partial input signals flipping simultaneously occurs, according to the result of simulating the event of at least partial input signals flipping simultaneously for the logic unit.

[0063] S203: Determine the reliability factor of the logic unit when the event of at least partial input signals flipping simultaneously occurs, according to the probability, influence probability, and delay change of the event of at least partial input signals flipping simultaneously; the reliability factor is used to evaluate the reliability of the delay performance of the logic unit.

[0064] The following takes the logic unit being a NAND gate as an example for illustration. As Figure 3 shown, Figure 3 is a schematic structural diagram of a NAND gate provided by an embodiment of the present invention. The NAND gate includes an input port A, an input port B, an output port OUT, PMOS transistors p1 and p2, and NMOS transistors n1 and n2. It should be noted that the logic units where simultaneous flip events occur are all logic units having at least two input signals or input ports.

[0065] In the case where no simultaneous flip event occurs, as Figure 4 shown, Figure 4 is a signal timing diagram of the NAND gate in the case where no simultaneous flip event occurs provided by an embodiment of the present invention. When the input signal of the input port A flips from the high level 1 to the low level 0, the input signal of the input port B remains stable at the high level 1. The state of the PMOS transistor p1 changes from off to on, and the state of the PMOS transistor p2 remains off. The output port OUT is connected to the power supply vdd through the PMOS transistor p1, so that the output port OUT changes from the original low level 0 to the high level 1.

[0066] In the case where a simultaneous flip event occurs, as Figure 5 shown, Figure 5 is a signal timing diagram of the NAND gate in the case where a simultaneous flip event occurs provided by an embodiment of the present invention. When the input port A flips from the high level 1 to the low level 0 and at the same time the input port B flips from the high level 1 to the low level 0, the PMOS transistors p1 and p2 are turned on simultaneously. The output port OUT is connected to the power supply vdd through the PMOS transistors p1 and p2, so that the output port OUT changes from the original low level 0 to the high level 1 more quickly. That is to say, the occurrence of the simultaneous flip event accelerates the delay change of the NAND gate. For the hold (maintain) timing, if the delay change speed is fast, there is a risk of generating violations.

[0067] However, in actual situations, when the input signal of input port B flips, and whether it exactly flips simultaneously with the input signal of input port A is a probabilistic event. Assuming that the input signal of input port B does not exactly flip simultaneously with the input signal of input port A, for example, the input signal of input port B flips 1 ps later than the input signal of input port A, then the impact of the simultaneous flip event will also be different. In fact, the impact of non-exact simultaneous flipping on the delay performance of the logic unit is smaller than that of exact simultaneous flipping.

[0068] The commonly used reliability evaluation method assumes that the input signals of input port A and input port B will definitely flip exactly simultaneously, without considering what the probability of flipping is (in fact, the probability is very low), nor considering whether the flipping will definitely affect the delay performance. Therefore, the accuracy of the reliability evaluation is relatively low.

[0069] In the embodiments of the present invention, the reliability factor is determined based on the event probability that at least part of the input signals of the logic unit flip simultaneously, the impact probability of the event that at least part of the input signals flip simultaneously on the performance of the logic unit, and the performance change of the logic unit when the event that at least part of the input signals flip simultaneously occurs. That is to say, in the embodiments of the present invention, not only the occurrence probability of the simultaneous flip event is considered, but also the impact probability of the simultaneous flip event on the performance change is considered. Therefore, the reliability factor in the embodiments of the present invention can more accurately judge the impact of the event that at least part of the input signals flip simultaneously on the performance reliability of the logic unit, and thus the performance reliability of the integrated circuit can be more accurately evaluated through the reliability factor.

[0070] Based on the above embodiments, in some embodiments of the present invention, as Figure 6 shown, Figure 6 is a flowchart for determining the probability of a first event occurring in a logic unit provided by an embodiment of the present invention. Determining the probability of a first event occurring in a logic unit, that is, the event that at least part of the input signals flip simultaneously, includes:

[0071] S601: Analyze all the input signals of the logic unit to determine the predicted flip time periods of all the input signals of the logic unit;

[0072] S602: Determine whether there is an overlap in the predicted flip time periods of at least part of the input signals among all the input signals; if yes, proceed to S603;

[0073] S603: Determine the overlapping time period of the predicted flip time periods of at least part of the input signals as the simultaneous flip time period;

[0074] S604: Determine the flip probabilities of each input signal among at least part of the input signals according to the predicted flip time periods of each input signal among at least part of the input signals and the simultaneous flip time period;

[0075] S605: Determine the probability of an event in which at least some of the input signals of the logic unit flip simultaneously according to the flip probabilities of the respective input signals in at least some of the input signals.

[0076] In some embodiments of the present invention, analyzing all the input signals of the logic unit to determine the predicted flip time periods of all the input signals of the logic unit includes: performing static timing analysis (STA) on all the input signals of the logic unit to determine the predicted flip time periods of all the input signals of the logic unit.

[0077] Since the flip time of each input signal is affected by the delay of the logic unit and its front-end devices, after performing static timing analysis on the input signals, the earliest possible flip time and the latest possible flip time when the input signals flip can be obtained. According to the earliest possible flip time and the latest possible flip time, the predicted flip time period can be determined. Among them, the predicted flip time period of each input signal is equal to the difference between the latest possible flip time and the earliest possible flip time of the input signal.

[0078] After determining the predicted flip time periods of all the input signals of the logic unit, determine whether there is an overlap in the predicted flip time periods of at least some of the input signals among all the input signals. As Figure 7 shown, Figure 7 FIG. 14 is a schematic structural diagram of a NAND gate provided in another embodiment of the present invention. Taking a NAND gate with four input ports or input signals as an example, after performing static timing analysis on the input signals A, B, C, and D to determine the predicted flip time periods of the input signals A, B, C, and D, determine whether the predicted flip time periods of the input signals A, B, C, and D all overlap. If only the predicted flip time periods of the input signals A, B, and C have overlapping parts, and the input signal D has no overlapping parts with the input signals A, B, and C, then it is determined that only the predicted flip time periods of some of the input signals A, B, and C among all the input signals overlap.

[0079] Among them, the more the number of input signals with overlapping predicted flip time periods, the greater the impact of the simultaneous flip event on the delay performance of the logic unit. If only the predicted flip time periods of the input signals A, B, and C have overlapping parts, then the event that has the greatest impact on the performance of the logic unit is the event that the input signals A, B, and C flip simultaneously. Therefore, the reliability factor can be calculated according to the result of simulating the event that the input signals A, B, and C flip simultaneously on the logic unit, so that the value of the reliability factor is the maximum value that can be obtained, to evaluate the reliability of the logic unit in the worst case.

[0080] Of course, in the embodiments of the present invention, only the case where the predicted transition periods of some input signals overlap is taken as an example for illustration, and it is not limited thereto. In other embodiments, there may also be cases where the predicted transition periods of all input signals overlap, or where the predicted transition periods of all input signals do not overlap. If the predicted transition periods of all input signals overlap, the reliability factor can be calculated based on the result of simulating the event of all input signals transitioning simultaneously in the logic unit.

[0081] If the predicted transition periods of at least some input signals overlap, determine the overlapping period of the predicted transition periods of at least some input signals as the simultaneous transition period. As Figure 8 shown, Figure 8 is a timing diagram of the input signals of the logic unit provided by an embodiment of the present invention. The predicted transition period T is determined according to the latest possible transition time Amax and the earliest possible transition time Amin of the input signal A A and the predicted transition period T is determined according to the latest possible transition time Bmax and the earliest possible transition time Bmin of the input signal B B and the predicted transition period T is determined according to the latest possible transition time Cmax and the earliest possible transition time Cmin of the input signal C C , and then the simultaneous transition period T1 is determined according to the predicted transition periods T A , T B and T C .

[0082] After that, according to the predicted transition periods and the simultaneous transition period of each input signal among at least some input signals, determine the transition probability of each input signal among at least some input signals. Among them, the transition probability of each input signal is equal to the quotient of the simultaneous transition period of each input signal and its predicted transition period. Then, according to the transition probabilities of each input signal among at least some input signals, determine the probability of the event that at least some input signals transition simultaneously in the logic unit. Among them, the probability of the event that at least some input signals transition simultaneously in the logic unit is equal to the product of the transition probabilities of each input signal.

[0083] For example, after determining that the overlapping period of the predicted transition periods of the input signals A, B, and C is the simultaneous transition period T1, determine the transition probability P of the input signal A A = T1 / T A = T1 / (Amax - Amin), the transition probability P of the input signal B B = T1 / T B = T1 / (Bmax - Bmin), the transition probability P of the input signal C C = T1 / T C= T1 / (Cmax - Cmin). Then, determine the probability P of the event that at least part of the input signals of the NAND gate flip simultaneously! = P A *P B *P C .

[0084] Based on the above embodiments, in some embodiments of the present invention, according to the result of simulating the occurrence of the first event, that is, the event that at least part of the input signals flip simultaneously, for the logic unit, determining the influence probability of the first event, that is, the event that at least part of the input signals flip simultaneously, on the performance of the logic unit includes:

[0085] According to the result of simulating the occurrence of the event that at least part of the input signals flip simultaneously for the logic unit, determine the influence period of at least part of the input signals flipping simultaneously;

[0086] According to the influence period and the simultaneous flip period, determine the influence probability of the event that at least part of the input signals flip simultaneously on the performance of the logic unit.

[0087] As Figure 9 shown, Figure 9 is the timing diagram of the input signals of the logic unit provided by another embodiment of the present invention. Assume that the input signal A flips at 5 ps and the input signal B flips between 5 ps and 10 ps. Then, the simultaneous flip event of the input signal A and the input signal B has an influence on the delay of the logic unit greater than 10%, that is, it has a greater impact on the delay performance of the logic unit. However, if the input signal B flips after more than 10 ps, then the simultaneous flip event of the input signal A and the input signal B has an influence on the delay of the logic unit less than 10% and does not have a greater impact on the delay performance of the logic unit.

[0088] Based on this, in the embodiments of the present invention, simulate the occurrence of the event that at least part of the input signals flip simultaneously for the logic unit, and then according to the result of the simulation, determine the influence period of at least part of the input signals flipping simultaneously, and according to the influence period and the simultaneous flip period, determine the influence probability of the event that at least part of the input signals flip simultaneously on the performance of the logic unit. Among them, the influence probability Y = T2 / T1, where T2 is the influence period and T1 is the simultaneous flip period.

[0089] Based on the above embodiments, in some embodiments of the present invention, according to the result of simulating the occurrence of the event that at least part of the input signals flip simultaneously for the logic unit, determining the influence period of at least part of the input signals flipping simultaneously includes:

[0090] According to the input signal data in the result of simulating the occurrence of the event that at least part of the input signals flip simultaneously for the logic unit, determine the actual flip period of any one of the at least part of the input signals;

[0091] Determine the influence period during which at least part of the input signals flip simultaneously according to the actual flip period and a preset constant.

[0092] As shown in Table 1, the inventor found through data statistics that the influence period is equal to the product of the actual flip period (transition) and a constant. Based on this, in the embodiments of the present invention, after determining the actual flip period of any one of the input signals in at least part of the input signals according to the input signal data in the result of simulating the event that at least part of the input signals flip simultaneously for the logic unit, determine the influence period during which at least part of the input signals flip simultaneously according to the actual flip period and a preset constant. Wherein, the influence period T2 = T T *a, where T T is the actual flip period, as Figure 4 shown, the slanted line part is the actual flip period T T , and a is a constant. Optionally, 0.6 ≤ a ≤ 0.7. In a specific embodiment, a is equal to 2 / 3.

[0093] Table 1

[0094] <![CDATA[Influence period T2 (30% - 70%)]]> <![CDATA[T T = 25 ps]]> <![CDATA[T T = 50 ps]]> <![CDATA[T T = 75 ps]]> <![CDATA[T T = 1005 ps]]> HDBLVT08_AN3B_8 17 35 55 71 HDBLVT08_AR4B_Y2_4 17 32 46 61 HDBSVT08_AN4_2 15 30 45 63 HDBSVT08_ND4_CB_2 14 28 42 59 HDBSVT08_NR3_T_2 14 28 44 61 HDBSVT08_AN3B_CB_1 13 25 40 54 HDBSVT11_ND3_T_2 14 27 40 54 HDBULT08_NR2_T_8 16 35 56 na HDBULT08_NR2B_V1_3 14 31 38 na

[0095] It should be noted that the selected influence period T2 is the period during which the influence on the delay performance of the logic unit is greater than 10%, such as the period of 30% - 70%. Based on this, after determining the influence period, determine the influence probability on the performance of the logic unit according to the influence period and the simultaneous flip period.

[0096] Based on any of the above embodiments, in some embodiments of the present invention, determining the performance change of the logic unit when the first event occurs according to the result of simulating the first event for the logic unit includes: determining the performance change of the logic unit when at least part of the input signals flip simultaneously according to the input signal data and the output signal data in the result of simulating the event that at least part of the input signals flip simultaneously for the logic unit. For example, according to the data of the output signal OUT and the input signal A obtained when at least part of the input signals flip simultaneously, the delay time of the logic unit can be determined, and further the performance change of the logic unit when at least part of the input signals flip simultaneously can be determined.

[0097] In some embodiments of the present invention, if it is determined that some of the input signals in all the input signals will flip simultaneously, then the logic unit can be simulated to obtain a simulation result under the condition of simulating the simultaneous flip of some of the input signals, and the performance change of the logic unit when at least part of the input signals flip simultaneously can be determined according to the simulation result. For example, the NAND gate can be simulated when the input signals A, B, and C flip simultaneously, and then the delay change of the NAND gate can be determined according to the simulation result.

[0098] Of course, the present invention is not limited to this. In some other embodiments, the performance change can also be the maximum performance change in the worst case, that is, the delay change when all input signals flip simultaneously. Based on this, the logic unit can be simulated under the condition of simulating all input signals flipping simultaneously to obtain a simulation result, and the maximum performance change of the logic unit when the event of at least the input signals flipping simultaneously occurs can be determined according to the simulation result, so that the value of the finally obtained reliability factor is the maximum value that can be taken, in order to evaluate the reliability of the logic unit in the worst case. For example, the NAND gate can also be simulated when the input signals A, B, C, and D flip simultaneously, and then the maximum delay change of the NAND gate can be determined according to the simulation result.

[0099] After determining the probability of the event that at least some input signals of the logic unit flip simultaneously, the influence probability of the event that at least some input signals flip simultaneously on the performance of the logic unit, and the performance change of the logic unit when the event that at least some input signals flip simultaneously occurs, the reliability factor of the logic unit when the first event occurs can be determined according to the probability, influence probability, and performance change of the occurrence of the first event. Among them, the reliability factor is equal to the product of the probability, influence probability, and performance change of the occurrence of the first event.

[0100] That is, in some embodiments of the present invention, determining the reliability factor of the logic unit when the first event occurs according to the probability, influence probability, and performance change of the occurrence of the first event includes:

[0101] Determine the reliability factor of the logic unit when the first event occurs according to the formula K = S*(T2 / T1)*P!; where K is the reliability factor, S is the performance change, T2 / T1 is the influence probability, T2 is the influence period, T1 is the simultaneous flip period, and P! is the probability of the occurrence of the first event, and P! is equal to the product of the flip probabilities of each input signal.

[0102] On this basis, the embodiments of the present invention can more accurately judge the influence of the first event on the reliability of the logic unit through the reliability factor, and further can more accurately evaluate the reliability of the integrated circuit including the logic unit through the reliability factor.

[0103] As an optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide a reliability evaluation method for evaluating the reliability of an integrated circuit having a logic unit. As Figure 10 shown, Figure 10 is a flowchart of the reliability evaluation method provided by an embodiment of the present invention. The reliability evaluation method includes:

[0104] S1001: Identify each logic unit in the circuit to be verified. The circuit to be verified includes multiple logic units;

[0105] S1002: Determine the reliability factor of each logic unit in the circuit to be verified when a first event occurs. The reliability factor is determined based on the probability of the first event occurring in the logic unit, the probability of the first event affecting the performance of the logic unit, and the performance change of the logic unit when the first event occurs. The probability of the first event occurring is determined by analyzing the signals of the logic unit, and the impact probability and performance change are determined based on the results of simulating the first event occurring in the logic unit;

[0106] S1003: Evaluate the reliability of the circuit to be verified when the first event occurs based on the reliability factors of each logic unit in the circuit to be verified.

[0107] In some embodiments of the present invention, the first event includes: an event in which at least some of the input signals flip simultaneously; the performance includes: delay performance. Among them, the reliability factor of each logic unit in the circuit to be verified when the first event occurs can be determined by the method provided in any of the above embodiments, which will not be elaborated here.

[0108] In some embodiments of the present invention, evaluating the reliability of the circuit to be verified when the first event occurs based on the reliability factors of each logic unit in the circuit to be verified includes:

[0109] Calculate the sum of the reliability factors of each logic unit in the circuit to be verified;

[0110] Determine whether the sum of the reliability factors is greater than a preset value;

[0111] Based on the judgment result, evaluate the reliability of the circuit to be verified when the first event occurs.

[0112] In the embodiments of the present invention, the circuit to be verified can be a circuit in a chip, or a circuit in a chip design, and of course, it can also be an integrated circuit in other devices, which will not be elaborated here.

[0113] In the embodiments of the present invention, if the sum of the reliability factors is greater than the preset value, it indicates that the reliability of the circuit to be verified is poor. If the sum of the reliability factors is less than or equal to the preset value, it indicates that the reliability of the circuit to be verified is good.

[0114] Based on this, the reliability factor can be used to conveniently locate the circuits in the chip that are the most unstable and most vulnerable to events such as signal mutations. In these circuits, the probability of the first event occurring is high and / or the performance change is large. These problems must be solved in the chip. Therefore, it is necessary to optimize these circuits. For those circuits with a low occurrence probability or a small impact even if they occur, optimization can be considered as appropriate. In this way, targeted optimization of reliability problems caused by events such as signal mutations can be achieved.

[0115] As an optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide a reliability factor determination device for determining the reliability factor of a logic unit. As Figure 11 shown, Figure 11 FIG. is a schematic structural diagram of a reliability factor determination device provided by an embodiment of the present invention, including:

[0116] An analysis module 111, configured to analyze the signals of the logic unit to obtain the probability of the first event occurring in the logic unit;

[0117] A first processing module 112, configured to obtain the influence probability of the first event on the performance of the logic unit and the performance change of the logic unit when the first event occurs according to the result of simulating the occurrence of the first event in the logic unit;

[0118] A second processing module 113, configured to determine the reliability factor of the logic unit when the first event occurs according to the probability of the first event occurring, the influence probability, and the performance change; the reliability factor is used to verify the reliability of the performance of the logic unit.

[0119] Based on the above embodiments, in some embodiments of the present invention, the first event includes: an event in which at least some input signals are flipped simultaneously; the performance includes: delay performance.

[0120] Based on the above embodiments, in some embodiments of the present invention, when the analysis module 111 analyzes the signals of the logic unit to determine the probability of the first event occurring in the logic unit, it includes:

[0121] Analyze all the input signals of the logic unit to determine the predicted flip time periods of all the input signals of the logic unit;

[0122] Determine whether there is an overlap in the predicted flip time periods of at least some of the input signals; if so, determine the overlap period of the predicted flip time periods of at least some of the input signals as the simultaneous flip time period;

[0123] According to the predicted flip time periods of each input signal in at least some of the input signals and the simultaneous flip time period, determine the flip probability of each input signal in at least some of the input signals;

[0124] Determine the probability of an event where at least some of the input signals of the logic unit flip simultaneously based on the flip probabilities of the individual input signals in at least part of the input signal.

[0125] Based on the above embodiments, in some embodiments of the present invention, the first processing module 112 determines the influence probability of the first event on the performance of the logic unit according to the result of the first event occurring in the simulated logic unit, including:

[0126] Determine the influence period of at least some of the input signals flipping simultaneously according to the result of the event where at least some of the input signals of the simulated logic unit flip simultaneously;

[0127] Determine the influence probability of the event where at least some of the input signals flip simultaneously on the performance of the logic unit according to the influence period and the simultaneous flip period.

[0128] Based on the above embodiments, in some embodiments of the present invention, the analysis module 111 analyzes all the input signals of the logic unit, and determining the predicted flip periods of all the input signals of the logic unit includes:

[0129] Perform static timing analysis on all the input signals of the logic unit to determine the predicted flip periods of all the input signals of the logic unit.

[0130] Based on the above embodiments, in some embodiments of the present invention, the first processing module 112 determines the influence period of at least some of the input signals flipping simultaneously according to the result of the event where at least some of the input signals of the simulated logic unit flip simultaneously, including:

[0131] Determine the actual flip period of any one of the at least some of the input signals according to the result of simulating the event where at least some of the input signals of the logic unit flip simultaneously;

[0132] Determine the influence period of at least some of the input signals flipping simultaneously according to the actual flip period and a preset constant.

[0133] Based on any of the above embodiments, in some embodiments of the present invention, the first processing module 112 determines the performance change of the logic unit when the first event occurs according to the result of simulating the first event occurring in the logic unit, including:

[0134] Determine the performance change of the logic unit when the event where at least some of the input signals flip simultaneously occurs according to the result of simulating the event where at least some of the input signals of the logic unit flip simultaneously.

[0135] Based on any of the above embodiments, in some embodiments of the present invention, the second processing module 113 determines the reliability factor of the logic unit when the first event occurs according to the probability of the first event occurring, the influence probability, and the performance change, including:

[0136] According to the formula K = S*(T2 / T1)*P!, determine the reliability factor of the logic unit when the first event occurs; where K is the reliability factor, S is the performance change, T2 / T1 is the impact probability, T2 is the impact period, T1 is the simultaneous flip period, and P! is the probability of the first event occurring, and P! is equal to the product of the flip probabilities of each input signal.

[0137] Based on any of the above embodiments, in some embodiments of the present invention, the logic unit includes a sequential logic unit and a combinational logic unit; the sequential logic unit includes a register; the combinational logic unit includes a logic gate.

[0138] As an optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention provide a reliability evaluation device for evaluating the reliability of a circuit. As Figure 12 shown, Figure 12 is a schematic structural diagram of a reliability evaluation device provided by an embodiment of the present invention. The reliability evaluation device includes:

[0139] A first determination module 121, configured to determine each logic unit in the circuit to be verified, and the circuit includes a plurality of logic units;

[0140] A second determination module 122, configured to determine the reliability factor of each logic unit in the circuit to be verified when the first event occurs. The reliability factor is determined according to the probability of the first event occurring in the logic unit, the impact probability of the first event on the performance of the logic unit, and the performance change of the logic unit when the first event occurs. The probability of the first event occurring is determined by analyzing the signals of the logic unit, and the impact probability and performance change are determined according to the result of simulating the first event occurring in the logic unit;

[0141] A verification module 123, configured to evaluate the reliability of the circuit to be verified when the first event occurs according to the reliability factors of each logic unit in the circuit to be verified.

[0142] Based on the above embodiments, in some embodiments of the present invention, the first event includes: an event in which at least some input signals flip simultaneously; the performance includes: delay performance.

[0143] Based on any of the above embodiments, in some embodiments of the present invention, the verification module 123 evaluates the reliability of the circuit to be verified when the first event occurs according to the reliability factors of each logic unit in the circuit to be verified, including:

[0144] Calculating the sum of the reliability factors of each logic unit in the circuit to be verified;

[0145] Determining whether the sum of the reliability factors is greater than a preset value;

[0146] According to the judgment result, the reliability of the circuit to be verified when the first event occurs is evaluated.

[0147] In the embodiments of the present invention, the circuit to be verified may be a circuit in a chip, or a circuit in a chip design, and of course may also be an integrated circuit in other devices, which will not be elaborated here.

[0148] In the embodiments of the present invention, if the sum of the reliability factors is greater than the preset value, it indicates that the reliability of the circuit to be verified is poor; if the sum of the reliability factors is less than or equal to the preset value, it indicates that the reliability of the circuit to be verified is good.

[0149] As an optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention further provide a computer device, which includes:

[0150] A memory that stores at least one set of instructions;

[0151] A processor that executes at least one set of instructions to perform the reliability factor determination method provided in any one of the above embodiments, or the reliability evaluation method provided in any one of the above embodiments.

[0152] The electronic devices in the embodiments of the present invention include but are not limited to mobile communication devices, ultra-mobile personal computer devices, portable entertainment devices, servers, and other electronic devices with data interaction functions. Among them, mobile communication devices include but are not limited to smart phones and multimedia phones, ultra-mobile personal computer devices include but are not limited to tablet computers, portable entertainment devices include but are not limited to e-books and handheld game consoles, and servers include but are not limited to computer devices.

[0153] As an optional implementation of the disclosed content of the embodiments of the present invention, the embodiments of the present invention further provide a readable storage medium that stores at least one set of instructions, and the at least one set of instructions is used to cause the processor to execute the reliability factor determination method provided in any one of the above embodiments, or the reliability evaluation method provided in any one of the above embodiments.

[0154] The readable storage medium of the embodiments of the present invention includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. The information can be host-readable instructions, data structures, program modules, or other data. Examples of the host's storage medium include, but are not limited to, phase change memory (PAM), static random access memory (SAM), dynamic random access memory (DAM), other types of random access memory (AM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassette tapes, magnetic tape magnetic disk storage, or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0155] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0156] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for determining a reliability factor, characterized in that Comprising: Analyzing the signals of the logic unit to determine the probability of a first event occurring in the logic unit; Determining the probability of the first event affecting the performance of the logic unit and the performance change of the logic unit when the first event occurs according to the result of simulating the first event occurring in the logic unit, where the probability of the first event affecting the performance of the logic unit is the probability that the first event affects the performance of the logic unit; Determining the reliability factor of the logic unit when the first event occurs according to the probability of the first event occurring, the probability of the impact, and the performance change; the reliability factor is used to evaluate the reliability of the performance of the logic unit.

2. The reliability factor determination method according to claim 1, wherein The first event includes: an event where at least some of the input signals flip simultaneously; the performance includes: delay performance.

3. The reliability factor determination method according to claim 2, characterized in that The analyzing the signals of the logic unit to determine the probability of a first event occurring in the logic unit includes: Analyzing all the input signals of the logic unit to determine the predicted flip time periods of all the input signals of the logic unit; Determining whether there is an overlap in the predicted flip time periods of at least some of the input signals among all the input signals; if so, determining the overlapping time period of the predicted flip time periods of the at least some of the input signals as the simultaneous flip time period; Determining the flip probability of each input signal among the at least some of the input signals according to the predicted flip time periods of each input signal among the at least some of the input signals and the simultaneous flip time period; Determining the probability of the event that at least some of the input signals flip simultaneously in the logic unit according to the flip probability of each input signal among the at least some of the input signals.

4. The reliability factor determination method according to claim 3, characterized in that, The determining the probability of the first event affecting the performance of the logic unit according to the result of simulating the first event occurring in the logic unit includes: Determining the impact time period of at least some of the input signals flipping simultaneously according to the result of simulating the event that at least some of the input signals flip simultaneously in the logic unit; Determining the probability of the event that at least some of the input signals flip simultaneously affecting the performance of the logic unit according to the impact time period and the simultaneous flip time period.

5. The reliability factor determination method according to claim 3, characterized in that, The analyzing all the input signals of the logic unit to determine the predicted flip time periods of all the input signals of the logic unit includes: Performing static timing analysis on all the input signals of the logic unit to determine the predicted flip time periods of all the input signals of the logic unit.

6. The reliability factor determination method according to claim 4, characterized in that, The determining the impact time period of at least some of the input signals flipping simultaneously according to the result of simulating the event that at least some of the input signals flip simultaneously in the logic unit includes: Determining the actual flip time period of any one of the input signals among the at least some of the input signals according to the input signal data in the result of simulating the event that at least some of the input signals flip simultaneously in the logic unit; Determining the impact time period of at least some of the input signals flipping simultaneously according to the actual flip time period and a preset constant.

7. The reliability factor determination method according to claim 2, characterized in that The determining the performance change of the logic unit when the first event occurs according to the result of simulating the first event occurring in the logic unit includes: Determine the performance change of the logic unit when the event of at least partial input signals flipping simultaneously occurs based on the input signal data and output signal data in the result of simulating the event of at least partial input signals flipping simultaneously for the logic unit.

8. The reliability factor determination method according to claim 4, characterized in that, The determining of the reliability factor of the logic unit when the first event occurs according to the probability of the occurrence of the first event, the influence probability, and the performance change includes: Determine the reliability factor of the logic unit when the first event occurs according to the formula K = S * (T2 / T1) * P!; Wherein, K is the reliability factor, S is the performance change, T2 / T1 is the influence probability, T2 is the influence period, T1 is the simultaneous flipping period, P! is the probability of the occurrence of the first event, and P! is equal to the product of the flipping probabilities of the respective input signals.

9. The reliability factor determination method according to claim 1, characterized in that The logic unit includes a sequential logic unit and a combinational logic unit; the sequential logic unit includes a register; the combinational logic unit includes logic gates.

10. A reliability evaluation method, characterized in that, Including: Determine each logic unit in the circuit to be verified, where the circuit to be verified includes multiple logic units; Determine the reliability factor of each logic unit in the circuit to be verified when the first event occurs, where the reliability factor is determined according to the probability of the occurrence of the first event for the logic unit, the influence probability of the first event on the performance of the logic unit, and the performance change of the logic unit when the first event occurs. The probability of the occurrence of the first event is determined by analyzing the signals of the logic unit, and the influence probability and the performance change are determined according to the result of simulating the first event for the logic unit. The influence probability of the first event on the performance of the logic unit is the probability that the first event affects the performance of the logic unit; Evaluate the reliability of the circuit to be verified when the first event occurs according to the reliability factors of each logic unit in the circuit to be verified.

11. The reliability assessment method according to claim 10, characterized in that, The first event includes: the event of at least partial input signals flipping simultaneously; the performance includes: delay performance.

12. The reliability evaluation method according to claim 10, wherein The evaluating of the reliability of the circuit to be verified when the first event occurs according to the reliability factors of each logic unit in the circuit to be verified includes: Calculate the sum of the reliability factors of each logic unit in the circuit to be verified; Judge whether the sum of the reliability factors is greater than a preset value; Evaluate the reliability of the circuit to be verified when the first event occurs according to the judgment result.

13. A reliability factor determination device, characterized in that Including: An analysis module for analyzing the signals of the logic unit to obtain the probability of the occurrence of the first event for the logic unit; A first processing module for determining the influence probability of the first event on the performance of the logic unit and the performance change of the logic unit when the first event occurs according to the result of simulating the first event for the logic unit. The influence probability of the first event on the performance of the logic unit is the probability that the first event affects the performance of the logic unit; A second processing module, configured to determine a reliability factor of the logic unit when the first event occurs according to the probability of the occurrence of the first event, the influence probability, and the performance change; the reliability factor is used to verify the reliability of the performance of the logic unit.

14. A reliability evaluation device, characterized in that, Comprising: A first determination module, configured to determine each logic unit in the circuit to be verified, where the circuit to be verified includes a plurality of logic units; A second determination module, configured to determine the reliability factor of each logic unit in the circuit to be verified when the first event occurs, where the reliability factor is determined according to the probability of the occurrence of the first event by the logic unit, the influence probability of the first event on the performance of the logic unit, and the performance change of the logic unit when the first event occurs. The probability of the occurrence of the first event is determined by analyzing the signals of the logic unit, and the influence probability and the performance change are determined according to the result of simulating the occurrence of the first event for the logic unit. The influence probability of the first event on the performance of the logic unit is the probability that the first event has an impact on the performance of the logic unit; A verification module, configured to evaluate the reliability of the circuit to be verified when the first event occurs according to the reliability factors of the logic units in the circuit to be verified.

15. A computer device, characterized in that, Comprising: A memory, storing at least one set of instructions; A processor, configured to execute the at least one set of instructions to perform the reliability factor determination method according to any one of claims 1 to 9, or the reliability evaluation method according to any one of claims 10 to 12.

16. A readable storage medium, characterized in that, The readable storage medium stores at least one set of instructions, and the at least one set of instructions is used to cause the processor to execute the reliability factor determination method according to any one of claims 1 to 9, or the reliability evaluation method according to any one of claims 10 to 12.

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