Display panel, method for manufacturing display panel, and display terminal

Abstract

The present application relates to a display panel, a method for preparing a display panel, and a display terminal, wherein the display panel includes an array substrate and a plurality of thin film transistors, wherein the plurality of thin film transistors are arranged on one side of the array substrate, and each of the thin film transistors includes a plurality of layers, wherein at least one of the plurality of thin film transistors is a vertical transistor, and the layers of the vertical transistors are stacked in a direction perpendicular to the array substrate. The present application reduces the size of the thin film transistors in the display panel by making at least one of the plurality of thin film transistors in the display panel a vertical transistor, and stacking the layers of the vertical transistors in a direction perpendicular to the array substrate, thereby improving the penetration rate and aperture rate of the display panel, and improving the black line problem that occurs when the display panel displays images.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a method for preparing a display panel, and a display terminal. Background Art

[0002] With the development of the times, displays have become more and more popular. With the advent of the 5G era, interactive display devices are gaining more and more attention. In addition to conventional close-range touch functions, more and more application scenarios require remote touch functions. For example, in a large conference room or classroom, a speaker can use a long-range laser pen instead of fingers to mark or write on the screen, which improves the efficiency and convenience of interaction.

[0003] For displays, in order to save costs, photosensitive devices need to be made on array (i.e., Array) substrates or color film (i.e., CF) substrates and packaged inside the display. This design reduces costs, but the introduction of sensors also reduces the aperture ratio and penetration rate of the display part, while reducing the resolution of the display. In order to solve these problems, the method of enhancing the backlight intensity can be adopted, but enhancing the backlight intensity will increase the cost of the entire machine and increase the power consumption of the display, so that remote light-sensitive touch displays can only be used in some lower-end scenarios, and the scope of application is limited. Summary of the invention

[0004] In view of this, the present application proposes a display panel, a method for preparing a display panel and a display terminal, which can reduce the size of the thin film transistor in the display panel, thereby improving the transmittance and aperture ratio of the display panel, and improving the black line problem that occurs when the display panel displays the picture.

[0005] According to one aspect of the present application, a display panel is provided, which includes an array substrate and a plurality of thin film transistors, wherein the plurality of thin film transistors are arranged on one side of the array substrate, and each of the thin film transistors includes a plurality of layers, wherein at least one of the plurality of thin film transistors is a vertical transistor, and the layers of the vertical transistors are stacked in a direction perpendicular to the array substrate.

[0006] Furthermore, the vertical transistor includes a first electrode layer, an interlayer insulating layer, a second electrode layer, an active layer, a gate insulating layer and a third electrode layer which are stacked in a direction perpendicular to the array substrate.

[0007] Further, the vertical transistor includes a gate, a source and a drain, wherein the gate of the vertical transistor is arranged in the third electrode layer of the vertical transistor; the source of the vertical transistor is arranged in the first electrode layer of the vertical transistor, and the drain of the vertical transistor is arranged in the second electrode layer of the vertical transistor; or, the drain of the vertical transistor is arranged in the first electrode layer of the vertical transistor, and the source of the vertical transistor is arranged in the second electrode layer of the vertical transistor.

[0008] Furthermore, the first electrode layer of the vertical transistor is disposed on one side of the array substrate, wherein a first region and a second region are disposed on a side of the first electrode layer of the vertical transistor away from the array substrate.

[0009] Furthermore, the interlayer insulating layer of the vertical transistor includes a first interlayer insulating layer and a second interlayer insulating layer, and the first interlayer insulating layer of the vertical transistor is connected to the second interlayer insulating layer of the vertical transistor, wherein the first interlayer insulating layer of the vertical transistor is arranged in a first region of the vertical transistor; and the second interlayer insulating layer of the vertical transistor is arranged in a region adjacent to the first region of the vertical transistor on one side of the array substrate.

[0010] Furthermore, the second electrode layer of the vertical transistor is arranged on a side of the interlayer insulating layer of the vertical transistor away from the array substrate, wherein the shape of the second electrode layer of the vertical transistor is similar to the shape of the interlayer insulating layer of the vertical transistor, and a third region and a fourth region are arranged on the side of the second electrode layer of the vertical transistor away from the array substrate.

[0011] Further, the active layer of the vertical transistor includes a first active layer, a second active layer, a third active layer and a fourth active layer, and the first active layer, the second active layer, the third active layer and the fourth active layer of the vertical transistor are connected to each other in sequence, wherein the first active layer of the vertical transistor is arranged in the third region of the vertical transistor; the second active layer of the vertical transistor is arranged between the first active layer and the third active layer of the vertical transistor, and is respectively connected to the edge of the first active layer and the edge of the third active layer of the vertical transistor; the third active layer of the vertical transistor is arranged in the second region of the vertical transistor; and the fourth active layer of the vertical transistor is arranged on one side of the array substrate.

[0012] Furthermore, the gate insulation layer of the vertical transistor is arranged on a side of the active layer of the vertical transistor away from the array substrate, and the third electrode layer of the vertical transistor is arranged on a side of the gate insulation layer of the vertical transistor away from the substrate, wherein the shape of the gate insulation layer of the vertical transistor is similar to the shape of the third electrode layer of the vertical transistor.

[0013] According to another aspect of the present application, a method for preparing a display panel is provided, and the method for preparing a display panel is used to prepare the display panel, and the method for preparing a display panel comprises: preparing the array substrate; preparing the plurality of thin film transistors on one side of the array substrate, wherein at least one of the plurality of thin film transistors is a vertical transistor, and each layer of the vertical transistor is prepared along a direction perpendicular to the array substrate, thereby obtaining the display panel.

[0014] According to another aspect of the present application, a display terminal is provided. The display terminal includes a terminal body and the display panel, wherein the terminal body is connected to the display panel.

[0015] By making at least one of the multiple thin film transistors in the display panel a vertical transistor and stacking the layers of the vertical transistors in a direction perpendicular to the array substrate, according to various aspects of the present application, the size of the thin film transistors in the display panel can be reduced, thereby improving the transmittance and aperture ratio of the display panel, and improving the black line problem that occurs when the display panel displays images. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0017] Figure 1 A schematic diagram showing the structure of a display panel and a display screen in the related art.

[0018] Figure 2 A schematic structural diagram of a display panel according to an embodiment of the present application is shown.

[0019] Figure 3 A schematic structural diagram of a display panel according to an embodiment of the present application is shown.

[0020] Figure 4 A schematic structural diagram of a display panel according to an embodiment of the present application is shown.

[0021] Figure 5 A schematic diagram showing a method for preparing a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0023] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0024] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0025] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the examples of various specific processes and materials provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials. In some instances, methods, means, components and circuits well known to those skilled in the art are not described in detail, so as to highlight the subject matter of the present application.

[0026] Figure 1 A schematic diagram showing the structure of a display panel and a display screen in the related art.

[0027] like Figure 1As shown, the left half is a schematic diagram of the structure of the display panel 11 in the related art. Among them, the display panel 11 can be a remote light touch display panel, 111 can be a backlight panel, 112 can be an array substrate, 113 can be a color film substrate, and 12 can be a laser pen. A red color group unit (i.e., R), a green color group unit (i.e., G), a blue color group unit (i.e., B), a light control sensor unit (i.e., Sensor) and a black matrix (i.e., BM) are arranged between the array substrate 112 and the color film substrate 113. Each color group unit can transmit light, while the part blocked by the black matrix (for example, the metal wiring in the light control sensor unit) cannot transmit light.

[0028] Specifically, in Figure 1 In the display, since the light sensing part of the light control sensor unit is equipped with some metal wiring or display materials, a black matrix needs to be introduced as a light shielding layer to shield the light sensor part to improve the display quality. However, the introduction of the black matrix will greatly reduce the aperture ratio and penetration rate of the display, and if the width and density of the black matrix are not appropriate, it will produce the following Figure 1 The right half of the display screen 13 shows black lines visible to the naked eye, which limits the application scenarios of the remote optical touch display.

[0029] In view of this, the present application provides a display panel, the display panel includes an array substrate and a plurality of thin film transistors, the plurality of thin film transistors are arranged on one side of the array substrate, each of the thin film transistors includes a plurality of layers, wherein at least one of the plurality of thin film transistors is a vertical transistor, and the layers of the vertical transistors are stacked in a direction perpendicular to the array substrate. By making at least one of the plurality of thin film transistors in the display panel a vertical transistor, and stacking the layers of the vertical transistors in a direction perpendicular to the array substrate, the present application can reduce the size of the thin film transistors in the display panel, thereby improving the penetration rate and aperture rate of the display panel, and improving the black line problem that occurs when the display panel displays images.

[0030] Figure 2 A schematic structural diagram of a display panel according to an embodiment of the present application is shown.

[0031] like Figure 2 As shown, in the display panel of the embodiment of the present application, the display panel can be cut open along a fixed section line in the display panel to obtain Figure 2 The structural diagram of the display panel is shown in FIG. Figure 2 The structure mainly includes a vertical transistor structure, which is exemplary. Other types of transistors may also be provided for the entire display panel. The present application does not limit the type of each transistor in the display panel.

[0032] Further, the layers of the vertical transistor are stacked in a direction perpendicular to the array substrate. In the vertical transistor, each layer may be stacked in sequence in a direction perpendicular to the array substrate, or some layers may be stacked in a direction perpendicular to the array substrate. The layers of the vertical transistor may also be partially overlapped. It is understood that the stacking order and stacking method of the layers of the vertical transistor in the embodiment of the present application may be set as needed, and the present application does not limit the stacking order and stacking method of the layers of the vertical transistor.

[0033] Furthermore, the vertical transistor includes a first electrode layer, an interlayer insulating layer, a second electrode layer, an active layer, a gate insulating layer, and a third electrode layer stacked in a direction perpendicular to the array substrate. Figure 2 In the embodiment, the first electrode layer 22, the interlayer insulating layer 23, the second electrode layer 24, the active layer 25, the gate insulating layer 26 and the third electrode layer 27 are stacked in a direction perpendicular to the array substrate. The array substrate 21 can provide a support surface for the plurality of vertical transistors. It can be understood that other layers such as encapsulation layers can also be provided in the vertical transistors, and the present application does not limit the number of layers of the vertical transistors.

[0034] Further, the vertical transistor includes a gate, a source and a drain, wherein the gate of the vertical transistor is arranged in the third electrode layer of the vertical transistor; the source of the vertical transistor is arranged in the first electrode layer of the vertical transistor, and the drain of the vertical transistor is arranged in the second electrode layer of the vertical transistor; or, the drain of the vertical transistor is arranged in the first electrode layer of the vertical transistor, and the source of the vertical transistor is arranged in the second electrode layer of the vertical transistor.

[0035] by Figure 2 For example, the gate of the vertical transistor can be set in the third electrode layer 27, the source of the vertical transistor can be set in the first electrode layer 22 or in the second electrode layer 24, and the drain of the vertical transistor can be set in the first electrode layer 22 or in the second electrode layer 24. It can be understood that whether the source and drain of the vertical transistor are specifically set in the first electrode layer or the second electrode layer can be determined according to the type of the vertical transistor. For example, when the type of the vertical transistor is N-type, the source of the vertical transistor can be set in the first electrode layer, and the drain of the vertical transistor can be set in the second electrode layer. It can be understood that the present application does not limit the specific type of the vertical transistor.

[0036] Furthermore, the first electrode layer of the vertical transistor is disposed on one side of the array substrate, wherein a first region and a second region are disposed on a side of the first electrode layer of the vertical transistor away from the array substrate.

[0037] See also Figure 2 , the first region may be a region in the first electrode layer 22 of the vertical transistor that contacts the interlayer insulating layer 23; the second region may be a region in the first electrode layer 22 of the vertical transistor that contacts the active layer 25. It can be understood that the size and shape of the first region and the second region of any vertical transistor can be set according to actual needs, and the present application does not limit the size and shape of the first region and the second region.

[0038] Furthermore, the interlayer insulating layer of the vertical transistor includes a first interlayer insulating layer and a second interlayer insulating layer, and the first interlayer insulating layer of the vertical transistor is connected to the second interlayer insulating layer of the vertical transistor, wherein the first interlayer insulating layer of the vertical transistor is arranged in a first region of the vertical transistor; and the second interlayer insulating layer of the vertical transistor is arranged in a region adjacent to the first region of the vertical transistor on one side of the array substrate.

[0039] Continue to see Figure 2 , the first interlayer insulating layer of the vertical transistor is arranged in the first region of the first electrode layer 22, that is, the first interlayer insulating layer of the vertical transistor is in contact with the first region on the surface of the first electrode layer 22. At the same time, the second interlayer insulating layer of the vertical transistor is arranged in a region adjacent to the first region of the vertical transistor, that is, a region in contact with the interlayer insulating layer 23 in the array substrate 21 of the vertical transistor.

[0040] Furthermore, the shape of the first interlayer insulating layer may be a combination of a first trapezoid and a second trapezoid, and the shape of the second interlayer insulating layer may be a rectangle, wherein the first trapezoid may be a right-angled trapezoid disposed on the first electrode layer 22; and the second trapezoid may be disposed opposite to the first trapezoid in a direction perpendicular to the array substrate. Figure 2 In the embodiment, on a side close to the second region of the vertical transistor, one side of the first trapezoid and one side of the second trapezoid are located in the same straight line. The inclined plane where the straight line is located is a first slope, and the acute angle between the first slope and the direction perpendicular to the array substrate can be a first slope. The first trapezoid can be in contact with the second interlayer insulation.

[0041] Furthermore, the height of the first interlayer insulating layer is greater than the height of the second interlayer insulating layer. Figure 2 In the embodiment, the height difference between the first interlayer insulating layer and the second interlayer insulating layer may be the height of the second trapezoid, the inclined surface where the other side of the second trapezoid is located may be the second slope, and the second slope is in contact with the second electrode layer 24. The acute angle between the second slope and the direction perpendicular to the array substrate 21 may be the second slope.

[0042] It is worth noting that, in the embodiment of the present application, the interlayer insulating layer of the vertical transistor is divided into a first interlayer insulating layer and a second interlayer insulating layer, but in the actual preparation process of the vertical transistor, the first interlayer insulating layer and the second interlayer insulating layer can be deposited on the array substrate and the first electrode layer at the same time, that is, the first interlayer insulating layer and the second interlayer insulating layer can actually be a whole. In addition to the interlayer insulating layer, the second electrode layer 24, the active layer 25, the gate insulating layer 26 and the third electrode layer 27 of the embodiment of the present application also have a similar division method as the interlayer insulating layer, which will not be repeated.

[0043] Furthermore, the second electrode layer of the vertical transistor is arranged on a side of the interlayer insulating layer of the vertical transistor away from the array substrate, wherein the shape of the second electrode layer of the vertical transistor is similar to the shape of the interlayer insulating layer of the vertical transistor, and a third region and a fourth region are arranged on the side of the second electrode layer of the vertical transistor away from the array substrate.

[0044] See also Figure 2 , the third region can be arranged relative to the first region of the vertical transistor along a direction perpendicular to the array substrate. For example, the orthographic projection of the third region on the array substrate 21 can be the same as the orthographic projection of the first region of the vertical transistor on the array substrate 21, or can be retracted by a fixed length along the orthographic projection of the first region of the vertical transistor on the array substrate 21. The fourth region can be arranged relative to the second interlayer insulating layer of the vertical transistor along a direction perpendicular to the array substrate, that is, the orthographic projection of the fourth region on the array substrate 21 can be the same as the orthographic projection of the second interlayer insulating layer of the vertical transistor on the array substrate 21. In addition, the second electrode layer 24 of the vertical transistor can be arranged along the interlayer insulating layer 23 and completely cover the interlayer insulating layer 23, and the shape of the second electrode layer 24 can be similar to the shape of the interlayer insulating layer 23.

[0045] Further, the active layer of the vertical transistor includes a first active layer, a second active layer, a third active layer and a fourth active layer, and the first active layer, the second active layer, the third active layer and the fourth active layer of the vertical transistor are connected to each other in sequence, wherein the first active layer of the vertical transistor is arranged in the third region of the vertical transistor; the second active layer of the vertical transistor is arranged between the first active layer and the third active layer of the vertical transistor, and is respectively connected to the edge of the first active layer and the edge of the third active layer of the vertical transistor; the third active layer of the vertical transistor is arranged in the second region of the vertical transistor; and the fourth active layer of the vertical transistor is arranged on one side of the array substrate.

[0046] Continue to see Figure 2, the active layer 25 of the vertical transistor can be divided into four sections, namely the first active layer, the second active layer, the third active layer and the fourth active layer. Among them, the first active layer can be arranged in the third region of the vertical transistor, and the orthographic projection range of the first active layer on the array substrate 21 is smaller than the size of the third region. That is, the first active layer can contact a part of the third region, but not the entire region of the third region.

[0047] Further, see Figure 2 The second active layer of the vertical transistor may be attached to one side of the interlayer insulating layer and one side of the second electrode layer, and the direction of the second active layer may form a fixed angle with the direction perpendicular to the array substrate 21. The direction of the second active layer may form a third slope, and the acute angle between the direction of the second active layer and the direction perpendicular to the array substrate 21 may be the third slope.

[0048] Further, see Figure 2 The third active layer of the vertical transistor can be set in the second area of ​​the vertical transistor and connected to the fourth active layer and the second active layer of the vertical transistor respectively; the fourth active layer of the vertical transistor can contact the area adjacent to the second area in the array substrate 21.

[0049] Preferably, the active layer of the vertical transistor is made of a-Si:H material, and the film thickness of the active layer of the vertical transistor is in the range of 3000 angstroms to 8000 angstroms.

[0050] Furthermore, the gate insulation layer of the vertical transistor is arranged on a side of the active layer of the vertical transistor away from the array substrate, and the third electrode layer of the vertical transistor is arranged on a side of the gate insulation layer of the vertical transistor away from the substrate, wherein the shape of the gate insulation layer of the vertical transistor is similar to the shape of the third electrode layer of the vertical transistor.

[0051] For example, see Figure 2 , the gate insulating layer of the vertical transistor may be in a zigzag shape. The gate insulating layer of the vertical transistor may also be divided into a first gate insulating layer, a second gate insulating layer and a third gate insulating layer in the same manner as the second active layer is divided. The second gate insulating layer of the vertical transistor may be connected to the first gate insulating layer and the third gate insulating layer, respectively. The direction of the second gate insulating layer of the vertical transistor may be at a fixed angle to the direction perpendicular to the array substrate 21, forming a fourth slope, and the acute angle between the direction of the second gate insulating layer of the vertical transistor and the direction perpendicular to the array substrate 21 may be a fourth slope.

[0052] Likewise, in Figure 2In the embodiment, the third electrode layer of the vertical transistor may be in a zigzag shape. The third electrode layer of the vertical transistor may also be divided into a fourth electrode layer, a fifth electrode layer and a sixth electrode layer in the same manner as the second active layer. The fifth electrode layer of the vertical transistor may be connected to the fourth electrode layer and the sixth electrode layer, respectively. The direction of the fifth electrode layer of the vertical transistor may be at a fixed angle to the direction perpendicular to the array substrate 21, forming a fifth slope, and the acute angle between the direction of the fifth electrode layer of the vertical transistor and the direction perpendicular to the array substrate 21 may be a fifth slope.

[0053] Furthermore, the first slope, the second slope, the third slope, the fourth slope and the fifth slope of a vertical transistor can be flexibly set as needed. Figure 2 In the embodiment, the fifth slope is less than the fourth slope, so that the third electrode layer is steeper, thereby further improving the penetration rate and aperture ratio of the display panel. It can be understood that the present application does not limit the first slope, the second slope, the third slope, the fourth slope and the fifth slope in the vertical transistor.

[0054] Exemplarily, the materials used for the first electrode layer, the second electrode layer and the third electrode layer include aluminum or copper, and the thickness of the first electrode layer, the second electrode layer and the third electrode layer is in the range of 2000 angstroms to 7000 angstroms. The materials used for the interlayer insulating layer and the gate insulating layer include SiNx film layers, and the thickness of the interlayer insulating layer and the gate insulating layer is in the range of 2000 angstroms to 10000 angstroms. The thickness of the interlayer insulating layer and the gate insulating layer can be adjusted according to the inclination degree of the corresponding slope and the process capability.

[0055] Figure 3 A schematic structural diagram of a display panel according to an embodiment of the present application is shown.

[0056] like Figure 3 As shown, Figure 3 This is a variation of the display panel of the embodiment of the present application. Figure 3 , the display panel may include an array substrate 31 and at least one vertical transistor. Figure 3 Each layer of the vertical transistor may include a first electrode layer 32, an interlayer insulating layer 33, a second electrode layer 34, an active layer 35, a gate insulating layer 36, and a third electrode layer 37. The first electrode layer 32, the interlayer insulating layer 33, the second electrode layer 34, the active layer 35, the gate insulating layer 36, and the third electrode layer 37 are stacked in a direction perpendicular to the array substrate.

[0057] Compared to Figure 2 The structure of the vertical transistor in Figure 3In the embodiment, the two edge portions of the third electrode layer 37 may be cut off, that is, Figure 3 The length of the fourth electrode may be less than Figure 2 The length of the fourth electrode, Figure 3 The length of the sixth electrode may be less than Figure 2 The length of the sixth electrode. Of course, Figure 3 For example, the active layer, the first electrode layer, the second electrode layer and the interlayer insulating layer may be Figure 2 same, Figure 3 The length of the first gate insulating layer may also be less than Figure 2 The length of the first insulating layer in the middle. Such a setting can further reduce the size of the vertical transistor, thereby further improving the penetration rate and aperture ratio of the display panel. It can be understood that more variations can be made based on various embodiments of the present application, which will not be repeated.

[0058] Figure 4 A schematic structural diagram of a display panel according to an embodiment of the present application is shown.

[0059] like Figure 4 As shown, the display panel may be provided with two types of vertical transistors, namely Figure 2 The vertical transistor 44 and Figure 3 The vertical transistor 46 is shown in FIG. Figure 4 The display panel is also provided with an array substrate 41, a liquid crystal layer 42, a color group layer 43 and a color filter substrate 44. Among them, the color group layer 43 can be provided with a plurality of black matrices.

[0060] See also Figure 4 , the black matrix 47 corresponding to the vertical transistor 44 is larger than the black matrix 48 corresponding to the vertical transistor 46. Since the vertical transistor 46 shortens the size of the third electrode layer and the gate insulating layer of the vertical transistor, the size of the black matrix corresponding to the vertical transistor 46 can be further reduced, thereby further improving the penetration rate and aperture ratio of the display panel. It can be understood that Figure 4 The structure in is exemplary, and the present application does not limit the number of various types of vertical transistors.

[0061] The present application also provides a display terminal, which includes a terminal body and the display panel, wherein the terminal body is connected to the display panel.

[0062] In addition, the present application also provides a method for preparing a display panel, the method for preparing a display panel is used to prepare the display panel, and the method for preparing a display panel includes:

[0063] Step S10: preparing the array substrate;

[0064] Step S20: preparing the plurality of thin film transistors on one side of the array substrate, wherein at least one of the plurality of thin film transistors is a vertical transistor, and each layer of the vertical transistor is prepared along a direction perpendicular to the array substrate, thereby obtaining the display panel.

[0065] Figure 5 A schematic diagram showing a method for preparing a display panel according to an embodiment of the present application.

[0066] like Figure 5 As shown, step S20 may include steps S21 to S24, wherein:

[0067] Step S21: disposing the first electrode layer on one side of the array substrate;

[0068] Step S22: disposing an interlayer insulating layer of at least one vertical transistor on a side of the array substrate facing the first electrode layer and on a side of the first electrode layer facing away from the array substrate, and disposing the second electrode layer on a side of the interlayer insulating layer facing away from the array substrate;

[0069] Step S23: disposing the active layer on the side of the second electrode layer away from the array substrate, partially covering the second electrode layer, the interlayer insulating layer, the first electrode layer and the array substrate, and disposing the gate insulating layer on the side of the active layer away from the array substrate, and disposing the third electrode layer on the side of the gate insulating layer away from the array substrate, to prepare a vertical transistor;

[0070] Step S24: Covering the side of the vertical transistor obtained in step 23 away from the array substrate with a passivation layer 51;

[0071] Step S25: Covering the seventh electrode layer 52 on the side of the passivation layer 51 away from the array substrate, and forming a through hole in the passivation layer 51 to electrically connect the seventh electrode layer 52 to the source or drain of the vertical transistor, thereby preparing the display panel.

[0072] It should be noted that step S24 and step S25 are exemplary. In practical applications, other electrodes, through holes or metal wirings may be provided as required. The present application does not limit the specific preparation process of the vertical transistor.

[0073] To summarize, the embodiment of the present application reduces the size of the thin film transistors in the display panel by making at least one of the multiple thin film transistors in the display panel a vertical transistor and stacking the layers of the vertical transistors in a direction perpendicular to the array substrate, thereby avoiding the problem of decreased transmittance and aperture ratio of the display panel due to the additional introduction of photosensitive units, thereby improving the transmittance and aperture ratio of the display panel, and improving the black line problem that appears when the display panel displays an image, thereby expanding the application scenarios of remote optical touch display panels, and being suitable for LCD, OLED, u-LED, mini-LED and other fields.

[0074] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0075] The display panel, the method for preparing the display panel and the display terminal provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel includes an array substrate and a plurality of thin film transistors, wherein the plurality of thin film transistors are arranged on one side of the array substrate, and each of the thin film transistors includes a plurality of layers, wherein: At least two of the plurality of thin film transistors are vertical transistors, and each layer of the vertical transistors is stacked in a direction perpendicular to the array substrate; The vertical transistor comprises a first electrode layer, an interlayer insulating layer, a second electrode layer, an active layer, a gate insulating layer and a third electrode layer stacked in a direction perpendicular to the array substrate; The two vertical transistors are respectively a first vertical transistor and a second vertical transistor, the size of the gate insulation layer of the first vertical transistor is smaller than the size of the gate insulation layer of the second vertical transistor, and the size of the third electrode layer of the first vertical transistor is smaller than the size of the third electrode layer of the second vertical transistor.

2. The display panel according to claim 1, characterized in that: The vertical transistor includes a gate, a source and a drain, wherein: The gate of the vertical transistor is arranged in the third electrode layer of the vertical transistor; The source of the vertical transistor is arranged in the first electrode layer of the vertical transistor, and the drain of the vertical transistor is arranged in the second electrode layer of the vertical transistor; or, the drain of the vertical transistor is arranged in the first electrode layer of the vertical transistor, and the source of the vertical transistor is arranged in the second electrode layer of the vertical transistor.

3. The display panel according to claim 1, characterized in that: The first electrode layer of the vertical transistor is arranged on one side of the array substrate, wherein: A first region and a second region are disposed on a side of the first electrode layer of the vertical transistor away from the array substrate.

4. The display panel according to claim 3, characterized in that: The interlayer insulating layer of the vertical transistor includes a first interlayer insulating layer and a second interlayer insulating layer, and the first interlayer insulating layer of the vertical transistor is connected to the second interlayer insulating layer of the vertical transistor, wherein: The first interlayer insulating layer of the vertical transistor is disposed in a first region of the vertical transistor; The second interlayer insulating layer of the vertical transistor is disposed in a region adjacent to the first region of the vertical transistor in one side of the array substrate.

5. The display panel according to claim 4, characterized in that: The second electrode layer of the vertical transistor is arranged on a side of the interlayer insulating layer of the vertical transistor away from the array substrate, wherein: The shape of the second electrode layer of the vertical transistor is similar to the shape of the interlayer insulating layer of the vertical transistor. A third region and a fourth region are arranged on a side of the second electrode layer of the vertical transistor away from the array substrate.

6. The display panel according to claim 5, characterized in that: The active layer of the vertical transistor includes a first active layer, a second active layer, a third active layer and a fourth active layer, and the first active layer, the second active layer, the third active layer and the fourth active layer of the vertical transistor are sequentially connected to each other, wherein: The first active layer of the vertical transistor is arranged in a third region of the vertical transistor; The second active layer of the vertical transistor is disposed between the first active layer and the third active layer of the vertical transistor, and is respectively connected to the edge of the first active layer and the edge of the third active layer of the vertical transistor; The third active layer of the vertical transistor is disposed in the second region of the vertical transistor; The fourth active layer of the vertical transistor is disposed on one side of the array substrate.

7. The display panel according to claim 6, characterized in that: The gate insulation layer of the vertical transistor is arranged on a side of the active layer of the vertical transistor away from the array substrate, and the third electrode layer of the vertical transistor is arranged on a side of the gate insulation layer of the vertical transistor away from the substrate, wherein the shape of the gate insulation layer of the vertical transistor is similar to the shape of the third electrode layer of the vertical transistor.

8. A method for preparing a display panel, characterized in that: The method for preparing the display panel is used to prepare the display panel according to any one of claims 1 to 7, and the method for preparing the display panel comprises: preparing the array substrate; The plurality of thin film transistors are prepared on one side of the array substrate, wherein at least two of the plurality of thin film transistors are vertical transistors, and each layer of the vertical transistors is prepared along a direction perpendicular to the array substrate, thereby obtaining the display panel; The vertical transistor comprises a first electrode layer, an interlayer insulating layer, a second electrode layer, an active layer, a gate insulating layer and a third electrode layer stacked in a direction perpendicular to the array substrate; The two vertical transistors are respectively a first vertical transistor and a second vertical transistor, the size of the gate insulation layer of the first vertical transistor is smaller than the size of the gate insulation layer of the second vertical transistor, and the size of the third electrode layer of the first vertical transistor is smaller than the size of the third electrode layer of the second vertical transistor.

9. A display terminal, characterized in that: The display terminal comprises a terminal body and the display panel according to any one of claims 1 to 7, wherein the terminal body is connected to the display panel.

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