Printed circuit board

Abstract

A printed circuit board is provided. The printed circuit board includes an insulating layer, a metal pad disposed on one side of the insulating layer, a via hole passing through the insulating layer to expose at least a portion of the metal pad, and a via filling at least a portion of the via hole, wherein the via includes a first metal layer and a second metal layer disposed on the first metal layer, and an average size of grains in the first metal layer and an average size of grains in the second metal layer are different from each other.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0092417, filed on July 24, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a printed circuit board. BACKGROUND

[0003] When a via is formed on a printed circuit board, in order to improve heat dissipation characteristics and the like, it is preferable to form a filled via in which an inner space is filled with a metal material. However, due to limitations of currently developed technology, a large-sized filled via has a problem of voids and dishing. In this case, not only the reliability of the board can be problematic, but it can also be difficult to implement a stacked via structure that is advantageous in terms of board heat dissipation or signal transfer characteristics. In addition, the via is generally formed to extend onto the board when the inner space of the via is filled. In this case, the metal layer extending onto the board has a large thickness, and an additional process such as etching or the like can be required to reduce the thickness of the thick metal layer. SUMMARY

[0004] An aspect of the present disclosure is to provide a printed circuit board capable of preventing voids from occurring in a via.

[0005] Another aspect of the present disclosure is to provide a printed circuit board having excellent reliability.

[0006] Another aspect of the present disclosure is to provide a printed circuit board capable of preventing dishing from occurring in a via.

[0007] Another aspect of the present disclosure is to provide a printed circuit board including a stacked via.

[0008] Another aspect of the present disclosure is to provide a printed circuit board having excellent heat dissipation characteristics.

[0009] Another aspect of the present disclosure is to provide a printed circuit board capable of rapidly transferring a signal.

[0010] Another aspect of the present disclosure is to provide a printed circuit board capable of reducing plating thickness.

[0011] Another aspect of the present disclosure is to provide a printed circuit board having a simplified manufacturing process and reduced manufacturing costs.

[0012] In accordance with an aspect of the disclosure, a printed circuit board includes an insulating layer, a metal pad disposed on one side of the insulating layer, a via hole passing through the insulating layer to expose at least a portion of the metal pad, and a via filling at least a portion of the via hole, wherein the via includes a first metal layer and a second metal layer disposed on the first metal layer, and an average size of grains in the first metal layer and an average size of grains in the second metal layer are different from each other.

[0013] In accordance with another aspect of the disclosure, a printed circuit board includes an insulating layer, a metal pad disposed on one side of the insulating layer, a via hole passing through the insulating layer to expose at least a portion of the metal pad, and a via filling at least a portion of the via hole, wherein the via includes a first metal layer and a second metal layer, the second metal layer includes a first region and a second region, and the second metal layer is disposed on the first metal layer, and an average size of grains in the first region of the second metal layer and an average size of grains in the second region are different from each other.

[0014] In accordance with another aspect of the disclosure, a printed circuit board includes an insulating layer, a metal pad disposed on one side of the insulating layer, a via hole passing through the insulating layer to expose at least a portion of the metal pad, and a via filling at least a portion of the via hole. The via includes a first metal layer and a second metal layer disposed on the first metal layer, the first metal layer includes a first region and a second region, and an average size of grains in the first region of the first metal layer and an average size of grains in the second region are different from each other. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other aspects, features, and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a cross-sectional view schematically illustrating a printed circuit board according to an example embodiment of the disclosure;

[0017] Figure 2 is a graph illustrating average sizes of grains in respective regions of a metal layer of a printed circuit board according to an example embodiment;

[0018] Figure 3 is an image of a cross-section of a via of a printed circuit board according to an example embodiment, as observed by an optical microscope;

[0019] Figure 4 is a graph illustrating results of analyzing a via of a printed circuit board using electron backscatter diffraction (EBSD);

[0020] Figure 5 is a cross-sectional view schematically illustrating a printed circuit board according to another example embodiment; and

[0021] Figure 6 is a cross-sectional view schematically illustrating a multi-layer printed circuit board according to an example embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0023] Printed circuit board

[0024] Figure 1 is a cross-sectional view schematically illustrating a printed circuit board according to an example embodiment of the present disclosure.

[0025] Figure 2 is a graph illustrating average sizes of grains in respective regions of a metal layer of a printed circuit board according to an example embodiment.

[0026] The average size of the grains is determined based on an average value of sizes of the grains included in each region. Alternatively, the average size of the grains can be determined based on an average particle diameter of the grains included in each region.

[0027] It is apparent that the actual average size of the grains in the respective regions of the metal layer can be different from the average sizes of the grains shown in the drawings. Also, it is shown in the drawings that there are voids between the grains; however, the voids can actually be filled with the grains.

[0028] Based on the drawings, the printed circuit board according to an example embodiment includes an insulating layer 110, a metal pad 120, a via hole VH, and a via 130.

[0029] Although not particularly limited, the insulating layer 110 can be formed with a thermosetting insulating resin such as an epoxy resin or a thermoplastic insulating resin such as a polyimide, or a resin prepared by impregnating a core material such as a glass cloth, a glass fabric, etc. and / or an inorganic filler in a thermosetting resin or a thermoplastic resin. For example, a prepreg, an Ajinomoto build-up film (ABF), etc. can be used. If necessary, a photosensitive dielectric (PID) can be used.

[0030] The metal pad 120 is disposed on one side of the insulating layer 110. As shown in the drawings, the metal pad 120 can be embedded in one side of the insulating layer 110, or, unlike the drawings, can be disposed on one side of the insulating layer 110. Also, when a plurality of insulating layers 110 are disposed, the metal pad 120 is disposed on each of the insulating layers 110 and is covered by the insulating layer 110 disposed on another layer.

[0031] The metal pad 120 can have various functions according to its design; for example, the metal pad 120 can be used as a wire or a heat transfer path. The metal pad 120 can include a metal material such as Cu, Al, Ag, Sn, Au, Ni, Pb, Ti, or an alloy thereof.

[0032] A via hole VH passes through the insulating layer 110 to expose at least a portion of the metal pad 120. Accordingly, a wall surface of the via hole VH is surrounded by the insulating layer 110, and the metal pad 120 is disposed on a bottom surface of the via hole VH. The shape of the via hole VH is not particularly limited, but can have, for example, a cylindrical shape, a tapered shape having a reduced width in a direction in which the via hole VH passes through the insulating layer 110 toward the metal pad 120. A method for forming the via hole VH is not limited, but can include, for example, laser processing, mechanical processing, or the like.

[0033] The via 130 can fill at least a portion of the via hole VH, and can be connected to the metal pad 120. The via 130 includes a first metal layer 131, a second metal layer 132 disposed on the first metal layer 131, and a third metal layer 133 disposed on the second metal layer 132. However, according to its design, the via 130 can include only the second metal layer 132 and the third metal layer 133 disposed on the second metal layer 132, and can not include the first metal layer 131.

[0034] In addition, the first metal layer 131 to the third metal layer 133 can extend onto a top surface of the insulating layer 110. This can enable the first metal layer 131 to the third metal layer 133 to be used as a via pad or connected to a wiring layer disposed on the same layer. However, as described below, the second metal layer 132 can not extend onto the top surface of the insulating layer 110, and can only fill an inner space of the via hole VH. In this case, the third metal layer 133 on the top surface of the insulating layer 110 can be directly disposed on the first metal layer 131.

[0035] The first metal layer 131 covers at least a portion of a wall surface of the via hole VH and at least a portion of an area of the metal pad 120 exposed through the via hole VH. The first metal layer 131 can extend onto a top surface of the insulating layer 110.

[0036] A method for forming the first metal layer 131 is not particularly limited, but can be electroless plating or electrolytic plating. The first metal layer 131 can be a seed layer introduced to enhance the bonding force between the insulating layer 110 and the second metal layer 132.

[0037] According to circumstances, the printed circuit board can not include the first metal layer 131. For example, in the case where the insulating layer 110 is formed of a material having excellent bonding force to metal, the first metal layer 131 serving as a seed layer can not be needed. In this case, the second metal layer 132 covers at least a portion of a wall surface of the via hole VH and at least a portion of an area of the metal pad 120 exposed through the via hole VH, and can fill a portion of the via hole VH.

[0038] The second metal layer 132 covers at least a portion of the first metal layer 131 and partially fills the via hole VH. In addition, the second metal layer 132 can extend onto a top surface of the insulating layer 110, and can be disposed on the first metal layer 131 disposed on the top surface of the insulating layer 110.

[0039] The thickness of the second metal layer 132 disposed on the top surface of the insulating layer 110 can be significantly smaller, and for example, can be smaller than the thickness of the third metal layer 133. When the thickness of the second metal layer 132 on the top surface of the insulating layer 110 is small, the total thickness of the metal layer extending onto the top surface of the insulating layer 110 can be reduced. The method of measuring the thickness of the second metal layer 132 includes, but is not limited to, the method of measuring the thickness of the second metal layer 132 understood by those skilled in the art.

[0040] In addition, the second metal layer 132 can not extend onto the top surface of the insulating layer 110, and can fill only the via hole VH. In this case, the third metal layer 133 can be directly disposed on the first metal layer 131 on the top surface of the insulating layer 110. Alternatively, in the case where the via hole 130 does not include the first metal layer 131, the third metal layer 133 can be directly disposed on the top surface of the insulating layer 110.

[0041] In addition, as shown in the drawings, the second metal layer 132 can have a recessed portion recessed toward the metal pad 120 on an interface between the second metal layer 132 and the third metal layer 133. Accordingly, in the thickness direction of the insulating layer, the thickness of the second metal layer 132 near the center of the via hole 130 can be smaller than the thickness of the second metal layer 132 at the periphery of the via hole 130. For example, the thickness of the second metal layer 132 can increase in a direction from the center of the recessed portion toward the periphery of the via hole 130. In addition, at least a portion of the recessed portion can be filled with the third metal layer 133. In the drawings, the recessed portion is shown to have a curved shape, but is not limited thereto.

[0042] The second metal layer 132 can be formed by electrolytic plating, and in particular, can be formed by pulse periodic reversal (PPR) plating involving periodically reversing the direction of pulse current. The PPR plating can facilitate the formation of the second metal layer 132, thereby filling a portion of the via hole VH with significantly large grains.

[0043] Further, the plating solution used in the PPR plating can include additives such as an accelerator, an inhibitor, etc., and can not include a leveling agent. The PPR plating is performed to fill the via hole VH, and this is because the surface of the plating layer does not need to be uniformly formed or extended onto the top surface of the insulating layer 110. Since the leveling agent functions as an electrochemically weak inhibitor, there can be an adverse effect that it is difficult to fill the via hole without voids when the plating solution used in the PPR plating includes the leveling agent.

[0044] Further, during the PPR plating, it can be preferable that the average current density of the forward current and the reverse current during the PPR plating is greater than or equal to 0.5 ASD (Ampere per Square Decimeter) and less than or equal to 5 ASD. If the average current density is less than 0.5 ASD, the plating time becomes long, and if the average current density is greater than 5 ASD, a side effect of forming uneven plating occurs. On the other hand, when plating is performed under the condition that the average current density is greater than or equal to 0.5 ASD and less than or equal to 5 ASD during the PPR plating, the inside of the via hole can be effectively filled with a large-sized grain without voids. Further, it can be preferable that the current includes at least one reverse current when the PPR plating. When the reverse current is applied, two effects can be expected. First, the reverse current can enable the via hole to be filled while maintaining the thickness of the plating layer on the insulating layer small, because the amount of the plating layer plated on the insulating layer is greater than the amount of the plating layer inside the via due to the resistance difference between the two electrodes. Further, the reverse current can enable the distribution of the additives on the insulating layer and inside the via to be adjusted to be different. The reverse current can cause desorption of the additives, and can enable the accelerator that can be adsorbed under the condition of a relatively slow flow rate to be concentrated inside the via. In order to have such an effect that there is a relatively increased amount of plating inside the via while there is a small plating thickness on the insulating layer, it is preferable that the time of the reverse current is 10 ms or more.

[0045] Further, it can be preferable that the cycle time at the time of the PPR plating is 100 ms. When the cycle time is less than 100 ms, the adsorption and desorption of the additives become unstable, resulting in a difference in the distribution of the additives in each region in the product. This can result in an adverse effect of uneven plating.

[0046] The second metal layer 132 has a first region 132A and a second region 132B. The first region 132A of the second metal layer 132 is disposed inside the via 130, and the second region 132B of the second metal layer 132 is disposed inside the via 130 and can surround the first region 132A of the second metal layer 132.

[0047] Furthermore, the average size of the grains in the first region 132A and the second region 132B of the second metal layer 132 is different from each other. Specifically, the average size of the grains in the first region 132A of the second metal layer 132 may be larger than the average size of the grains in the second region 132B of the second metal layer 132.

[0048] When PPR electroplating is performed, it is confirmed that the second region 132B of the second metal layer 132 with a significantly small average grain size is formed as a first region 132A with a large average grain size surrounding the second metal layer 132.

[0049] Furthermore, the average grain size in the second metal layer 132 and the average grain size in the third metal layer 133 may be different from each other. For example, the average grain size in the second metal layer 132 may be larger than the average grain size in the third metal layer 133. The second metal layer 132 formed by PPR electroplating can have a relatively large average grain size.

[0050] However, depending on the conditions under which the second metal layer 132 is formed, the average size of the grains in the second metal layer 132 may be smaller than the average size of the grains in the third metal layer 133. For example, if the second region 132B of the second metal layer 132 is formed to be large, the average size of the grains in the entire region of the second metal layer 132 may be reduced. In this case, the average size of the grains in the second metal layer 132 may be smaller than the average size of the grains in the third metal layer 133. Methods for measuring the grain sizes of the first metal layer 131, the second metal layer 132, and the third metal layer 133 include, but are not limited to, methods for measuring the grain sizes of the first metal layer 131, the second metal layer 132, and the third metal layer 133 known to those skilled in the art.

[0051] A third metal layer 133 may be disposed on the second metal layer 132 and fill the remaining portion of the via VH. Optionally, the third metal layer 133 may extend to the top surface of the insulating layer 110 and be disposed on the first metal layer 131 or the second metal layer 132. In this case, the thickness of the third metal layer 133 disposed on the top surface of the insulating layer 110 may be greater than the thickness of the second metal layer 132 disposed on the top surface of the insulating layer 110.

[0052] Furthermore, as shown in the accompanying drawings, the third metal layer 133 may fill at least a portion of the recess in the second metal layer 132. Therefore, the third metal layer 133 may have a protrusion projecting toward the bottom of the via.

[0053] The third metal layer 133 can be formed by electrolytic plating (specifically, direct current (DC) plating). The third metal layer 133, having a relatively small average grain size, can be formed by DC plating and can be used to fill the remaining via holes VH.

[0054] The plating solution used in DC plating may include accelerators, inhibitors, and leveling agents. Therefore, the plating solution used in DC plating may differ from the plating solution used in PPR plating. Since the surface of the third metal layer 133 formed by DC plating needs to be uniformly formed, it is preferable that the plating solution used in DC plating includes a leveling agent compared to the plating solution used in PPR plating.

[0055] Furthermore, the average size of the grains in the third metal layer 133 may be smaller than the average size of the grains in the first region 132A of the second metal layer 132, and may be larger than the average size of the grains in the second region 132B of the second metal layer 132. For example, the average size of the grains in the metal layers may increase in the following order: the average size of the grains in the second region 132B of the second metal layer 132, the average size of the grains in the third metal layer 133, and the average size of the grains in the first region 132A of the second metal layer 132.

[0056] Furthermore, the average size of the grains in the third metal layer 133 may be smaller than the average size of the grains in the second metal layer 132. Specifically, the average size of the grains in the third metal layer 133 may be smaller than the average size of the grains in the entire region of the second metal layer 132 (including the first region 132A and the second region 132B of the second metal layer 132).

[0057] However, depending on the formation conditions of the second metal layer 132, the average size of the grains in the third metal layer 133 can be larger than the average size of the grains in the second metal layer 132. For example, if the second region 132B of the second metal layer 132 is formed to be large, the average size of the grains in the second metal layer 132 can be reduced, and in this case, the average size of the grains in the third metal layer 133 can be larger than the average size of the grains in the second metal layer 132.

[0058] Furthermore, the interface between the second metal layer 132 and the third metal layer 133 may be inconspicuous and difficult to observe with the naked eye. Additionally, the interface between the second metal layer 132 and the third metal layer 133 may not have a smooth shape. Furthermore, the interface between the first region 132A and the second region 132B of the second metal layer 132 may be inconspicuous and difficult to observe with the naked eye.

[0059] Furthermore, when forming blind vias on a printed circuit board, it is preferable to form filled vias in which the vias are filled with a metal material to improve heat dissipation and other properties. However, due to limitations in currently developed technologies, when forming filled vias at large sizes, voids and pits can occur. In this case, not only will substrate reliability be problematic, but it will also be difficult to achieve a stacked via structure that is advantageous in terms of heat dissipation or signal transmission characteristics. Moreover, when filling vias, the vias are typically formed to extend onto the substrate, and in this case, the metal layer extending onto the substrate has a large thickness. To reduce the thickness of the metal layer, additional processes (such as etching) may be required.

[0060] According to this disclosure, a portion of the via VH is filled with a second metal layer 132 comprising a first region 132A having a large average grain size by PPR plating, and the remaining portion of the via VH is filled with a third metal layer 133 having a small average grain size by DC plating, thereby forming a via 130. Furthermore, prior to forming the second metal layer 132, a first metal layer 131 may be formed on the wall and bottom surfaces of the via VH by electroless plating or the like.

[0061] It is confirmed that when the via 130 is formed using the plating method disclosed in this disclosure, the via VH can be filled with a second metal layer 132 and a third metal layer 133 without creating voids or pits. In this respect, a printed circuit board with excellent reliability can be provided by preventing void generation. Furthermore, by preventing pit generation, a stacked via structure can be easily achieved, thereby providing a printed circuit board with excellent heat dissipation characteristics and the ability to transmit signals quickly. In addition, according to this disclosure, the thickness of the metal layers extending onto the substrate can be reduced, thus eliminating the need for additional processes such as etching, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0062] Figure 3 This is an image showing a cross-section of a via on a printed circuit board according to an example embodiment, as observed through an optical microscope.

[0063] As previously described, a first metal layer 131 is formed on the wall and bottom surfaces of the via hole VH by electroless plating, and a second metal layer 132 is formed by PPR plating to fill a portion of the via hole VH, and a third metal layer 133 is formed by DC plating to fill the remaining portion of the via hole VH.

[0064] During PPR plating, large grains are used to fill vias by setting the average current density from 0.5 ASD to 5 ASD, and the plating thickness is controlled by reverse current.

[0065] Optical microscopy revealed that the average grain size in the second metal layer 132 formed by PPR plating was larger than the average grain size in the third metal layer 133 formed by DC plating. Furthermore, the thickness of the second metal layer 132 on the top surface of the insulating layer 110 was very small.

[0066] Figure 4 This is a diagram showing the results of analyzing vias on a printed circuit board using electron backscatter diffraction (EBSD).

[0067] EBSD analysis was used to analyze the second metal layer 132 and the third metal layer 133 formed by PPR plating and DC plating, respectively, to more accurately analyze the average grain size in the second metal layer 132 and the third metal layer 133. The results confirmed that the second metal layer 132 has a first region 132A and a second region 132B with different average grain sizes.

[0068] Specifically, based on the accompanying drawings, the average grain size in the first region 132A of the second metal layer 132 is larger than the average grain size in the second region 132B of the second metal layer 132. That is, in addition to the first region 132A having a large average grain size, the second metal layer 132 also has a second region 132B with a significantly smaller average grain size.

[0069] Furthermore, the average size of the grains in the third metal layer 133 is smaller than the average size of the grains in the first region 132A of the second metal layer 132, and larger than the average size of the grains in the second region 132B of the second metal layer 132.

[0070] Figure 5 This is a schematic cross-sectional view of a printed circuit board according to another example embodiment.

[0071] Reference Figure 5 According to another example embodiment, the printed circuit board also includes a fourth metal layer 134 disposed on the top surface of the insulating layer 110.

[0072] The fourth metal layer 134 may be a thin metal film attached to the top surface of the insulating layer 110. For example, a board of stacked thin metal films may be used as the insulating layer 110, wherein a thin metal film, such as copper foil, is attached to at least the top surface of the insulating layer 110. In this case, a portion of the thin metal film is not removed and is retained during the formation of the printed circuit board, thereby forming the fourth metal layer 134.

[0073] The first metal layer 131 may be disposed on the fourth metal layer 134 on the top surface of the insulating layer 110. However, as mentioned above, the first metal layer 131 may be omitted, and the second metal layer 132 and / or the third metal layer 133 may be disposed on the fourth metal layer 134 on the top surface of the insulating layer 110.

[0074] Figure 6 This is a schematic cross-sectional view of a multilayer printed circuit board according to an example embodiment.

[0075] Reference Figure 6 The multilayer printed circuit board includes multiple insulating layers 110, multiple metal pads 120, multiple vias VH and multiple vias 130.

[0076] In this configuration, multiple insulating layers 110 are stacked to form a stacked structure, and multiple metal pads 120 are disposed on one side of the multiple insulating layers 110. Multiple vias VH pass through the multiple insulating layers 110 to expose at least a portion of the multiple metal pads 120, and multiple vias 130 fill the multiple vias VH.

[0077] Furthermore, at least two of the vias 130 may be stacked on top of each other in the direction of the stacked insulating layer 110. That is, at least two of the vias 130 may have a stacked via structure. Such a structure can provide a printed circuit board with excellent heat dissipation characteristics and the ability to transmit signals quickly.

[0078] Throughout this specification, it will be understood that when an element is referred to as being "on" another element, "connected to," or "bonded to" another element, the element may be directly "on" another element, directly "connected to," or directly "bonded to" another element, or there may be other elements in between. In contrast, when an element is referred to as being "directly on" another element, directly "connected to," or "bonded to" another element, there are no elements or layers in between. The same reference numerals always denote the same element. As used herein, the term "and / or" includes any one or more of the associated listed items, or a combination thereof. It will be apparent that although the terms first, second, third, etc., may be used herein to describe various components, assemblies, regions, layers, and / or parts, these components, assemblies, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one component, assembly, region, layer, or part from another component, assembly, region, layer, or part. Therefore, without departing from the teachings of the exemplary embodiments, the first component, first part, first region, first layer or first portion discussed above may be referred to as the second component, second part, second region, second layer or second portion.

[0079] The terminology used herein describes specific exemplary embodiments only, and this disclosure is not limited thereto. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. It will also be understood that the terms “comprising” and / or “including” as used herein enumerate the presence of the stated features, integers, steps, operations, components, elements, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, elements, and / or groups thereof.

[0080] As described above, as an effect of this disclosure, a printed circuit board capable of preventing voids from appearing in vias can be provided.

[0081] As another effect of this disclosure, a printed circuit board with excellent reliability can be provided.

[0082] As another effect of this disclosure, a printed circuit board is provided that can prevent pitting of vias.

[0083] As another effect of this disclosure, a printed circuit board including stacked vias can be provided.

[0084] As another effect of this disclosure, a printed circuit board with excellent heat dissipation characteristics can be provided.

[0085] As another effect of this disclosure, a printed circuit board capable of rapidly transmitting signals can be provided.

[0086] As another effect of this disclosure, a printed circuit board capable of reducing plating thickness can be provided.

[0087] As another effect of this disclosure, a printed circuit board with a simplified manufacturing process and reduced manufacturing costs can be provided.

[0088] Although exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board comprising: an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole passing through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, wherein the via comprises a first metal layer and a second metal layer disposed on the first metal layer, the first metal layer being located between the metal pad and the second metal layer, an average size of grains in the first metal layer and an average size of grains in the second metal layer are different from each other, and the average size of grains in the second metal layer is smaller than the average size of grains in a first region of the first metal layer. the average size of grains in the first metal layer is larger than the average size of grains in the second metal layer.

2. The printed circuit board of claim 1, wherein, the first metal layer includes a recess facing the metal pad on an interface between the first metal layer and the second metal layer, and 3. The printed circuit board of claim 1, wherein, the second metal layer fills at least a portion of the recess. the first metal layer further includes a second region, and 4. The printed circuit board of claim 1, wherein, the average size of grains in the first region and the second region of the first metal layer are different from each other. the first region of the first metal layer is disposed inside the via, and 5. The printed circuit board of claim 4, wherein, the second region of the first metal layer is disposed inside the via and surrounds the first region. the average size of grains in the first region of the first metal layer is larger than the average size of grains in the second region.

6. The printed circuit board of claim 5, wherein, the average size of grains in the second metal layer is larger than the average size of grains in the second region of the first metal layer.

7. The printed circuit board of claim 6, wherein, the via further includes a third metal layer covering at least a portion of a region of the metal pad exposed through the via hole and at least a portion of a wall surface of the via hole, and 8. The printed circuit board of any of claims 1-7, wherein, the first metal layer is disposed on the third metal layer. the second metal layer and the third metal layer extend onto a top surface of the insulating layer.

9. The printed circuit board of claim 8, wherein, on the top surface of the insulating layer, a thickness of the third metal layer is smaller than a thickness of the second metal layer.

10. The printed circuit board of claim 9, wherein, the via further includes a fourth metal layer disposed on the top surface of the insulating layer, and 11. The printed circuit board of claim 9, wherein, the third metal layer is disposed on the fourth metal layer. the insulating layer, the metal pad, the via hole, and the via each include a plurality of insulating layers, a plurality of metal pads, a plurality of via holes, and a plurality of vias, 12. The printed circuit board of claim 1, wherein, wherein: the plurality of insulating layers are stacked to form a stacked structure, the plurality of metal pads are disposed on one side of the plurality of insulating layers, the plurality of via holes pass through the plurality of insulating layers to expose at least a portion of the plurality of metal pads, the plurality of vias fill the plurality of via holes, and at least two of the plurality of vias are stacked in a direction in which the plurality of insulating layers are stacked.

13. A printed circuit board comprising: an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole passing through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, ​ ​ The via includes a first metal layer and a second metal layer, the second metal layer includes a first region away from a wall surface and a bottom surface of the via hole and a second region close to the wall surface and the bottom surface of the via hole and disposed on the first metal layer, and An average size of grains in the first region of the second metal layer and an average size of grains in the second region are different from each other.

14. The printed circuit board of claim 13, wherein, The first region of the second metal layer is disposed inside the via, and The second region of the second metal layer is disposed inside the via and surrounds the first region.

15. The printed circuit board of claim 14, wherein, An average size of grains in the first region of the second metal layer is greater than an average size of grains in the second region.

16. The printed circuit board of claim 15, wherein, The printed circuit board further includes a third metal layer disposed on the second metal layer, and An average size of grains in the third metal layer is smaller than an average size of grains in the first region of the second metal layer and greater than an average size of grains in the second region.

17. The printed circuit board of claim 16, wherein, The second metal layer does not extend onto a top surface of the insulating layer.

18. The printed circuit board of claim 17, wherein, The third metal layer is disposed directly on the first metal layer disposed on the top surface of the insulating layer.

19. A printed circuit board, comprising: an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole passing through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, wherein the via includes a first metal layer and a second metal layer disposed on the first metal layer, the first metal layer includes a first region away from a wall surface and a bottom surface of the via hole and a second region close to the wall surface and the bottom surface of the via hole, and An average size of grains in the first region of the first metal layer and an average size of grains in the second region are different from each other. An average size of grains in the first region of the first metal layer is greater than an average size of grains in the second region of the first metal layer.

20. The printed circuit board of claim 19, wherein, An average size of grains in the second metal layer is smaller than an average size of grains in the first region of the first metal layer and greater than an average size of grains in the second region of the first metal layer.

21. The printed circuit board of claim 19 or 20, wherein, ​

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