Multi-level trench semiconductor device and manufacturing method thereof

Abstract

The present application discloses a multi-level trench semiconductor device and a manufacturing method thereof, including: an epitaxial wafer, the epitaxial wafer including a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate; a deep trench arranged on the side of the epitaxial layer away from the semiconductor substrate; the deep trench includes a plurality of sub-grooves arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; in two adjacent sub-grooves, the width of the sub-groove close to the bottom of the deep trench is smaller than the width of the sub-groove away from the bottom of the deep trench; the sidewall and bottom of the deep trench have a doping layer; the surface of the epitaxial layer on the side away from the semiconductor substrate has an electric field buffer surrounding the opening of the deep trench, the electric field buffer is in contact with the doping layer; the doping layer and the electric field buffer are both anti-doped with the epitaxial layer. The technical solution of the present application can enhance the manufacturability and reliability of the device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a multi-level trench semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] The main structure of electronic devices to realize various functions is the integrated circuit, and semiconductor devices are important electronic components of integrated circuits. SiC is a wide bandgap semiconductor material that has developed rapidly in the past decade. Compared with other semiconductor materials, such as Si, GaN and GaAs, SiC materials have the advantages of wide bandgap, high thermal conductivity, high carrier saturation mobility, and high power density. SiC can be thermally oxidized to form silicon dioxide, making it possible to realize power devices and circuits such as SiC MOSFET and SBD (Schottky barrier diodes). Since the 1990s, power devices such as SiC MOSFET and SBD have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0004] Due to the characteristics of silicon carbide materials, if doping with a greater implantation depth is to be achieved, high-energy ion implantation will cause damage to its lattice. In order to perform doping regions with a greater depth in silicon carbide materials, it is necessary to form deep trenches in the silicon carbide material and form doping layers on the surface of the deep trenches as doping regions. However, due to the greater depth of the deep trenches, the thickness of the doping layer in the deep trenches is uneven, which affects the performance of the device. Summary of the invention

[0005] In view of this, the present application provides a multi-level trench semiconductor device and a method for manufacturing the same, the scheme is as follows:

[0006] A multi-level trench semiconductor device, comprising:

[0007] An epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on a surface of the semiconductor substrate;

[0008] A deep trench is provided on the side of the epitaxial layer away from the semiconductor substrate; the deep trench comprises a plurality of sub-trenches arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; of two adjacent sub-trenches, the width of the sub-trench close to the bottom of the deep trench is smaller than the width of the sub-trench far from the bottom of the deep trench;

[0009] The sidewalls and bottom of the deep trench have a doping layer;

[0010] The surface of the epitaxial layer on the side facing away from the semiconductor substrate has an electric field buffer zone surrounding the deep trench opening, and the electric field buffer zone is in contact with the doped layer;

[0011] Wherein, the doped layer and the electric field buffer zone are both anti-doped with respect to the epitaxial layer.

[0012] Preferably, in the above-mentioned multi-level trench semiconductor device, the doping layer is an ion implantation layer located in the sidewall surface and the bottom surface of the deep trench.

[0013] Preferably, in the above-mentioned multi-level trench semiconductor device, the electric field buffer zone and the doping layer are located in the same ion implantation layer.

[0014] Preferably, in the above-mentioned multi-level trench semiconductor device, the electric field buffer zone and the doping layer are different ion implantation layers.

[0015] Preferably, in the above-mentioned multi-level trench semiconductor device, the doping layer is an epitaxial covering layer covering the side wall surface and the bottom surface of the deep trench.

[0016] Preferably, in the above-mentioned multi-level trench semiconductor device, the electric field buffer zone and the doped layer are the same epitaxial covering layer.

[0017] Preferably, in the above-mentioned multi-level trench semiconductor device, the epitaxial layer is a silicon carbide epitaxial layer, and the depth of the deep trench is not less than 1 μm.

[0018] Preferably, in the above-mentioned multi-level trench semiconductor device, in a direction parallel to the epitaxial wafer, the width of the electric field buffer zone is 200nm-500nm.

[0019] The present application also provides a method for manufacturing a multi-level trench semiconductor device, comprising:

[0020] Provided is an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on a surface of the semiconductor substrate;

[0021] A deep trench is formed on the side of the epitaxial layer away from the semiconductor substrate; the deep trench includes a plurality of sub-trenches arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; of two adjacent sub-trenches, the width of the sub-trench close to the bottom of the deep trench is smaller than the width of the sub-trench far from the bottom of the deep trench;

[0022] forming a doping layer that is doped inversely to the epitaxial layer; the sidewalls and the bottom of the deep trench have the doping layer;

[0023] The surface of the epitaxial layer on the side facing away from the semiconductor substrate has an electric field buffer zone surrounding the deep trench opening, and the electric field buffer zone is in contact with the doped layer.

[0024] Preferably, in the above manufacturing method, the deep trench has M sub-grooves, and in the first direction, the M sub-grooves are sequentially from the first-order sub-groove to the M-th-order sub-groove, and M is a positive integer greater than 1; before forming the deep trench, the electric field buffer zone is formed by a single ion implantation; after forming the deep trench, the deep trench penetrates the electric field buffer zone, and the electric field buffer zone contacts the sidewall of the first-order sub-groove;

[0025] Forming a doped layer that is counter-doped to the epitaxial layer, comprising:

[0026] By another ion implantation, synchronous ion implantation is performed in the side wall surface of each level of sub-grooves, in the step surface between two adjacent sub-grooves, and in the bottom surface of the M-th level of sub-grooves to form the doping layer;

[0027] Wherein, the electric field buffer zone and the doping layer are different ion implantation layers.

[0028] Preferably, in the above manufacturing method, the deep trench has M sub-grooves, and in the first direction, the M sub-grooves are sequentially from the first-order sub-groove to the M-order sub-groove, and M is a positive integer greater than 1;

[0029] Forming a doping layer that is counter-doped with the epitaxial layer, comprising:

[0030] Through the same ion implantation, ion implantation is performed simultaneously in the surface of the surrounding area of ​​the deep trench opening, in the sidewall surface of each sub-trench, in the step surface between two adjacent sub-trench, and in the bottom surface of the M-th sub-trench, so as to form the electric field buffer zone and the doping layer simultaneously;

[0031] Wherein, the electric field buffer zone and the doping layer are located in the same ion implantation layer.

[0032] Preferably, in the above manufacturing method, the deep trench having M+1 sub-trench is formed in the surface of the epitaxial layer on one side away from the semiconductor substrate, and in the first direction, the M+1 sub-trench is sequentially from the 1st level sub-trench to the M+1th level sub-trench, and M is a positive integer greater than 1;

[0033] Forming a doped layer that is counter-doped to the epitaxial layer, comprising:

[0034] By epitaxial process, an epitaxial covering layer is formed on the surface of the epitaxial layer facing away from the semiconductor substrate, on the sidewall surface of each sub-groove, on the step surface between two adjacent sub-grooves, and on the bottom surface of the M-th sub-groove;

[0035] The surface of the epitaxial layer on one side facing away from the semiconductor substrate is thinned until the epitaxial covering layer on the step surface between the first-level sub-groove and the second-level sub-groove is exposed to serve as the electric field buffer zone.

[0036] From the above description, it can be known that in the multi-level trench semiconductor device and its manufacturing method provided by the technical solution of the present application, the multi-level trench semiconductor device includes: an epitaxial wafer, the epitaxial wafer includes a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate; a deep trench is arranged on the side of the epitaxial layer away from the semiconductor substrate; the deep trench includes a plurality of sub-grooves arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; in two adjacent sub-grooves, the width of the sub-groove close to the bottom of the deep trench is smaller than the width of the sub-groove away from the bottom of the deep trench; the sidewalls and bottom of the deep trench have a doping layer; the surface of the epitaxial layer on the side away from the semiconductor substrate has an electric field buffer surrounding the deep trench opening, and the electric field buffer is in contact with the doping layer; wherein the doping layer and the electric field buffer are both anti-doped with the epitaxial layer.

[0037] Since the depth of the deep groove is large, the thickness of the doped layer in the deep groove will gradually decrease in the first direction, especially near the opening position. Since the thickness of the doped layer is thin, leakage at this position is avoided, as well as leakage or breakdown caused by electric field concentration, which can enhance the manufacturability and reliability of the device. The technical solution of the present application realizes the voltage buffering function through an electric field buffer zone. Through a multi-level groove structure, it can avoid the contradiction between the forward conduction impedance of the device caused by a single-width groove and the withstand voltage of the Schottky region and the reliability of the surface electric field, further enhancing the withstand voltage capability of the SBD device while maintaining a low forward conduction impedance. The electric field buffer zone can enhance the process tolerance of the device, avoid leakage near the opening caused by the Schottky contact process, as well as leakage or breakdown problems caused by electric field concentration, and enhance the manufacturability and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0039] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0040] Figure 1 A schematic structural diagram of a multi-level trench semiconductor device provided in an embodiment of the present application;

[0041] Figure 2 A schematic structural diagram of another multi-level trench semiconductor device provided in an embodiment of the present application;

[0042] Figure 3-Figure 11 A process flow chart of a method for manufacturing a multi-level trench semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0044] Due to the characteristics of silicon carbide materials, the ion implantation depth can only be within 1μm, and the typical depth is 600nm. If higher energy ion implantation is used, although the implantation depth can be increased, higher energy ion implantation, especially Al ion implantation, will cause lattice damage and affect the reliability of the device.

[0045] A deep trench can be formed first, and the required doping layer can be formed in the deep trench to achieve doping at a greater depth. If the depth of the deep trench exceeds 1 μm, the ion implantation distribution will be discontinuous on the sidewall of the deep trench and the thickness will be thinner near the opening of the deep trench, resulting in device breakdown and leakage. Although the deep trench with inclined sidewalls can solve the problems of discontinuous sidewall ion implantation and thin thickness near the opening of the deep trench to a certain extent by setting the width to gradually increase from top to bottom, if the sidewall is tilted to a large extent, the cell area will be increased, affecting the integration. If the sidewall is tilted to a small extent, the improvement effect on the problem is limited, and it is difficult to mass produce.

[0046] The use of a deep trench with a multi-level trench structure can solve the problem of uneven distribution of ion implantation on the sidewall, but it cannot effectively solve the problem of thin ion implantation depth at the opening position.

[0047] In order to solve the above problems, in the technical solution of the embodiment of the present application, a multi-level groove structure is adopted to solve the problem of discontinuity of the sidewall doping layer, and through the electric field buffer zone, the reliability problem caused by the thin thickness of the doping layer at the opening position can be solved.

[0048] At present, the optimization design of breakdown voltage and on-resistance of silicon carbide SBD, especially high-voltage SBD devices, is mutually influential and contradictory. It is generally difficult to obtain low on-resistance when obtaining high breakdown voltage, especially for planar JBS devices. When designing high withstand voltage, it is difficult to achieve P+ injection with a junction depth of more than 1um due to the limitation of process equipment due to the injection depth of the P+ region. In view of this problem, the industry has proposed a structure of trench SBD, which can achieve a deeper P+ structure. However, the SBD structure of a single-width groove needs to compromise between the groove depth and the forward conduction impedance of the device, and also needs to compromise between the groove spacing and the withstand voltage and surface electric field strength of the Schottky region between the grooves, which brings contradictions to the design of high withstand voltage SBD devices. The technical solution of the present application provides a novel multi-level trench structure semiconductor device, constructs a novel trench SBD device, can avoid the contradiction between the forward conduction impedance of the device caused by the single-width trench structure during device design and the withstand voltage and surface electric field reliability of the Schottky region, and further enhances the withstand voltage capability of the SBD device while maintaining a low forward conduction impedance.

[0049] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0050] like Figure 1 As shown, Figure 1 A schematic structural diagram of a multi-level trench semiconductor device provided in an embodiment of the present application includes:

[0051] An epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate 11 and an epitaxial layer 12 located on a surface of the semiconductor substrate 11;

[0052] A deep trench 13 is provided on the side of the epitaxial layer away from the semiconductor substrate; the deep trench 13 includes a plurality of sub-trench 131 arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench 13 points to the bottom (i.e. Figure 1 In the direction from top to bottom in the deep groove), of two adjacent sub-grooves 131, the width of the sub-groove 131 close to the bottom of the deep groove is smaller than the width of the sub-groove 131 away from the bottom of the deep groove, that is, in the first direction, the width of the previous sub-groove 131 is larger than the width of the next sub-groove 131;

[0053] The sidewall and bottom of the deep trench 13 have a doping layer 14;

[0054] The surface of the epitaxial layer 12 facing away from the semiconductor substrate 11 has an electric field buffer zone 15 surrounding the deep trench opening, and the electric field buffer zone 15 is in contact with the doping layer 14;

[0055] The doped layer 14 and the electric field buffer zone 15 are both counter-doped with the epitaxial layer 12 .

[0056] The depth of the sub-groove 131 directly contacting the electric field buffer zone 15 is set to t1. In the first direction, the depths of the sub-grooves of each level are sequentially t1 to tn, where n is a positive integer. The sizes and relative size relationships of t1 to tn can be set based on process requirements, and the present application embodiment does not specifically limit this.

[0057] The deep trench in the multi-level trench semiconductor device described in the embodiment of the present application is a multi-level trench structure, so the distances between the two adjacent deep trenches 13 and the sub-trench opposite to each other are S1, S2, ... Sn, respectively, and the distance between the electric field buffer regions 15 is S0, then:

[0058] S0<S1<S2<…<Sn

[0059] In the multi-level trench semiconductor device described in the embodiment of the present application, the multi-level trench structure can solve the discontinuity problem of the doping layer 14 in the deep trench, and the electric field buffer zone 15 can solve the leakage and breakdown problems caused by the thin thickness of the doping layer 14 at the opening position, thereby enhancing the manufacturability and reliability of the device.

[0060] In a first embodiment, the doping layer 14 may be formed by an ion implantation process. In this case, the doping layer 14 is an ion implantation layer located in the sidewall surface and the bottom surface of the deep trench 13 .

[0061] When the doping layer 14 is formed by an ion implantation process, the doping layer 14 and the electric field buffer zone 15 can be formed simultaneously by the same ion implantation. In this case, the electric field buffer zone 15 and the doping layer 14 are located in the same ion implantation layer. In other embodiments, the doping layer 14 and the electric field buffer zone 15 can be prepared separately by two ion implantation processes. In this case, the electric field buffer zone 15 and the doping layer 14 are different ion implantation layers.

[0062] In the second implementation manner, the doping layer 14 may also be formed by an epitaxial process. In this case, the doping layer 14 is an epitaxial covering layer covering the sidewall surface and the bottom surface of the deep trench 13 .

[0063] When the doping layer 14 is formed by an epitaxial process, the doping layer 14 and the electric field buffer zone 15 may be formed simultaneously by the same epitaxial process. At this time, the electric field buffer zone 15 and the doping layer 14 are the same epitaxial covering layer.

[0064] In the embodiment of the present application, the epitaxial layer 12 is a silicon carbide epitaxial layer, and the depth of the deep trench 13 is not less than 1 μm. Due to the properties of silicon carbide materials, it is impossible to directly form an ion implantation region with a depth of not less than 1 μm by ion implantation. The technical solution of the present application can form a doped layer 14 in a greater depth of the silicon carbide material through a multi-level trench structure.

[0065] Optionally, in a direction parallel to the epitaxial wafer (i.e. Figure 1 In the horizontal direction), the width L of the electric field buffer zone 15 is 200nm-500nm to achieve better anti-leakage and anti-breakdown effects.

[0066] In the embodiment of the present application, the semiconductor substrate 11 and the epitaxial layer 12 are of the same type doped, and the doping concentration of the semiconductor substrate 11 is relatively large. For example, the semiconductor substrate 11 can be set to be N+ type doped (N type heavily doped), and the epitaxial layer 12 can be N- type doped (N type lightly doped). The doped layer 14 and the electric field buffer zone 15 are of the same type doped, and both are anti-doped with the epitaxial layer 12. For example, the doped layer 14 and the electric field buffer zone 15 can be set to be P+ type doped (P type heavily doped).

[0067] like Figure 2 As shown, Figure 2 A schematic diagram of another multi-level trench semiconductor device provided in an embodiment of the present application, based on Figure 1 As shown, Figure 2 The structure shown also includes:

[0068] In the deep trench 13 with the doping layer 14, there is a filling medium 16, and the filling medium 16 includes an insulating medium, polysilicon and a metal with good dense hole filling properties, etc. The metal includes titanium-tungsten alloy, titanium and green light;

[0069] A patterned first electrode 171 is provided on the surface of the epitaxial layer 12 facing away from the semiconductor substrate 11 , and the first electrode 171 has Schottky contact with the electric field buffer 15 and the doped layer 14 and the filling medium 16 in the deep trench 13 ;

[0070] A second Schottky contact electrode 172 is provided on a surface of the semiconductor substrate 11 on a side away from the epitaxial layer 12;

[0071] The epitaxial layer 12 has a cell region and a terminal region 19. The terminal region 19 includes a junction terminal extension (JTE) or a field limiting ring (FLR). The deep trench 13 is located in the cell region, and the surface of the epitaxial layer 12 on one side away from the semiconductor substrate 11 is covered with an insulating dielectric layer 18 in the area outside the first electrode 171, and the insulating dielectric layer 18 includes silicon nitride and silicon dioxide. The epitaxial layer 12 has a cutting region 20 for cutting and separating different devices.

[0072] The embodiment of the present application provides a novel multi-level trench semiconductor device, which realizes the voltage buffering function through the electric field buffer 15. The multi-level trench structure can avoid the contradiction between the device forward conduction impedance caused by a single-width trench and the Schottky region withstand voltage and surface electric field reliability, further enhancing the withstand voltage capability of the SBD device while maintaining a low forward conduction impedance. The electric field buffer 15 can enhance the process tolerance of the device, avoid leakage near the opening of the Schottky contact process, and leakage or breakdown caused by electric field concentration, and enhance the manufacturability and reliability of the device.

[0073] Based on the above embodiments, another embodiment of the present application further provides a method for manufacturing a multi-level trench semiconductor device, such as Figure 3-Figure 5 As shown, the production method includes:

[0074] Step S11: Figure 3 As shown, an epitaxial wafer is provided. The epitaxial wafer includes a semiconductor substrate 11 and an epitaxial layer 12 located on the surface of the semiconductor substrate 11 .

[0075] Step S12: Figure 4 As shown, a deep trench 13 is formed on the side of the epitaxial layer 12 away from the semiconductor substrate 11; the deep trench 13 includes a plurality of sub-trench 131 arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench 13 points to the bottom; of two adjacent sub-trench 131, the width of the sub-trench 131 close to the bottom of the deep trench 13 is smaller than the width of the sub-trench 131 away from the bottom of the deep trench 13;

[0076] The deep trench 13 is fabricated by ICP, RIE or laser hole burning.

[0077] Step S13: Figure 5 As shown, a doping layer 14 is formed which is doped inversely to the epitaxial layer 12; the sidewall and the bottom of the deep trench 13 have the doping layer 14;

[0078] The surface of the epitaxial layer 12 facing away from the semiconductor substrate 11 has an electric field buffer zone 15 surrounding the opening of the deep trench 13 , and the electric field buffer zone 15 is in contact with the doping layer 14 .

[0079] In the manufacturing method described in the embodiment of the present application, the deep trench 13 may be provided with M sub-trench 131. In the first direction, the M sub-trench 131 is sequentially from the first-order sub-trench to the M-order sub-trench, where M is a positive integer greater than 1, and M=n. At this time, the doping layer 14 that is doped inversely with the epitaxial layer 12 is formed, including: Figure 6 As shown, through the same ion implantation, the surface of the surrounding area of ​​the deep trench 13 opening, the sidewall surface of each sub-groove 131, and the step ( Figure 6 Ions are implanted synchronously in the surface of the M-th level sub-groove (in the area indicated by the dotted circle) and in the bottom surface of the M-th level sub-groove to form the electric field buffer zone 15 and the doping layer 14 synchronously; wherein the electric field buffer zone 15 and the doping layer 14 are located in the same ion implantation layer. In this method, the first mask 01 is required to be used for ion implantation, and the first mask 01 has ion implantation windows 011 corresponding to the deep grooves 13 one by one, and the ion implantation windows 011 expose the corresponding deep grooves 13 and the area around their openings corresponding to the electric field buffer zone 15.

[0080] When ion implantation is performed in the deep trench 13, by controlling the ion implantation direction, P+ ion implantation is performed at a certain angle in the side wall, so as to form a doping layer 14 in the side wall surface.

[0081] In another embodiment, before forming the deep trench 13, Figure 7 As shown, the electric field buffer region 15 is formed by one ion implantation. The second mask 02 may be used for ion implantation. The second mask 02 has ion implantation windows 011 corresponding to the deep trenches 13. The ion implantation windows 011 expose the corresponding deep trenches 13 and the area around their openings corresponding to the electric field buffer region 15. The first mask 01 and the second mask 02 are the same mask.

[0082] Then as Figure 8 As shown, a deep trench 13 is formed. After the deep trench 13 is formed, the deep trench 13 penetrates the electric field buffer region 15, and the electric field buffer region 15 contacts the sidewall of the first-level sub-trench.

[0083] based on Figure 7 and Figure 8 , forming a doping layer 14 that is anti-doped with the epitaxial layer 12, comprising:

[0084] like Fig. 9 As shown, by another ion implantation, simultaneous ion implantation is performed in the sidewall surfaces of each sub-groove 131, in the step surface between two adjacent sub-grooves 131, and in the bottom surface of the M-th sub-groove to form the doping layer 14;

[0085] The electric field buffer region 15 and the doping layer 14 are different ion implantation layers. At this time, the doping concentrations of the electric field buffer region 15 and the doping layer 14 may be the same or different.

[0086] exist Fig. 9 In the illustrated manner, a third mask 03 is used for ion implantation. The third mask 03 has ion implantation windows 011 corresponding to the deep trenches 13 one by one. The ion implantation windows 011 expose the corresponding deep trenches 13 and shield other areas.

[0087] In other methods, when forming the deep trench 13, as Fig.10 As shown, the deep trench 13 having M+1 sub-grooves is formed in the surface of the epitaxial layer 12 on one side away from the semiconductor substrate 11. In the first direction, the M+1 sub-grooves are sequentially from the 1st sub-groove to the M+1th sub-groove, and M is a positive integer greater than 1.

[0088] based on Fig.10 In the manner shown, forming a doped layer 14 that is anti-doped with the epitaxial layer 12 includes:

[0089] First, if Fig.11 As shown, an epitaxial covering layer 31 is formed on the surface of the epitaxial layer 12 facing away from the semiconductor substrate 11, on the side wall surfaces of each sub-groove 131, on the step surface between two adjacent sub-grooves 131, and on the bottom surface of the M-th sub-groove through an epitaxial process;

[0090] Then, the surface of the epitaxial layer 12 facing away from the semiconductor substrate 11 is thinned until the epitaxial covering layer 31 on the step surface between the first-level sub-groove and the second-level sub-groove is exposed. The epitaxial covering layer 31 on the step surface serves as the electric field buffer zone 15 .

[0091] The various embodiments in this specification are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0092] It should be noted that in the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0093] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0094] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a multi-level trench semiconductor device, characterized in that: include: Provided is an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on a surface of the semiconductor substrate; A deep trench is formed on the side of the epitaxial layer away from the semiconductor substrate; the deep trench includes a plurality of sub-trenches arranged in sequence in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; of two adjacent sub-trenches, the width of the sub-trench close to the bottom of the deep trench is smaller than the width of the sub-trench far from the bottom of the deep trench; forming a doping layer that is doped inversely to the epitaxial layer; the sidewalls and the bottom of the deep trench have the doping layer; The surface of the epitaxial layer facing away from the semiconductor substrate has an electric field buffer zone surrounding the deep trench opening, the doped layer and the epitaxial layer are anti-doped, and the electric field buffer zone is in contact with the doped layer; The deep trench has M sub-grooves, and in the first direction, the M sub-grooves are sequentially from the first-order sub-groove to the M-order sub-groove, where M is a positive integer greater than 1; Before forming the deep trench, the electric field buffer zone is formed by a single ion implantation; after forming the deep trench, the deep trench penetrates the electric field buffer zone, and the electric field buffer zone contacts the side wall of the first-level sub-trench; forming a doping layer that is inversely doped with the epitaxial layer, including: performing synchronous ion implantation in the side wall surface of each level of sub-trench, the step surface between two adjacent sub-trench, and the bottom surface of the M-th level sub-trench through another ion implantation to form the doping layer; wherein the electric field buffer zone and the doping layer are different ion implantation layers; Or, forming a doped layer that is doped inversely to the epitaxial layer, comprising: by a same ion implantation, ion implantation is performed synchronously in the surface of the surrounding area of ​​the deep trench opening, in the sidewall surface of each level of sub-trench, in the step surface between two adjacent sub-trench, and in the bottom surface of the M-th level of sub-trench, so as to synchronously form the electric field buffer zone and the doped layer; wherein the electric field buffer zone and the doped layer are located in the same ion implantation layer; Or, the deep trench having M+1 sub-grooves is formed in the surface of the epitaxial layer on one side away from the semiconductor substrate, and in the first direction, the M+1 sub-grooves are sequentially from the 1st sub-groove to the M+1th sub-groove, where M is a positive integer greater than 1; a doped layer that is counter-doped to the epitaxial layer is formed, including: forming an epitaxial covering layer on the surface of the epitaxial layer on the side away from the semiconductor substrate, on the sidewall surfaces of each sub-groove, on the step surface between two adjacent sub-grooves, and on the bottom surface of the Mth sub-groove through an epitaxial process; and thinning the surface of the epitaxial layer on the side away from the semiconductor substrate until the epitaxial covering layer on the step surface between the 1st sub-groove and the 2nd sub-groove is exposed to serve as the electric field buffer zone.

2. The method according to claim 1, characterized in that: The epitaxial layer is a silicon carbide epitaxial layer, and the depth of the deep trench is not less than 1 μm.

3. The method according to claim 1, characterized in that: In a direction parallel to the epitaxial wafer, the width of the electric field buffer zone is 200nm-500nm.

Images