Method for manufacturing image display device and image display device

Abstract

A manufacturing method of an image display device and an image display device are provided. The manufacturing method of an embodiment includes a process of preparing a substrate having a semiconductor layer including a light emitting layer on a first substrate, a process of forming a first insulating film on a second substrate on which a circuit including a circuit element and a first wiring layer is formed, a process of forming a plug connected to the circuit element in the first insulating film, a process of joining the semiconductor layer to the second substrate and electrically connecting the plug to the semiconductor layer, a process of processing the semiconductor layer and forming a light emitting element electrically connected to the plug, a process of forming a second insulating film covering the light emitting element and the first insulating film, a process of removing a part of the second insulating film and exposing a part of the light emitting element, and a process of forming a second wiring layer on the second insulating film.

Description

Technical Field

[0001] The embodiments of the present invention relate to a method for manufacturing an image display device and an image display device. Background Technology

[0002] There is a desire to achieve a thin image display device with high brightness, wide viewing angle, high contrast, and low power consumption. To meet these market demands, display devices utilizing self-emissive elements are being developed.

[0003] As self-emissive elements, display devices using finely crafted micro-LEDs are anticipated. A method for manufacturing such devices has been described that sequentially transfers individually formed micro-LEDs onto a driving circuit. However, as the resolution of high-definition displays such as Full HD, 4K, and 8K increases, the transfer process, which involves forming a large number of micro-LEDs individually and sequentially transferring them onto a substrate forming the driving circuit, requires a significant amount of time. Furthermore, issues such as poor connections between the micro-LEDs and the driving circuit may arise, leading to a decrease in yield.

[0004] The following technique is known: growing a semiconductor layer including a light-emitting layer on a Si substrate, forming electrodes on the semiconductor layer, and then attaching it to a circuit board on which a driving circuit is formed (e.g., Patent Document 1).

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2002-141492 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] One embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer process of the light-emitting element and improves the yield, as well as an image display device.

[0010] Technical solutions for solving technical problems

[0011] A method for manufacturing an image display device according to one embodiment of the present invention includes a step of preparing a substrate having a semiconductor layer including a light-emitting layer on a first substrate; a step of forming a first insulating film on a second substrate having a circuit including circuit elements and a first wiring layer; a step of forming a plug connected to the circuit elements within the first insulating film; a step of bonding the semiconductor layer to the second substrate and electrically connecting the plug to the semiconductor layer; a step of processing the semiconductor layer to form a light-emitting element electrically connected to the plug; a step of forming a second insulating film covering the light-emitting element and the first insulating film; a step of removing a portion of the second insulating film to expose a portion of the light-emitting element; and a step of forming a second wiring layer on the second insulating film.

[0012] An image display device according to one embodiment of the present invention includes: a circuit element, a first wiring layer electrically connected to the circuit element, a first insulating film covering the circuit element and the first wiring layer, a plug formed on the first insulating film and connected to the first wiring layer, a first semiconductor layer of a first conductivity type disposed on the plug and connected to the plug, a light-emitting layer disposed on the first semiconductor layer, a light-emitting element disposed on the light-emitting layer and including a second semiconductor layer of a second conductivity type different from the first conductivity type, a second insulating film covering at least a portion of the light-emitting element, the plug and the first insulating film, and a second wiring layer connected to the light-emitting element and disposed on the second insulating film.

[0013] An image display device according to one embodiment of the present invention includes: a circuit element, a first wiring layer electrically connected to the circuit element, a first insulating film covering the circuit element and the first wiring layer, a plug formed on the first insulating film, a first semiconductor layer of a first conductivity type disposed on and connected to the plug, a light-emitting layer disposed on the first semiconductor layer, a light-emitting element disposed on the light-emitting layer and including a second semiconductor layer of a second conductivity type different from the first conductivity type, a second insulating film covering at least a portion of the light-emitting element, the plug and the first insulating film, a second wiring layer disposed on the second insulating film and connected to the light-emitting element, and a third wiring layer disposed on the first insulating film and connected to the circuit element via the first wiring layer. The second insulating film has: a first opening exposing the second semiconductor layer surface of the light-emitting element, and a second opening exposing a portion of the third wiring layer. The second wiring layer includes a transparent electrode located on the second semiconductor layer and connecting the light-emitting surface of the light-emitting element facing the first insulating film side to the third wiring layer.

[0014] An image display device according to one embodiment of the present invention includes: a plurality of transistors, a first wiring layer electrically connected to the plurality of transistors, a first insulating film covering the plurality of transistors and the first wiring layer, a plurality of plugs formed on the first insulating film and connected to the first wiring layer, a first semiconductor layer of a first conductivity type disposed on the plugs, a light-emitting layer disposed on the first semiconductor layer, a second semiconductor layer of a second conductivity type disposed on the light-emitting layer and different from the first conductivity type, a second insulating film covering the first insulating film, the plugs, the first semiconductor layer and the light-emitting layer and covering at least a portion of the second semiconductor layer, and a second wiring layer that is exposed from the second insulating film corresponding to the plurality of transistors and connected to transparent electrodes disposed on a plurality of exposed surfaces of the second semiconductor layer.

[0015] The effects of the invention

[0016] According to one embodiment of the present invention, a method for manufacturing an image display device and an image display device that shortens the transfer process of the light-emitting element and improves the yield can be realized. Attached Figure Description

[0017] Figure 1 This is a schematic cross-sectional view illustrating a portion of the image display device according to the first embodiment.

[0018] Figure 2 This is a schematic cross-sectional view illustrating a portion of a variation of the image display device according to the first embodiment.

[0019] Figure 3A This is a schematic cross-sectional view illustrating a portion of a variation of the image display device according to the first embodiment.

[0020] Figure 3B This is a schematic cross-sectional view illustrating a portion of a variation of the image display device according to the first embodiment.

[0021] Figure 4 This is a schematic block diagram illustrating the image display device of the first embodiment.

[0022] Figure 5A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0023] Figure 5B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0024] Figure 6A This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0025] Figure 6BThis is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0026] Figure 6C This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0027] Figure 7A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0028] Figure 7B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0029] Figure 7C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0030] Figure 8A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0031] Figure 8B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0032] Figure 8C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0033] Figure 9A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0034] Figure 9B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0035] Figure 9C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0036] Figure 10A This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0037] Figure 10B This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0038] Figure 11A This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0039] Figure 11BThis is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0040] Figure 12 This is a schematic perspective view illustrating a method for manufacturing an image display device according to the first embodiment.

[0041] Figure 13 This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the first embodiment.

[0042] Figure 14A This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0043] Figure 14B This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0044] Figure 14C This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0045] Figure 14D This is a schematic cross-sectional view illustrating a manufacturing method of a modified example of the image display device according to the first embodiment.

[0046] Figure 15 This is a schematic cross-sectional view illustrating a portion of the image display device according to the second embodiment.

[0047] Figure 16 This is a schematic block diagram illustrating the image display device of the second embodiment.

[0048] Figure 17A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0049] Figure 17B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0050] Figure 18A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0051] Figure 18B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0052] Figure 18C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the second embodiment.

[0053] Figure 19 This is a schematic cross-sectional view illustrating a portion of the image display device according to the third embodiment.

[0054] Figure 20A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0055] Figure 20B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0056] Figure 21A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0057] Figure 21B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0058] Figure 21C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the third embodiment.

[0059] Figure 22 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fourth embodiment.

[0060] Figure 23 This is a schematic cross-sectional view of a portion of an image display device illustrating a variation of the fourth embodiment.

[0061] Figure 24A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fourth embodiment.

[0062] Figure 24B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fourth embodiment.

[0063] Figure 25A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fourth embodiment.

[0064] Figure 25B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fourth embodiment.

[0065] Figure 26 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fifth embodiment.

[0066] Figure 27A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0067] Figure 27B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0068] Figure 28AThis is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0069] Figure 28B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to the fifth embodiment.

[0070] Figure 29 This is a schematic cross-sectional view of a portion of an image display device illustrating a variation of the fifth embodiment.

[0071] Figure 30A This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment.

[0072] Figure 30B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment.

[0073] Figure 31 This is a graph illustrating the characteristics of a pixel LED element.

[0074] Figure 32 This is a block diagram illustrating the image display device according to the sixth embodiment.

[0075] Figure 33 This is a block diagram illustrating a modified example of the sixth embodiment of an image display device.

[0076] Figure 34 This is a perspective view schematically illustrating the image display device of the first to fifth embodiments and the above-described modifications. Detailed Implementation

[0077] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0078] It should be noted that the accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., may not be the same as the actual situation. In addition, even when showing the same parts, the dimensions and ratios between them may sometimes be expressed differently due to the accompanying drawings.

[0079] It should be noted that in this application specification and various figures, the same reference numerals are used for the main components that are the same as the components described in the figures, and detailed descriptions are appropriately omitted.

[0080] (First Implementation)

[0081] Figure 1 This is a schematic cross-sectional view of a portion of an image display device illustrating an embodiment.

[0082] Figure 1The structure of the sub-pixels 20 of the image display device according to this embodiment is schematically shown. The pixels 10 constituting the image displayed on the image display device are composed of a plurality of sub-pixels 20.

[0083] The following explanation sometimes uses a three-dimensional coordinate system of XYZ. Subpixels 20 are arranged on a two-dimensional plane. This two-dimensional plane with the subpixels 20 arranged is the XY plane. The subpixels 20 are arranged along the X-axis and the Y-axis.

[0084] Sub-pixel 20 has a light-emitting surface 153S that is approximately parallel to the XY plane. The light-emitting surface 153S mainly outputs light in the positive direction of the Z-axis, which is orthogonal to the XY plane.

[0085] Figure 1 The diagram schematically illustrates a cross-section when the sub-pixel 20 is cut with a face parallel to the XZ plane.

[0086] like Figure 1 As shown, the sub-pixel 20 of the image display device includes: a transistor 103, a first wiring layer 110, a first interlayer insulating film 112, a connector 116k, a light-emitting element 150, a second interlayer insulating film 156, and a second wiring layer 160. The sub-pixel 20 also includes a color filter 180. The color filter (wavelength conversion component) 180 is disposed on a surface resin layer 170 via a transparent thin film adhesive layer 188. The surface resin layer 170 is disposed on the light-emitting element 150, the interlayer insulating film 156, and the wiring layer 160.

[0087] Transistor 103 is formed on substrate 102. On substrate 102, in addition to transistor 103 for driving light-emitting element 150, other transistors, resistors, capacitors, and other circuit elements are formed, and circuit 101 is constructed by wiring, etc. For example, transistor 103 corresponds to the transistor described later. Figure 4 In addition to the driving transistor 26 shown, the selection transistor 24 and capacitor 28 are also circuit elements. Hereinafter, let's assume that circuit 101 includes: a component forming region 104 where circuit elements are formed, an insulating layer 105, a wiring layer 110, vias connecting the wiring layer 110 and the circuit elements, and an insulating film 108 that provides insulation between circuit elements. Sometimes, it is referred to as circuit board 100, which includes other major structural components such as substrate 102, circuit 101, and interlayer insulating film 112.

[0088] Transistor 103 includes a p-type semiconductor region 104b, n-type semiconductor regions 104s and 104d, and a gate 107. The gate 107 is disposed over the p-type semiconductor region 104b via an insulating layer 105. The insulating layer 105 insulates the device forming region 104 from the gate 107 and is provided to adequately insulate it from other adjacent circuit elements. When a voltage is applied to the gate 107, a channel can be formed in the p-type semiconductor region 104b. Transistor 103 is an n-channel transistor, such as an n-channel MOSFET.

[0089] A device forming region 104 is disposed on a substrate 102. The substrate 102 is, for example, a Si substrate. The device forming region 104 includes a p-type semiconductor region 104b and n-type semiconductor regions 104s and 104d. The p-type semiconductor region 104b is disposed near the surface of the substrate 102. The n-type semiconductor regions 104s and 104d are disposed within the p-type semiconductor region 104b, spaced apart from each other, near the surface of the p-type semiconductor region 104b.

[0090] An insulating layer 105 is provided on the surface of the substrate 102. The insulating layer 105 covers the element forming region 104, and also covers the surfaces of the p-type semiconductor region 104b and the n-type semiconductor regions 104s and 104d. The insulating layer 105 is, for example, SiO2. Depending on the region it covers, the insulating layer 105 may also be a multilayer insulating layer containing SiO2 or Si3N4, etc. The insulating layer 105 may also include a layer of insulating material with a high dielectric constant.

[0091] Gate 107 is disposed on p-type semiconductor region 104b via insulating layer 105. Gate 107 is disposed between n-type semiconductor regions 104s and 104d. Gate 107 is, for example, polycrystalline Si. Gate 107 may also contain silicide or the like, which have lower resistance than polycrystalline Si.

[0092] In this example, the gate 107 and the insulating layer 105 are covered by an insulating film 108. The insulating film 108 is, for example, SiO2 or Si3N4. In order to make the surface flat for forming the wiring layer 110, an organic insulating film such as PSG (Phosphorus Silicon Glass) or BPSG (Boron Phosphorus Silicon Glass) may also be provided.

[0093] Through-holes 111s and 111d are formed in the insulating film 108. A first wiring layer 110 is formed on the insulating film 108. The first wiring layer 110 includes multiple wirings with different potentials, including wirings 110s and 110d. It should be noted that, in this way, Figure 1In subsequent cross-sectional views, the wiring layer will be marked next to one of the wirings included in the wiring layer. Vias 111s and 111d are respectively disposed between the wirings 110s and 110d in the wiring layer 110 and the n-type semiconductor regions 104s and 104d, and electrically connect them. The wiring layer 110 and the vias 111s and 111d are formed, for example, of metals such as Al and Cu. The wiring layer 110 and the vias 111s and 111d may also contain high-melting-point metals, etc.

[0094] A first interlayer insulating film 112 is further provided on the insulating film 108 and the wiring layer 110. The interlayer insulating film (first insulating film) 112 is, for example, an organic insulating film such as PSG or BPSG. The first interlayer insulating film 112 is also used in the circuit board 100 as a protective film to protect its surface, or as a planarization film for the plug 116k formed on the interlayer insulating film 112.

[0095] A planarization film 114 is further formed on the first interlayer insulating film 112. The planarization film 114 is an insulating film or layer, and like the interlayer insulating film 112, it is, for example, an organic insulating film such as PSG or BPSG or an inorganic insulating film such as SOG (Spin On Glass).

[0096] The plug 116k is embedded in the planarization film 114. The plug 116k and the planarization film 114 each have a surface on the same plane that is approximately parallel to the XY plane.

[0097] A connecting portion 115k is provided between the plug 116k and the wiring 110d. The connecting portion 115k is formed of a conductive component and electrically connects the plug 116k and the wiring 110d. The plug 116k and the connecting portion 115k are, for example, formed of the same material as the first wiring layer 110. The plug 116k and the connecting portion 115k may also contain a high-melting-point metal.

[0098] Figure 2 This is a schematic cross-sectional view illustrating a portion of a variation of the image display device of this embodiment.

[0099] like Figure 2 As shown, in the sub-pixel 20a of this modified example, the plug 116k is connected to the wiring 110d without passing through the connecting part 115k.

[0100] like Figure 1In the case where a connecting portion 115k is provided, the outer periphery of the plug 116k can be formed to protrude further outward than the outer periphery of the wiring 110d in an XY top view. In this modified example, if the plug 116k is closer to the inner side than the outer periphery of the wiring 110d in an XY top view, the connecting portion 115k may not be provided, and the plug 116k may be directly placed on the wiring 110d. That is, the connecting portion can be provided according to the positional relationship between the plug and the wiring to be connected, or according to the shape of the plug and the wiring to be connected, or the connection can be made without a connecting portion. This is the same for the embodiments and modifications described later, but below, unless otherwise specified, the structure with a connecting portion will be described.

[0101] return Figure 1 Let's continue with the explanation.

[0102] The light-emitting element 150 is disposed on the plug 116k via a light-shielding plate 130a. The light-shielding plate 130a will be described later. The light-emitting element 150 includes an n-type semiconductor layer (first semiconductor layer) 151, a light-emitting layer 152, and a p-type semiconductor layer (second semiconductor layer) 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are sequentially laminated from the interlayer insulating film 112 in the positive Z-axis direction. That is, each layer of the light-emitting element 150 is laminated from the interlayer insulating film 112 to the light-emitting surface 153S. The n-type semiconductor layer 151 is electrically connected to the plug 116k.

[0103] The light-emitting element 150 has, for example, a roughly square or rectangular shape in the XY top view, but the corners may also be rounded. The light-emitting element 150 may also have, for example, an elliptical or circular shape in the XY top view. By appropriately selecting the shape and arrangement of the light-emitting element in the top view, the degree of design freedom is increased.

[0104] Light-emitting element 150, for example, is suitable for use with In X Al Y Ga 1-X-Y Nitride semiconductors such as N (0≦X, 0≦Y, X+Y<1). In one embodiment of the present invention, the light-emitting element 150 is a so-called blue light-emitting diode, and the wavelength of the light emitted by the light-emitting element 150 is, for example, about 467nm±20nm. The wavelength of the light emitted by the light-emitting element 150 can also be about 410nm±20nm, a blue-violet light. The wavelength of the light emitted by the light-emitting element 150 is not limited to the above values ​​and can be any appropriate value.

[0105] In this embodiment, the light-shielding plate 130a, the plug 116k, and the connecting portion 115k can be disposed between the light-emitting element 150 and the wiring 110d for the main electrode of the transistor 103. Therefore, the light-emitting element 150 and the transistor 103 can be easily connected without forming deep through holes in the interlayer insulating film 112, etc.

[0106] The second interlayer insulating film (second insulating film) 156 covers the first interlayer insulating film 112, the third wiring layer 130, the sides of the light-emitting element 150, and the buffer layer 140. The second interlayer insulating film 156 is preferably formed of white resin. White resin can be achieved, for example, by distributing finely dispersed particles such as titanium dioxide of appropriate particle size in an organic material. By making the interlayer insulating film 156 a white resin, light emitted laterally and downward from the light-emitting element 150 can be reflected, effectively increasing the brightness of the light-emitting element 150.

[0107] The second interlayer insulating film 156 can also be made of black resin. By making the interlayer insulating film 156 of black resin, the scattering of light within the sub-pixel can be suppressed, and stray light (glare) can be suppressed more effectively. Image display devices with suppressed stray light can display clearer images.

[0108] The interlayer insulating film 156 also has the function of protecting the light-emitting element 150 and planarizing the surface for the wiring layer 160 formed on the second interlayer insulating film 156.

[0109] The second interlayer insulating film 156 has an opening 158. The opening 158 is formed by removing a portion of the interlayer insulating film 156 above the light-emitting element 150. The opening 158 is formed to expose the light-emitting surface 153S from the interlayer insulating film 156. The light-emitting surface 153S is the surface of the p-type semiconductor layer 153 facing the surface adjacent to the light-emitting layer 152. The light-emitting surface 153S is preferably roughened. By roughening the surface of the light-emitting element 150, the light extraction efficiency can be improved.

[0110] A second wiring layer 160 is disposed on the interlayer insulating film 156. The wiring layer 160 includes wiring 160a. Although not shown in the figure, wiring 160a is connected to a power line that supplies power to the sub-pixel 20.

[0111] In this example, a third wiring layer 130 is provided on the planarization film 114 and the connector 116k. The third wiring layer 130 includes a light-shielding plate 130a. The light-shielding plate 130a is disposed between the n-type semiconductor layer 151 and the connector 116k. The light-shielding plate 130a is ohmically connected to the connector 116k.

[0112] A light-shielding plate 130a is provided for each sub-pixel, and the above-mentioned multiple light-shielding plates 130a are electrically insulated. A light-emitting element 150 is provided on each of the light-shielding plates 130a.

[0113] The wiring layer 130, i.e., the light-shielding plate 130a, is formed of a material with high conductivity. The light-shielding plate 130a may contain, for example, Ti, Al, or an alloy of Ti and Sn. It may also contain Cu, V, or noble metals with high light reflectivity such as Ag and Pt. Because the light-shielding plate 130a is formed of the aforementioned metal material with high conductivity, the light-emitting element 150 is electrically connected to the circuit 101 with low resistance.

[0114] The outer periphery of the light-shielding plate 130a includes the outer periphery when the light-emitting element 150 is projected from above the Z-axis in an XY top view. Therefore, the light-shielding plate 130a can reflect the downward scattered light from the light-emitting element 150 towards the light-emitting surface 153S, preventing it from reaching the transistor 103. By appropriately selecting the material of the light-shielding plate 130a, the downward scattered light from the light-emitting element 150 can be reflected towards the light-emitting surface 153S, thereby improving luminous efficiency. Furthermore, by blocking the downward scattered light from the light-emitting element 150 with the light-shielding plate 130a, light reaching the transistor 103 can be suppressed, preventing malfunction of the transistor 103.

[0115] In this embodiment, the cathode electrode of the light-emitting element 150, i.e., the n-type semiconductor layer 151, is connected to the drain electrode of the driving transistor 103 via the light-shielding plate 130a, the plug 116k, and the connection portion 115k.

[0116] A transparent electrode 159a is disposed on the wiring 160a. The transparent electrode 159a is disposed across the light-emitting surface 153S of the open p-type semiconductor layer 153. The transparent electrode 159a is disposed between the wiring 160a and the light-emitting surface 153S, electrically connecting the wiring 160a and the p-type semiconductor layer 153.

[0117] The surface resin layer 170 covers the second interlayer insulating film 156, the transparent conductive film including the transparent electrode 159a, and the second wiring layer 160. The surface resin layer 170 is a transparent resin that protects the interlayer insulating film 156, the transparent electrode 159a, and the wiring layer 160, and provides a planarized surface for bonding the color filter 180.

[0118] The color filter 180 includes a light-blocking portion 181 and a color conversion portion 182. The color conversion portion 182 is positioned directly above the light-emitting surface 153S of the light-emitting element 150, according to the shape of the light-emitting surface 153S. In the color filter 180, the portion other than the color conversion portion 182 constitutes the light-blocking portion 181. The light-blocking portion 181 is a so-called black matrix, which reduces blurring caused by color mixing of light emitted from the adjacent color conversion portion 182, thereby enabling the display of a clear image.

[0119] The color conversion unit 182 may be one or two layers, for example. Figure 1This indicates a two-layer section. Whether the color conversion unit 182 has one or two layers is determined by the color, i.e., the wavelength, of the light emitted by the sub-pixel 20. When the emitted color of the sub-pixel 20 is red or green, the color conversion unit 182 is preferably two-layered. When the emitted color of the sub-pixel 20 is blue, it is preferably one-layered.

[0120] In the case where the color conversion section 182 has two layers, the first layer, which is closer to the light-emitting element 150, is the color conversion layer 183, and the second layer is the filter layer 184. That is, the filter layer 184 is laminated on the color conversion layer 183.

[0121] The color conversion layer 183 is a layer that converts the wavelength of light emitted by the light-emitting element 150 to a desired wavelength. In the case of a sub-pixel 20 emitting red light, the wavelength of light emitted by the light-emitting element 150, 467nm ± 20nm, is converted, for example, to light with a wavelength of approximately 630nm ± 20nm. In the case of a sub-pixel 20 emitting green light, the wavelength of light emitted by the light-emitting element 150, 467nm ± 20nm, is converted, for example, to light with a wavelength of approximately 532nm ± 20nm.

[0122] The filter layer 184 blocks the wavelength component of blue light that remains after the color conversion layer 183 has not been converted.

[0123] When the light emitted by sub-pixel 20 is blue, sub-pixel 20 can output light via color conversion layer 183 or directly without color conversion layer 183. When the wavelength of the light emitted by light-emitting element 150 is approximately 467nm ± 20nm, sub-pixel 20 can also output light without color conversion layer 183. When the wavelength of the light emitted by light-emitting element 150 is 410nm ± 20nm, a color conversion layer 183 is preferably provided to convert the wavelength of the output light to approximately 467nm ± 20nm.

[0124] Even in the case of the blue sub-pixel 20, the sub-pixel 20 can have a filter layer 184. By providing the filter layer 184 in the blue sub-pixel 20, it is possible to suppress the minute external light reflections generated on the surface of the light-emitting element 150.

[0125] (Modified Example)

[0126] A variation of the sub-pixel structure will be explained.

[0127] Figure 3A and Figure 3B These are schematic cross-sectional views illustrating a portion of variations of the image display device according to this embodiment.

[0128] exist Figure 3AIn subsequent cross-sectional views of subpixels, to avoid complexity, the surface resin layer 170 and the color filter 180 are not shown. Unless otherwise specified, the surface resin layer 170 and the color filter 180 are provided on the second interlayer insulating film and the second wiring layer. The same applies to other embodiments and variations thereof described later.

[0129] exist Figure 3A In this case, the difference between sub-pixel 20b and the case of the first embodiment described above lies in the wiring structure connected to the light-emitting element 150. The other major structural components are the same as in the case of the first embodiment described above; for the same major structural components, the same reference numerals are used, and detailed descriptions are omitted where appropriate.

[0130] like Figure 3A As shown, sub-pixel 20b includes wiring 160a1. Wiring 160a1 is formed as wiring contained in the second wiring layer 160. In this modified example, electrical connection to the p-type semiconductor layer 153 is achieved by connecting one end of wiring 160a1 to a portion of the light-emitting surface 153S. In this modified example, the process of forming a transparent conductive film including a transparent electrode can be omitted.

[0131] like Figure 3B As shown, in sub-pixel 20c, the second interlayer insulating film 156a is made of transparent resin. The interlayer insulating film 156a does not have an opening corresponding to the light-emitting surface 153S. The light-emitting surface 153S is directly connected to the wiring 160a2 of the second wiring layer 160.

[0132] The light-emitting element 150 emits light from the light-emitting surface 153S via the interlayer insulating film 156a. In this modified example, the processes of forming an opening in the interlayer insulating film 156a and roughening the light-emitting surface 153S can be omitted.

[0133] In this embodiment, any structure of the sub-pixels 20, 20a to 20c shown above can be included. Furthermore, variations of the sub-pixels can be applied in the same manner as in this embodiment for each of the embodiments described below.

[0134] Figure 4 This is a schematic block diagram illustrating the image display device of this embodiment.

[0135] like Figure 4 As shown, the image display device 1 of this embodiment has a display area 2. Subpixels 20 are arranged in the display area 2. The subpixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X-axis and m subpixels are arranged along the Y-axis.

[0136] Pixel 10 includes multiple subpixels 20 that emit light of different colors. Subpixel 20R emits red light. Subpixel 20G emits green light. Subpixel 20B emits blue light. The emission color and brightness of a pixel 10 are determined by the emission of three subpixels 20R, 20G, and 20B at the desired brightness.

[0137] A pixel 10 comprises three subpixels 20R, 20G, and 20B, which are arranged in a straight line along the X-axis, as shown in this example. Each pixel 10 can arrange subpixels of the same color in the same column, or, as shown in this example, arrange subpixels of different colors in each column.

[0138] The image display device 1 also includes a power line 3 and a ground line 4. The power line 3 and ground line 4 are arranged in a grid pattern along the sub-pixels 20. The power line 3 and ground line 4 are electrically connected to each sub-pixel 20, supplying power to each sub-pixel 20 from a DC power supply connected between a power terminal 3a and a GND terminal 4a. The power terminal 3a and GND terminal 4a are respectively located at the ends of the power line 3 and ground line 4, and are connected to a DC power supply circuit located outside the display area 2. The power terminal 3a supplies a positive voltage with reference to the GND terminal 4a.

[0139] The image display device 1 also includes scan lines 6 and signal lines 8. The scan lines 6 are routed in a direction parallel to the X-axis. That is, the scan lines 6 are routed along the row direction of the sub-pixels 20. The signal lines 8 are routed in a direction parallel to the Y-axis. That is, the signal lines 8 are routed along the column direction of the sub-pixels 20.

[0140] The image display device 1 also includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are disposed along the outer edge of the display area 2. The row selection circuit 5 is disposed along the Y-axis of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via scan lines 6 and supplies selection signals to each sub-pixel 20.

[0141] The signal voltage output circuit 7 is positioned along the outer edge of the display area 2. The signal voltage output circuit 7 is positioned along the X-axis of the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 of each row via signal lines 8, supplying signal voltage to each sub-pixel 20.

[0142] Sub-pixel 20 includes: a light-emitting element 22, a selection transistor 24, a driving transistor 26, and a capacitor 28. Figure 4 In this context, the selection transistor 24 is sometimes referred to as T1, the driving transistor 26 as T2, and the capacitor 28 as Cm.

[0143] The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is an n-channel MOSFET, and the n-electrode (cathode) of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to... Figure 1 Transistor 103, light-emitting element 22 corresponding to Figure 1 The light-emitting element 150, etc. The current flowing to the light-emitting element 22 is determined based on the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a brightness corresponding to the current flowing in the light-emitting element 22.

[0144] The select transistor 24 is connected via the main electrode between the gate electrode of the drive transistor 26 and the signal line 8. The gate electrode of the select transistor 24 is connected to the scan line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and the ground line 4.

[0145] The row selection circuit 5 selects a row from the arrangement of m rows of sub-pixels 20 and supplies a selection signal to the scan line 6. The signal voltage output circuit 7 supplies a signal voltage with the required analog voltage value to each sub-pixel 20 of the selected row. The signal voltage is applied between the gate and source of the driving transistor 26 of the selected row's sub-pixel 20. The signal voltage is held by the capacitor 28. The driving transistor 26 flows a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light with a brightness corresponding to the flowing current.

[0146] The row selection circuit 5 sequentially switches the selected rows, supplying selection signals. That is, the row selection circuit 5 scans the rows arranged by the sub-pixels 20. Current corresponding to the signal voltage flows to the light-emitting elements 22 of the sequentially scanned sub-pixels 20, causing them to emit light. Each pixel 10 emits light with a color and brightness determined by the light emission color and brightness emitted by the RGB sub-pixels 20, displaying an image in the display area 2.

[0147] The manufacturing method of the image display device 1 according to this embodiment will be described.

[0148] Figures 5A to 11B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0149] like Figure 5A As shown, a semiconductor growth substrate 1194 is prepared. The semiconductor growth substrate 1194 has a semiconductor layer 1150 grown on a crystal growth substrate (first substrate) 1001. The crystal growth substrate 1001 is, for example, a Si substrate or a sapphire substrate. A Si substrate is preferred.

[0150] In this example, a buffer layer 1140 is formed on one side of the crystal growth substrate 1001. The buffer layer 1140 is suitable for using nitrides such as AlN.

[0151] In the semiconductor growth substrate 1194, a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151 are sequentially laminated onto the buffer layer 1140 from the buffer layer 1140 side. The growth of the semiconductor layer 1150 is suitable, for example, using a metal-organic chemical vapor deposition (MOCVD) method. The semiconductor layer 1150 is, for example, In... X Al Y Ga 1-X-Y N(0≦X, 0≦Y, X+Y<1), etc.

[0152] A metal layer 1130 is formed on the side of the semiconductor layer 1150 opposite to the side facing the crystal growth substrate 1001. In other words, the metal layer 1130 is formed on the side of the n-type semiconductor layer 1151 opposite to the side where the light-emitting layer 152 is located. That is, the metal layer 1130 is formed on an open surface of the n-type semiconductor layer 1151. The metal layer is formed, for example, by sputtering. The metal layer 1130 may contain, for example, an alloy of Ti, Al, Ti, and Sn. It may also contain noble metals with high light reflectivity, such as Cu, V, Ag, and Pt.

[0153] like Figure 5B As shown, a circuit board 1100 is prepared. The circuit board (second board) 1100 includes... Figure 1 The circuit 101 described in the figure. The semiconductor growth substrate 1194 can be reversed. That is, as shown by the arrow in the figure, one side of the circuit substrate 1100 is aligned with the side of the metal layer 1130 formed on the semiconductor layer 1150, so that the two sides are bonded together. The bonding surface of the circuit substrate 1100 is the exposed surface of the planarization film 114 and the exposed surface of the plug 116k exposed on the same plane as the planarization film 114.

[0154] In wafer bonding that brings two substrates together, for example, the two substrates are heated and then bonded together by hot pressing. Low-melting-point metals or low-melting-point alloys can also be used during hot pressing. Examples of low-melting-point metals include Sn and In, while examples of low-melting-point alloys include alloys with Zn, In, Ga, Sn, and Bi as the main components.

[0155] In wafer bonding, in addition to the above description, the bonding surfaces of each substrate can be flattened by chemical mechanical polishing (CMP) and then cleaned by plasma treatment in a vacuum to ensure close contact.

[0156] Figures 6A to 6C This illustrates a variation of the wafer bonding process. In the wafer bonding process, it can also replace... Figure 5B The process is as follows: Figures 6A to 6C Any one of them.

[0157] like Figure 6A As shown, the semiconductor layer 1150 is grown and laminated on the crystal growth substrate 1001 from one side of the crystal growth substrate 1001 in the order of n-type semiconductor layer 1151, light-emitting layer 1152, and p-type semiconductor layer 1153. A support substrate 1190 is bonded to the open surface of the p-type semiconductor layer 1153. The support substrate 1190 is formed, for example, of Si or quartz. Afterwards, the crystal growth substrate 1001 is removed. The removal of the crystal growth substrate 1001 can be achieved, for example, by wet etching or laser stripping.

[0158] After removing the crystal growth substrate 1001 and the buffer layer 1140, a metal layer 1130 is formed on the surface of the open n-type semiconductor layer 1151.

[0159] like Figure 6B As shown, a metal layer 1120 can also be formed on the circuit board 1100. In this variation, because the metal layers are bonded to each other, wafer bonding can be performed more easily by using the same metal material or an alloy containing the same metal material in each metal layer. It should be noted that the metal layers can be formed on at least one side of the semiconductor growth substrate 1194 and the circuit board 1100.

[0160] like Figure 6C As shown, when the semiconductor layer 1150 is crystal grown on the crystal growth substrate 1001, the semiconductor growth substrate can be formed without a buffer layer. In this case, the process of removing the buffer layer after wafer bonding can be omitted.

[0161] Let's return to the manufacturing process after wafer bonding and continue the explanation.

[0162] like Figure 7A As shown, the crystal growth substrate 1001 is removed. The removal of the crystal growth substrate 1001 can be achieved, for example, by laser stripping or wet etching. The circuit board 1100 is bonded to the semiconductor layer 1150 via the metal layer 1130 through wafer bonding.

[0163] like Figure 7BAs shown, the metal layer 1130 and semiconductor layer 1150 are etched to form a desired shape. The metal layer 1130 is etched to form a wiring layer 130. This wiring layer 130 includes a light-shielding plate 130a. The light-shielding plate 130a is etched to form the shape described above. The semiconductor layer 1150 is further etched to form the shape of a light-emitting element 150. The light-emitting element 150 can be formed, for example, using a dry etching process, and is suitable for using anisotropic plasma etching (RIE).

[0164] like Figure 7C As shown, an interlayer insulating film 156 is formed by covering a planarization film 114, a wiring layer 130, and a light-emitting element 150. An opening 158 is formed in the interlayer insulating film at a position corresponding to the light-emitting element 150 by etching, exposing the surface of the p-type semiconductor layer 153. The etching can be wet etching or dry etching.

[0165] Subsequently, in order to improve the luminous efficiency, the light-emitting surface 153S of the exposed p-type semiconductor layer 153 is roughened.

[0166] A second wiring layer 160, including an opening 158, is formed as a film, and wirings 160a, etc., are formed by photolithography. The wirings 160a are not connected to the p-type semiconductor layer 153.

[0167] A transparent conductive film is formed covering the light-emitting surface 153S of the wiring layer 160, the second interlayer insulating film 156, and the p-type semiconductor layer 153. The transparent conductive film can be an ITO film or a ZnO film, etc. The desired transparent electrode 159a is formed by photolithography.

[0168] A transparent electrode 159a is formed on the wiring 160a and also on the light-emitting surface 153S of the p-type semiconductor layer 153. Therefore, the wiring 160a and the p-type semiconductor layer 153 are electrically connected. Preferably, the transparent electrode 159a is provided to cover the entire exposed light-emitting surface 153S, and the transparent electrode 159a is connected to the light-emitting surface 153S.

[0169] The following describes the process of forming the plug 116k.

[0170] Figures 8A to 9C This is a cross-sectional view illustrating the process of forming the plug 116k on the circuit board 1100.

[0171] like Figure 8A As shown, a circuit board 1100 is prepared, and an insulating film 108 and an interlayer insulating film 1112 covering the first wiring layer 110 are formed in the circuit board 1100.

[0172] like Figure 8B As shown, a contact hole h1 is formed in the interlayer insulating film 1112a. The contact hole h1 is formed at the location where the wiring 110d is provided, and the contact hole h1 is formed to a depth reaching the wiring 110d.

[0173] like Figure 8C As shown, a metal layer 1116 is formed on the entire surface of the first interlayer insulating film 112. While the metal layer 1116 is being formed, the contact hole h1 is filled with the same conductive material as the metal layer 1116 to form a connection portion 115k.

[0174] It should be noted that, without the connection portion 115k formed, in Figure 8A In the circuit board 1100, the interlayer insulating film 1112 forms a large contact hole corresponding to the outer periphery shape of the plug 116k. Then, the contact hole is filled and a metal layer 1116 is formed. Alternatively, the metal layer 1116 can be formed after grinding and polishing until the wiring 110d is exposed, without forming a contact hole.

[0175] like Figure 9A As shown, the plug 116k and the connector 115k are formed by photolithography and dry etching.

[0176] like Figure 9B As shown, in order to cover the interlayer insulating film 112 and the plug 116k, a planarization film 1114 is coated and then fired.

[0177] like Figure 9C As shown, the surface of the planarization film 1114 is polished to expose the surface of the plug 116k. Polishing of the planarization film 1114 can be performed, for example, using CMP. This forms the plug 116k and the connector 115k.

[0178] Next, the manufacturing method of the modified sub-pixels 20b and 20c will be described.

[0179] Figure 10A and Figure 10B This indicates the manufacturing process corresponding to sub-pixel 20b in the modified example. Figure 11A and Figure 11B This indicates the manufacturing process corresponding to sub-pixel 20c in the modified example. Figures 10A to 11B They represent in Figure 7B The process that follows the first process is to form sub-pixels 20b and 20c.

[0180] like Figure 10A As shown, in the modified example of sub-pixel 20b, after an interlayer insulating film 156 is formed covering the planarization film 114, the wiring layer 130 and the light-emitting element 150, an opening 158 is formed to expose the light-emitting surface 153S of the p-type semiconductor layer 153.

[0181] like Figure 10B As shown, wiring 160a1 forms wiring layer 160. Wiring 160a1 replaces the electrical connection made by transparent electrode and is connected to the light-emitting surface 153S of p-type semiconductor layer 153.

[0182] like Figure 11A As shown, in the modified example of sub-pixel 20c, a second interlayer insulating film 156a is formed by covering the planarization film 114, the wiring layer 130 and the light-emitting element 150.

[0183] like Figure 11B As shown, after forming contact holes in the interlayer insulating film 156a, a second wiring layer 160 is formed. The wiring 160a2 of the second wiring layer 160 is connected to the light-emitting surface 153S of the p-type semiconductor layer 153 via the contact holes.

[0184] In this way, sub-pixel 20 and the modified sub-pixels 20b and 20c are formed.

[0185] A portion of the circuitry other than sub-pixel 20 is formed in the circuit board 100. For example, the row selection circuit 5 ( Figure 4 The line selection circuit 5 can be formed on the circuit board 100 together with the driving transistor and the selection transistor. That is, sometimes the line selection circuit 5 is assembled simultaneously with the manufacturing process described above. On the other hand, the signal voltage output circuit 7 is expected to be assembled in a semiconductor device manufactured using a manufacturing process that allows for high integration through fine processing. The signal voltage output circuit 7 is mounted on other substrates along with the CPU and other major circuit components, for example, before or after the color filter described later is assembled, and is interconnected with the wiring of the circuit board 100.

[0186] Preferably, the circuit board 1100 is a chip including the circuit 101. The circuit 101 for one or more image display devices is formed on the circuit board 1100. Alternatively, in the case of a larger screen size, the circuit 101 for constituting an image display device may be divided into multiple circuit boards 1100, and all the divided circuits may be combined to constitute an image display device.

[0187] In addition, the preferred crystal growth substrate 1001 is a wafer of the same size as the wafer-shaped circuit board 1100.

[0188] Figure 12 This is a perspective view illustrating a method for manufacturing an image display device according to this embodiment.

[0189] like Figure 12 As shown, multiple semiconductor growth substrates 1194 can also be prepared so that the semiconductor layer 1150 formed on multiple crystal growth substrates 1001 is bonded to a circuit substrate 1100.

[0190] A plurality of circuits 101 are arranged in a grid pattern on the circuit board 1100, for example. The circuits 101 include all the sub-pixels 20 and the like required for an image display device 1. A spacing of about the width of a scribe line is provided between adjacent circuits 101. No circuit elements are arranged at or near the ends of the circuits 101.

[0191] The semiconductor layer 1150 is formed so that its ends coincide with the ends of the crystal growth substrate 1001. Therefore, by aligning and bonding the ends of the semiconductor growth substrate 1194 with the ends of the circuit 101, the ends of the bonded semiconductor layer 1150 can be aligned with the ends of the circuit 101.

[0192] When the semiconductor layer 1150 is grown on the crystal growth substrate 1001, the crystal quality tends to degrade at and near the end of the semiconductor layer 1150. Therefore, by aligning the end of the semiconductor layer 1150 with the end of the circuit 101, the area near the end of the semiconductor layer 1150 on the semiconductor growth substrate 1194 where the crystal quality tends to degrade can be avoided from being used in the display area of ​​the image display device 1.

[0193] Alternatively, multiple circuit boards 1100a can be prepared and bonded to a semiconductor layer 1150 formed on a crystal growth substrate 1001 of a semiconductor growth substrate 1194.

[0194] Figure 13 This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0195] It should be noted that, in Figure 13 To avoid complications, wiring within the circuit board 100 and the interlayer insulating films 112 and 156 are not shown. Additionally, Figure 13 This refers to a part of the color conversion components such as the color filter 180. Here, the structure including the plug 116k, the connector 115k, the light-emitting element 150, the wiring layers 130 and 160, the interlayer insulating film 156, and the surface resin layer 170 is referred to as the light-emitting circuit section 172. In addition, the structure on which the light-emitting circuit section 172 is provided on the circuit board 100 is referred to as the structure 1192.

[0196] like Figure 13 As shown, the color filter 180 is bonded to the structure 1192 on one side. The other side of the color filter 180 is bonded to the glass substrate 186. A transparent film adhesive layer 188 is provided on one side of the color filter 180, and the filter is bonded to the side of the light-emitting circuit section 172 of the structure 1192 via the transparent film adhesive layer 188.

[0197] In this example, the color filter 180 has color conversion sections arranged in the positive direction of the X-axis in the order of red, green, and blue. For red and green, a red color conversion layer 183R and a green color conversion layer 183G are respectively provided in the first layer, and a light-filtering layer 184 is provided in the second layer. For blue, a single-layer color conversion layer 183B is provided. A light-blocking section 181 is provided between each color conversion section.

[0198] Align the positions of the color conversion layers 183R, 183G, and 183B with the position of the light-emitting element 150, and attach the color filter 180 to the structure 1192.

[0199] Figures 14A to 14D This is a schematic cross-sectional view illustrating a variation of the manufacturing method of the image display device according to this embodiment.

[0200] Figures 14A to 14D This describes a method for forming color filters using inkjet printing.

[0201] like Figure 14A As shown, a structure 1192 on which a light-emitting circuit section 172 is prepared to be attached to a circuit board 100 is shown.

[0202] like Figure 14B As shown, a light-shielding portion 181 is formed on the structure 1192. The light-shielding portion 181 is formed, for example, using screen printing or photolithography.

[0203] like Figure 14C As shown, a phosphor corresponding to the emitted color is ejected from the inkjet nozzle to form a color conversion layer 183. The phosphor is colored in the area where the light-shielding portion 181 is not formed. The phosphor can be a fluorescent paint, such as a common phosphor material or a quantum dot phosphor material. When using a quantum dot phosphor material, it is possible to achieve various emitted colors, and the monochromaticity is increased, which improves color reproducibility, and is therefore preferred. After being drawn through the inkjet nozzle, it is dried at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

[0204] As described above, for blue-emitting subpixels, since there are cases where the color conversion section is not formed, phosphor is not emitted. Furthermore, for blue-emitting subpixels, when a blue color conversion layer is formed, since the color conversion section only needs to be one layer, it is preferable that the coating thickness of the blue phosphor is the same as the thickness of the light-shielding section 181.

[0205] like Figure 14D As shown, the paint for the filter layer 184 is ejected from the inkjet nozzle. The paint is coated over the phosphor film. The combined thickness of the color conversion layer 183 and the filter layer 184 is the same as the thickness of the light-shielding portion 181.

[0206] In this way, it is possible to manufacture the image display device 1.

[0207] The effects of the image display device 1 in this embodiment will be explained.

[0208] In the manufacturing method of the image display device 1 of this embodiment, a semiconductor layer 1150, including a light-emitting layer 1152 for a light-emitting element 150, is bonded to a circuit board 1100 (100) including circuit elements such as a transistor 103 that drives the light-emitting element 150. Then, the semiconductor layer 1150 is etched to form the light-emitting element 150. Therefore, compared to the case where a single, monolithically formed light-emitting element is transferred onto the circuit board 1100a, the process of transferring the light-emitting element can be significantly shortened.

[0209] For example, in a 4K image display device, the number of subpixels exceeds 24 million, and in an 8K image display device, the number exceeds 99 million. Mounting such a large number of light-emitting elements individually onto a circuit board requires a significant amount of time, making it difficult to realistically implement image display devices formed from micro-LEDs at a reasonable cost. Furthermore, mounting a large number of light-emitting elements individually can lead to poor connections during installation, reducing yield and inevitably increasing costs.

[0210] In contrast, in the manufacturing method of the image display device 1 in this embodiment, since the semiconductor layer 1150 is attached to the circuit board 1100 (100) as a whole before the semiconductor layer 1150 is monolithically formed, the transfer process is completed in one step.

[0211] After the light-emitting element is directly formed on the circuit board by etching or the like, the light-emitting element is electrically connected to the circuit element in the circuit board 1100 (100) by forming a plug. Therefore, a uniform connection structure can be achieved and the reduction in yield can be suppressed.

[0212] In the process of electrically connecting the light-emitting element and the circuit element by forming the plug 116k, it is not necessary to provide a deep through hole that penetrates the interlayer insulating film 112, 156, and the n-type semiconductor layer 151 and the transistor 103 can be electrically connected with a low resistance value.

[0213] Furthermore, since it is not necessary to pre-monopolize the semiconductor layer 1150 or form electrodes at the positions corresponding to the circuit elements, but rather to attach it to the circuit substrate 1100 (100) on a wafer-level scale, no alignment is required. Therefore, the attachment process can be easily performed in a short time. Because no alignment is required during attachment, it is also easy to miniaturize the light-emitting element 150, making it suitable for high-definition displays.

[0214] In this embodiment, when bonding the semiconductor layer 1150 to the circuit substrate 1100 wafer, a metal layer 1130 is pre-formed on the semiconductor layer 1150. Therefore, by appropriately selecting the material of the metal layer, wafer bonding can be easily performed.

[0215] The metal layer formed during wafer bonding can serve as the third wiring layer 130, used in connections between the light-emitting element 150 and external components. By making an ohmic connection between the third wiring layer 130 and the n-type semiconductor layer 151, the connector 116k can be electrically connected to the n-type semiconductor layer 151 with a low resistance value.

[0216] Because the third wiring layer 130 may include a light shield 130a, it is possible to prevent circuit elements such as the transistor 103 from malfunctioning due to the scattering of light that is not needed by the light-emitting element 150.

[0217] (Second Implementation)

[0218] Figure 15 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0219] Figure 15 The diagram schematically illustrates the cross-section when the sub-pixel 220 is cut with a face parallel to the XZ plane.

[0220] In this embodiment, the difference from the other embodiments described above lies in the structure of the light-emitting element 250 and the structure of the transistor 203 that drives the light-emitting element 250. For major structural components that are the same as in the other embodiments described above, the same reference numerals are used, and detailed descriptions are omitted where appropriate.

[0221] like Figure 15 As shown, the sub-pixel 220 of the image display device in this embodiment includes a transistor 203 and a light-emitting element 250. The transistor 203 is formed on an element forming region 204 formed on the substrate 102. The element forming region 204 includes an n-type semiconductor region 204b and p-type semiconductor regions 204s and 204d. The n-type semiconductor region 204b is disposed near the surface of the substrate 102. The p-type semiconductor regions 204s and 204d are disposed within the n-type semiconductor region 204b and spaced apart from each other near the surface of the n-type semiconductor region 204b.

[0222] Gate 107 is disposed on n-type semiconductor region 204b via insulating layer 105. Gate 107 is disposed between p-type semiconductor regions 204s and 204d.

[0223] The upper structure and wiring of transistor 203 are the same as in the other embodiments described above. In this embodiment, transistor 203 is a p-channel transistor, such as a p-channel MOSFET.

[0224] In this example, similar to the other embodiments described above, a third wiring layer and a light-shielding plate are not formed on the first interlayer insulating film 112; instead, a p-type semiconductor layer 253 is directly disposed on the plug 116a. A connection portion 115a is disposed between the plug 116a and the wiring 110d. The plug 116a and the wiring 110d are electrically connected by the connection portion 115a.

[0225] As in this example, the plug 116a is preferably positioned such that its outer periphery includes the outer periphery of the light-emitting element 250 projected onto the plug 116a in an XY top view. In this example, the plug 116a also serves as a light shield.

[0226] The light-emitting element 250 includes a p-type semiconductor layer 253, a light-emitting layer 252, and an n-type semiconductor layer 251. The light-emitting element 250 is, for example, roughly square or rectangular in XY top view, but the corners may also be rounded.

[0227] The light-emitting element 250 can be made of the same material as in the other embodiments described above. For example, the light-emitting element 250 emits blue light with a wavelength of about 467nm ± 20nm or blue-violet light with a wavelength of 410nm ± 20nm.

[0228] As described above, the n-type semiconductor layer 251 of the light-emitting element 250 is disposed on the plug 116a. Preferably, the plug 116a is ohmically connected to the n-type semiconductor layer 251.

[0229] A second interlayer insulating film (second insulating film) 156 covers the first interlayer insulating film 112, the sides of the light-emitting element 250, and the planarization film 114. The second interlayer insulating film 156 has an opening 258. The opening 258 is formed on the light-emitting element 250, and the interlayer insulating film 156 is not disposed on the light-emitting surface 251S of the light-emitting element 250. The interlayer insulating film 156 is suitable for using white resin to reflect the light emitted by the light-emitting element 250 and effectively output it from the opening 258.

[0230] The light-emitting surface 251S is the surface of the n-type semiconductor layer 251 that faces the surface adjacent to the light-emitting layer 252. The light-emitting surface 251S is roughened.

[0231] Wiring layer 260 is disposed on interlayer insulating film 156. Wiring layer 260 includes wiring 260k. Wiring 260k is related to the wiring described later. Figure 16The grounding wire 4 is shown as a connection. A transparent electrode 259k is provided on the wiring 260k. The transparent electrode 259k is provided across the entire surface of the light-emitting surface 251S. The transparent electrode 259k is positioned between the wiring 260k and the light-emitting surface 251S, electrically connecting the wiring 260k and the light-emitting surface 251S. Therefore, the n-type semiconductor layer 251 is connected to the grounding wire via the transparent electrode 259k and the wiring 260k.

[0232] A surface resin layer 170 is provided on the interlayer insulating film 156 and the transparent electrode 259k. A color filter 180 is provided on the surface resin layer 170 via a transparent film adhesive layer 188.

[0233] Figure 16 This is a schematic block diagram illustrating the image display device of this embodiment.

[0234] like Figure 16 As shown, the image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. Similar to the other embodiments described above, sub-pixels 220 are arranged in a grid pattern in the display area 2, for example.

[0235] Sub-pixel 220 includes a light-emitting element 222, a selection transistor 224, a driving transistor 226, and a capacitor 228. Figure 16 In this context, the select transistor 224 is sometimes referred to as T1, the drive transistor 226 as T2, and the capacitor 228 as Cm.

[0236] In this embodiment, the light-emitting element 222 is disposed on the ground line 4 side, and the driving transistor 226, which is connected in series with the light-emitting element 222, is disposed on the power line 3 side. That is, the driving transistor 226 is connected closer to the high potential side than the light-emitting element 222. The driving transistor 226 is a p-channel MOSFET.

[0237] A select transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. A capacitor 228 is connected between the gate electrode of the driving transistor 226 and the power supply line 3.

[0238] In order to drive the p-channel MOSFET, i.e., the driving transistor 226, the row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage with a polarity different from that in the other embodiments described above to the scan line 206 and the signal line 208.

[0239] In this embodiment, because the driving transistor 226 is p-channel, the polarity of the signal voltage differs from that in the other embodiments described above. Specifically, the row selection circuit 205 supplies a selection signal to the scan line 206 to sequentially select a row from the arrangement of m rows of sub-pixels 220. The signal voltage output circuit 207 supplies a signal voltage with the required analog voltage value to each sub-pixel 220 of the selected row. The driving transistor 226 of the selected row's sub-pixel 220 flows a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light with a brightness corresponding to the flowing current.

[0240] The manufacturing method of the image display device 201 according to this embodiment will be described.

[0241] Figures 17A to 18C This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0242] like Figure 17A As shown, in this embodiment, preparation and in Figure 5A The semiconductor growth substrate 1294 is different from the semiconductor growth substrate 1194 already described. The semiconductor growth substrate 1294 has a semiconductor layer 1150 grown on the crystal growth substrate 1001. In this example, the semiconductor layer 1150 is grown via a buffer layer 1140.

[0243] In this embodiment, the semiconductor growth substrate 1294 is laminated from the crystal growth substrate 1001 in the following order: an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153. In the early stages of crystal growth, crystal defects are easily generated due to lattice constant inconsistencies, resulting in an n-type crystal. Therefore, laminating from the n-type semiconductor layer 1151 as described in this embodiment has advantages such as increased manufacturing process margin and easier yield improvement.

[0244] In this example, no metal layer is formed on the side of the p-type semiconductor layer 1153, but it is bonded to the circuit substrate 1100.

[0245] like Figure 17B As shown, on the prepared circuit board 1100, a plug 116a and a connection portion 115a are formed within a planarization film 114. The formation process of the planarization film 114, the plug 116a, and the connection portion 115a can be the same as that of... Figures 8A to 9C The procedures described are the same.

[0246] The semiconductor growth substrate 1294 is flipped upside down and attached to the circuit substrate 1100. As shown by the arrow in the figure, one side of the circuit substrate 1100 is aligned with the open side of the p-type semiconductor layer 1153 of the semiconductor layer 1150, and the two sides are attached. The bonding surface of the circuit substrate 1100 is the planarization film 114 and the exposed surface of the connector 116a exposed on the same plane as the planarization film 114.

[0247] It should be noted that in the above-mentioned wafer bonding, it is also possible to combine it with... Figures 6A to 6C The situation is the same as the variations described above. That is, it can be done as already described. Figure 6A As explained in the description, after the semiconductor layer 1150 is transferred to the support substrate, the semiconductor growth substrate 1294 is attached to the circuit substrate 1100 without reversing. Alternatively, as already described... Figure 6B As described in the instructions, a metal layer is disposed on semiconductor layer 1150. Alternatively, as already described... Figure 6C As explained in the description, the semiconductor layer 1150 grown by crystal is attached without passing through the buffer layer 1140.

[0248] like Figure 18A As shown, after the semiconductor layer 1150 is bonded to the circuit substrate 1100, the crystal growth substrate 1001 is removed.

[0249] like Figure 18B As shown, similar to the other embodiments described above, the semiconductor layer 1150 is etched to form the light-emitting element 250.

[0250] like Figure 18C As shown, after removing the buffer layer 240, an interlayer insulating film 156 is formed covering the planarization film 114, the plug 116a, and the light-emitting element 150. An opening 258 is formed in the interlayer insulating film 156 to roughen the light-emitting surface 251S. Then, a second wiring layer 260 including wiring 260k is formed, and a transparent electrode 259k is formed on the second wiring layer 260 using an ITO film or the like.

[0251] The effects of the image display device 201 in this embodiment will be explained.

[0252] In this embodiment, the same effects as in the other embodiments described above are achieved. That is, since the individual light-emitting element 250 is formed by etching after the semiconductor layer 1150 is bonded to the circuit board 1100, the transfer process of the light-emitting element can be significantly shortened.

[0253] In addition to the effects of the other embodiments described above, in this embodiment, by making the n-type semiconductor layer 251 the light-emitting surface 251S, it is easier to roughen the surface, and by connecting the wiring 260k to the light-emitting surface 251S, a sub-pixel with high luminous efficiency can be formed.

[0254] In this embodiment, by using the plug 116a as a light shield, the formation of a light-shielding metal layer can be omitted.

[0255] (Third Implementation)

[0256] In other embodiments described above, wiring layers 160 and 260 formed on the second interlayer insulating film 156 are used to electrically connect the light-emitting surface of the light-emitting element to power lines and ground lines, etc. In this embodiment, wiring layer 330 formed between the light-emitting element and the circuit element is used to electrically connect the light-emitting surface of the light-emitting element to power lines and ground lines, etc.

[0257] Figure 19 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0258] Figure 19 The diagram schematically illustrates the cross-section when the sub-pixel 320 is cut with a face parallel to the XZ plane.

[0259] In this embodiment, the structure of the light-emitting element 250 is the same as in the second embodiment. That is, the light-emitting element 250 has a lower p-type semiconductor layer 253, a light-emitting layer 252, and an n-type semiconductor layer 251 having a light-emitting surface 251S. The driving transistor 203 of the light-emitting element 250 is a p-channel transistor. For the main components of the same structure as in the other embodiments described above, the same reference numerals are used, and detailed descriptions are omitted as appropriate.

[0260] like Figure 19 As shown, the sub-pixel 320 of the image display device in this embodiment includes a transistor 203 and a light-emitting element 250. The transistor 203 is formed in an element forming region 204 formed on the substrate 102. The element forming region 204 includes an n-type semiconductor region 204b and p-type semiconductor regions 204s and 204d, and the transistor 203 is a p-channel transistor.

[0261] The structure of the upper part of the transistor 203 on the circuit board 100 and the wiring structure are the same as those in the second embodiment described above.

[0262] A planarization film 114 is formed on the first interlayer insulating film 112. A plug 116a1 is embedded in the planarization film 114, and the exposed surface of the plug 116a1 is formed in a plane substantially the same as the planarization film 114. This plane is substantially parallel to the XY plane. The plug 116a1 is connected to the wiring 110d via a connecting portion 115a provided in the interlayer insulating film 112.

[0263] A wiring layer (third wiring layer) 330 is provided on the planarization film 114 and the plug 116a1. The wiring layer 330 includes wirings 330a and 330k. Wiring 330a is disposed on the plug 116a1, electrically connecting wiring 330a and plug 116a1.

[0264] A light-emitting element 250 is provided on the wiring 330a. The light-emitting element 250 is laminated from the wiring 330a side to the light-emitting surface 251S side in the order of p-type semiconductor layer 253, light-emitting layer 252, and n-type semiconductor layer 251. That is, the wiring 330a is connected to the p-type semiconductor layer 253. Preferably, the wiring 330a is ohmically connected to the p-type semiconductor layer 253 and connected to the wiring 110d via the plug 116a1 and the connecting part 115a.

[0265] In this example, wiring 330a is also used as a light shield. That is, the outer periphery of wiring 330a is set to include the outer periphery of the light-emitting element 250 projected onto wiring 330a in XY top view.

[0266] 330k wiring and Figure 16 The grounding wire 4 is shown as a connection. Wiring 330k is provided, for example, to surround wiring 330a.

[0267] The second interlayer insulating film 156 is formed on the planarization film 114, the wiring layer 330, and the light-emitting element 250. The interlayer insulating film 156 has openings 258 and 262. The opening 258 is located at a position corresponding to the light-emitting element 250, thus exposing the light-emitting surface 251S. The opening 262 is located at a position corresponding to the wiring 330k.

[0268] A transparent electrode (second wiring layer) 259k is provided throughout the light-emitting surface 251S. The transparent electrode 259k is provided throughout the entire surface of the opening 262 and throughout the wiring 330k exposed from the opening 262. The transparent electrode 259k is disposed between the light-emitting surface 251S and the opening 262, and electrically connects the light-emitting surface 251S and the wiring 330k.

[0269] Thus, the anode electrode of the light-emitting element 250, i.e., the p-type semiconductor layer 253, is connected to the driving transistor 203, and the cathode electrode, i.e., the n-type semiconductor layer 251, is connected to the ground wire. In this embodiment, the light-emitting element 250 is driven by the p-channel transistor 203. For example, a driving circuit may be used... Figure 16 The circuit structure shown is shown.

[0270] The manufacturing method of the image display device according to this embodiment will be described.

[0271] Figures 20A to 21B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0272] like Figure 20A As shown, a semiconductor growth substrate 1294 is prepared for growing a semiconductor layer 1150 on a crystal growth substrate 1001. In this embodiment, the semiconductor growth substrate 1294 is grown and formed on the crystal growth substrate 1001 from one side of the crystal growth substrate 1001 via a buffer layer 1140, in the order of an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153.

[0273] Furthermore, a metal layer 1130 is formed on the prepared semiconductor growth substrate 1294. The metal layer 1130 is formed on the side of the p-type semiconductor layer 1153 facing the side where the light-emitting layer 1152 is located. It should be noted that by forming a thin film layer using a hole-injection-compatible material at the interface between the p-type semiconductor layer 1153 and the metal layer 1130, the driving voltage of the light-emitting element 250 can be further reduced. As the aforementioned hole-injection-compatible material, ITO film is suitable for application, for example.

[0274] like Figure 20B As shown, a plug 116a1 and a connection portion 115a are formed on the circuit board 1100 within a planarization film 114. The formation process of the planarization film 114, the plug 116a1, and the connection portion 115a is similar to that in... Figures 8A to 9C The situation described in the text is the same.

[0275] The semiconductor growth substrate 1294, on which the metal layer 1130 is formed, is flipped upside down and bonded to the circuit substrate 1100. As shown by the arrow in the figure, one side of the circuit substrate 1100 is aligned with the metal layer 1130, and the two are bonded together. The bonding surface of the circuit substrate 1100 is the planarization film 114 and the exposed surface of the plug 116a1 exposed on the same plane as the planarization film 114.

[0276] like Figure 21A As shown, after the circuit board 1100 and the semiconductor growth substrate 1294 on which the metal layer 1130 is formed are bonded together, the crystal growth substrate 1001 is removed.

[0277] like Figure 21B As shown, the semiconductor layer 1150 is processed to form a light-emitting element 250. The light-emitting element 250 is formed by etching.

[0278] After the light-emitting element 250 is formed, the metal layer 1130 is processed to form the third wiring layer 330. The third wiring layer 330 is formed by etching.

[0279] like Figure 21C As shown, a second interlayer insulating film 156 is formed to cover the wiring layer 330, the planarization film 114 and the sides of the light-emitting element 250.

[0280] Openings 258 and 262 are formed in the interlayer insulating film 156. Opening 258 is etched until the n-type semiconductor layer 251 is reached, exposing the light-emitting surface 251S. Opening 262 is etched until the wiring 330k is reached, exposing the wiring 330k.

[0281] A transparent conductive film is formed on the exposed light-emitting surface 251S and the wiring 330k, and the n-type semiconductor layer 251 and the wiring 330k are connected by a transparent electrode 259k.

[0282] The effects of the image display device according to this embodiment will be explained.

[0283] The image display device of this embodiment has the same effects as the other embodiments described above, and also has the following effects.

[0284] In this embodiment, the sub-pixels 320 of the image display device are electrically connected to the light-emitting surface 251S side by transparent electrodes, and electrically connected to the side opposite to the light-emitting surface 251S by wiring layer 330, plug 116a1, and connecting portion 115a. Therefore, all wiring on the light-emitting surface 251S side can be transparent electrodes, which can improve the luminous efficiency of the light-emitting element 250 and reduce the cost of wiring process.

[0285] By making the wiring layers on the light-emitting surface 251S side all transparent electrodes formed of transparent conductive film, and making the wiring of power lines and ground lines, etc., the inner layer, i.e. the third wiring layer 330, the degree of freedom of wiring patterns of power lines and ground lines, etc., can be increased, and the design efficiency of image display devices can be improved.

[0286] (Fourth Implementation)

[0287] In this embodiment, the plug structure differs from that in the other embodiments described above. In this embodiment, the third wiring layer 330, which corresponds to the third embodiment, and the plug 116a1 are integrally formed. The other major structural components are the same as in the third embodiment; for the same major structural components, the same reference numerals are used, and detailed descriptions are omitted where appropriate.

[0288] Figure 22 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0289] like Figure 22As shown, the sub-pixel 420 of the image display device in this embodiment includes a wiring layer and a connection portion 115a. The wiring layer 430 includes a plug 430a. In this example, the connection portion 115a is disposed between the plug 430a and the wiring 110d. The plug 430a is connected to the wiring 110d via the connection portion 115a. A light-emitting element 250 is provided on the plug 430a, and the plug 430a and the p-type semiconductor layer 253 are electrically connected.

[0290] The plug 430a also functions as a light shield. That is, the outer periphery of the plug 430a is positioned such that it includes the outer periphery of the light-emitting element 250 projected onto the plug 430a in an XY top view. This reflects downward-scattered light from the light-emitting element 250, improving luminous efficiency and suppressing light from reaching circuit components, thus preventing malfunctions.

[0291] The wiring layer 430 includes wiring 430k, a portion of which is exposed through an opening 262 formed in the second interlayer insulating film 156. A portion of the wiring 430k exposed through the opening 262 is covered by a transparent electrode 259k. The wiring 430k is electrically connected to the light-emitting surface 251S via the transparent electrode 259k. It should be noted that the wiring 430k, as described later in the manufacturing method description, is formed simultaneously with the plug 430a.

[0292] (Example of a variation of a subpixel)

[0293] Figure 23 This is a schematic cross-sectional view illustrating a portion of the image display device of this variant example.

[0294] In the sub-pixel 420 described above, the p-type semiconductor layer 253 formed on the lower layer of the light-emitting element 250 is connected to the p-channel transistor 203 via a connector 430a and a connection portion 115a. In this modified example, the wiring 430k exposed through the opening 262 is connected to the n-channel transistor 103 via the connection portion. The light-emitting surface 251S is connected to the connector 430a exposed from the opening 262. The structure of this sub-pixel 420a can also be applied as a modified example of the sub-pixel 320 of the third embodiment described above.

[0295] like Figure 23 As shown, in this modified example, sub-pixel 420a includes a wiring 430k and a connection portion 115k. Wiring 430k is connected to wiring 110d via the connection portion 115k. Wiring layer 430 includes a connector 430a, which connects to... Figure 4 The power line 3 shown is connected. In this modified example, the light-emitting element 250 is driven by an n-channel transistor 103. Figure 4 The driving circuit.

[0296] The manufacturing method of this embodiment will be described.

[0297] Figures 24A to 25B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0298] Preparation and in Figure 17A The semiconductor growth substrate 1294, which has a metal layer 1130 formed thereon, is the same as the semiconductor growth substrate described herein.

[0299] like Figure 24A As shown, in this embodiment, a contact hole h2 reaching the wiring 110d is formed on the first interlayer insulating film 1112 of the prepared circuit board 1100, and a metal layer 4120 is formed over the entire surface of the interlayer insulating film 1112. The contact hole h2 is also filled during the formation of the metal layer 4120. The metal layer 4120 is formed, for example, by sputtering, similar to other embodiments described above. The metal layer 4120 may contain, for example, Ti, Al, an alloy of Ti and Sn. It may also contain Cu, V, or noble metals with high light reflectivity such as Ag and Pt.

[0300] After the metal layer 4120 is formed, the open surfaces of the metal layer 4120 are polished and planarized using CMP or similar methods.

[0301] The contact hole h2 is filled with the material of the metal layer 4120 to form the connection portion 115a. The metal layer 4120 is connected to the wiring 110d by the connection portion 115a.

[0302] The semiconductor growth substrate 1294, on which the metal layer 1130 is formed, is bonded to the circuit substrate 1100, on which the metal layer 4120 and the connection portion 115a are formed, via the metal layer 1130.

[0303] like Figure 24B As shown, the crystal growth substrate 1001 is removed by laser irradiation or by wet etching.

[0304] like Figure 25A As shown, the metal layers 1130 and 4120 after bonding are etched to form a wiring layer 430 including a plug 430a and wiring 430k.

[0305] like Figure 25B As shown, the wiring layer 430, including the plug 430a and wiring 430k, is embedded together with the light-emitting element 250 in the second interlayer insulating film 156. The interlayer insulating film 156 is formed by covering the wiring layer 430, the side of the light-emitting element 250, and the first interlayer insulating film 112.

[0306] An opening 258 is formed in the interlayer insulating film 156 at a position corresponding to the light-emitting surface 251S, and an opening 262 is formed at a position corresponding to the wiring 430k. Then, a transparent electrode 259k is formed on the light-emitting surface 251S and the wiring 430k exposed from the openings 258 and 262, electrically connecting the light-emitting surface 251S and the wiring 430k.

[0307] The manufacturing method of sub-pixel 420a can also be carried out in the same way as described above.

[0308] The effects of the image display device according to this embodiment will be explained.

[0309] In addition to the effects of the other embodiments described above, the image display device of this embodiment also has the following effect: In the formation process of sub-pixels 420 and 420a, since a metal layer is formed on the circuit board and polished before bonding the semiconductor layer 1150 to the circuit board 1100, the process of forming a planarization film can be omitted.

[0310] The plug 430a is configured to include the outer periphery of the light-emitting element 250 projected onto the plug 430a in XY top view, and can therefore be used as a light shield. Thus, the process of forming a wiring layer including the light shield can be omitted.

[0311] (Fifth Implementation)

[0312] In this embodiment, an image display device with higher luminous efficiency is achieved by forming multiple light-emitting surfaces, equivalent to multiple light-emitting elements, on a single semiconductor layer including a light-emitting layer. In the following description, the same reference numerals are used for the main structural components that are the same as in the other embodiments described above, and detailed descriptions are omitted where appropriate.

[0313] Figure 26 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0314] like Figure 26 As shown, the image display device has a subpixel group 520. The subpixel group 520 includes: transistors 203-1 and 203-2, a first wiring layer 510, a first interlayer insulating film 112, plugs 516a1 and 516a2, a semiconductor layer 550, a second interlayer insulating film 556, and a second wiring layer 560.

[0315] In this embodiment, by turning on p-channel transistors 203-1 and 203-2, holes are injected into semiconductor layer 550 via connectors 516a1 and 516a2, and electrons are injected into semiconductor layer 550 via second wiring layer 560, causing light-emitting layer 552 to emit light. A driving circuit, for example, is suitable for... Figure 16The circuit structure shown is illustrated. Alternatively, other embodiments described above can be used, where the n-type and p-type semiconductor layers are interchanged. A structure where the semiconductor layers are driven by an n-channel transistor can also be employed. In this case, the driving circuit is suitable for… Figure 4 The circuit structure.

[0316] The semiconductor layer 550 includes two light-emitting surfaces 551S1 and 551S2, and the sub-pixel group 520 actually includes two sub-pixels. In this embodiment, as in the other embodiments described above, the display area is formed by arranging the sub-pixel group 520, which actually includes two sub-pixels, in a grid pattern.

[0317] Transistors 203-1 and 203-2 are formed in device formation regions 204-1 and 204-2, respectively. In this example, device formation regions 204-1 and 204-2 are n-type semiconductor layers, and p-type semiconductor layers are formed separately from the n-type semiconductor layers. The n-type semiconductor layer includes a channel region, and the p-type semiconductor layer includes a source region and a drain region, respectively.

[0318] An insulating layer 105 is formed on the component forming regions 204-1 and 204-2, and gates 107-1 and 107-2 are formed through the insulating layer 105, respectively. Gates 107-1 and 107-2 are the gates of transistors 203-1 and 203-2. Transistors 203-1 and 203-2 are p-channel transistors, such as p-channel MOSFETs.

[0319] An insulating film 108 covers the two transistors 203-1 and 203-2. A wiring layer 510 is formed on the insulating film 108.

[0320] Through-holes 111s1 and 111d1 are provided between the p-type semiconductor layer and the wiring layer 510 of transistor 203-1, respectively. Through-holes 111s2 and 111d2 are provided between the p-type semiconductor layer and the wiring layer 510 of transistor 203-2.

[0321] The first wiring layer 510 includes wirings 510s1, 510s2, 510d1, and 510d2. Wirings 510s1 and 510s2 are electrically connected to the p-type semiconductor layers corresponding to the source electrodes of transistors 203-1 and 203-2, respectively, via vias 111s1 and 111s2. Although not shown in the diagram, wirings 510s1 and 510s2 are connected to power lines.

[0322] Wirings 510d1 and 510d2 are connected to the p-type semiconductor layers corresponding to the drain electrodes of transistors 203-1 and 203-2 via vias 111d1 and 111d2, respectively.

[0323] The first interlayer insulating film 112 covers transistors 203-1 and 203-2, wiring layer 510, and plugs 516a1 and 516a2.

[0324] A planarization film 114 is formed on the first interlayer insulating film 112. Plugs 516a1 and 516a2 are embedded in the planarization film 114, and the planarization film 114 and plugs 516a1 and 516a2 have surfaces that are on the same plane in an XY top view. This surface faces the side of the interlayer insulating film 112. That is, a planarization film 114 is provided between plugs 516a1 and 516a2.

[0325] A connecting part 515a1 is provided between plug 516a1 and wiring 510d1. Connecting part 515a1 electrically connects plug 516a1 and wiring 510d1. A connecting part 515a2 is provided between plug 516a2 and wiring 510d2. Connecting part 515a2 electrically connects plug 516a2 and wiring 510d2.

[0326] Semiconductor layer 550 is disposed on planarization film 114 and plugs 516a1, 516a2.

[0327] Semiconductor layer 550 includes a p-type semiconductor layer 553, a light-emitting layer 552, and an n-type semiconductor layer 551. Semiconductor layer 550 is laminated from the interlayer insulating film 112 side towards the light-emitting surfaces 551S1 and 551S2 side, in the order of p-type semiconductor layer 553, light-emitting layer 552, and n-type semiconductor layer 551. Connectors 516a1 and 516a2 are connected to the p-type semiconductor layer 553.

[0328] A second interlayer insulating film (second insulating film) 556 covers the planarization film 114, plugs 516a1, 516a2, and semiconductor layer 550. The second interlayer insulating film 556 covers a portion of the semiconductor layer 550. Preferably, the second interlayer insulating film 556 covers the surface of the n-type semiconductor layer 551, except for the light-emitting surfaces (exposed surfaces) 551S1, 551S2 of the semiconductor layer 550. The interlayer insulating film 556 covers the side surfaces of the semiconductor layer 550. The interlayer insulating film 556 is preferably a white resin.

[0329] Openings 558-1 and 558-2 are formed in the portion of semiconductor layer 550 not covered by interlayer insulating film 556. Openings 558-1 and 558-2 are formed at positions corresponding to light-emitting surfaces 551S1 and 551S2. Light-emitting surfaces 551S1 and 551S2 are formed at spaced-apart positions on the n-type semiconductor layer 551. Light-emitting surface 551S1 is positioned on the n-type semiconductor layer 551 closer to transistor 203-1. Light-emitting surface 551S2 is positioned on the n-type semiconductor layer 551 closer to transistor 203-2.

[0330] Openings 558-1 and 558-2, when viewed from above in the XY direction, are, for example, square or rectangular. They are not limited to squares; they can also be polygons such as circles, ellipses, or hexagons. The luminous surfaces 551S1 and 551S2, when viewed from above in the XY direction, are also squares, rectangles, other polygons, or circles. The shapes of the luminous surfaces 551S1 and 551S2 can be similar to or different from the shapes of openings 558-1 and 558-2.

[0331] The second wiring layer 560 is disposed on the interlayer insulating film 556. The wiring layer 560 includes wiring 560k. Wiring 560k is disposed on the second interlayer insulating film 556 disposed on the n-type semiconductor layer 551 between openings 558-1 and 558-2. Although not shown, wiring 560k is connected to the ground wire. It should be noted that... Figure 26 In this diagram, the marking for wiring layer 560 is combined with the marking for wiring 560k, indicating that wiring layer 560 includes wiring 560k. The same applies to Figure 28, which is described later.

[0332] Transparent electrodes 559k are disposed on the light-emitting surfaces 551S1 and 551S2 of the n-type semiconductor layer 551 exposed through openings 558-1 and 558-2, respectively. Transparent electrodes 559k are disposed on wiring 560k. Transparent electrodes 559k are disposed between light-emitting surface 551S1 and wiring 560k, and also between light-emitting surface 551S2 and wiring 560k. Transparent electrodes 559k are electrically connected to light-emitting surfaces 551S1 and 551S2 and wiring 560k.

[0333] As described above, transparent electrodes 559k are connected to the light-emitting surfaces 551S1 and 551S2 exposed from openings 558-1 and 558-2. Therefore, electrons supplied from the transparent electrodes 559k are supplied to the n-type semiconductor layer 551 from their respective exposed light-emitting surfaces 551S1 and 551S2. On the other hand, holes are supplied to the p-type semiconductor layer 553 via plugs 516a1 and 516a2.

[0334] Transistors 203-1 and 203-2 are driving transistors for adjacent sub-pixels and are driven sequentially. Therefore, holes supplied from either transistor 203-1 or 203-2 are injected into the light-emitting layer 552, and electrons supplied from wiring 560k are injected into the light-emitting layer 552, causing the light-emitting layer 552 to emit light.

[0335] The opening 558-1 and the light-emitting surface 551S1 are positioned closer to the transistor 203-1 on the n-type semiconductor layer 551. Therefore, when the transistor 203-1 is turned on, holes are injected through the wiring 510d1, the connection portion 515a1, and the plug 516a1, thereby causing the light-emitting surface 551S1 to emit light.

[0336] On the other hand, the opening 558-2 and the light-emitting surface 551S2 are positioned closer to the transistor 203-2 on the n-type semiconductor layer 551. Therefore, when the transistor 203-2 is turned on, the light-emitting surface 551S2 emits light through the wiring 510d2, the connection portion 515a2, and the plug 516a2.

[0337] The manufacturing method of the image display device according to this embodiment will be described.

[0338] Figures 27A to 28B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this embodiment.

[0339] like Figure 27A As shown, a semiconductor growth substrate 1294, including a crystal growth substrate 1001 on which a semiconductor layer 1150 is epitaxially grown, forms plugs 516a1, 516a2 and connection portions 515a1, 515a2 on a prepared circuit substrate 5100, and they are bonded to each other by wafer bonding.

[0340] For the process of forming plugs 516a1, 516a2 and connecting portions 515a1, 515a2 on the circuit board 5100, the above-mentioned... Figures 8A to 9C The process described above. The forming process of plugs 516a1 and 516a2 can also be utilized in the above process. Figure 24A The process described herein. It should be noted that although the circuit structure of the circuit board 5100 differs from that of the other embodiments described above, the structure of almost all other parts is the same as the structure already described. Hereinafter, only the reference numerals will be replaced, and detailed descriptions will be omitted as appropriate.

[0341] like Figure 27B As shown, after the semiconductor layer 1150 is bonded to the circuit board 5100 on which the plugs 516a and 516a2 are formed, the crystal growth substrate 1001 is removed.

[0342] like Figure 28A As shown, semiconductor layer 1150 is etched to form semiconductor layer 550.

[0343] like Figure 28B As shown, an interlayer insulating film is formed covering the planarization film 114, plugs 516a1, 516a2 and semiconductor layer 550.

[0344] A wiring layer 560 is formed on the interlayer insulating film 556, and wiring 560k is formed by etching.

[0345] By removing the interlayer insulating film 556 at the positions corresponding to the light-emitting surfaces 551S1 and 551S2, openings 558-1 and 558-2 are formed respectively.

[0346] The exposed surfaces 551S1 and 551S2 through openings 558-1 and 558-2 are roughened. Then, a transparent electrode 559k is formed to electrically connect the light-emitting surfaces 551S1 and 551S2 to the wiring 560k.

[0347] In this way, a sub-pixel group 520 is formed, which has a semiconductor layer 550 sharing two light-emitting surfaces 551S1 and 551S2.

[0348] In this embodiment, two light-emitting surfaces 551S1 and 551S2 are provided on a semiconductor layer 550, but the number of light-emitting surfaces is not limited to two; three or more light-emitting surfaces may also be provided on a semiconductor layer 550. As an example, one or two columns of sub-pixels may also be implemented using a single semiconductor layer 550. Thus, as described later, the recombination current that does not contribute to light emission from each light-emitting surface can be reduced, and the effect of realizing finer light-emitting elements can be increased.

[0349] (Modified Example)

[0350] Figure 29 This is a schematic cross-sectional view of a portion of an image display device illustrating a variation of this embodiment.

[0351] In this modified example, the difference from the fifth embodiment described above is that two n-type semiconductor layers 5551a1 and 5551a2 are provided on the light-emitting layer 552. Other aspects are the same as in the fifth embodiment; the same reference numerals are used for the same main structural components, and detailed descriptions are omitted where appropriate.

[0352] like Figure 29 As shown, the image display device of this modified example has a sub-pixel group 520a. The sub-pixel group 520a includes a semiconductor layer 550a. The semiconductor layer 550a includes a p-type semiconductor layer 553, a light-emitting layer 552, and n-type semiconductor layers 5551a1 and 5551a2. The p-type semiconductor layer 553, the light-emitting layer 552, and the n-type semiconductor layers 5551a1 and 5551a2 are sequentially laminated from the interlayer insulating film 556 toward the light-emitting surfaces 5551S1 and 5551S2.

[0353] n-type semiconductor layers 5551a1 and 5551a2 are arranged on the light-emitting layer 552, spaced apart along the X-axis. An interlayer insulating film 556 is provided between the n-type semiconductor layers 5551a1 and 5551a2, and the n-type semiconductor layers 5551a1 and 5551a2 are separated by the interlayer insulating film 556.

[0354] The n-type semiconductor layers 5551a1 and 5551a2 have roughly the same shape when viewed from above in the XY direction. Their shape is roughly square or rectangular, but can also be other polygonal or circular shapes.

[0355] The n-type semiconductor layers 5551a1 and 5551a2 have light-emitting surfaces 5551S1 and 5551S2, respectively. The light-emitting surfaces 5551S1 and 5551S2 are the surfaces of the n-type semiconductor layers 5551a1 and 5551a2 exposed through openings 558-1 and 558-2, respectively.

[0356] The shapes of the light-emitting surfaces 5551S1 and 5551S2 in the XY top view are the same as those of the light-emitting surfaces in the fifth embodiment, having approximately the same shape, such as a roughly square shape. The shapes of the light-emitting surfaces 5551S1 and 5551S2 are not limited to the square shape of this embodiment; they can also be polygons such as circles, ellipses, or hexagons. The shapes of the light-emitting surfaces 5551S1 and 5551S2 can be similar to the shapes of the openings 558-1 and 558-2, or they can be different shapes.

[0357] Transparent electrodes 559k are respectively provided on the light-emitting surfaces 5551S1 and 5551S2. Transparent electrodes 559k are also provided on the wiring 560k. Transparent electrodes 559k are positioned between the wiring 560k and the light-emitting surface 5551S1, and also between the wiring 560k and the light-emitting surface 5551S2. Transparent electrodes 559k electrically connect the wiring 560k and the light-emitting surfaces 5551S1 and 5551S2.

[0358] Figure 30A and Figure 30B This is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to this modified example.

[0359] In this modified example, before the circuit board 5100, on which the plugs 516a1, 516a2 and the connecting portions 515a1, 515a2 are formed by bonding the semiconductor layer 1150, the method applicable to the fifth embodiment is as follows. Figure 27A and Figure 27B The same procedures described above. The following sections will explain the procedures that follow.

[0360] like Figure 30A As shown, in this modified example, for Figure 27B The p-type semiconductor layer 1153, the light-emitting layer 1152 and the n-type semiconductor layer 1151 are etched to form the light-emitting layer 552 and the p-type semiconductor layer 553. Then, further etching is performed to form two n-type semiconductor layers 5551a1 and 5551a2.

[0361] The n-type semiconductor layers 5551a1 and 5551a2 can also be formed by deep etching. For example, the etching for forming the n-type semiconductor layers 5551a1 and 5551a2 can be performed to a depth reaching the light-emitting layer 552 or the p-type semiconductor layer 553. In this case, when the n-type semiconductor layer is deeply etched, the etch position of the n-type semiconductor layer 1151 is expected to be separated from the outer periphery of the light-emitting surfaces 5551S1 and 5551S2 of the n-type semiconductor layer, as described later, by more than 1 μm. By separating the etch position from the outer periphery of the light-emitting surfaces 5551S1 and 5551S2, recombination current can be suppressed.

[0362] like Figure 30B As shown, an interlayer insulating film is formed covering the planarization film 114, plugs 516a1 and 516a2, and semiconductor layer 550a. A wiring layer 560 is formed on the interlayer insulating film 556, and wiring 560k is formed by etching.

[0363] Openings 558-1 and 558-2 are formed at positions corresponding to the light-emitting surfaces 5551S1 and 5551S2 on the interlayer insulating film, respectively. The light-emitting surfaces 5551S1 and 5551S2 of the p-type semiconductor layer exposed through openings 558-1 and 558-2 are roughened. Then, a transparent electrode 559k is formed.

[0364] In this way, a sub-pixel group 520a with two light-emitting surfaces 5551S1 and 5551S2 is formed.

[0365] The situation in this modified example is the same as that in the fifth embodiment. The number of light-emitting surfaces is not limited to two. Three or more light-emitting surfaces may be provided in one semiconductor layer 550a.

[0366] The effects of the image display device according to this embodiment will be explained.

[0367] Figure 31 This is a graph illustrating the characteristics of a pixel LED element.

[0368] Figure 31 The vertical axis represents luminous efficiency [%). The horizontal axis uses relative values ​​to represent the current density of the current flowing in the pixel LED element.

[0369] like Figure 31 As shown, in the region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is approximately constant or monotonically increasing. In the region where the relative value of the current density is greater than 1.0, the luminous efficiency monotonically decreases. That is to say, for a pixel LED element, there exists an appropriate current density that maximizes the luminous efficiency.

[0370] The goal is to achieve a highly efficient image display device by suppressing the current density to a level where sufficient brightness can be obtained from the light-emitting element. However, Figure 21 shows that at low current densities, the luminous efficiency tends to decrease as the current density decreases.

[0371] As described in the first to fourth embodiments, the light-emitting element is formed by individually separating the entire semiconductor layer 1150, including the light-emitting layer, using etching or the like. At this time, the junction surface between the light-emitting layer and the n-type semiconductor layer is exposed at the end. Similarly, the junction surface between the light-emitting layer and the p-type semiconductor layer is exposed at the end.

[0372] In the presence of the aforementioned ends, electrons and holes recombine at the ends. However, this recombination does not contribute to light emission. The recombination at the ends is almost unrelated to the current flowing through the light-emitting element. It can be considered that the recombination occurs based on the length of the junction surface at the ends that contributes to light emission.

[0373] When two light-emitting elements of the same size cube shape emit light, since the ends are formed on the four sides of each light-emitting element, a total of eight ends may be generated.

[0374] In contrast, in this embodiment, the semiconductor layers 550 and 550a, which have two light-emitting surfaces, have four ends. In the region between openings 558-1 and 558-2, the injection of electrons and holes is reduced, contributing almost nothing to light emission; therefore, the number of ends that contribute to light emission can be considered as six. Thus, in this embodiment, the number of ends of the semiconductor layer is effectively reduced, thereby reducing recombination that does not contribute to light emission, and the reduction in recombination current may lower the driving current.

[0375] In cases where the distance between sub-pixels is shortened for purposes such as high resolution, or where the current density is relatively high, the distance between the light-emitting surfaces 553S1 and 553S2 is shortened in the sub-pixel group 520 of the fifth embodiment. In this case, when the p-type semiconductor layer 553 is shared, a portion of the electrons injected to the adjacent light-emitting surface may be shunted, potentially causing the undriven side of the light-emitting surface to emit faint light. In a modified example, because the p-type semiconductor layer is separated for each light-emitting surface, it is possible to reduce faint light emission from the undriven side of the light-emitting surface.

[0376] In this embodiment, the semiconductor layer including the light-emitting layer is laminated from the first interlayer insulating film 112 side in the order of n-type semiconductor layer, light-emitting layer, and p-type semiconductor layer, and the exposed surface of the p-type semiconductor layer is roughened. This is preferred from the perspective of improving luminous efficiency. Alternatively, similar to the other embodiments described above, the lamination order of the p-type semiconductor layer and the n-type semiconductor layer can be changed, and the lamination can be performed in the order of p-type semiconductor layer, light-emitting layer, and n-type semiconductor layer.

[0377] (Sixth Implementation Method)

[0378] The aforementioned image display device, as an image display module with an appropriate number of pixels, can be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0379] Figure 32 This is a block diagram illustrating the image display device of this embodiment.

[0380] Figure 32 This shows the main structural components of a computer monitor.

[0381] like Figure 32 As shown, the image display device 601 includes an image display module 602. The image display module 602 is, for example, an image display device with the structure described in the first embodiment. The image display module 602 includes: a display area 2 with sub-pixels 20 arranged thereon, a row selection circuit 5, and a signal voltage output circuit 7.

[0382] The image display device 601 also includes a controller 670. The controller 670 takes in control signals separated and generated by an interface circuit (not shown) as input, and controls the driving of each sub-pixel and the driving sequence for the row selection circuit 5 and the signal voltage output circuit 7.

[0383] (Modified Example)

[0384] Figure 33 This is a block diagram illustrating the image display device of this modified example.

[0385] Figure 33 This indicates the structure of a high-definition, thin television.

[0386] like Figure 33 As shown, the image display device 701 includes an image display module 702. The image display module 702 is, for example, an image display device 1 with the structure described in the first embodiment. The image display device 701 includes a controller 770 and a frame memory 780. The controller 770 controls the driving sequence of each sub-pixel of the display area 2 based on control signals supplied by the bus 740. The frame memory 780 stores one frame of display data for processing such as smooth motion image reproduction.

[0387] The image display device 701 includes an I / O circuit 710. The I / O circuit 710 provides interface circuitry for connecting to external terminals and devices. The I / O circuit 710 includes, for example, a USB interface for connecting an external hard disk device, an audio interface, etc.

[0388] The image display device 701 includes a receiving unit 720 and a signal processing unit 730. The receiving unit 720 is connected to an antenna 722 and separates and generates the required signal based on the radio waves received by the antenna 722. The signal processing unit 730 includes a DSP (Digital Signal Processor) and a CPU (Central Processing Unit), etc. The signal separated and generated by the receiving unit 720 is further separated and generated by the signal processing unit 730 into image data and audio data, etc.

[0389] By using a high-frequency communication module such as a mobile phone's GPS receiver for transmitting / receiving and WiFi, the receiving unit 720 and signal processing unit 730 can also be used for other image display devices. For example, an image display device with an image display module having an appropriate screen size and resolution can be a portable information terminal such as a smartphone and a car navigation system.

[0390] The image display module in this embodiment is not limited to the structure of the image display device in the first embodiment, but may also be a variation or other embodiment.

[0391] Figure 34 This is a perspective view schematically illustrating the image display device of the first to fifth embodiments and the above-described modifications.

[0392] like Figure 34 As shown, the image display devices of the first to fifth embodiments, as described above, have a light-emitting circuit 172 with a large number of sub-pixels provided on the circuit board 100. A color filter 180 is provided on the light-emitting circuit 172. It should be noted that, in the sixth embodiment, the structure including the circuit board 100, the light-emitting circuit 172, and the color filter 180 is an image display module 602 and 702, which are assembled in the image display devices 601 and 701.

[0393] According to the embodiments described above, a method for manufacturing an image display device that shortens the transfer process of the light-emitting element and improves the yield rate, as well as an image display device, can be realized.

[0394] The above description illustrates several embodiments of the present invention. These embodiments are mentioned as examples and are not intended to limit the scope of the invention. The new embodiments described above can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The above embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents. Furthermore, the various embodiments described can be combined with each other for implementation.

[0395] Explanation of reference numerals in the attached figures

[0396] 1, 201, 601, 701 Image display device; 2 Display area; 3 Power line; 4 Ground line; 5, 205 Row selection circuit; 6, 206 Scan line; 7, 207 Signal voltage output circuit; 8, 208 Signal line; 10 Pixel; 20, 20a, 20b, 20c Subpixel; 22, 222 Light-emitting element; 24, 224 Select transistor; 26, 226 Drive transistor; 28, 228 Capacitor; 100 Circuit board; 101 Circuit; 103, 203, 203-1, 203-2 Transistor; 104, 204, 204-1, 204-2 Element forming area; 105 Insulating layer; 107, 107-1, 107-2 Gate; 108 Insulating film; 110 First wiring layer; 112 First insulating film; 114 Planarization film; 115 a, 115k, 515a1, 515a2 connectors; 116a, 116a1, 116k plugs; 130, 330 third wiring layers; 130a light shield; 150, 250 light-emitting elements; 156, 156a, 556 second insulating films; 159a, 259k, 559k transparent electrodes; 160, 260, 360, 560 second wiring layers; 180 color filters; 430 wiring layers; 430a, 430k plugs (wiring); 520, 520a sub-pixel groups; 670, 770 controllers; 1001 crystal growth substrate; 1100, 5100 circuit boards; 1130 metal layer; 1140 buffer layer; 1150 semiconductor layer; 1190 support substrate; 1192 structure; 1194, 1294 semiconductor growth substrates.

Claims

1. A method for manufacturing an image display device, characterized in that, have: A process for preparing a substrate having a semiconductor layer including a light-emitting layer on a first substrate; The process of forming a first insulating film on a second substrate having a circuit including circuit elements and a first wiring layer; The process of forming a plug connected to the circuit element within the first insulating film; The process of forming a metal layer in the semiconductor layer; The process of bonding the semiconductor layer to the second substrate and electrically connecting the plug to the semiconductor layer; The process of processing the metal layer to form the third wiring layer; The process of processing the semiconductor layer to form a light-emitting element that is electrically connected to the plug; The process of forming a second insulating film covering the light-emitting element and the first insulating film; The process of removing a portion of the second insulating film to expose a portion of the light-emitting element; The process of forming a second wiring layer on the second insulating film; The third wiring layer includes wiring between the plug and the semiconductor layer; Another wiring is provided separately from the wiring and electrically connected to the second wiring layer.

2. The method for manufacturing the image display device as claimed in claim 1, characterized in that, The semiconductor layers are laminated from one side of the first substrate in the following order: a first semiconductor layer of a first conductivity type, the light-emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type. The first conductivity type is n-type. The second conductivity type is p-type.

3. The method for manufacturing the image display device as described in claim 1, characterized in that, The process of forming the plug includes the following steps: before bonding the substrate to the second substrate, forming a first metal layer that is electrically connected to the circuit element, planarizing the first metal layer, and processing the first metal layer to form the plug.

4. The method for manufacturing the image display device as claimed in claim 1, characterized in that, The process of forming the plug includes the following steps: planarizing the first insulating film and the plug in one step before bonding the substrate to the second substrate.

5. The method for manufacturing the image display device as claimed in claim 1, characterized in that, It also includes a step of removing a portion of the second insulating film to expose the third wiring layer.

6. The method for manufacturing the image display device as claimed in claim 1, characterized in that, The second wiring layer includes wiring connected to the exposed surface of the light-emitting element.

7. The method for manufacturing the image display device as claimed in claim 1, characterized in that, The first substrate contains silicon or sapphire.

8. The method for manufacturing the image display device as claimed in claim 1, characterized in that, The semiconductor layer includes gallium nitride-based compound semiconductors. The second substrate contains silicon.

9. The method for manufacturing the image display device as claimed in claim 1, characterized in that, It also includes a process of forming a wavelength conversion component on the light-emitting element.

10. An image display device, characterized in that, have: Circuit elements; The first wiring layer is electrically connected to the circuit element; A first insulating film covers the circuit elements and the first wiring layer; A plug, which is formed on the first insulating film and connected to the first wiring layer; A light-emitting element includes: a first semiconductor layer of a first conductivity type disposed on and connected to the plug; a light-emitting layer disposed on the first semiconductor layer; and a second semiconductor layer of a second conductivity type disposed on the light-emitting layer and different from the first conductivity type, wherein the first semiconductor layer is located between the plug and the light-emitting layer. A second insulating film covers at least a portion of the light-emitting element, the plug, and the first insulating film; The second wiring layer is connected to the light-emitting element and is disposed on the second insulating film; The third wiring layer includes a wiring disposed between the plug and the first semiconductor layer and another wiring disposed away from the wiring and electrically connected to the second wiring layer.

11. The image display device as claimed in claim 10, characterized in that, The second insulating film has: a first opening that exposes the light-emitting surface of the light-emitting element facing the first insulating film, and a second opening that exposes a portion of the third wiring layer. The second wiring layer includes a transparent electrode that connects the third wiring layer to the light-emitting surface.

12. The image display device as claimed in claim 10, characterized in that, The second insulating film has an opening that exposes the light-emitting surface of the light-emitting element, which faces the first insulating film. It also has a transparent electrode connecting the second wiring layer to the light-emitting surface. The exposed surface from the opening includes a rough surface.

13. The image display device as claimed in claim 10, characterized in that, The first conductivity type is p-type. The second conductivity type is n-type.

14. The image display device as claimed in claim 10, characterized in that, The light-emitting element includes a gallium nitride-based compound semiconductor. The circuit elements are formed on a substrate containing silicon.

15. The image display device as claimed in claim 10, characterized in that, The light-emitting element also has a wavelength conversion component.

16. An image display device, characterized in that, have: Circuit elements; The first wiring layer is electrically connected to the circuit element; A first insulating film covers the circuit elements and the first wiring layer; A plug, which is formed on the first insulating film; A light-emitting element includes: a first semiconductor layer of a first conductivity type disposed on and connected to the plug; a light-emitting layer disposed on the first semiconductor layer; and a second semiconductor layer of a second conductivity type disposed on the light-emitting layer and different from the first conductivity type, wherein the first semiconductor layer is located between the plug and the light-emitting layer. A second insulating film covers at least a portion of the light-emitting element, the plug, and the first insulating film; The second wiring layer is connected to the light-emitting element and is disposed on the second insulating film; A third wiring layer is disposed between the plug and the first semiconductor layer, and includes wiring connected to the circuit element via the first wiring layer and another wiring disposed away from the wiring and electrically connected to the second wiring layer; The second insulating film has: a first opening that exposes the surface of the second semiconductor layer of the light-emitting element, and a second opening that exposes a portion of the third wiring layer. The second wiring layer includes a transparent electrode located in the second semiconductor layer, which connects the light-emitting surface of the light-emitting element, which faces the first insulating film, to the third wiring layer. The other wiring is electrically connected to the light-emitting surface via the transparent electrode disposed in the second opening.

17. An image display device, characterized in that, have: Multiple transistors; A first wiring layer, which is electrically connected to the plurality of transistors; A first insulating film covers the plurality of transistors and the first wiring layer; Multiple plugs are formed on the first insulating film and connected to the first wiring layer; A first semiconductor layer of a first conductivity type is disposed on the plurality of plugs; A light-emitting layer is disposed on the first semiconductor layer, and the first semiconductor layer is located between the plurality of plugs and the light-emitting layer; A second semiconductor layer of a second conductivity type is disposed on the light-emitting layer, and the conductivity type is different from that of the first conductivity type. A second insulating film covers the first insulating film, the plurality of plugs, the first semiconductor layer and the light-emitting layer, and covers at least a portion of the second semiconductor layer; The second wiring layer, corresponding to the plurality of transistors, is exposed from the second insulating film and connected to transparent electrodes disposed on the plurality of exposed surfaces of the second semiconductor layer. The third wiring layer includes wiring between the plug and the first semiconductor layer; Another wiring is provided separately from the wiring and electrically connected to the second wiring layer.

18. The image display device as claimed in claim 17, characterized in that, The second semiconductor layer is separated from the second insulating film.

Images