A gate oxide layer of a high voltage device and a manufacturing method thereof

Abstract

A method for manufacturing a gate oxide layer for a high-voltage device comprises: providing a silicon-based substrate and depositing a pad layer of silicon oxide on the silicon-based substrate; providing an active region on the silicon-based substrate; providing a high-voltage gate oxide region in the active region and removing the pad layer of silicon oxide; growing a first gate oxide layer in the high-voltage gate oxide region using a normal-pressure diffusion furnace process; cleaning the surface impurities of the first gate oxide layer; and growing a second gate oxide layer on the first gate oxide layer after the surface impurities have been cleaned using a high-temperature oxide film process. The gate oxide layer of the high-temperature device of the present invention undergoes two heat treatment processes, which increases the thickness of the gate oxide layer. This causes defect lines to be randomly arranged in the second gate oxide layer and the first gate oxide layer, preventing them from diffusing into the gate oxide layer of the vertically stacked composite structure. This avoids the problem of leakage paths forming between the upper surface of the second gate oxide layer and the lower surface of the first gate oxide layer, improves the reliability of the gate oxide layer, and enhances the voltage resistance of the high-voltage device by 33.3%.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a gate oxide layer of a high-voltage device and a manufacturing method thereof. Background Art

[0002] As is well known, in semiconductor devices, in high-voltage integrated circuits, the low-voltage logic generates control signals to control the high-voltage driver. The output is then boosted to a high voltage level by the high-voltage circuitry of the high-voltage device. Consequently, high-voltage devices must operate under high voltage conditions, so their gate oxide layers also require a certain thickness to achieve a high source-drain withstand voltage.

[0003] When forming two or more gate oxides of varying thickness in high-voltage devices, existing processes employ a single full thermal oxidation process for the high-voltage (thick) gate oxide regions. For the low-voltage (thin) gate oxide regions, a single or multiple photolithography process is used to remove excess gate oxide before a second full thermal oxidation process. The primary cause of high-voltage device failure is often the quality of the thick gate oxide layer. However, conventional atmospheric pressure diffusion furnace growth methods cannot meet the high-pressure requirements for thick gate oxide, thus impacting device performance.

[0004] Seeking a manufacturing method that is simple to operate, has high process integration, can effectively adjust the thickness of the gate oxide layer, and significantly improves the voltage resistance of the semiconductor device while improving the reliability of the semiconductor device, as well as the high-voltage device gate oxide layer obtained by the method has become one of the technical problems that technicians in this field urgently need to solve.

[0005] Therefore, in response to the problems existing in the prior art, the designers of this case, relying on their many years of experience in this industry, actively researched and improved the gate oxide layer of a high-voltage device and the manufacturing method thereof. Summary of the Invention

[0006] The present invention provides a method for manufacturing a gate oxide layer of a high-voltage device in view of the defects in the prior art that the traditional atmospheric pressure diffusion furnace tube growth method cannot meet the quality requirements of thick gate oxide under high-pressure conditions, thereby affecting device performance.

[0007] The present invention aims to provide a high-temperature device gate oxide layer manufactured by a manufacturing method of a gate oxide layer of a high-voltage device in response to the defects in the prior art such as the traditional atmospheric pressure diffusion furnace tube growth method cannot meet the thick gate oxide quality requirements under high-pressure conditions, thereby affecting device performance.

[0008] To achieve the first object of the present invention, the present invention provides a method for manufacturing a gate oxide layer of a high-voltage device, the method comprising:

[0009] Executing step S1: providing a silicon-based substrate, and depositing a pad layer of silicon oxide on the silicon-based substrate;

[0010] Executing step S2: providing an active area on the silicon-based substrate, and isolating the active area by a shallow trench isolation structure;

[0011] Executing step S3: providing a high-voltage gate oxide region in the active area and removing the pad silicon oxide;

[0012] Executing step S4: growing a first gate oxide layer in the high-voltage gate oxide region by a normal pressure diffusion furnace process;

[0013] Executing step S5: cleaning surface impurities from the first gate oxide layer;

[0014] Executing step S6: further growing a second gate oxide layer on the first gate oxide layer after surface impurities have been cleaned by a high temperature oxide film process.

[0015] Optionally, when the first gate oxide layer is grown in the atmospheric pressure diffusion furnace, oxygen and water vapor are introduced as oxidants.

[0016] Optionally, after the growth of the first gate oxide layer is completed, surface impurities of the first gate oxide layer of the gate oxide layer of the high-voltage device are cleaned by using an acidic solution.

[0017] Optionally, the acidic solution is phosphoric acid or hydrofluoric acid.

[0018] Optionally, a growth rate of the first gate oxide layer is greater than a growth rate of the second gate oxide layer.

[0019] Optionally, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0020] To achieve the second purpose of the present invention, the present invention provides a gate oxide layer prepared by the manufacturing method of the gate oxide layer of the high-voltage device described in the present invention, wherein the gate oxide layer includes a first gate oxide layer grown in the high-voltage gate oxide region by a normal pressure diffusion furnace process, and a second gate oxide layer further grown on the first gate oxide layer after surface impurities are cleaned by a high-temperature oxidation film process.

[0021] Optionally, the first gate oxide layer and the second gate oxide layer are a composite film structure stacked vertically from bottom to top on the silicon-based substrate.

[0022] In summary, the gate oxide layer of the high-temperature device of the present invention undergoes two heat treatment processes, which increases the thickness of the gate oxide layer, causing the defect lines to be randomly arranged in the second gate oxide layer and the first gate oxide layer, and unable to diffuse into the gate oxide layer of the vertically stacked composite structure, thereby avoiding the problem of leakage path formation between the upper surface of the second gate oxide layer and the lower surface of the first gate oxide layer, improving the reliability of the gate oxide layer, and enhancing the voltage resistance of the high-voltage device by 33.3%. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG2 is a flow chart of a method for manufacturing a gate oxide layer of a high voltage device according to the present invention;

[0024] Figure 2 FIG2 is a structural schematic diagram of the process of forming the first gate oxide layer of the gate oxide layer of the high voltage device of the present invention;

[0025] Figure 3 FIG2 is a structural schematic diagram of the process of forming the second gate oxide layer of the gate oxide layer of the high voltage device of the present invention;

[0026] Figure 4(a) shows the gate oxide breakdown time test diagram of different processes at 15.5V in NMOS devices;

[0027] FIG4( b ) shows a graph of gate oxide breakdown time test of a PMOS device at 15.5 V with different processes. DETAILED DESCRIPTION

[0028] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following embodiments will be described in detail with reference to the accompanying drawings.

[0029] See also Figure 1 , Figure 1 The flowchart of the method for manufacturing the gate oxide layer of the high voltage device of the present invention is shown. The method for manufacturing the gate oxide layer of the high voltage device includes:

[0030] Executing step S1: providing a silicon-based substrate, and depositing a pad layer of silicon oxide on the silicon-based substrate;

[0031] Executing step S2: providing an active area on the silicon-based substrate, and isolating the active area by a shallow trench isolation structure;

[0032] Executing step S3: providing a high-voltage gate oxide region in the active area and removing the pad silicon oxide;

[0033] Executing step S4: growing a first gate oxide layer in the high-voltage gate oxide region by a normal pressure diffusion furnace process;

[0034] Executing step S5: cleaning surface impurities from the first gate oxide layer;

[0035] Executing step S6: further growing a second gate oxide layer on the first gate oxide layer after surface impurities have been cleaned by a high temperature oxide film process.

[0036] Obviously, the gate oxide layer of the high-voltage device manufactured using the method for manufacturing a gate oxide layer of a high-voltage device of the present invention comprises a first gate oxide layer grown in the high-voltage gate oxide region by a normal pressure diffusion furnace process, and a second gate oxide layer further grown on the first gate oxide layer after surface impurities have been cleaned by a high-temperature oxidation film process. The first gate oxide layer and the second gate oxide layer form a composite film structure stacked vertically from the bottom to the top of the silicon-based substrate.

[0037] To more intuitively disclose the technical solution of the present invention and highlight the beneficial effects of the present invention, the gate oxide layer of the high-voltage device and its manufacturing method and principle are now described in conjunction with specific embodiments. In the specific embodiments, the thickness and material of the functional film layer of the high-voltage device, as well as other process steps before and after the formation of the gate oxide layer of the high-voltage device, are merely examples and should not be construed as limiting the technical solution of the present invention.

[0038] See also Figure 2 、 Figure 3 , and refer to Figure 1 , Figure 2 It is a structural schematic diagram of the formation process of the first gate oxide layer of the gate oxide layer of the high voltage device of the present invention. Figure 3 The figure shows a schematic diagram of the formation process of the second gate oxide layer of the gate oxide layer of the high-voltage device of the present invention. The gate oxide layer 2 of the high-voltage device 1 comprises a first gate oxide layer 21 grown in the high-voltage gate oxide region 20 using an atmospheric pressure diffusion furnace process, and a second gate oxide layer 22 grown on the first gate oxide layer 21 after surface impurities have been cleaned using a high-temperature oxidation film process. The first gate oxide layer 21 and the second gate oxide layer 22 form a composite film structure stacked vertically from bottom to top on the silicon-based substrate 3.

[0039] Without limitation, the active region is the ion implantation region of the logic N-type well or P-type well. Specifically, after ion implantation is completed in the logic N-type well or P-type well serving as the active region, a first gate oxide layer 21 and a second gate oxide layer 22 of varying thicknesses are grown using normal pressure diffusion and low pressure diffusion processes, respectively, to thereby obtain a gate oxide layer 2 of the high-voltage device 1 of quality that meets process requirements.

[0040] As a specific embodiment, in the present invention, the high-voltage device 1 is subjected to a period of high temperature, and the high-voltage gate oxide region 20 is grown with a first gate oxide layer 21 using a normal pressure diffusion furnace process. During the growth of the first gate oxide layer 21 in the normal pressure diffusion furnace, oxygen and water vapor are introduced as oxidants.

[0041] After the first gate oxide layer 21 is grown, the first gate oxide layer 21 of the gate oxide layer 2 of the high-voltage device 1 is cleaned of surface impurities. More specifically, an acidic solution is used to clean the impurities on the surface of the first gate oxide layer 21. The acidic solution includes, but is not limited to, phosphoric acid or hydrofluoric acid.

[0042] After cleaning the surface of the first gate oxide layer 21 of the gate oxide layer 2 to remove impurities, a second gate oxide layer 22 is further grown on the cleaned first gate oxide layer 21 using a high-temperature oxidation film process. The first gate oxide layer 21 and the second gate oxide layer 22 form a composite film structure stacked vertically from bottom to top on the silicon-based substrate 3. Preferably, the growth rate of the first gate oxide layer 21 is greater than the growth rate of the second gate oxide layer 22. The thickness of the first gate oxide layer 21 is greater than the thickness of the second gate oxide layer 22.

[0043] As a person skilled in the art, it is not difficult to understand that the gate oxide layer 2 of the high-temperature device 1 of the present invention undergoes two heat treatment processes, which increases the thickness of the gate oxide layer 2, so that the defect lines are randomly arranged in the second gate oxide layer 22 and the first gate oxide layer 21, and cannot diffuse into the gate oxide layer 2 of the vertically stacked composite structure, thereby avoiding the problem of leakage path formation between the upper surface of the second gate oxide layer 22 and the lower surface of the first gate oxide layer 21, improving the reliability of the gate oxide layer 2, and enhancing the voltage resistance of the high-voltage device 1.

[0044] Please continue reading Figure 4(a) to Figure 4(b) , and refer to Figures 1 to 3 , Figure 4(a) shows a test diagram of the gate oxide breakdown time of different processes at 15.5V in an NMOS device. Figure 4(b) shows a test diagram of the gate oxide breakdown time of different processes at 15.5V in a PMOS device. Among them, the different processes include, in the NMOS device, the number 4a furnace tube thermal growth, 5a high temperature oxide film deposition, 6a high temperature oxide film N2 rapid annealing, 7a high temperature oxide film O2 rapid annealing, 8a high temperature oxide film interlayer dielectric layer heat treatment, 9a high temperature oxide film composite gate oxide layer heat treatment. Similarly, the different processes include, in the PMOS device, the number 4b furnace tube thermal growth, 5b high temperature oxide film deposition, 6b high temperature oxide film N2 rapid annealing, 7b high temperature oxide film O2 rapid annealing, 8b high temperature oxide film interlayer dielectric layer heat treatment, 9b high temperature oxide film composite gate oxide layer heat treatment.

[0045] As can be seen from the figure, the gate oxide layer 2 of the high-temperature device 1 of the present invention undergoes two heat treatment processes, which increases the thickness of the gate oxide layer 2, causing the defect lines to be randomly arranged in the second gate oxide layer 22 and the first gate oxide layer 21, and unable to diffuse into the gate oxide layer 2 of the vertically stacked composite structure. This avoids the problem of leakage path formation between the upper surface of the second gate oxide layer 22 and the lower surface of the first gate oxide layer 21, improves the reliability of the gate oxide layer 2, and enhances the voltage resistance of the high-voltage device 1 by 33.3%.

[0046] In summary, the gate oxide layer of the high-temperature device of the present invention undergoes two heat treatment processes, which increases the thickness of the gate oxide layer, causing the defect lines to be randomly arranged in the second gate oxide layer and the first gate oxide layer, and unable to diffuse into the gate oxide layer of the vertically stacked composite structure, thereby avoiding the problem of leakage path formation between the upper surface of the second gate oxide layer and the lower surface of the first gate oxide layer, improving the reliability of the gate oxide layer, and enhancing the voltage resistance of the high-voltage device by 33.3%.

[0047] Those skilled in the art will appreciate that various modifications and variations may be made to the present invention without departing from the spirit or scope of the present invention. Therefore, if any modification or variation falls within the scope of protection of the appended claims and their equivalents, the present invention is considered to cover such modifications and variations.

Claims

1. A method for manufacturing a gate oxide layer of a high voltage device, characterized in that: The method for manufacturing the gate oxide layer of the high-voltage device comprises: Executing step S1: providing a silicon-based substrate, and depositing a pad layer of silicon oxide on the silicon-based substrate; Executing step S2: providing an active area on the silicon-based substrate, and isolating the active area by a shallow trench isolation structure; Executing step S3: providing a high-voltage gate oxide region in the active area and removing the pad silicon oxide; Executing step S4: growing a first gate oxide layer in the high-voltage gate oxide region by a normal pressure diffusion furnace process; Executing step S5: cleaning surface impurities from the first gate oxide layer; Executing step S6: further growing a second gate oxide layer on the first gate oxide layer after surface impurities have been cleaned by a high-temperature oxide film process; The growth rate of the first gate oxide layer is greater than the growth rate of the second gate oxide layer, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

2. The method for manufacturing a gate oxide layer of a high voltage device according to claim 1, wherein: When the atmospheric pressure diffusion furnace tube grows the first gate oxide layer, oxygen and water vapor are introduced as oxidants.

3. The method for manufacturing a gate oxide layer of a high voltage device according to claim 1, wherein: After the growth of the first gate oxide layer is completed, the surface impurities of the first gate oxide layer of the gate oxide layer of the high-voltage device are cleaned by using an acidic solution.

4. The method for manufacturing a gate oxide layer of a high voltage device as claimed in claim 3, wherein: The acidic solution is phosphoric acid or hydrofluoric acid.

5. A gate oxide layer prepared by the method for manufacturing a gate oxide layer of a high voltage device as claimed in claim 1, characterized in that: The gate oxide layer comprises a first gate oxide layer grown in the high-voltage gate oxide region by a normal pressure diffusion furnace process, and a second gate oxide layer further grown on the first gate oxide layer after surface impurities are cleaned by a high temperature oxide film process.

6. The gate oxide layer of the high voltage device according to claim 5, wherein: The first gate oxide layer and the second gate oxide layer are a composite film structure vertically stacked from bottom to top of the silicon-based substrate.

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