A method for planarizing the surface of a semiconductor device

Abstract

The present invention relates to a method for planarizing the surface of a semiconductor device, which includes the following steps: depositing an oxide layer and silicon nitride on a silicon substrate; oxidizing an opening region to form a terminal region oxide layer; depositing a hard mask layer; performing photolithography and then etching the hard mask layer; using the hard mask layer as an etching barrier layer to perform active region trench etching; removing the damaged layer in the trench and then growing a gate oxide layer; depositing polysilicon on the surface, and filling all the trenches with polysilicon; performing CMP polishing to achieve planarization of the wafer surface; synchronously etching the silicon nitride and the oxide layer, and stopping at the cell region oxide layer; etching the polysilicon and the oxide layer in the cell region trench that are higher than the silicon plane, and stopping at the surface of the silicon substrate to achieve planarization. The present invention avoids polysilicon residue in the terminal region, does not require introducing an extra process to remove the hard mask layer, has a simple process, can accurately capture the endpoint signal, achieve the planarization effect, and ensure the uniformity of the product.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a method for surface planarization of semiconductor devices. Background Art

[0002] Currently, in the process of sub-micron fine trench power devices, after the oxide layer in the terminal region is formed, there will be a step as Figure 1 shown, and then after polysilicon deposition as Figure 2 shown; as Figure 3 shown, first perform a CMP grinding process on the polysilicon, and then perform a CMP grinding process on the oxide layer in the terminal region, and finally achieve global planarization of the wafer to prepare for subsequent small line width processes. Due to the formation of bird's beak during terminal oxidation, polysilicon is extremely likely to remain after grinding at the bird's beak after polysilicon deposition, and staying on the oxide layer poses a greater challenge to the process.

[0003] There are several technical solutions relatively close to the present invention as follows:

[0004] (1) Application No.: CN201710733237.4 discloses a method for fabricating a three-dimensional memory, which uses dry etching, including: etching the top polysilicon and stopping at the nitride; then etching the hard mask SiN layer and stopping at the oxide. By using dry etching, the use of CMP is reduced.

[0005] Application No.: CN201410459207.5 discloses a method for manufacturing a superjunction semiconductor device, which etches deep trenches on the wafer surface; fills P-type single-crystalline silicon in the deep trenches; CMP removes the P-type polysilicon on the surface of the hard mask layer, and performs P-type impurity implantation using the remaining hard mask layer as a mask to form a P-type layer.

[0006] Application No.: CN201210496251.4 discloses a superjunction epitaxial CMP process method. After fabricating the polysilicon trench gate, no back-etching is performed, but instead, the trench back-etching and trench epitaxial growth processes are directly completed. After the epitaxial growth is completed, a CMP process is performed. This step of CMP can simultaneously grind the trench gate polysilicon and the trench epitaxy, and ensure the flatness of their surfaces, preventing the problem of epitaxial residue.

[0007] Application No.: CN201710761488.3 discloses a CMP method for the interlayer insulating oxide layer in the core region of 3D NAND, including: providing a substrate; depositing an NO stack on the substrate; depositing a SiON layer on the NO stack and performing ISSG treatment; depositing an oxide layer on the SiON layer after ISSG treatment; etching a stepped structure to complete the core region; depositing an interlayer insulating oxide layer in the core region, which at least fills the peripheral region of the stepped structure; performing CMP treatment on the substrate structure deposited with the interlayer insulating oxide layer in the core region, using the SiON layer treated by ISSG as the polishing stop layer. By using the SiON layer treated by ISSG as the polishing stop layer, the polishing selectivity of the polishing stop layer is improved, the thickness of the mask stop layer is reduced, and further the step height after removing the polishing stop layer is reduced. Adopting this CMP method can improve the uniformity of the oxidation thickness of the channel hole plug and reduce the variation of the storage device characteristics.

[0008] However, the above method does not process the polysilicon residue in the terminal region and does not solve the planarization problem in the terminal region. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a surface planarization method for semiconductor devices, avoid polysilicon residue in the terminal region, do not need to introduce an extra process to remove the hard mask layer, the process is simple, can accurately capture the end point signal, achieve the planarization effect, and ensure the uniformity of products in mass production.

[0010] The content of the present invention is a surface planarization method for semiconductor devices, including the following steps.

[0011] 1) Deposit an oxide layer and silicon nitride on a silicon substrate.

[0012] 2) Oxidize the opened area to form an oxide layer in the terminal region.

[0013] 3) Deposit a hard mask layer.

[0014] 4) Perform photolithography, and then etch the hard mask layer. Due to the material characteristics of the hard mask, the hard grinding side remains consistent during trench etching, and precise control of trench CD can be achieved.

[0015] 5) Use the hard mask layer as an etching barrier layer to perform active region trench etching.

[0016] 6) Remove the damaged layer in the trench, and then grow a gate oxide layer.

[0017] 7) Deposit polysilicon on the surface, and the polysilicon fills all the trenches.

[0018] 8) Perform CMP polishing. First polish the surface polysilicon, and then polish the hard mask layer and the oxide layer at the LOCOS to achieve planarization of the wafer surface;

[0019] 9) Etch the silicon nitride and the oxide layer synchronously, and stop at the oxide layer in the cell area;

[0020] 10) Etch the polysilicon and the oxide layer in the trench of the cell area that are higher than the silicon plane, and stop at the surface of the silicon substrate to finally achieve planarization.

[0021] Preferably, the thickness of the oxide layer deposited on the silicon substrate is 270 - 330 Å (i.e., 300 ± 30 Å), and the thickness of the silicon nitride is 900 - 1100 Å (i.e., 1000 ± 100 Å).

[0022] Preferably, the terminal area oxide layer is formed by the LOCOS process.

[0023] Preferably, the hard mask layer includes two layers, the bottom layer is silicon oxide, and the surface layer is silicon nitride. The thickness of the hard mask layer is 6000 - 6800 Å (i.e., 6400 ± 400 Å). The thinner growth of the bottom oxide layer can reduce the generation of stress. The thinner growth of the oxide layer avoids fewer high-temperature processes, and can significantly relieve the stress problem.

[0024] Preferably, the method for removing the damaged layer in the trench is dry etching, and generally a dry etching machine is used to remove it.

[0025] Preferably, the method for synchronously etching the silicon nitride and the oxide layer is to select a substance with a similar etching rate for the silicon nitride and the oxide layer to etch the silicon nitride and the oxide layer. The etching substance is generally an F-based etching gas.

[0026] The beneficial effect of the present invention is that the present invention is applicable to any semiconductor device that requires CMP and hard mask etching. Especially in power semiconductor devices, while achieving a stable mass production solution, it can implement the surface planarization CMP (Chemical Mechanical Planarization) process step, and this technical solution can be directly compatible with the hard mask controlled trench CD technology without the need to introduce an extra hard mask removal process, and finally achieve a good planarization effect on the wafer surface.

[0027] The terminal layer oxide layer forms a bird's beak. The polysilicon of the present invention is directly deposited on the hard mask oxide layer, and the terminal oxide layer is lifted, and polysilicon residue is not easily caused at the place where the bird's beak is formed; at the same time, adding a hard mask layer can ensure the trench size without the need to introduce an extra process to remove the hard mask layer, achieving the purpose of simplifying the process.

[0028] During the polishing of the terminal area oxide layer, due to the presence of the silicon nitride stop layer, the endpoint signal can be accurately captured, achieving a planarization effect, and mass production can ensure the uniformity of the product.

[0029] On the basis of maintaining the original process plan, the present invention can polish by means of endpoint capture through the CMP process. While achieving large-scale production, it can ensure the uniformity of its products and achieve better compatibility with subsequent process steps.

[0030] The present invention integrates the trench hard mask layer to control the CD technology. While achieving precise control of the critical dimension, it does not require an additional hard mask removal process, reducing the introduction of other process steps.

[0031] The product involved in the present invention can be a power device or an integrated circuit field using the CMP process. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic structural diagram of the terminal area deposited oxide layer of the prior art.

[0033] Figure 2 It is a schematic structural diagram of the deposited polysilicon of the prior art.

[0034] Figure 3 It is a schematic structural diagram after the CMP polishing process of the prior art.

[0035] Figures 4-13 They are the process steps from step 1) to step 10) of the present invention respectively.

[0036] Figure 14 It is a process flow chart of the present invention.

[0037] In the figure, 1 is a silicon substrate, 2 is a cell area oxide layer, 3 is silicon nitride, 4 is a terminal area oxide layer, 5 is a hard mask layer, 6 is an active area trench, 7 is a gate oxide layer after damage layer removal, and 8 is polysilicon. DETAILED DESCRIPTION OF THE INVENTION

[0038] Example 1

[0039] A method for surface planarization of a semiconductor device, comprising the following steps:

[0040] Step 1: As Figure 4 shown, deposit a cell area oxide layer 2 and silicon nitride 3 on a silicon substrate 1;

[0041] Step 2: As Figure 5 shown, oxidize the opened area formed by etching to form a terminal area oxide layer 4;

[0042] Step 3: As Figure 6 shown, deposit a hard mask layer 5;

[0043] Step 4: As shown in Figure 7 , first perform photolithography, and then etch the hard mask layer 5, silicon nitride 3, and cell region oxide layer 2.

[0044] Step 5: As shown in Figure 8 , use the hard mask layer as an etch stop layer to form the active region trench 6.

[0045] Step 6: As shown in Figure 9 , use dry etching to remove the damaged layer in the trench, and then perform gate oxide oxidation after the damaged layer is removed to obtain the gate oxide layer 7 after the damaged layer is removed.

[0046] Step 7: As shown in Figure 10 , deposit polysilicon 8 on the device surface, and the polysilicon fills all the trenches.

[0047] Step 8: As shown in Figure 11 , perform CMP polishing. First polish the surface polysilicon, and then polish the hard mask layer and the oxide layer at the LOCOS to achieve planarization of the wafer surface.

[0048] Step 9: As shown in Figure 12 , use an etching selectivity similar to that of silicon nitride and the oxide layer, and stop on the thin oxide layer in the cell region.

[0049] Step 10: As shown in Figure 13 , etch the polysilicon and thin oxide in the cell region trench that are higher than the silicon plane, and stop on the silicon substrate surface to finally achieve planarization.

[0050] The process method described in the present invention: The oxide layer generation and filling processes remain unchanged. A hard mask deposition process is added after the original LOCOS oxide layer, and at the same time, a hard mask layer etching process and a trench etching process using the hard mask layer as a stop layer are added. For the damaged layer formed on the sidewall after trench etching, a method with stronger chemical etching in dry etching is used to remove it. After polysilicon deposition, a planarization CMP process is performed on the device surface. First, polish the polysilicon, and then polish the oxide layer, and stop on the silicon nitride surface. The CMP process can easily capture the EDP curve at the silicon nitride dielectric layer, and dry etching is used to achieve final planarization.

[0051] Those of ordinary skill in the art should understand that: The discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples; Under the concept of the present disclosure, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of one or more embodiments of the present application as described above, and they are not provided in detail for the sake of brevity.

[0052] One or more embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of the present application shall be included within the scope of protection of the present disclosure.

Claims

1. A method for planarizing the surface of a semiconductor device, characterized in that, it includes the following steps, 1) Deposit a cell region oxide layer and silicon nitride on a silicon substrate; 2) Oxidize the open region to form a terminal region oxide layer; 3) Deposit a hard mask layer; 4) Perform photolithography, and then etch the hard mask layer; 5) Use the hard mask layer as an etch stop layer to perform active region trench etching; 6) Remove the damaged layer in the trench, and then grow a gate oxide layer; 7) Deposit polysilicon on the surface, and the polysilicon fills all the trenches; 8) Perform CMP polishing, first polish the surface polysilicon, and then polish the hard mask layer and the terminal region oxide layer at the LOCOS to achieve planarization of the wafer surface; 9) Simultaneously etch the silicon nitride and the terminal region oxide layer, and stop at the cell region oxide layer; 10) Etch the polysilicon and the cell region oxide layer in the cell region trench that is higher than the silicon plane, and stop at the surface of the silicon substrate to finally achieve planarization.

2. The method for planarizing the surface of a semiconductor device according to claim 1, characterized in that, the thickness of the oxide layer deposited on the silicon substrate is 270 - 330 angstroms.

3. The method for planarizing the surface of a semiconductor device according to claim 1, characterized in that, the thickness of the silicon nitride deposited on the silicon substrate is 900 - 1100 angstroms.

4. The method for planarizing the surface of a semiconductor device according to claim 1, characterized in that, the terminal region oxide layer is formed by the LOCOS process.

5. The method for planarizing the surface of a semiconductor device according to any one of claims 1 - 4, characterized in that, the hard mask layer includes two layers, the bottom layer is silicon oxide, and the surface layer is silicon nitride.

6. The method for planarizing the surface of a semiconductor device according to claim 5, characterized in that, the thickness of the hard mask layer is 6000 - 6800 angstroms.

7. The method for planarizing the surface of a semiconductor device according to any one of claims 1 - 4, characterized in that, the method for removing the damaged layer in the trench is dry etching.

8. The method for planarizing the surface of a semiconductor device according to any one of claims 1 - 4, characterized in that, the method for simultaneously etching the silicon nitride and the oxide layer is to select a substance with similar etching rates for the silicon nitride and the oxide layer to etch the silicon nitride and the oxide layer.

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